1 /**
2 ******************************************************************************
3 * @file stm32f2xx_ll_spi.h
4 * @author MCD Application Team
5 * @brief Header file of SPI LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32F2xx_LL_SPI_H
21 #define STM32F2xx_LL_SPI_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f2xx.h"
29
30 /** @addtogroup STM32F2xx_LL_Driver
31 * @{
32 */
33
34 #if defined (SPI1) || defined (SPI2) || defined (SPI3)
35
36 /** @defgroup SPI_LL SPI
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private macros ------------------------------------------------------------*/
43
44 /* Exported types ------------------------------------------------------------*/
45 #if defined(USE_FULL_LL_DRIVER)
46 /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
47 * @{
48 */
49
50 /**
51 * @brief SPI Init structures definition
52 */
53 typedef struct
54 {
55 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
56 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
57
58 This feature can be modified afterwards using unitary
59 function @ref LL_SPI_SetTransferDirection().*/
60
61 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
62 This parameter can be a value of @ref SPI_LL_EC_MODE.
63
64 This feature can be modified afterwards using unitary
65 function @ref LL_SPI_SetMode().*/
66
67 uint32_t DataWidth; /*!< Specifies the SPI data width.
68 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
69
70 This feature can be modified afterwards using unitary
71 function @ref LL_SPI_SetDataWidth().*/
72
73 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
74 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
75
76 This feature can be modified afterwards using unitary
77 function @ref LL_SPI_SetClockPolarity().*/
78
79 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
80 This parameter can be a value of @ref SPI_LL_EC_PHASE.
81
82 This feature can be modified afterwards using unitary
83 function @ref LL_SPI_SetClockPhase().*/
84
85 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin)
86 or by software using the SSI bit.
87 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
88
89 This feature can be modified afterwards using unitary
90 function @ref LL_SPI_SetNSSMode().*/
91
92 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used
93 to configure the transmit and receive SCK clock.
94 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
95 @note The communication clock is derived from the master clock.
96 The slave clock does not need to be set.
97
98 This feature can be modified afterwards using unitary
99 function @ref LL_SPI_SetBaudRatePrescaler().*/
100
101 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
102 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
103
104 This feature can be modified afterwards using unitary
105 function @ref LL_SPI_SetTransferBitOrder().*/
106
107 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
108 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
109
110 This feature can be modified afterwards using unitary
111 functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
112
113 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
114 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
115
116 This feature can be modified afterwards using unitary
117 function @ref LL_SPI_SetCRCPolynomial().*/
118
119 } LL_SPI_InitTypeDef;
120
121 /**
122 * @}
123 */
124 #endif /* USE_FULL_LL_DRIVER */
125
126 /* Exported constants --------------------------------------------------------*/
127 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
128 * @{
129 */
130
131 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
132 * @brief Flags defines which can be used with LL_SPI_ReadReg function
133 * @{
134 */
135 #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
136 #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
137 #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
138 #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
139 #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
140 #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
141 #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
142 /**
143 * @}
144 */
145
146 /** @defgroup SPI_LL_EC_IT IT Defines
147 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
148 * @{
149 */
150 #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
151 #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
152 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
153 /**
154 * @}
155 */
156
157 /** @defgroup SPI_LL_EC_MODE Operation Mode
158 * @{
159 */
160 #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
161 #define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
162 /**
163 * @}
164 */
165
166 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
167 * @{
168 */
169 #define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */
170 #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */
171 /**
172 * @}
173 */
174
175 /** @defgroup SPI_LL_EC_PHASE Clock Phase
176 * @{
177 */
178 #define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
179 #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
180 /**
181 * @}
182 */
183
184 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
185 * @{
186 */
187 #define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
188 #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
189 /**
190 * @}
191 */
192
193 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
194 * @{
195 */
196 #define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
197 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
198 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
199 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
200 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
201 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
202 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
203 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
204 /**
205 * @}
206 */
207
208 /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
209 * @{
210 */
211 #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
212 #define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
213 /**
214 * @}
215 */
216
217 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
218 * @{
219 */
220 #define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
221 #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
222 #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
223 #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
224 /**
225 * @}
226 */
227
228 /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
229 * @{
230 */
231 #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
232 #define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
233 #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
234 /**
235 * @}
236 */
237
238 /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
239 * @{
240 */
241 #define LL_SPI_DATAWIDTH_8BIT 0x00000000U /*!< Data length for SPI transfer: 8 bits */
242 #define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /*!< Data length for SPI transfer: 16 bits */
243 /**
244 * @}
245 */
246 #if defined(USE_FULL_LL_DRIVER)
247
248 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
249 * @{
250 */
251 #define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
252 #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
253 /**
254 * @}
255 */
256 #endif /* USE_FULL_LL_DRIVER */
257
258 /**
259 * @}
260 */
261
262 /* Exported macro ------------------------------------------------------------*/
263 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
264 * @{
265 */
266
267 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
268 * @{
269 */
270
271 /**
272 * @brief Write a value in SPI register
273 * @param __INSTANCE__ SPI Instance
274 * @param __REG__ Register to be written
275 * @param __VALUE__ Value to be written in the register
276 * @retval None
277 */
278 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
279
280 /**
281 * @brief Read a value in SPI register
282 * @param __INSTANCE__ SPI Instance
283 * @param __REG__ Register to be read
284 * @retval Register value
285 */
286 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
287 /**
288 * @}
289 */
290
291 /**
292 * @}
293 */
294
295 /* Exported functions --------------------------------------------------------*/
296 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
297 * @{
298 */
299
300 /** @defgroup SPI_LL_EF_Configuration Configuration
301 * @{
302 */
303
304 /**
305 * @brief Enable SPI peripheral
306 * @rmtoll CR1 SPE LL_SPI_Enable
307 * @param SPIx SPI Instance
308 * @retval None
309 */
LL_SPI_Enable(SPI_TypeDef * SPIx)310 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
311 {
312 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
313 }
314
315 /**
316 * @brief Disable SPI peripheral
317 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
318 * @rmtoll CR1 SPE LL_SPI_Disable
319 * @param SPIx SPI Instance
320 * @retval None
321 */
LL_SPI_Disable(SPI_TypeDef * SPIx)322 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
323 {
324 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
325 }
326
327 /**
328 * @brief Check if SPI peripheral is enabled
329 * @rmtoll CR1 SPE LL_SPI_IsEnabled
330 * @param SPIx SPI Instance
331 * @retval State of bit (1 or 0).
332 */
LL_SPI_IsEnabled(const SPI_TypeDef * SPIx)333 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx)
334 {
335 return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
336 }
337
338 /**
339 * @brief Set SPI operation mode to Master or Slave
340 * @note This bit should not be changed when communication is ongoing.
341 * @rmtoll CR1 MSTR LL_SPI_SetMode\n
342 * CR1 SSI LL_SPI_SetMode
343 * @param SPIx SPI Instance
344 * @param Mode This parameter can be one of the following values:
345 * @arg @ref LL_SPI_MODE_MASTER
346 * @arg @ref LL_SPI_MODE_SLAVE
347 * @retval None
348 */
LL_SPI_SetMode(SPI_TypeDef * SPIx,uint32_t Mode)349 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
350 {
351 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
352 }
353
354 /**
355 * @brief Get SPI operation mode (Master or Slave)
356 * @rmtoll CR1 MSTR LL_SPI_GetMode\n
357 * CR1 SSI LL_SPI_GetMode
358 * @param SPIx SPI Instance
359 * @retval Returned value can be one of the following values:
360 * @arg @ref LL_SPI_MODE_MASTER
361 * @arg @ref LL_SPI_MODE_SLAVE
362 */
LL_SPI_GetMode(const SPI_TypeDef * SPIx)363 __STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx)
364 {
365 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
366 }
367
368 /**
369 * @brief Set serial protocol used
370 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
371 * @rmtoll CR2 FRF LL_SPI_SetStandard
372 * @param SPIx SPI Instance
373 * @param Standard This parameter can be one of the following values:
374 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
375 * @arg @ref LL_SPI_PROTOCOL_TI
376 * @retval None
377 */
LL_SPI_SetStandard(SPI_TypeDef * SPIx,uint32_t Standard)378 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
379 {
380 MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
381 }
382
383 /**
384 * @brief Get serial protocol used
385 * @rmtoll CR2 FRF LL_SPI_GetStandard
386 * @param SPIx SPI Instance
387 * @retval Returned value can be one of the following values:
388 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
389 * @arg @ref LL_SPI_PROTOCOL_TI
390 */
LL_SPI_GetStandard(const SPI_TypeDef * SPIx)391 __STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx)
392 {
393 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
394 }
395
396 /**
397 * @brief Set clock phase
398 * @note This bit should not be changed when communication is ongoing.
399 * This bit is not used in SPI TI mode.
400 * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
401 * @param SPIx SPI Instance
402 * @param ClockPhase This parameter can be one of the following values:
403 * @arg @ref LL_SPI_PHASE_1EDGE
404 * @arg @ref LL_SPI_PHASE_2EDGE
405 * @retval None
406 */
LL_SPI_SetClockPhase(SPI_TypeDef * SPIx,uint32_t ClockPhase)407 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
408 {
409 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
410 }
411
412 /**
413 * @brief Get clock phase
414 * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
415 * @param SPIx SPI Instance
416 * @retval Returned value can be one of the following values:
417 * @arg @ref LL_SPI_PHASE_1EDGE
418 * @arg @ref LL_SPI_PHASE_2EDGE
419 */
LL_SPI_GetClockPhase(const SPI_TypeDef * SPIx)420 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx)
421 {
422 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
423 }
424
425 /**
426 * @brief Set clock polarity
427 * @note This bit should not be changed when communication is ongoing.
428 * This bit is not used in SPI TI mode.
429 * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
430 * @param SPIx SPI Instance
431 * @param ClockPolarity This parameter can be one of the following values:
432 * @arg @ref LL_SPI_POLARITY_LOW
433 * @arg @ref LL_SPI_POLARITY_HIGH
434 * @retval None
435 */
LL_SPI_SetClockPolarity(SPI_TypeDef * SPIx,uint32_t ClockPolarity)436 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
437 {
438 MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
439 }
440
441 /**
442 * @brief Get clock polarity
443 * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
444 * @param SPIx SPI Instance
445 * @retval Returned value can be one of the following values:
446 * @arg @ref LL_SPI_POLARITY_LOW
447 * @arg @ref LL_SPI_POLARITY_HIGH
448 */
LL_SPI_GetClockPolarity(const SPI_TypeDef * SPIx)449 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx)
450 {
451 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
452 }
453
454 /**
455 * @brief Set baud rate prescaler
456 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
457 * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
458 * @param SPIx SPI Instance
459 * @param BaudRate This parameter can be one of the following values:
460 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
461 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
462 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
463 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
464 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
465 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
466 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
467 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
468 * @retval None
469 */
LL_SPI_SetBaudRatePrescaler(SPI_TypeDef * SPIx,uint32_t BaudRate)470 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
471 {
472 MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
473 }
474
475 /**
476 * @brief Get baud rate prescaler
477 * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
478 * @param SPIx SPI Instance
479 * @retval Returned value can be one of the following values:
480 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
481 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
482 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
483 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
484 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
485 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
486 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
487 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
488 */
LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef * SPIx)489 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx)
490 {
491 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
492 }
493
494 /**
495 * @brief Set transfer bit order
496 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
497 * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
498 * @param SPIx SPI Instance
499 * @param BitOrder This parameter can be one of the following values:
500 * @arg @ref LL_SPI_LSB_FIRST
501 * @arg @ref LL_SPI_MSB_FIRST
502 * @retval None
503 */
LL_SPI_SetTransferBitOrder(SPI_TypeDef * SPIx,uint32_t BitOrder)504 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
505 {
506 MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
507 }
508
509 /**
510 * @brief Get transfer bit order
511 * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
512 * @param SPIx SPI Instance
513 * @retval Returned value can be one of the following values:
514 * @arg @ref LL_SPI_LSB_FIRST
515 * @arg @ref LL_SPI_MSB_FIRST
516 */
LL_SPI_GetTransferBitOrder(const SPI_TypeDef * SPIx)517 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx)
518 {
519 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
520 }
521
522 /**
523 * @brief Set transfer direction mode
524 * @note For Half-Duplex mode, Rx Direction is set by default.
525 * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
526 * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
527 * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
528 * CR1 BIDIOE LL_SPI_SetTransferDirection
529 * @param SPIx SPI Instance
530 * @param TransferDirection This parameter can be one of the following values:
531 * @arg @ref LL_SPI_FULL_DUPLEX
532 * @arg @ref LL_SPI_SIMPLEX_RX
533 * @arg @ref LL_SPI_HALF_DUPLEX_RX
534 * @arg @ref LL_SPI_HALF_DUPLEX_TX
535 * @retval None
536 */
LL_SPI_SetTransferDirection(SPI_TypeDef * SPIx,uint32_t TransferDirection)537 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
538 {
539 MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
540 }
541
542 /**
543 * @brief Get transfer direction mode
544 * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
545 * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
546 * CR1 BIDIOE LL_SPI_GetTransferDirection
547 * @param SPIx SPI Instance
548 * @retval Returned value can be one of the following values:
549 * @arg @ref LL_SPI_FULL_DUPLEX
550 * @arg @ref LL_SPI_SIMPLEX_RX
551 * @arg @ref LL_SPI_HALF_DUPLEX_RX
552 * @arg @ref LL_SPI_HALF_DUPLEX_TX
553 */
LL_SPI_GetTransferDirection(const SPI_TypeDef * SPIx)554 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx)
555 {
556 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
557 }
558
559 /**
560 * @brief Set frame data width
561 * @rmtoll CR1 DFF LL_SPI_SetDataWidth
562 * @param SPIx SPI Instance
563 * @param DataWidth This parameter can be one of the following values:
564 * @arg @ref LL_SPI_DATAWIDTH_8BIT
565 * @arg @ref LL_SPI_DATAWIDTH_16BIT
566 * @retval None
567 */
LL_SPI_SetDataWidth(SPI_TypeDef * SPIx,uint32_t DataWidth)568 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
569 {
570 MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
571 }
572
573 /**
574 * @brief Get frame data width
575 * @rmtoll CR1 DFF LL_SPI_GetDataWidth
576 * @param SPIx SPI Instance
577 * @retval Returned value can be one of the following values:
578 * @arg @ref LL_SPI_DATAWIDTH_8BIT
579 * @arg @ref LL_SPI_DATAWIDTH_16BIT
580 */
LL_SPI_GetDataWidth(const SPI_TypeDef * SPIx)581 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx)
582 {
583 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
584 }
585
586 /**
587 * @}
588 */
589
590 /** @defgroup SPI_LL_EF_CRC_Management CRC Management
591 * @{
592 */
593
594 /**
595 * @brief Enable CRC
596 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
597 * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
598 * @param SPIx SPI Instance
599 * @retval None
600 */
LL_SPI_EnableCRC(SPI_TypeDef * SPIx)601 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
602 {
603 SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
604 }
605
606 /**
607 * @brief Disable CRC
608 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
609 * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
610 * @param SPIx SPI Instance
611 * @retval None
612 */
LL_SPI_DisableCRC(SPI_TypeDef * SPIx)613 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
614 {
615 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
616 }
617
618 /**
619 * @brief Check if CRC is enabled
620 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
621 * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
622 * @param SPIx SPI Instance
623 * @retval State of bit (1 or 0).
624 */
LL_SPI_IsEnabledCRC(const SPI_TypeDef * SPIx)625 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx)
626 {
627 return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
628 }
629
630 /**
631 * @brief Set CRCNext to transfer CRC on the line
632 * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
633 * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
634 * @param SPIx SPI Instance
635 * @retval None
636 */
LL_SPI_SetCRCNext(SPI_TypeDef * SPIx)637 __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
638 {
639 SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
640 }
641
642 /**
643 * @brief Set polynomial for CRC calculation
644 * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
645 * @param SPIx SPI Instance
646 * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
647 * @retval None
648 */
LL_SPI_SetCRCPolynomial(SPI_TypeDef * SPIx,uint32_t CRCPoly)649 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
650 {
651 WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
652 }
653
654 /**
655 * @brief Get polynomial for CRC calculation
656 * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
657 * @param SPIx SPI Instance
658 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
659 */
LL_SPI_GetCRCPolynomial(const SPI_TypeDef * SPIx)660 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx)
661 {
662 return (uint32_t)(READ_REG(SPIx->CRCPR));
663 }
664
665 /**
666 * @brief Get Rx CRC
667 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
668 * @param SPIx SPI Instance
669 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
670 */
LL_SPI_GetRxCRC(const SPI_TypeDef * SPIx)671 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx)
672 {
673 return (uint32_t)(READ_REG(SPIx->RXCRCR));
674 }
675
676 /**
677 * @brief Get Tx CRC
678 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
679 * @param SPIx SPI Instance
680 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
681 */
LL_SPI_GetTxCRC(const SPI_TypeDef * SPIx)682 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx)
683 {
684 return (uint32_t)(READ_REG(SPIx->TXCRCR));
685 }
686
687 /**
688 * @}
689 */
690
691 /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
692 * @{
693 */
694
695 /**
696 * @brief Set NSS mode
697 * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
698 * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
699 * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
700 * @param SPIx SPI Instance
701 * @param NSS This parameter can be one of the following values:
702 * @arg @ref LL_SPI_NSS_SOFT
703 * @arg @ref LL_SPI_NSS_HARD_INPUT
704 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
705 * @retval None
706 */
LL_SPI_SetNSSMode(SPI_TypeDef * SPIx,uint32_t NSS)707 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
708 {
709 MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
710 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
711 }
712
713 /**
714 * @brief Get NSS mode
715 * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
716 * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
717 * @param SPIx SPI Instance
718 * @retval Returned value can be one of the following values:
719 * @arg @ref LL_SPI_NSS_SOFT
720 * @arg @ref LL_SPI_NSS_HARD_INPUT
721 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
722 */
LL_SPI_GetNSSMode(const SPI_TypeDef * SPIx)723 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx)
724 {
725 uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
726 uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
727 return (Ssm | Ssoe);
728 }
729
730 /**
731 * @}
732 */
733
734 /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
735 * @{
736 */
737
738 /**
739 * @brief Check if Rx buffer is not empty
740 * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
741 * @param SPIx SPI Instance
742 * @retval State of bit (1 or 0).
743 */
LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef * SPIx)744 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx)
745 {
746 return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
747 }
748
749 /**
750 * @brief Check if Tx buffer is empty
751 * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
752 * @param SPIx SPI Instance
753 * @retval State of bit (1 or 0).
754 */
LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef * SPIx)755 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef *SPIx)
756 {
757 return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
758 }
759
760 /**
761 * @brief Get CRC error flag
762 * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
763 * @param SPIx SPI Instance
764 * @retval State of bit (1 or 0).
765 */
LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef * SPIx)766 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx)
767 {
768 return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
769 }
770
771 /**
772 * @brief Get mode fault error flag
773 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
774 * @param SPIx SPI Instance
775 * @retval State of bit (1 or 0).
776 */
LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef * SPIx)777 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx)
778 {
779 return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
780 }
781
782 /**
783 * @brief Get overrun error flag
784 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
785 * @param SPIx SPI Instance
786 * @retval State of bit (1 or 0).
787 */
LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef * SPIx)788 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
789 {
790 return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
791 }
792
793 /**
794 * @brief Get busy flag
795 * @note The BSY flag is cleared under any one of the following conditions:
796 * -When the SPI is correctly disabled
797 * -When a fault is detected in Master mode (MODF bit set to 1)
798 * -In Master mode, when it finishes a data transmission and no new data is ready to be
799 * sent
800 * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
801 * each data transfer.
802 * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
803 * @param SPIx SPI Instance
804 * @retval State of bit (1 or 0).
805 */
LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef * SPIx)806 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef *SPIx)
807 {
808 return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
809 }
810
811 /**
812 * @brief Get frame format error flag
813 * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
814 * @param SPIx SPI Instance
815 * @retval State of bit (1 or 0).
816 */
LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef * SPIx)817 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx)
818 {
819 return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
820 }
821
822 /**
823 * @brief Clear CRC error flag
824 * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
825 * @param SPIx SPI Instance
826 * @retval None
827 */
LL_SPI_ClearFlag_CRCERR(SPI_TypeDef * SPIx)828 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
829 {
830 CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
831 }
832
833 /**
834 * @brief Clear mode fault error flag
835 * @note Clearing this flag is done by a read access to the SPIx_SR
836 * register followed by a write access to the SPIx_CR1 register
837 * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
838 * @param SPIx SPI Instance
839 * @retval None
840 */
LL_SPI_ClearFlag_MODF(SPI_TypeDef * SPIx)841 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
842 {
843 __IO uint32_t tmpreg_sr;
844 tmpreg_sr = SPIx->SR;
845 (void) tmpreg_sr;
846 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
847 }
848
849 /**
850 * @brief Clear overrun error flag
851 * @note Clearing this flag is done by a read access to the SPIx_DR
852 * register followed by a read access to the SPIx_SR register
853 * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
854 * @param SPIx SPI Instance
855 * @retval None
856 */
LL_SPI_ClearFlag_OVR(SPI_TypeDef * SPIx)857 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
858 {
859 __IO uint32_t tmpreg;
860 tmpreg = SPIx->DR;
861 (void) tmpreg;
862 tmpreg = SPIx->SR;
863 (void) tmpreg;
864 }
865
866 /**
867 * @brief Clear frame format error flag
868 * @note Clearing this flag is done by reading SPIx_SR register
869 * @rmtoll SR FRE LL_SPI_ClearFlag_FRE
870 * @param SPIx SPI Instance
871 * @retval None
872 */
LL_SPI_ClearFlag_FRE(SPI_TypeDef * SPIx)873 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
874 {
875 __IO uint32_t tmpreg;
876 tmpreg = SPIx->SR;
877 (void) tmpreg;
878 }
879
880 /**
881 * @}
882 */
883
884 /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
885 * @{
886 */
887
888 /**
889 * @brief Enable error interrupt
890 * @note This bit controls the generation of an interrupt when an error condition
891 * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
892 * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
893 * @param SPIx SPI Instance
894 * @retval None
895 */
LL_SPI_EnableIT_ERR(SPI_TypeDef * SPIx)896 __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
897 {
898 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
899 }
900
901 /**
902 * @brief Enable Rx buffer not empty interrupt
903 * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
904 * @param SPIx SPI Instance
905 * @retval None
906 */
LL_SPI_EnableIT_RXNE(SPI_TypeDef * SPIx)907 __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
908 {
909 SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
910 }
911
912 /**
913 * @brief Enable Tx buffer empty interrupt
914 * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
915 * @param SPIx SPI Instance
916 * @retval None
917 */
LL_SPI_EnableIT_TXE(SPI_TypeDef * SPIx)918 __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
919 {
920 SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
921 }
922
923 /**
924 * @brief Disable error interrupt
925 * @note This bit controls the generation of an interrupt when an error condition
926 * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
927 * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
928 * @param SPIx SPI Instance
929 * @retval None
930 */
LL_SPI_DisableIT_ERR(SPI_TypeDef * SPIx)931 __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
932 {
933 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
934 }
935
936 /**
937 * @brief Disable Rx buffer not empty interrupt
938 * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
939 * @param SPIx SPI Instance
940 * @retval None
941 */
LL_SPI_DisableIT_RXNE(SPI_TypeDef * SPIx)942 __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
943 {
944 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
945 }
946
947 /**
948 * @brief Disable Tx buffer empty interrupt
949 * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
950 * @param SPIx SPI Instance
951 * @retval None
952 */
LL_SPI_DisableIT_TXE(SPI_TypeDef * SPIx)953 __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
954 {
955 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
956 }
957
958 /**
959 * @brief Check if error interrupt is enabled
960 * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
961 * @param SPIx SPI Instance
962 * @retval State of bit (1 or 0).
963 */
LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef * SPIx)964 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef *SPIx)
965 {
966 return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
967 }
968
969 /**
970 * @brief Check if Rx buffer not empty interrupt is enabled
971 * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
972 * @param SPIx SPI Instance
973 * @retval State of bit (1 or 0).
974 */
LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef * SPIx)975 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx)
976 {
977 return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
978 }
979
980 /**
981 * @brief Check if Tx buffer empty interrupt
982 * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
983 * @param SPIx SPI Instance
984 * @retval State of bit (1 or 0).
985 */
LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef * SPIx)986 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef *SPIx)
987 {
988 return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
989 }
990
991 /**
992 * @}
993 */
994
995 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
996 * @{
997 */
998
999 /**
1000 * @brief Enable DMA Rx
1001 * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
1002 * @param SPIx SPI Instance
1003 * @retval None
1004 */
LL_SPI_EnableDMAReq_RX(SPI_TypeDef * SPIx)1005 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
1006 {
1007 SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
1008 }
1009
1010 /**
1011 * @brief Disable DMA Rx
1012 * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
1013 * @param SPIx SPI Instance
1014 * @retval None
1015 */
LL_SPI_DisableDMAReq_RX(SPI_TypeDef * SPIx)1016 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
1017 {
1018 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
1019 }
1020
1021 /**
1022 * @brief Check if DMA Rx is enabled
1023 * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
1024 * @param SPIx SPI Instance
1025 * @retval State of bit (1 or 0).
1026 */
LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef * SPIx)1027 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
1028 {
1029 return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
1030 }
1031
1032 /**
1033 * @brief Enable DMA Tx
1034 * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
1035 * @param SPIx SPI Instance
1036 * @retval None
1037 */
LL_SPI_EnableDMAReq_TX(SPI_TypeDef * SPIx)1038 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
1039 {
1040 SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
1041 }
1042
1043 /**
1044 * @brief Disable DMA Tx
1045 * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
1046 * @param SPIx SPI Instance
1047 * @retval None
1048 */
LL_SPI_DisableDMAReq_TX(SPI_TypeDef * SPIx)1049 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
1050 {
1051 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
1052 }
1053
1054 /**
1055 * @brief Check if DMA Tx is enabled
1056 * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
1057 * @param SPIx SPI Instance
1058 * @retval State of bit (1 or 0).
1059 */
LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef * SPIx)1060 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
1061 {
1062 return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
1063 }
1064
1065 /**
1066 * @brief Get the data register address used for DMA transfer
1067 * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
1068 * @param SPIx SPI Instance
1069 * @retval Address of data register
1070 */
LL_SPI_DMA_GetRegAddr(const SPI_TypeDef * SPIx)1071 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(const SPI_TypeDef *SPIx)
1072 {
1073 return (uint32_t) &(SPIx->DR);
1074 }
1075
1076 /**
1077 * @}
1078 */
1079
1080 /** @defgroup SPI_LL_EF_DATA_Management DATA Management
1081 * @{
1082 */
1083
1084 /**
1085 * @brief Read 8-Bits in the data register
1086 * @rmtoll DR DR LL_SPI_ReceiveData8
1087 * @param SPIx SPI Instance
1088 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
1089 */
LL_SPI_ReceiveData8(SPI_TypeDef * SPIx)1090 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
1091 {
1092 return (*((__IO uint8_t *)&SPIx->DR));
1093 }
1094
1095 /**
1096 * @brief Read 16-Bits in the data register
1097 * @rmtoll DR DR LL_SPI_ReceiveData16
1098 * @param SPIx SPI Instance
1099 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
1100 */
LL_SPI_ReceiveData16(SPI_TypeDef * SPIx)1101 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
1102 {
1103 return (uint16_t)(READ_REG(SPIx->DR));
1104 }
1105
1106 /**
1107 * @brief Write 8-Bits in the data register
1108 * @rmtoll DR DR LL_SPI_TransmitData8
1109 * @param SPIx SPI Instance
1110 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
1111 * @retval None
1112 */
LL_SPI_TransmitData8(SPI_TypeDef * SPIx,uint8_t TxData)1113 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
1114 {
1115 #if defined (__GNUC__)
1116 __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
1117 *spidr = TxData;
1118 #else
1119 *((__IO uint8_t *)&SPIx->DR) = TxData;
1120 #endif /* __GNUC__ */
1121 }
1122
1123 /**
1124 * @brief Write 16-Bits in the data register
1125 * @rmtoll DR DR LL_SPI_TransmitData16
1126 * @param SPIx SPI Instance
1127 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
1128 * @retval None
1129 */
LL_SPI_TransmitData16(SPI_TypeDef * SPIx,uint16_t TxData)1130 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
1131 {
1132 #if defined (__GNUC__)
1133 __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
1134 *spidr = TxData;
1135 #else
1136 SPIx->DR = TxData;
1137 #endif /* __GNUC__ */
1138 }
1139
1140 /**
1141 * @}
1142 */
1143 #if defined(USE_FULL_LL_DRIVER)
1144 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
1145 * @{
1146 */
1147
1148 ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx);
1149 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
1150 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
1151
1152 /**
1153 * @}
1154 */
1155 #endif /* USE_FULL_LL_DRIVER */
1156 /**
1157 * @}
1158 */
1159
1160 /**
1161 * @}
1162 */
1163
1164 /** @defgroup I2S_LL I2S
1165 * @{
1166 */
1167
1168 /* Private variables ---------------------------------------------------------*/
1169 /* Private constants ---------------------------------------------------------*/
1170 /* Private macros ------------------------------------------------------------*/
1171
1172 /* Exported types ------------------------------------------------------------*/
1173 #if defined(USE_FULL_LL_DRIVER)
1174 /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
1175 * @{
1176 */
1177
1178 /**
1179 * @brief I2S Init structure definition
1180 */
1181
1182 typedef struct
1183 {
1184 uint32_t Mode; /*!< Specifies the I2S operating mode.
1185 This parameter can be a value of @ref I2S_LL_EC_MODE
1186
1187 This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
1188
1189 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
1190 This parameter can be a value of @ref I2S_LL_EC_STANDARD
1191
1192 This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
1193
1194
1195 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
1196 This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
1197
1198 This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
1199
1200
1201 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
1202 This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
1203
1204 This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
1205
1206
1207 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
1208 This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
1209
1210 Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
1211 and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
1212
1213
1214 uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
1215 This parameter can be a value of @ref I2S_LL_EC_POLARITY
1216
1217 This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
1218
1219 } LL_I2S_InitTypeDef;
1220
1221 /**
1222 * @}
1223 */
1224 #endif /*USE_FULL_LL_DRIVER*/
1225
1226 /* Exported constants --------------------------------------------------------*/
1227 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
1228 * @{
1229 */
1230
1231 /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
1232 * @brief Flags defines which can be used with LL_I2S_ReadReg function
1233 * @{
1234 */
1235 #define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
1236 #define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
1237 #define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
1238 #define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
1239 #define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
1240 #define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
1241 /**
1242 * @}
1243 */
1244
1245 /** @defgroup SPI_LL_EC_IT IT Defines
1246 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
1247 * @{
1248 */
1249 #define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
1250 #define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
1251 #define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
1252 /**
1253 * @}
1254 */
1255
1256 /** @defgroup I2S_LL_EC_DATA_FORMAT Data format
1257 * @{
1258 */
1259 #define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel length 16bit */
1260 #define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel length 32bit */
1261 #define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel length 32bit */
1262 #define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel length 32bit */
1263 /**
1264 * @}
1265 */
1266
1267 /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
1268 * @{
1269 */
1270 #define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */
1271 #define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
1272 /**
1273 * @}
1274 */
1275
1276 /** @defgroup I2S_LL_EC_STANDARD I2s Standard
1277 * @{
1278 */
1279 #define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */
1280 #define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
1281 #define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
1282 #define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
1283 #define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
1284 /**
1285 * @}
1286 */
1287
1288 /** @defgroup I2S_LL_EC_MODE Operation Mode
1289 * @{
1290 */
1291 #define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
1292 #define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
1293 #define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
1294 #define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
1295 /**
1296 * @}
1297 */
1298
1299 /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
1300 * @{
1301 */
1302 #define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
1303 #define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
1304 /**
1305 * @}
1306 */
1307
1308 #if defined(USE_FULL_LL_DRIVER)
1309
1310 /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
1311 * @{
1312 */
1313 #define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */
1314 #define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
1315 /**
1316 * @}
1317 */
1318
1319 /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
1320 * @{
1321 */
1322
1323 #define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
1324 #define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
1325 #define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
1326 #define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
1327 #define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
1328 #define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
1329 #define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
1330 #define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
1331 #define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
1332 #define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
1333 /**
1334 * @}
1335 */
1336 #endif /* USE_FULL_LL_DRIVER */
1337
1338 /**
1339 * @}
1340 */
1341
1342 /* Exported macro ------------------------------------------------------------*/
1343 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
1344 * @{
1345 */
1346
1347 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
1348 * @{
1349 */
1350
1351 /**
1352 * @brief Write a value in I2S register
1353 * @param __INSTANCE__ I2S Instance
1354 * @param __REG__ Register to be written
1355 * @param __VALUE__ Value to be written in the register
1356 * @retval None
1357 */
1358 #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1359
1360 /**
1361 * @brief Read a value in I2S register
1362 * @param __INSTANCE__ I2S Instance
1363 * @param __REG__ Register to be read
1364 * @retval Register value
1365 */
1366 #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1367 /**
1368 * @}
1369 */
1370
1371 /**
1372 * @}
1373 */
1374
1375
1376 /* Exported functions --------------------------------------------------------*/
1377
1378 /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
1379 * @{
1380 */
1381
1382 /** @defgroup I2S_LL_EF_Configuration Configuration
1383 * @{
1384 */
1385
1386 /**
1387 * @brief Select I2S mode and Enable I2S peripheral
1388 * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
1389 * I2SCFGR I2SE LL_I2S_Enable
1390 * @param SPIx SPI Instance
1391 * @retval None
1392 */
LL_I2S_Enable(SPI_TypeDef * SPIx)1393 __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
1394 {
1395 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
1396 }
1397
1398 /**
1399 * @brief Disable I2S peripheral
1400 * @rmtoll I2SCFGR I2SE LL_I2S_Disable
1401 * @param SPIx SPI Instance
1402 * @retval None
1403 */
LL_I2S_Disable(SPI_TypeDef * SPIx)1404 __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
1405 {
1406 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
1407 }
1408
1409 /**
1410 * @brief Check if I2S peripheral is enabled
1411 * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
1412 * @param SPIx SPI Instance
1413 * @retval State of bit (1 or 0).
1414 */
LL_I2S_IsEnabled(const SPI_TypeDef * SPIx)1415 __STATIC_INLINE uint32_t LL_I2S_IsEnabled(const SPI_TypeDef *SPIx)
1416 {
1417 return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
1418 }
1419
1420 /**
1421 * @brief Set I2S data frame length
1422 * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
1423 * I2SCFGR CHLEN LL_I2S_SetDataFormat
1424 * @param SPIx SPI Instance
1425 * @param DataFormat This parameter can be one of the following values:
1426 * @arg @ref LL_I2S_DATAFORMAT_16B
1427 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
1428 * @arg @ref LL_I2S_DATAFORMAT_24B
1429 * @arg @ref LL_I2S_DATAFORMAT_32B
1430 * @retval None
1431 */
LL_I2S_SetDataFormat(SPI_TypeDef * SPIx,uint32_t DataFormat)1432 __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
1433 {
1434 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
1435 }
1436
1437 /**
1438 * @brief Get I2S data frame length
1439 * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
1440 * I2SCFGR CHLEN LL_I2S_GetDataFormat
1441 * @param SPIx SPI Instance
1442 * @retval Returned value can be one of the following values:
1443 * @arg @ref LL_I2S_DATAFORMAT_16B
1444 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
1445 * @arg @ref LL_I2S_DATAFORMAT_24B
1446 * @arg @ref LL_I2S_DATAFORMAT_32B
1447 */
LL_I2S_GetDataFormat(const SPI_TypeDef * SPIx)1448 __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(const SPI_TypeDef *SPIx)
1449 {
1450 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
1451 }
1452
1453 /**
1454 * @brief Set I2S clock polarity
1455 * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
1456 * @param SPIx SPI Instance
1457 * @param ClockPolarity This parameter can be one of the following values:
1458 * @arg @ref LL_I2S_POLARITY_LOW
1459 * @arg @ref LL_I2S_POLARITY_HIGH
1460 * @retval None
1461 */
LL_I2S_SetClockPolarity(SPI_TypeDef * SPIx,uint32_t ClockPolarity)1462 __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
1463 {
1464 SET_BIT(SPIx->I2SCFGR, ClockPolarity);
1465 }
1466
1467 /**
1468 * @brief Get I2S clock polarity
1469 * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
1470 * @param SPIx SPI Instance
1471 * @retval Returned value can be one of the following values:
1472 * @arg @ref LL_I2S_POLARITY_LOW
1473 * @arg @ref LL_I2S_POLARITY_HIGH
1474 */
LL_I2S_GetClockPolarity(const SPI_TypeDef * SPIx)1475 __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(const SPI_TypeDef *SPIx)
1476 {
1477 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
1478 }
1479
1480 /**
1481 * @brief Set I2S standard protocol
1482 * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
1483 * I2SCFGR PCMSYNC LL_I2S_SetStandard
1484 * @param SPIx SPI Instance
1485 * @param Standard This parameter can be one of the following values:
1486 * @arg @ref LL_I2S_STANDARD_PHILIPS
1487 * @arg @ref LL_I2S_STANDARD_MSB
1488 * @arg @ref LL_I2S_STANDARD_LSB
1489 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
1490 * @arg @ref LL_I2S_STANDARD_PCM_LONG
1491 * @retval None
1492 */
LL_I2S_SetStandard(SPI_TypeDef * SPIx,uint32_t Standard)1493 __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
1494 {
1495 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
1496 }
1497
1498 /**
1499 * @brief Get I2S standard protocol
1500 * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
1501 * I2SCFGR PCMSYNC LL_I2S_GetStandard
1502 * @param SPIx SPI Instance
1503 * @retval Returned value can be one of the following values:
1504 * @arg @ref LL_I2S_STANDARD_PHILIPS
1505 * @arg @ref LL_I2S_STANDARD_MSB
1506 * @arg @ref LL_I2S_STANDARD_LSB
1507 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
1508 * @arg @ref LL_I2S_STANDARD_PCM_LONG
1509 */
LL_I2S_GetStandard(const SPI_TypeDef * SPIx)1510 __STATIC_INLINE uint32_t LL_I2S_GetStandard(const SPI_TypeDef *SPIx)
1511 {
1512 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
1513 }
1514
1515 /**
1516 * @brief Set I2S transfer mode
1517 * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
1518 * @param SPIx SPI Instance
1519 * @param Mode This parameter can be one of the following values:
1520 * @arg @ref LL_I2S_MODE_SLAVE_TX
1521 * @arg @ref LL_I2S_MODE_SLAVE_RX
1522 * @arg @ref LL_I2S_MODE_MASTER_TX
1523 * @arg @ref LL_I2S_MODE_MASTER_RX
1524 * @retval None
1525 */
LL_I2S_SetTransferMode(SPI_TypeDef * SPIx,uint32_t Mode)1526 __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
1527 {
1528 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
1529 }
1530
1531 /**
1532 * @brief Get I2S transfer mode
1533 * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
1534 * @param SPIx SPI Instance
1535 * @retval Returned value can be one of the following values:
1536 * @arg @ref LL_I2S_MODE_SLAVE_TX
1537 * @arg @ref LL_I2S_MODE_SLAVE_RX
1538 * @arg @ref LL_I2S_MODE_MASTER_TX
1539 * @arg @ref LL_I2S_MODE_MASTER_RX
1540 */
LL_I2S_GetTransferMode(const SPI_TypeDef * SPIx)1541 __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(const SPI_TypeDef *SPIx)
1542 {
1543 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
1544 }
1545
1546 /**
1547 * @brief Set I2S linear prescaler
1548 * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
1549 * @param SPIx SPI Instance
1550 * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
1551 * @retval None
1552 */
LL_I2S_SetPrescalerLinear(SPI_TypeDef * SPIx,uint8_t PrescalerLinear)1553 __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
1554 {
1555 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
1556 }
1557
1558 /**
1559 * @brief Get I2S linear prescaler
1560 * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
1561 * @param SPIx SPI Instance
1562 * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
1563 */
LL_I2S_GetPrescalerLinear(const SPI_TypeDef * SPIx)1564 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(const SPI_TypeDef *SPIx)
1565 {
1566 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
1567 }
1568
1569 /**
1570 * @brief Set I2S parity prescaler
1571 * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
1572 * @param SPIx SPI Instance
1573 * @param PrescalerParity This parameter can be one of the following values:
1574 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
1575 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
1576 * @retval None
1577 */
LL_I2S_SetPrescalerParity(SPI_TypeDef * SPIx,uint32_t PrescalerParity)1578 __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
1579 {
1580 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
1581 }
1582
1583 /**
1584 * @brief Get I2S parity prescaler
1585 * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
1586 * @param SPIx SPI Instance
1587 * @retval Returned value can be one of the following values:
1588 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
1589 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
1590 */
LL_I2S_GetPrescalerParity(const SPI_TypeDef * SPIx)1591 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(const SPI_TypeDef *SPIx)
1592 {
1593 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
1594 }
1595
1596 /**
1597 * @brief Enable the master clock output (Pin MCK)
1598 * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
1599 * @param SPIx SPI Instance
1600 * @retval None
1601 */
LL_I2S_EnableMasterClock(SPI_TypeDef * SPIx)1602 __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
1603 {
1604 SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
1605 }
1606
1607 /**
1608 * @brief Disable the master clock output (Pin MCK)
1609 * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
1610 * @param SPIx SPI Instance
1611 * @retval None
1612 */
LL_I2S_DisableMasterClock(SPI_TypeDef * SPIx)1613 __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
1614 {
1615 CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
1616 }
1617
1618 /**
1619 * @brief Check if the master clock output (Pin MCK) is enabled
1620 * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
1621 * @param SPIx SPI Instance
1622 * @retval State of bit (1 or 0).
1623 */
LL_I2S_IsEnabledMasterClock(const SPI_TypeDef * SPIx)1624 __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(const SPI_TypeDef *SPIx)
1625 {
1626 return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
1627 }
1628
1629 /**
1630 * @}
1631 */
1632
1633 /** @defgroup I2S_LL_EF_FLAG FLAG Management
1634 * @{
1635 */
1636
1637 /**
1638 * @brief Check if Rx buffer is not empty
1639 * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
1640 * @param SPIx SPI Instance
1641 * @retval State of bit (1 or 0).
1642 */
LL_I2S_IsActiveFlag_RXNE(const SPI_TypeDef * SPIx)1643 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx)
1644 {
1645 return LL_SPI_IsActiveFlag_RXNE(SPIx);
1646 }
1647
1648 /**
1649 * @brief Check if Tx buffer is empty
1650 * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
1651 * @param SPIx SPI Instance
1652 * @retval State of bit (1 or 0).
1653 */
LL_I2S_IsActiveFlag_TXE(const SPI_TypeDef * SPIx)1654 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(const SPI_TypeDef *SPIx)
1655 {
1656 return LL_SPI_IsActiveFlag_TXE(SPIx);
1657 }
1658
1659 /**
1660 * @brief Get busy flag
1661 * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
1662 * @param SPIx SPI Instance
1663 * @retval State of bit (1 or 0).
1664 */
LL_I2S_IsActiveFlag_BSY(const SPI_TypeDef * SPIx)1665 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(const SPI_TypeDef *SPIx)
1666 {
1667 return LL_SPI_IsActiveFlag_BSY(SPIx);
1668 }
1669
1670 /**
1671 * @brief Get overrun error flag
1672 * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
1673 * @param SPIx SPI Instance
1674 * @retval State of bit (1 or 0).
1675 */
LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef * SPIx)1676 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
1677 {
1678 return LL_SPI_IsActiveFlag_OVR(SPIx);
1679 }
1680
1681 /**
1682 * @brief Get underrun error flag
1683 * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
1684 * @param SPIx SPI Instance
1685 * @retval State of bit (1 or 0).
1686 */
LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef * SPIx)1687 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef *SPIx)
1688 {
1689 return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
1690 }
1691
1692 /**
1693 * @brief Get frame format error flag
1694 * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
1695 * @param SPIx SPI Instance
1696 * @retval State of bit (1 or 0).
1697 */
LL_I2S_IsActiveFlag_FRE(const SPI_TypeDef * SPIx)1698 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(const SPI_TypeDef *SPIx)
1699 {
1700 return LL_SPI_IsActiveFlag_FRE(SPIx);
1701 }
1702
1703 /**
1704 * @brief Get channel side flag.
1705 * @note 0: Channel Left has to be transmitted or has been received\n
1706 * 1: Channel Right has to be transmitted or has been received\n
1707 * It has no significance in PCM mode.
1708 * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
1709 * @param SPIx SPI Instance
1710 * @retval State of bit (1 or 0).
1711 */
LL_I2S_IsActiveFlag_CHSIDE(const SPI_TypeDef * SPIx)1712 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(const SPI_TypeDef *SPIx)
1713 {
1714 return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
1715 }
1716
1717 /**
1718 * @brief Clear overrun error flag
1719 * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
1720 * @param SPIx SPI Instance
1721 * @retval None
1722 */
LL_I2S_ClearFlag_OVR(SPI_TypeDef * SPIx)1723 __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
1724 {
1725 LL_SPI_ClearFlag_OVR(SPIx);
1726 }
1727
1728 /**
1729 * @brief Clear underrun error flag
1730 * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
1731 * @param SPIx SPI Instance
1732 * @retval None
1733 */
LL_I2S_ClearFlag_UDR(SPI_TypeDef * SPIx)1734 __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
1735 {
1736 __IO uint32_t tmpreg;
1737 tmpreg = SPIx->SR;
1738 (void)tmpreg;
1739 }
1740
1741 /**
1742 * @brief Clear frame format error flag
1743 * @rmtoll SR FRE LL_I2S_ClearFlag_FRE
1744 * @param SPIx SPI Instance
1745 * @retval None
1746 */
LL_I2S_ClearFlag_FRE(SPI_TypeDef * SPIx)1747 __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
1748 {
1749 LL_SPI_ClearFlag_FRE(SPIx);
1750 }
1751
1752 /**
1753 * @}
1754 */
1755
1756 /** @defgroup I2S_LL_EF_IT Interrupt Management
1757 * @{
1758 */
1759
1760 /**
1761 * @brief Enable error IT
1762 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
1763 * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
1764 * @param SPIx SPI Instance
1765 * @retval None
1766 */
LL_I2S_EnableIT_ERR(SPI_TypeDef * SPIx)1767 __STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
1768 {
1769 LL_SPI_EnableIT_ERR(SPIx);
1770 }
1771
1772 /**
1773 * @brief Enable Rx buffer not empty IT
1774 * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
1775 * @param SPIx SPI Instance
1776 * @retval None
1777 */
LL_I2S_EnableIT_RXNE(SPI_TypeDef * SPIx)1778 __STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
1779 {
1780 LL_SPI_EnableIT_RXNE(SPIx);
1781 }
1782
1783 /**
1784 * @brief Enable Tx buffer empty IT
1785 * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
1786 * @param SPIx SPI Instance
1787 * @retval None
1788 */
LL_I2S_EnableIT_TXE(SPI_TypeDef * SPIx)1789 __STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
1790 {
1791 LL_SPI_EnableIT_TXE(SPIx);
1792 }
1793
1794 /**
1795 * @brief Disable error IT
1796 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
1797 * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
1798 * @param SPIx SPI Instance
1799 * @retval None
1800 */
LL_I2S_DisableIT_ERR(SPI_TypeDef * SPIx)1801 __STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
1802 {
1803 LL_SPI_DisableIT_ERR(SPIx);
1804 }
1805
1806 /**
1807 * @brief Disable Rx buffer not empty IT
1808 * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
1809 * @param SPIx SPI Instance
1810 * @retval None
1811 */
LL_I2S_DisableIT_RXNE(SPI_TypeDef * SPIx)1812 __STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
1813 {
1814 LL_SPI_DisableIT_RXNE(SPIx);
1815 }
1816
1817 /**
1818 * @brief Disable Tx buffer empty IT
1819 * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
1820 * @param SPIx SPI Instance
1821 * @retval None
1822 */
LL_I2S_DisableIT_TXE(SPI_TypeDef * SPIx)1823 __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
1824 {
1825 LL_SPI_DisableIT_TXE(SPIx);
1826 }
1827
1828 /**
1829 * @brief Check if ERR IT is enabled
1830 * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
1831 * @param SPIx SPI Instance
1832 * @retval State of bit (1 or 0).
1833 */
LL_I2S_IsEnabledIT_ERR(const SPI_TypeDef * SPIx)1834 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(const SPI_TypeDef *SPIx)
1835 {
1836 return LL_SPI_IsEnabledIT_ERR(SPIx);
1837 }
1838
1839 /**
1840 * @brief Check if RXNE IT is enabled
1841 * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
1842 * @param SPIx SPI Instance
1843 * @retval State of bit (1 or 0).
1844 */
LL_I2S_IsEnabledIT_RXNE(const SPI_TypeDef * SPIx)1845 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx)
1846 {
1847 return LL_SPI_IsEnabledIT_RXNE(SPIx);
1848 }
1849
1850 /**
1851 * @brief Check if TXE IT is enabled
1852 * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
1853 * @param SPIx SPI Instance
1854 * @retval State of bit (1 or 0).
1855 */
LL_I2S_IsEnabledIT_TXE(const SPI_TypeDef * SPIx)1856 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(const SPI_TypeDef *SPIx)
1857 {
1858 return LL_SPI_IsEnabledIT_TXE(SPIx);
1859 }
1860
1861 /**
1862 * @}
1863 */
1864
1865 /** @defgroup I2S_LL_EF_DMA DMA Management
1866 * @{
1867 */
1868
1869 /**
1870 * @brief Enable DMA Rx
1871 * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
1872 * @param SPIx SPI Instance
1873 * @retval None
1874 */
LL_I2S_EnableDMAReq_RX(SPI_TypeDef * SPIx)1875 __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
1876 {
1877 LL_SPI_EnableDMAReq_RX(SPIx);
1878 }
1879
1880 /**
1881 * @brief Disable DMA Rx
1882 * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
1883 * @param SPIx SPI Instance
1884 * @retval None
1885 */
LL_I2S_DisableDMAReq_RX(SPI_TypeDef * SPIx)1886 __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
1887 {
1888 LL_SPI_DisableDMAReq_RX(SPIx);
1889 }
1890
1891 /**
1892 * @brief Check if DMA Rx is enabled
1893 * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
1894 * @param SPIx SPI Instance
1895 * @retval State of bit (1 or 0).
1896 */
LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef * SPIx)1897 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
1898 {
1899 return LL_SPI_IsEnabledDMAReq_RX(SPIx);
1900 }
1901
1902 /**
1903 * @brief Enable DMA Tx
1904 * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
1905 * @param SPIx SPI Instance
1906 * @retval None
1907 */
LL_I2S_EnableDMAReq_TX(SPI_TypeDef * SPIx)1908 __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
1909 {
1910 LL_SPI_EnableDMAReq_TX(SPIx);
1911 }
1912
1913 /**
1914 * @brief Disable DMA Tx
1915 * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
1916 * @param SPIx SPI Instance
1917 * @retval None
1918 */
LL_I2S_DisableDMAReq_TX(SPI_TypeDef * SPIx)1919 __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
1920 {
1921 LL_SPI_DisableDMAReq_TX(SPIx);
1922 }
1923
1924 /**
1925 * @brief Check if DMA Tx is enabled
1926 * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
1927 * @param SPIx SPI Instance
1928 * @retval State of bit (1 or 0).
1929 */
LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef * SPIx)1930 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
1931 {
1932 return LL_SPI_IsEnabledDMAReq_TX(SPIx);
1933 }
1934
1935 /**
1936 * @}
1937 */
1938
1939 /** @defgroup I2S_LL_EF_DATA DATA Management
1940 * @{
1941 */
1942
1943 /**
1944 * @brief Read 16-Bits in data register
1945 * @rmtoll DR DR LL_I2S_ReceiveData16
1946 * @param SPIx SPI Instance
1947 * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
1948 */
LL_I2S_ReceiveData16(SPI_TypeDef * SPIx)1949 __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
1950 {
1951 return LL_SPI_ReceiveData16(SPIx);
1952 }
1953
1954 /**
1955 * @brief Write 16-Bits in data register
1956 * @rmtoll DR DR LL_I2S_TransmitData16
1957 * @param SPIx SPI Instance
1958 * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
1959 * @retval None
1960 */
LL_I2S_TransmitData16(SPI_TypeDef * SPIx,uint16_t TxData)1961 __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
1962 {
1963 LL_SPI_TransmitData16(SPIx, TxData);
1964 }
1965
1966 /**
1967 * @}
1968 */
1969
1970 #if defined(USE_FULL_LL_DRIVER)
1971 /** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
1972 * @{
1973 */
1974
1975 ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx);
1976 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
1977 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
1978 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
1979
1980 /**
1981 * @}
1982 */
1983 #endif /* USE_FULL_LL_DRIVER */
1984
1985 /**
1986 * @}
1987 */
1988
1989 /**
1990 * @}
1991 */
1992
1993 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
1994
1995 /**
1996 * @}
1997 */
1998
1999 #ifdef __cplusplus
2000 }
2001 #endif
2002
2003 #endif /* STM32F2xx_LL_SPI_H */
2004
2005
