1 /**
2 ******************************************************************************
3 * @file stm32f2xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F2xx_LL_ADC_H
21 #define __STM32F2xx_LL_ADC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f2xx.h"
29
30 /** @addtogroup STM32F2xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
35
36 /** @defgroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
45 * @{
46 */
47
48 /* Internal mask for ADC group regular sequencer: */
49 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
50 /* - sequencer register offset */
51 /* - sequencer rank bits position into the selected register */
52
53 /* Internal register offset for ADC group regular sequencer configuration */
54 /* (offset placed into a spare area of literal definition) */
55 #define ADC_SQR1_REGOFFSET 0x00000000U
56 #define ADC_SQR2_REGOFFSET 0x00000100U
57 #define ADC_SQR3_REGOFFSET 0x00000200U
58 #define ADC_SQR4_REGOFFSET 0x00000300U
59
60 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
61 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
62
63 /* Definition of ADC group regular sequencer bits information to be inserted */
64 /* into ADC group regular sequencer ranks literals definition. */
65 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
66 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
67 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
68 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
69 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
70 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
71 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
72 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
73 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
74 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
75 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
76 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
77 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
78 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
79 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
80 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
81
82 /* Internal mask for ADC group injected sequencer: */
83 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
84 /* - data register offset */
85 /* - offset register offset */
86 /* - sequencer rank bits position into the selected register */
87
88 /* Internal register offset for ADC group injected data register */
89 /* (offset placed into a spare area of literal definition) */
90 #define ADC_JDR1_REGOFFSET 0x00000000U
91 #define ADC_JDR2_REGOFFSET 0x00000100U
92 #define ADC_JDR3_REGOFFSET 0x00000200U
93 #define ADC_JDR4_REGOFFSET 0x00000300U
94
95 /* Internal register offset for ADC group injected offset configuration */
96 /* (offset placed into a spare area of literal definition) */
97 #define ADC_JOFR1_REGOFFSET 0x00000000U
98 #define ADC_JOFR2_REGOFFSET 0x00001000U
99 #define ADC_JOFR3_REGOFFSET 0x00002000U
100 #define ADC_JOFR4_REGOFFSET 0x00003000U
101
102 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
103 #define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
104 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
105
106 /* Internal mask for ADC group regular trigger: */
107 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
108 /* - regular trigger source */
109 /* - regular trigger edge */
110 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
111
112 /* Mask containing trigger source masks for each of possible */
113 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
114 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
115 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4U * 0U)) | \
116 ((ADC_CR2_EXTSEL) >> (4U * 1U)) | \
117 ((ADC_CR2_EXTSEL) >> (4U * 2U)) | \
118 ((ADC_CR2_EXTSEL) >> (4U * 3U)))
119
120 /* Mask containing trigger edge masks for each of possible */
121 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
122 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
123 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4U * 0U)) | \
124 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \
125 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \
126 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)))
127
128 /* Definition of ADC group regular trigger bits information. */
129 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */
130 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (28U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */
131
132
133
134 /* Internal mask for ADC group injected trigger: */
135 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
136 /* - injected trigger source */
137 /* - injected trigger edge */
138 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
139
140 /* Mask containing trigger source masks for each of possible */
141 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
142 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
143 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4U * 0U)) | \
144 ((ADC_CR2_JEXTSEL) >> (4U * 1U)) | \
145 ((ADC_CR2_JEXTSEL) >> (4U * 2U)) | \
146 ((ADC_CR2_JEXTSEL) >> (4U * 3U)))
147
148 /* Mask containing trigger edge masks for each of possible */
149 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
150 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
151 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4U * 0U)) | \
152 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \
153 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \
154 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)))
155
156 /* Definition of ADC group injected trigger bits information. */
157 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */
158 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */
159
160 /* Internal mask for ADC channel: */
161 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
162 /* - channel identifier defined by number */
163 /* - channel differentiation between external channels (connected to */
164 /* GPIO pins) and internal channels (connected to internal paths) */
165 /* - channel sampling time defined by SMPRx register offset */
166 /* and SMPx bits positions into SMPRx register */
167 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
168 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
169 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
170 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
171 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
172
173 /* Channel differentiation between external and internal channels */
174 #define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */
175 #define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
176 #define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
177 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
178
179 /* Internal register offset for ADC channel sampling time configuration */
180 /* (offset placed into a spare area of literal definition) */
181 #define ADC_SMPR1_REGOFFSET 0x00000000U
182 #define ADC_SMPR2_REGOFFSET 0x02000000U
183 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
184
185 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U
186 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
187
188 /* Definition of channels ID number information to be inserted into */
189 /* channels literals definition. */
190 #define ADC_CHANNEL_0_NUMBER 0x00000000U
191 #define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
192 #define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
193 #define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
194 #define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
195 #define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
196 #define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
197 #define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
198 #define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
199 #define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)
200 #define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 )
201 #define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
202 #define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 )
203 #define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
204 #define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
205 #define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
206 #define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
207 #define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)
208 #define ADC_CHANNEL_18_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1 )
209
210 /* Definition of channels sampling time information to be inserted into */
211 /* channels literals definition. */
212 #define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
213 #define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
214 #define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
215 #define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
216 #define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
217 #define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
218 #define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
219 #define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
220 #define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
221 #define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
222 #define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
223 #define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
224 #define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
225 #define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
226 #define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
227 #define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
228 #define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
229 #define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
230 #define ADC_CHANNEL_18_SMP (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */
231
232 /* Internal mask for ADC analog watchdog: */
233 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
234 /* (concatenation of multiple bits used in different analog watchdogs, */
235 /* (feature of several watchdogs not available on all STM32 families)). */
236 /* - analog watchdog 1: monitored channel defined by number, */
237 /* selection of ADC group (ADC groups regular and-or injected). */
238
239 /* Internal register offset for ADC analog watchdog channel configuration */
240 #define ADC_AWD_CR1_REGOFFSET 0x00000000U
241
242 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
243
244 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
245 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
246
247 /* Internal register offset for ADC analog watchdog threshold configuration */
248 #define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U
249 #define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U
250 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
251
252 /* ADC registers bits positions */
253 #define ADC_CR1_RES_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */
254 #define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
255 /**
256 * @}
257 */
258
259
260 /* Private macros ------------------------------------------------------------*/
261 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
262 * @{
263 */
264
265 /**
266 * @brief Driver macro reserved for internal use: isolate bits with the
267 * selected mask and shift them to the register LSB
268 * (shift mask on register position bit 0).
269 * @param __BITS__ Bits in register 32 bits
270 * @param __MASK__ Mask in register 32 bits
271 * @retval Bits in register 32 bits
272 */
273 #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
274 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
275
276 /**
277 * @brief Driver macro reserved for internal use: set a pointer to
278 * a register from a register basis from which an offset
279 * is applied.
280 * @param __REG__ Register basis from which the offset is applied.
281 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
282 * @retval Pointer to register address
283 */
284 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
285 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
286
287 /**
288 * @}
289 */
290
291
292 /* Exported types ------------------------------------------------------------*/
293 #if defined(USE_FULL_LL_DRIVER)
294 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
295 * @{
296 */
297
298 /**
299 * @brief Structure definition of some features of ADC common parameters
300 * and multimode
301 * (all ADC instances belonging to the same ADC common instance).
302 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
303 * is conditioned to ADC instances state (all ADC instances
304 * sharing the same ADC common instance):
305 * All ADC instances sharing the same ADC common instance must be
306 * disabled.
307 */
308 typedef struct
309 {
310 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
311 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
312
313 This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
314
315 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
316 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
317
318 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
319
320 uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
321 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
322
323 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
324
325 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
326 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
327
328 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
329
330 } LL_ADC_CommonInitTypeDef;
331
332 /**
333 * @brief Structure definition of some features of ADC instance.
334 * @note These parameters have an impact on ADC scope: ADC instance.
335 * Affects both group regular and group injected (availability
336 * of ADC group injected depends on STM32 families).
337 * Refer to corresponding unitary functions into
338 * @ref ADC_LL_EF_Configuration_ADC_Instance .
339 * @note The setting of these parameters by function @ref LL_ADC_Init()
340 * is conditioned to ADC state:
341 * ADC instance must be disabled.
342 * This condition is applied to all ADC features, for efficiency
343 * and compatibility over all STM32 families. However, the different
344 * features can be set under different ADC state conditions
345 * (setting possible with ADC enabled without conversion on going,
346 * ADC enabled with conversion on going, ...)
347 * Each feature can be updated afterwards with a unitary function
348 * and potentially with ADC in a different state than disabled,
349 * refer to description of each function for setting
350 * conditioned to ADC state.
351 */
352 typedef struct
353 {
354 uint32_t Resolution; /*!< Set ADC resolution.
355 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
356
357 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
358
359 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
360 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
361
362 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
363
364 uint32_t SequencersScanMode; /*!< Set ADC scan selection.
365 This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION
366
367 This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */
368
369 } LL_ADC_InitTypeDef;
370
371 /**
372 * @brief Structure definition of some features of ADC group regular.
373 * @note These parameters have an impact on ADC scope: ADC group regular.
374 * Refer to corresponding unitary functions into
375 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
376 * (functions with prefix "REG").
377 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
378 * is conditioned to ADC state:
379 * ADC instance must be disabled.
380 * This condition is applied to all ADC features, for efficiency
381 * and compatibility over all STM32 families. However, the different
382 * features can be set under different ADC state conditions
383 * (setting possible with ADC enabled without conversion on going,
384 * ADC enabled with conversion on going, ...)
385 * Each feature can be updated afterwards with a unitary function
386 * and potentially with ADC in a different state than disabled,
387 * refer to description of each function for setting
388 * conditioned to ADC state.
389 */
390 typedef struct
391 {
392 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
393 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
394 @note On this STM32 series, setting of external trigger edge is performed
395 using function @ref LL_ADC_REG_StartConversionExtTrig().
396
397 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
398
399 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
400 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
401 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
402
403 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
404
405 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
406 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
407 @note This parameter has an effect only if group regular sequencer is enabled
408 (scan length of 2 ranks or more).
409
410 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
411
412 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
413 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
414 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
415
416 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
417
418 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
419 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
420
421 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
422
423 } LL_ADC_REG_InitTypeDef;
424
425 /**
426 * @brief Structure definition of some features of ADC group injected.
427 * @note These parameters have an impact on ADC scope: ADC group injected.
428 * Refer to corresponding unitary functions into
429 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
430 * (functions with prefix "INJ").
431 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
432 * is conditioned to ADC state:
433 * ADC instance must be disabled.
434 * This condition is applied to all ADC features, for efficiency
435 * and compatibility over all STM32 families. However, the different
436 * features can be set under different ADC state conditions
437 * (setting possible with ADC enabled without conversion on going,
438 * ADC enabled with conversion on going, ...)
439 * Each feature can be updated afterwards with a unitary function
440 * and potentially with ADC in a different state than disabled,
441 * refer to description of each function for setting
442 * conditioned to ADC state.
443 */
444 typedef struct
445 {
446 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
447 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
448 @note On this STM32 series, setting of external trigger edge is performed
449 using function @ref LL_ADC_INJ_StartConversionExtTrig().
450
451 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
452
453 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
454 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
455 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
456
457 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
458
459 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
460 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
461 @note This parameter has an effect only if group injected sequencer is enabled
462 (scan length of 2 ranks or more).
463
464 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
465
466 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
467 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
468 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
469
470 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
471
472 } LL_ADC_INJ_InitTypeDef;
473
474 /**
475 * @}
476 */
477 #endif /* USE_FULL_LL_DRIVER */
478
479 /* Exported constants --------------------------------------------------------*/
480 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
481 * @{
482 */
483
484 /** @defgroup ADC_LL_EC_FLAG ADC flags
485 * @brief Flags defines which can be used with LL_ADC_ReadReg function
486 * @{
487 */
488 #define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */
489 #define LL_ADC_FLAG_EOCS ADC_SR_EOC /*!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
490 #define LL_ADC_FLAG_OVR ADC_SR_OVR /*!< ADC flag ADC group regular overrun */
491 #define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */
492 #define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
493 #define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */
494 #define LL_ADC_FLAG_EOCS_MST ADC_CSR_EOC1 /*!< ADC flag ADC multimode master group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
495 #define LL_ADC_FLAG_EOCS_SLV1 ADC_CSR_EOC2 /*!< ADC flag ADC multimode slave 1 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
496 #define LL_ADC_FLAG_EOCS_SLV2 ADC_CSR_EOC3 /*!< ADC flag ADC multimode slave 2 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
497 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR1 /*!< ADC flag ADC multimode master group regular overrun */
498 #define LL_ADC_FLAG_OVR_SLV1 ADC_CSR_OVR2 /*!< ADC flag ADC multimode slave 1 group regular overrun */
499 #define LL_ADC_FLAG_OVR_SLV2 ADC_CSR_OVR3 /*!< ADC flag ADC multimode slave 2 group regular overrun */
500 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1 /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
501 #define LL_ADC_FLAG_JEOS_SLV1 ADC_CSR_JEOC2 /*!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
502 #define LL_ADC_FLAG_JEOS_SLV2 ADC_CSR_JEOC3 /*!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
503 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1 /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
504 #define LL_ADC_FLAG_AWD1_SLV1 ADC_CSR_AWD2 /*!< ADC flag ADC multimode slave 1 analog watchdog 1 */
505 #define LL_ADC_FLAG_AWD1_SLV2 ADC_CSR_AWD3 /*!< ADC flag ADC multimode slave 2 analog watchdog 1 */
506 /**
507 * @}
508 */
509
510 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
511 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
512 * @{
513 */
514 #define LL_ADC_IT_EOCS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
515 #define LL_ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC interruption ADC group regular overrun */
516 #define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
517 #define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */
518 /**
519 * @}
520 */
521
522 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
523 * @{
524 */
525 /* List of ADC registers intended to be used (most commonly) with */
526 /* DMA transfer. */
527 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
528 #define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000U /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
529 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001U /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
530 /**
531 * @}
532 */
533
534 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
535 * @{
536 */
537 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
538 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 ( ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
539 #define LL_ADC_CLOCK_SYNC_PCLK_DIV6 (ADC_CCR_ADCPRE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 6 */
540 #define LL_ADC_CLOCK_SYNC_PCLK_DIV8 (ADC_CCR_ADCPRE_1 | ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 8 */
541 /**
542 * @}
543 */
544
545 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
546 * @{
547 */
548 /* Note: Other measurement paths to internal channels may be available */
549 /* (connections to other peripherals). */
550 /* If they are not listed below, they do not require any specific */
551 /* path enable. In this case, Access to measurement path is done */
552 /* only by selecting the corresponding ADC internal channel. */
553 #define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /*!< ADC measurement paths all disabled */
554 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */
555 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */
556 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATE) /*!< ADC measurement path to internal channel Vbat */
557 /**
558 * @}
559 */
560
561 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
562 * @{
563 */
564 #define LL_ADC_RESOLUTION_12B 0x00000000U /*!< ADC resolution 12 bits */
565 #define LL_ADC_RESOLUTION_10B ( ADC_CR1_RES_0) /*!< ADC resolution 10 bits */
566 #define LL_ADC_RESOLUTION_8B (ADC_CR1_RES_1 ) /*!< ADC resolution 8 bits */
567 #define LL_ADC_RESOLUTION_6B (ADC_CR1_RES_1 | ADC_CR1_RES_0) /*!< ADC resolution 6 bits */
568 /**
569 * @}
570 */
571
572 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
573 * @{
574 */
575 #define LL_ADC_DATA_ALIGN_RIGHT 0x00000000U /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
576 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
577 /**
578 * @}
579 */
580
581 /** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
582 * @{
583 */
584 #define LL_ADC_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/
585 #define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */
586 /**
587 * @}
588 */
589
590 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
591 * @{
592 */
593 #define LL_ADC_GROUP_REGULAR 0x00000001U /*!< ADC group regular (available on all STM32 devices) */
594 #define LL_ADC_GROUP_INJECTED 0x00000002U /*!< ADC group injected (not available on all STM32 devices)*/
595 #define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003U /*!< ADC both groups regular and injected */
596 /**
597 * @}
598 */
599
600 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
601 * @{
602 */
603 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
604 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
605 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
606 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
607 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
608 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
609 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
610 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
611 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
612 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
613 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
614 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
615 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
616 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
617 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
618 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
619 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
620 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
621 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
622 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F2, ADC channel available only on ADC instance: ADC1. */
623 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F2, ADC channel available only on ADC instance: ADC1. */
624 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F2, ADC channel available only on ADC instance: ADC1. */
625 /**
626 * @}
627 */
628
629 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
630 * @{
631 */
632 #define LL_ADC_REG_TRIG_SOFTWARE 0x00000000U /*!< ADC group regular conversion trigger internal: SW start. */
633 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
634 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
635 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
636 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
637 #define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
638 #define LL_ADC_REG_TRIG_EXT_TIM2_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
639 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
640 #define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
641 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
642 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
643 #define LL_ADC_REG_TRIG_EXT_TIM5_CH1 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
644 #define LL_ADC_REG_TRIG_EXT_TIM5_CH2 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
645 #define LL_ADC_REG_TRIG_EXT_TIM5_CH3 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
646 #define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
647 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
648 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
649 /**
650 * @}
651 */
652
653 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
654 * @{
655 */
656 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
657 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CR2_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
658 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CR2_EXTEN_1 | ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
659 /**
660 * @}
661 */
662
663 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
664 * @{
665 */
666 #define LL_ADC_REG_CONV_SINGLE 0x00000000U /*!< ADC conversions are performed in single mode: one conversion per trigger */
667 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
668 /**
669 * @}
670 */
671
672 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
673 * @{
674 */
675 #define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000U /*!< ADC conversions are not transferred by DMA */
676 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
677 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DDS | ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
678 /**
679 * @}
680 */
681
682 /** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions)
683 * @{
684 */
685 #define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV 0x00000000U /*!< ADC flag EOC (end of unitary conversion) selected */
686 #define LL_ADC_REG_FLAG_EOC_UNITARY_CONV (ADC_CR2_EOCS) /*!< ADC flag EOS (end of sequence conversions) selected */
687 /**
688 * @}
689 */
690
691 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
692 * @{
693 */
694 #define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
695 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
696 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
697 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
698 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
699 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
700 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
701 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
702 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
703 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
704 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
705 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
706 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
707 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
708 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
709 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
710 /**
711 * @}
712 */
713
714 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
715 * @{
716 */
717 #define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group regular sequencer discontinuous mode disable */
718 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
719 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
720 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
721 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
722 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
723 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
724 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
725 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
726 /**
727 * @}
728 */
729
730 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
731 * @{
732 */
733 #define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
734 #define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
735 #define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
736 #define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
737 #define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
738 #define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
739 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
740 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
741 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
742 #define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
743 #define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
744 #define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
745 #define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
746 #define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
747 #define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
748 #define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
749 /**
750 * @}
751 */
752
753 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
754 * @{
755 */
756 #define LL_ADC_INJ_TRIG_SOFTWARE 0x00000000U /*!< ADC group injected conversion trigger internal: SW start. */
757 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
758 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
759 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
760 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
761 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH2 (ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
762 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
763 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH1 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
764 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH2 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
765 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_CR2_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
766 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
767 #define LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
768 #define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */
769 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
770 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH3 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
771 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
772 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
773 /**
774 * @}
775 */
776
777 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
778 * @{
779 */
780 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
781 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_CR2_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
782 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_CR2_JEXTEN_1 | ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
783 /**
784 * @}
785 */
786
787 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
788 * @{
789 */
790 #define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000U /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
791 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
792 /**
793 * @}
794 */
795
796
797 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
798 * @{
799 */
800 #define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
801 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
802 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
803 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
804 /**
805 * @}
806 */
807
808 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
809 * @{
810 */
811 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group injected sequencer discontinuous mode disable */
812 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
813 /**
814 * @}
815 */
816
817 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
818 * @{
819 */
820 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U) /*!< ADC group injected sequencer rank 1 */
821 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U) /*!< ADC group injected sequencer rank 2 */
822 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U) /*!< ADC group injected sequencer rank 3 */
823 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U) /*!< ADC group injected sequencer rank 4 */
824 /**
825 * @}
826 */
827
828 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
829 * @{
830 */
831 #define LL_ADC_SAMPLINGTIME_3CYCLES 0x00000000U /*!< Sampling time 3 ADC clock cycles */
832 #define LL_ADC_SAMPLINGTIME_15CYCLES (ADC_SMPR1_SMP10_0) /*!< Sampling time 15 ADC clock cycles */
833 #define LL_ADC_SAMPLINGTIME_28CYCLES (ADC_SMPR1_SMP10_1) /*!< Sampling time 28 ADC clock cycles */
834 #define LL_ADC_SAMPLINGTIME_56CYCLES (ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0) /*!< Sampling time 56 ADC clock cycles */
835 #define LL_ADC_SAMPLINGTIME_84CYCLES (ADC_SMPR1_SMP10_2) /*!< Sampling time 84 ADC clock cycles */
836 #define LL_ADC_SAMPLINGTIME_112CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0) /*!< Sampling time 112 ADC clock cycles */
837 #define LL_ADC_SAMPLINGTIME_144CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1) /*!< Sampling time 144 ADC clock cycles */
838 #define LL_ADC_SAMPLINGTIME_480CYCLES (ADC_SMPR1_SMP10) /*!< Sampling time 480 ADC clock cycles */
839 /**
840 * @}
841 */
842
843 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
844 * @{
845 */
846 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
847 /**
848 * @}
849 */
850
851 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
852 * @{
853 */
854 #define LL_ADC_AWD_DISABLE 0x00000000U /*!< ADC analog watchdog monitoring disabled */
855 #define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
856 #define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
857 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
858 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
859 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
860 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
861 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
862 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
863 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
864 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
865 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
866 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
867 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
868 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
869 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
870 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
871 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
872 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
873 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
874 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
875 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
876 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
877 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
878 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
879 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
880 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
881 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
882 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
883 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
884 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
885 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
886 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
887 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
888 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
889 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
890 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
891 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
892 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
893 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
894 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
895 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
896 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
897 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
898 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
899 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
900 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
901 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
902 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
903 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
904 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
905 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
906 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
907 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
908 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
909 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
910 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
911 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
912 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
913 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
914 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
915 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
916 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
917 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
918 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
919 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
920 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
921 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
922 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
923 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
924 /**
925 * @}
926 */
927
928 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
929 * @{
930 */
931 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */
932 #define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */
933 /**
934 * @}
935 */
936
937 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
938 * @{
939 */
940 #define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */
941 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
942 #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
943 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected simultaneous */
944 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
945 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
946 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
947 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
948 #if defined(ADC3)
949 #define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected simultaneous */
950 #define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected alternate trigger */
951 #define LL_ADC_MULTI_TRIPLE_INJ_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected simultaneous */
952 #define LL_ADC_MULTI_TRIPLE_REG_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: group regular simultaneous */
953 #define LL_ADC_MULTI_TRIPLE_REG_INTERL (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular interleaved */
954 #define LL_ADC_MULTI_TRIPLE_INJ_ALTERN (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
955 #endif
956 /**
957 * @}
958 */
959
960 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
961 * @{
962 */
963 #define LL_ADC_MULTI_REG_DMA_EACH_ADC 0x00000000U /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
964 #define LL_ADC_MULTI_REG_DMA_LIMIT_1 ( ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */
965 #define LL_ADC_MULTI_REG_DMA_LIMIT_2 ( ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words one by one, ADC2&1 then ADC1&3 then ADC3&2. */
966 #define LL_ADC_MULTI_REG_DMA_LIMIT_3 ( ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */
967 #define LL_ADC_MULTI_REG_DMA_UNLMT_1 (ADC_CCR_DDS | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */
968 #define LL_ADC_MULTI_REG_DMA_UNLMT_2 (ADC_CCR_DDS | ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words by pairs, ADC2&1 then ADC1&3 then ADC3&2. */
969 #define LL_ADC_MULTI_REG_DMA_UNLMT_3 (ADC_CCR_DDS | ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */
970 /**
971 * @}
972 */
973
974 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
975 * @{
976 */
977 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 0x00000000U /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles*/
978 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
979 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
980 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
981 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
982 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
983 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
984 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
985 #define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles */
986 #define LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 14 ADC clock cycles */
987 #define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles */
988 #define LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 16 ADC clock cycles */
989 #define LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 17 ADC clock cycles */
990 #define LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 18 ADC clock cycles */
991 #define LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 19 ADC clock cycles */
992 #define LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 20 ADC clock cycles */
993 /**
994 * @}
995 */
996
997 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
998 * @{
999 */
1000 #define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
1001 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
1002 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
1003 /**
1004 * @}
1005 */
1006
1007
1008
1009 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1010 * @note Only ADC IP HW delays are defined in ADC LL driver driver,
1011 * not timeout values.
1012 * For details on delays values, refer to descriptions in source code
1013 * above each literal definition.
1014 * @{
1015 */
1016
1017 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
1018 /* not timeout values. */
1019 /* Timeout values for ADC operations are dependent to device clock */
1020 /* configuration (system clock versus ADC clock), */
1021 /* and therefore must be defined in user application. */
1022 /* Indications for estimation of ADC timeout delays, for this */
1023 /* STM32 series: */
1024 /* - ADC enable time: maximum delay is 2us */
1025 /* (refer to device datasheet, parameter "tSTAB") */
1026 /* - ADC conversion time: duration depending on ADC clock and ADC */
1027 /* configuration. */
1028 /* (refer to device reference manual, section "Timing") */
1029
1030 /* Delay for internal voltage reference stabilization time. */
1031 /* Delay set to maximum value (refer to device datasheet, */
1032 /* parameter "tSTART"). */
1033 /* Unit: us */
1034 #define LL_ADC_DELAY_VREFINT_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */
1035
1036 /* Delay for temperature sensor stabilization time. */
1037 /* Literal set to maximum value (refer to device datasheet, */
1038 /* parameter "tSTART"). */
1039 /* Unit: us */
1040 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */
1041
1042 /**
1043 * @}
1044 */
1045
1046 /**
1047 * @}
1048 */
1049
1050
1051 /* Exported macro ------------------------------------------------------------*/
1052 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
1053 * @{
1054 */
1055
1056 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
1057 * @{
1058 */
1059
1060 /**
1061 * @brief Write a value in ADC register
1062 * @param __INSTANCE__ ADC Instance
1063 * @param __REG__ Register to be written
1064 * @param __VALUE__ Value to be written in the register
1065 * @retval None
1066 */
1067 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1068
1069 /**
1070 * @brief Read a value in ADC register
1071 * @param __INSTANCE__ ADC Instance
1072 * @param __REG__ Register to be read
1073 * @retval Register value
1074 */
1075 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1076 /**
1077 * @}
1078 */
1079
1080 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
1081 * @{
1082 */
1083
1084 /**
1085 * @brief Helper macro to get ADC channel number in decimal format
1086 * from literals LL_ADC_CHANNEL_x.
1087 * @note Example:
1088 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
1089 * will return decimal number "4".
1090 * @note The input can be a value from functions where a channel
1091 * number is returned, either defined with number
1092 * or with bitfield (only one bit must be set).
1093 * @param __CHANNEL__ This parameter can be one of the following values:
1094 * @arg @ref LL_ADC_CHANNEL_0
1095 * @arg @ref LL_ADC_CHANNEL_1
1096 * @arg @ref LL_ADC_CHANNEL_2
1097 * @arg @ref LL_ADC_CHANNEL_3
1098 * @arg @ref LL_ADC_CHANNEL_4
1099 * @arg @ref LL_ADC_CHANNEL_5
1100 * @arg @ref LL_ADC_CHANNEL_6
1101 * @arg @ref LL_ADC_CHANNEL_7
1102 * @arg @ref LL_ADC_CHANNEL_8
1103 * @arg @ref LL_ADC_CHANNEL_9
1104 * @arg @ref LL_ADC_CHANNEL_10
1105 * @arg @ref LL_ADC_CHANNEL_11
1106 * @arg @ref LL_ADC_CHANNEL_12
1107 * @arg @ref LL_ADC_CHANNEL_13
1108 * @arg @ref LL_ADC_CHANNEL_14
1109 * @arg @ref LL_ADC_CHANNEL_15
1110 * @arg @ref LL_ADC_CHANNEL_16
1111 * @arg @ref LL_ADC_CHANNEL_17
1112 * @arg @ref LL_ADC_CHANNEL_18
1113 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1114 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1115 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1116 *
1117 * (1) On STM32F2, parameter available only on ADC instance: ADC1.\n
1118 * @retval Value between Min_Data=0 and Max_Data=18
1119 */
1120 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1121 (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
1122
1123 /**
1124 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1125 * from number in decimal format.
1126 * @note Example:
1127 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1128 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1129 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1130 * @retval Returned value can be one of the following values:
1131 * @arg @ref LL_ADC_CHANNEL_0
1132 * @arg @ref LL_ADC_CHANNEL_1
1133 * @arg @ref LL_ADC_CHANNEL_2
1134 * @arg @ref LL_ADC_CHANNEL_3
1135 * @arg @ref LL_ADC_CHANNEL_4
1136 * @arg @ref LL_ADC_CHANNEL_5
1137 * @arg @ref LL_ADC_CHANNEL_6
1138 * @arg @ref LL_ADC_CHANNEL_7
1139 * @arg @ref LL_ADC_CHANNEL_8
1140 * @arg @ref LL_ADC_CHANNEL_9
1141 * @arg @ref LL_ADC_CHANNEL_10
1142 * @arg @ref LL_ADC_CHANNEL_11
1143 * @arg @ref LL_ADC_CHANNEL_12
1144 * @arg @ref LL_ADC_CHANNEL_13
1145 * @arg @ref LL_ADC_CHANNEL_14
1146 * @arg @ref LL_ADC_CHANNEL_15
1147 * @arg @ref LL_ADC_CHANNEL_16
1148 * @arg @ref LL_ADC_CHANNEL_17
1149 * @arg @ref LL_ADC_CHANNEL_18
1150 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1151 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1152 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1153 *
1154 * (1) On STM32F2, parameter available only on ADC instance: ADC1.\n
1155 * (1) For ADC channel read back from ADC register,
1156 * comparison with internal channel parameter to be done
1157 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1158 */
1159 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1160 (((__DECIMAL_NB__) <= 9U) \
1161 ? ( \
1162 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1163 (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1164 ) \
1165 : \
1166 ( \
1167 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1168 (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1169 ) \
1170 )
1171
1172 /**
1173 * @brief Helper macro to determine whether the selected channel
1174 * corresponds to literal definitions of driver.
1175 * @note The different literal definitions of ADC channels are:
1176 * - ADC internal channel:
1177 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1178 * - ADC external channel (channel connected to a GPIO pin):
1179 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1180 * @note The channel parameter must be a value defined from literal
1181 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1182 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1183 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1184 * must not be a value from functions where a channel number is
1185 * returned from ADC registers,
1186 * because internal and external channels share the same channel
1187 * number in ADC registers. The differentiation is made only with
1188 * parameters definitions of driver.
1189 * @param __CHANNEL__ This parameter can be one of the following values:
1190 * @arg @ref LL_ADC_CHANNEL_0
1191 * @arg @ref LL_ADC_CHANNEL_1
1192 * @arg @ref LL_ADC_CHANNEL_2
1193 * @arg @ref LL_ADC_CHANNEL_3
1194 * @arg @ref LL_ADC_CHANNEL_4
1195 * @arg @ref LL_ADC_CHANNEL_5
1196 * @arg @ref LL_ADC_CHANNEL_6
1197 * @arg @ref LL_ADC_CHANNEL_7
1198 * @arg @ref LL_ADC_CHANNEL_8
1199 * @arg @ref LL_ADC_CHANNEL_9
1200 * @arg @ref LL_ADC_CHANNEL_10
1201 * @arg @ref LL_ADC_CHANNEL_11
1202 * @arg @ref LL_ADC_CHANNEL_12
1203 * @arg @ref LL_ADC_CHANNEL_13
1204 * @arg @ref LL_ADC_CHANNEL_14
1205 * @arg @ref LL_ADC_CHANNEL_15
1206 * @arg @ref LL_ADC_CHANNEL_16
1207 * @arg @ref LL_ADC_CHANNEL_17
1208 * @arg @ref LL_ADC_CHANNEL_18
1209 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1210 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1211 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1212 *
1213 * (1) On STM32F2, parameter available only on ADC instance: ADC1.\n
1214 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
1215 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1216 */
1217 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1218 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
1219
1220 /**
1221 * @brief Helper macro to convert a channel defined from parameter
1222 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1223 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1224 * to its equivalent parameter definition of a ADC external channel
1225 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1226 * @note The channel parameter can be, additionally to a value
1227 * defined from parameter definition of a ADC internal channel
1228 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1229 * a value defined from parameter definition of
1230 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1231 * or a value from functions where a channel number is returned
1232 * from ADC registers.
1233 * @param __CHANNEL__ This parameter can be one of the following values:
1234 * @arg @ref LL_ADC_CHANNEL_0
1235 * @arg @ref LL_ADC_CHANNEL_1
1236 * @arg @ref LL_ADC_CHANNEL_2
1237 * @arg @ref LL_ADC_CHANNEL_3
1238 * @arg @ref LL_ADC_CHANNEL_4
1239 * @arg @ref LL_ADC_CHANNEL_5
1240 * @arg @ref LL_ADC_CHANNEL_6
1241 * @arg @ref LL_ADC_CHANNEL_7
1242 * @arg @ref LL_ADC_CHANNEL_8
1243 * @arg @ref LL_ADC_CHANNEL_9
1244 * @arg @ref LL_ADC_CHANNEL_10
1245 * @arg @ref LL_ADC_CHANNEL_11
1246 * @arg @ref LL_ADC_CHANNEL_12
1247 * @arg @ref LL_ADC_CHANNEL_13
1248 * @arg @ref LL_ADC_CHANNEL_14
1249 * @arg @ref LL_ADC_CHANNEL_15
1250 * @arg @ref LL_ADC_CHANNEL_16
1251 * @arg @ref LL_ADC_CHANNEL_17
1252 * @arg @ref LL_ADC_CHANNEL_18
1253 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1254 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1255 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1256 *
1257 * (1) On STM32F2, parameter available only on ADC instance: ADC1.\n
1258 * @retval Returned value can be one of the following values:
1259 * @arg @ref LL_ADC_CHANNEL_0
1260 * @arg @ref LL_ADC_CHANNEL_1
1261 * @arg @ref LL_ADC_CHANNEL_2
1262 * @arg @ref LL_ADC_CHANNEL_3
1263 * @arg @ref LL_ADC_CHANNEL_4
1264 * @arg @ref LL_ADC_CHANNEL_5
1265 * @arg @ref LL_ADC_CHANNEL_6
1266 * @arg @ref LL_ADC_CHANNEL_7
1267 * @arg @ref LL_ADC_CHANNEL_8
1268 * @arg @ref LL_ADC_CHANNEL_9
1269 * @arg @ref LL_ADC_CHANNEL_10
1270 * @arg @ref LL_ADC_CHANNEL_11
1271 * @arg @ref LL_ADC_CHANNEL_12
1272 * @arg @ref LL_ADC_CHANNEL_13
1273 * @arg @ref LL_ADC_CHANNEL_14
1274 * @arg @ref LL_ADC_CHANNEL_15
1275 * @arg @ref LL_ADC_CHANNEL_16
1276 * @arg @ref LL_ADC_CHANNEL_17
1277 * @arg @ref LL_ADC_CHANNEL_18
1278 */
1279 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1280 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1281
1282 /**
1283 * @brief Helper macro to determine whether the internal channel
1284 * selected is available on the ADC instance selected.
1285 * @note The channel parameter must be a value defined from parameter
1286 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1287 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1288 * must not be a value defined from parameter definition of
1289 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1290 * or a value from functions where a channel number is
1291 * returned from ADC registers,
1292 * because internal and external channels share the same channel
1293 * number in ADC registers. The differentiation is made only with
1294 * parameters definitions of driver.
1295 * @param __ADC_INSTANCE__ ADC instance
1296 * @param __CHANNEL__ This parameter can be one of the following values:
1297 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1298 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1299 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1300 *
1301 * (1) On STM32F2, parameter available only on ADC instance: ADC1.
1302 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1303 * Value "1" if the internal channel selected is available on the ADC instance selected.
1304 */
1305 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1306 ( \
1307 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1308 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1309 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
1310 )
1311 /**
1312 * @brief Helper macro to define ADC analog watchdog parameter:
1313 * define a single channel to monitor with analog watchdog
1314 * from sequencer channel and groups definition.
1315 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1316 * Example:
1317 * LL_ADC_SetAnalogWDMonitChannels(
1318 * ADC1, LL_ADC_AWD1,
1319 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1320 * @param __CHANNEL__ This parameter can be one of the following values:
1321 * @arg @ref LL_ADC_CHANNEL_0
1322 * @arg @ref LL_ADC_CHANNEL_1
1323 * @arg @ref LL_ADC_CHANNEL_2
1324 * @arg @ref LL_ADC_CHANNEL_3
1325 * @arg @ref LL_ADC_CHANNEL_4
1326 * @arg @ref LL_ADC_CHANNEL_5
1327 * @arg @ref LL_ADC_CHANNEL_6
1328 * @arg @ref LL_ADC_CHANNEL_7
1329 * @arg @ref LL_ADC_CHANNEL_8
1330 * @arg @ref LL_ADC_CHANNEL_9
1331 * @arg @ref LL_ADC_CHANNEL_10
1332 * @arg @ref LL_ADC_CHANNEL_11
1333 * @arg @ref LL_ADC_CHANNEL_12
1334 * @arg @ref LL_ADC_CHANNEL_13
1335 * @arg @ref LL_ADC_CHANNEL_14
1336 * @arg @ref LL_ADC_CHANNEL_15
1337 * @arg @ref LL_ADC_CHANNEL_16
1338 * @arg @ref LL_ADC_CHANNEL_17
1339 * @arg @ref LL_ADC_CHANNEL_18
1340 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1341 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1342 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1343 *
1344 * (1) On STM32F2, parameter available only on ADC instance: ADC1.\n
1345 * (1) For ADC channel read back from ADC register,
1346 * comparison with internal channel parameter to be done
1347 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1348 * @param __GROUP__ This parameter can be one of the following values:
1349 * @arg @ref LL_ADC_GROUP_REGULAR
1350 * @arg @ref LL_ADC_GROUP_INJECTED
1351 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
1352 * @retval Returned value can be one of the following values:
1353 * @arg @ref LL_ADC_AWD_DISABLE
1354 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
1355 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
1356 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
1357 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
1358 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
1359 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
1360 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
1361 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
1362 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
1363 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
1364 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
1365 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
1366 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
1367 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
1368 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
1369 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
1370 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
1371 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
1372 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
1373 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
1374 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
1375 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
1376 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
1377 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
1378 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
1379 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
1380 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
1381 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
1382 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
1383 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
1384 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
1385 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
1386 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
1387 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
1388 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
1389 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
1390 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
1391 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
1392 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
1393 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
1394 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
1395 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
1396 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
1397 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
1398 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
1399 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
1400 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
1401 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
1402 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
1403 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
1404 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
1405 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
1406 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
1407 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
1408 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
1409 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
1410 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
1411 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
1412 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
1413 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
1414 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
1415 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
1416 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
1417 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)
1418 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)
1419 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
1420 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
1421 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1)
1422 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
1423 *
1424 * (1) On STM32F2, parameter available only on ADC instance: ADC1.\n
1425 */
1426 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
1427 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
1428 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
1429 : \
1430 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
1431 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \
1432 : \
1433 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
1434 )
1435
1436 /**
1437 * @brief Helper macro to set the value of ADC analog watchdog threshold high
1438 * or low in function of ADC resolution, when ADC resolution is
1439 * different of 12 bits.
1440 * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
1441 * Example, with a ADC resolution of 8 bits, to set the value of
1442 * analog watchdog threshold high (on 8 bits):
1443 * LL_ADC_SetAnalogWDThresholds
1444 * (< ADCx param >,
1445 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
1446 * );
1447 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1448 * @arg @ref LL_ADC_RESOLUTION_12B
1449 * @arg @ref LL_ADC_RESOLUTION_10B
1450 * @arg @ref LL_ADC_RESOLUTION_8B
1451 * @arg @ref LL_ADC_RESOLUTION_6B
1452 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
1453 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1454 */
1455 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
1456 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))
1457
1458 /**
1459 * @brief Helper macro to get the value of ADC analog watchdog threshold high
1460 * or low in function of ADC resolution, when ADC resolution is
1461 * different of 12 bits.
1462 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1463 * Example, with a ADC resolution of 8 bits, to get the value of
1464 * analog watchdog threshold high (on 8 bits):
1465 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
1466 * (LL_ADC_RESOLUTION_8B,
1467 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
1468 * );
1469 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1470 * @arg @ref LL_ADC_RESOLUTION_12B
1471 * @arg @ref LL_ADC_RESOLUTION_10B
1472 * @arg @ref LL_ADC_RESOLUTION_8B
1473 * @arg @ref LL_ADC_RESOLUTION_6B
1474 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
1475 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1476 */
1477 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
1478 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))
1479
1480 /**
1481 * @brief Helper macro to get the ADC multimode conversion data of ADC master
1482 * or ADC slave from raw value with both ADC conversion data concatenated.
1483 * @note This macro is intended to be used when multimode transfer by DMA
1484 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
1485 * In this case the transferred data need to processed with this macro
1486 * to separate the conversion data of ADC master and ADC slave.
1487 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
1488 * @arg @ref LL_ADC_MULTI_MASTER
1489 * @arg @ref LL_ADC_MULTI_SLAVE
1490 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
1491 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1492 */
1493 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
1494 (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
1495
1496 /**
1497 * @brief Helper macro to select the ADC common instance
1498 * to which is belonging the selected ADC instance.
1499 * @note ADC common register instance can be used for:
1500 * - Set parameters common to several ADC instances
1501 * - Multimode (for devices with several ADC instances)
1502 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1503 * @param __ADCx__ ADC instance
1504 * @retval ADC common register instance
1505 */
1506 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
1507 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1508 (ADC123_COMMON)
1509 #elif defined(ADC1) && defined(ADC2)
1510 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1511 (ADC12_COMMON)
1512 #else
1513 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1514 (ADC1_COMMON)
1515 #endif
1516
1517 /**
1518 * @brief Helper macro to check if all ADC instances sharing the same
1519 * ADC common instance are disabled.
1520 * @note This check is required by functions with setting conditioned to
1521 * ADC state:
1522 * All ADC instances of the ADC common group must be disabled.
1523 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1524 * @note On devices with only 1 ADC common instance, parameter of this macro
1525 * is useless and can be ignored (parameter kept for compatibility
1526 * with devices featuring several ADC common instances).
1527 * @param __ADCXY_COMMON__ ADC common instance
1528 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1529 * @retval Value "0" if all ADC instances sharing the same ADC common instance
1530 * are disabled.
1531 * Value "1" if at least one ADC instance sharing the same ADC common instance
1532 * is enabled.
1533 */
1534 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
1535 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1536 (LL_ADC_IsEnabled(ADC1) | \
1537 LL_ADC_IsEnabled(ADC2) | \
1538 LL_ADC_IsEnabled(ADC3) )
1539 #elif defined(ADC1) && defined(ADC2)
1540 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1541 (LL_ADC_IsEnabled(ADC1) | \
1542 LL_ADC_IsEnabled(ADC2) )
1543 #else
1544 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1545 (LL_ADC_IsEnabled(ADC1))
1546 #endif
1547
1548 /**
1549 * @brief Helper macro to define the ADC conversion data full-scale digital
1550 * value corresponding to the selected ADC resolution.
1551 * @note ADC conversion data full-scale corresponds to voltage range
1552 * determined by analog voltage references Vref+ and Vref-
1553 * (refer to reference manual).
1554 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1555 * @arg @ref LL_ADC_RESOLUTION_12B
1556 * @arg @ref LL_ADC_RESOLUTION_10B
1557 * @arg @ref LL_ADC_RESOLUTION_8B
1558 * @arg @ref LL_ADC_RESOLUTION_6B
1559 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1560 */
1561 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1562 (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)))
1563
1564 /**
1565 * @brief Helper macro to convert the ADC conversion data from
1566 * a resolution to another resolution.
1567 * @param __DATA__ ADC conversion data to be converted
1568 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
1569 * This parameter can be one of the following values:
1570 * @arg @ref LL_ADC_RESOLUTION_12B
1571 * @arg @ref LL_ADC_RESOLUTION_10B
1572 * @arg @ref LL_ADC_RESOLUTION_8B
1573 * @arg @ref LL_ADC_RESOLUTION_6B
1574 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
1575 * This parameter can be one of the following values:
1576 * @arg @ref LL_ADC_RESOLUTION_12B
1577 * @arg @ref LL_ADC_RESOLUTION_10B
1578 * @arg @ref LL_ADC_RESOLUTION_8B
1579 * @arg @ref LL_ADC_RESOLUTION_6B
1580 * @retval ADC conversion data to the requested resolution
1581 */
1582 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \
1583 (((__DATA__) \
1584 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U))) \
1585 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)) \
1586 )
1587
1588 /**
1589 * @brief Helper macro to calculate the voltage (unit: mVolt)
1590 * corresponding to a ADC conversion data (unit: digital value).
1591 * @note Analog reference voltage (Vref+) must be known from
1592 * user board environment or can be calculated using ADC measurement.
1593 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
1594 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
1595 * (unit: digital value).
1596 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1597 * @arg @ref LL_ADC_RESOLUTION_12B
1598 * @arg @ref LL_ADC_RESOLUTION_10B
1599 * @arg @ref LL_ADC_RESOLUTION_8B
1600 * @arg @ref LL_ADC_RESOLUTION_6B
1601 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1602 */
1603 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
1604 __ADC_DATA__,\
1605 __ADC_RESOLUTION__) \
1606 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
1607 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1608 )
1609
1610
1611 /**
1612 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1613 * from ADC conversion data of internal temperature sensor.
1614 * @note Computation is using temperature sensor typical values
1615 * (refer to device datasheet).
1616 * @note Calculation formula:
1617 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
1618 * / Avg_Slope + CALx_TEMP
1619 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1620 * (unit: digital value)
1621 * Avg_Slope = temperature sensor slope
1622 * (unit: uV/Degree Celsius)
1623 * TS_TYP_CALx_VOLT = temperature sensor digital value at
1624 * temperature CALx_TEMP (unit: mV)
1625 * Caution: Calculation relevancy under reserve the temperature sensor
1626 * of the current device has characteristics in line with
1627 * datasheet typical values.
1628 * If temperature sensor calibration values are available on
1629 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
1630 * temperature calculation will be more accurate using
1631 * helper macro __LL_ADC_CALC_TEMPERATURE().
1632 * @note As calculation input, the analog reference voltage (Vref+) must be
1633 * defined as it impacts the ADC LSB equivalent voltage.
1634 * @note Analog reference voltage (Vref+) must be known from
1635 * user board environment or can be calculated using ADC measurement.
1636 * @note ADC measurement data must correspond to a resolution of 12bits
1637 * (full scale digital value 4095). If not the case, the data must be
1638 * preliminarily rescaled to an equivalent resolution of 12 bits.
1639 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
1640 * On STM32F2, refer to device datasheet parameter "Avg_Slope".
1641 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
1642 * On STM32F2, refer to device datasheet parameter "V25".
1643 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
1644 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
1645 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
1646 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
1647 * This parameter can be one of the following values:
1648 * @arg @ref LL_ADC_RESOLUTION_12B
1649 * @arg @ref LL_ADC_RESOLUTION_10B
1650 * @arg @ref LL_ADC_RESOLUTION_8B
1651 * @arg @ref LL_ADC_RESOLUTION_6B
1652 * @retval Temperature (unit: degree Celsius)
1653 */
1654 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
1655 __TEMPSENSOR_TYP_CALX_V__,\
1656 __TEMPSENSOR_CALX_TEMP__,\
1657 __VREFANALOG_VOLTAGE__,\
1658 __TEMPSENSOR_ADC_DATA__,\
1659 __ADC_RESOLUTION__) \
1660 (((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
1661 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
1662 * 1000UL) \
1663 - \
1664 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
1665 * 1000UL) \
1666 ) \
1667 ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
1668 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
1669 )
1670
1671 /**
1672 * @}
1673 */
1674
1675 /**
1676 * @}
1677 */
1678
1679
1680 /* Exported functions --------------------------------------------------------*/
1681 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
1682 * @{
1683 */
1684
1685 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
1686 * @{
1687 */
1688 /* Note: LL ADC functions to set DMA transfer are located into sections of */
1689 /* configuration of ADC instance, groups and multimode (if available): */
1690 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
1691
1692 /**
1693 * @brief Function to help to configure DMA transfer from ADC: retrieve the
1694 * ADC register address from ADC instance and a list of ADC registers
1695 * intended to be used (most commonly) with DMA transfer.
1696 * @note These ADC registers are data registers:
1697 * when ADC conversion data is available in ADC data registers,
1698 * ADC generates a DMA transfer request.
1699 * @note This macro is intended to be used with LL DMA driver, refer to
1700 * function "LL_DMA_ConfigAddresses()".
1701 * Example:
1702 * LL_DMA_ConfigAddresses(DMA1,
1703 * LL_DMA_CHANNEL_1,
1704 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
1705 * (uint32_t)&< array or variable >,
1706 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
1707 * @note For devices with several ADC: in multimode, some devices
1708 * use a different data register outside of ADC instance scope
1709 * (common data register). This macro manages this register difference,
1710 * only ADC instance has to be set as parameter.
1711 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
1712 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
1713 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
1714 * @param ADCx ADC instance
1715 * @param Register This parameter can be one of the following values:
1716 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
1717 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
1718 *
1719 * (1) Available on devices with several ADC instances.
1720 * @retval ADC register address
1721 */
LL_ADC_DMA_GetRegAddr(ADC_TypeDef * ADCx,uint32_t Register)1722 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
1723 {
1724 register uint32_t data_reg_addr = 0U;
1725
1726 if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
1727 {
1728 /* Retrieve address of register DR */
1729 data_reg_addr = (uint32_t)&(ADCx->DR);
1730 }
1731 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
1732 {
1733 /* Retrieve address of register CDR */
1734 data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
1735 }
1736
1737 return data_reg_addr;
1738 }
1739
1740 /**
1741 * @}
1742 */
1743
1744 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
1745 * @{
1746 */
1747
1748 /**
1749 * @brief Set parameter common to several ADC: Clock source and prescaler.
1750 * @rmtoll CCR ADCPRE LL_ADC_SetCommonClock
1751 * @param ADCxy_COMMON ADC common instance
1752 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1753 * @param CommonClock This parameter can be one of the following values:
1754 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
1755 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
1756 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6
1757 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8
1758 * @retval None
1759 */
LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)1760 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
1761 {
1762 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE, CommonClock);
1763 }
1764
1765 /**
1766 * @brief Get parameter common to several ADC: Clock source and prescaler.
1767 * @rmtoll CCR ADCPRE LL_ADC_GetCommonClock
1768 * @param ADCxy_COMMON ADC common instance
1769 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1770 * @retval Returned value can be one of the following values:
1771 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
1772 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
1773 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6
1774 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8
1775 */
LL_ADC_GetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON)1776 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
1777 {
1778 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE));
1779 }
1780
1781 /**
1782 * @brief Set parameter common to several ADC: measurement path to internal
1783 * channels (VrefInt, temperature sensor, ...).
1784 * @note One or several values can be selected.
1785 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1786 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1787 * @note Stabilization time of measurement path to internal channel:
1788 * After enabling internal paths, before starting ADC conversion,
1789 * a delay is required for internal voltage reference and
1790 * temperature sensor stabilization time.
1791 * Refer to device datasheet.
1792 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
1793 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
1794 * @note ADC internal channel sampling time constraint:
1795 * For ADC conversion of internal channels,
1796 * a sampling time minimum value is required.
1797 * Refer to device datasheet.
1798 * @rmtoll CCR TSVREFE LL_ADC_SetCommonPathInternalCh\n
1799 * CCR VBATE LL_ADC_SetCommonPathInternalCh
1800 * @param ADCxy_COMMON ADC common instance
1801 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1802 * @param PathInternal This parameter can be a combination of the following values:
1803 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1804 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1805 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1806 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
1807 * @retval None
1808 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)1809 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
1810 {
1811 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE, PathInternal);
1812 }
1813
1814 /**
1815 * @brief Get parameter common to several ADC: measurement path to internal
1816 * channels (VrefInt, temperature sensor, ...).
1817 * @note One or several values can be selected.
1818 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1819 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1820 * @rmtoll CCR TSVREFE LL_ADC_GetCommonPathInternalCh\n
1821 * CCR VBATE LL_ADC_GetCommonPathInternalCh
1822 * @param ADCxy_COMMON ADC common instance
1823 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1824 * @retval Returned value can be a combination of the following values:
1825 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1826 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1827 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1828 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
1829 */
LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON)1830 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
1831 {
1832 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE));
1833 }
1834
1835 /**
1836 * @}
1837 */
1838
1839 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
1840 * @{
1841 */
1842
1843 /**
1844 * @brief Set ADC resolution.
1845 * Refer to reference manual for alignments formats
1846 * dependencies to ADC resolutions.
1847 * @rmtoll CR1 RES LL_ADC_SetResolution
1848 * @param ADCx ADC instance
1849 * @param Resolution This parameter can be one of the following values:
1850 * @arg @ref LL_ADC_RESOLUTION_12B
1851 * @arg @ref LL_ADC_RESOLUTION_10B
1852 * @arg @ref LL_ADC_RESOLUTION_8B
1853 * @arg @ref LL_ADC_RESOLUTION_6B
1854 * @retval None
1855 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)1856 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
1857 {
1858 MODIFY_REG(ADCx->CR1, ADC_CR1_RES, Resolution);
1859 }
1860
1861 /**
1862 * @brief Get ADC resolution.
1863 * Refer to reference manual for alignments formats
1864 * dependencies to ADC resolutions.
1865 * @rmtoll CR1 RES LL_ADC_GetResolution
1866 * @param ADCx ADC instance
1867 * @retval Returned value can be one of the following values:
1868 * @arg @ref LL_ADC_RESOLUTION_12B
1869 * @arg @ref LL_ADC_RESOLUTION_10B
1870 * @arg @ref LL_ADC_RESOLUTION_8B
1871 * @arg @ref LL_ADC_RESOLUTION_6B
1872 */
LL_ADC_GetResolution(ADC_TypeDef * ADCx)1873 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
1874 {
1875 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_RES));
1876 }
1877
1878 /**
1879 * @brief Set ADC conversion data alignment.
1880 * @note Refer to reference manual for alignments formats
1881 * dependencies to ADC resolutions.
1882 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
1883 * @param ADCx ADC instance
1884 * @param DataAlignment This parameter can be one of the following values:
1885 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
1886 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
1887 * @retval None
1888 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)1889 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
1890 {
1891 MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);
1892 }
1893
1894 /**
1895 * @brief Get ADC conversion data alignment.
1896 * @note Refer to reference manual for alignments formats
1897 * dependencies to ADC resolutions.
1898 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
1899 * @param ADCx ADC instance
1900 * @retval Returned value can be one of the following values:
1901 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
1902 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
1903 */
LL_ADC_GetDataAlignment(ADC_TypeDef * ADCx)1904 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
1905 {
1906 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));
1907 }
1908
1909 /**
1910 * @brief Set ADC sequencers scan mode, for all ADC groups
1911 * (group regular, group injected).
1912 * @note According to sequencers scan mode :
1913 * - If disabled: ADC conversion is performed in unitary conversion
1914 * mode (one channel converted, that defined in rank 1).
1915 * Configuration of sequencers of all ADC groups
1916 * (sequencer scan length, ...) is discarded: equivalent to
1917 * scan length of 1 rank.
1918 * - If enabled: ADC conversions are performed in sequence conversions
1919 * mode, according to configuration of sequencers of
1920 * each ADC group (sequencer scan length, ...).
1921 * Refer to function @ref LL_ADC_REG_SetSequencerLength()
1922 * and to function @ref LL_ADC_INJ_SetSequencerLength().
1923 * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode
1924 * @param ADCx ADC instance
1925 * @param ScanMode This parameter can be one of the following values:
1926 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
1927 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
1928 * @retval None
1929 */
LL_ADC_SetSequencersScanMode(ADC_TypeDef * ADCx,uint32_t ScanMode)1930 __STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)
1931 {
1932 MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);
1933 }
1934
1935 /**
1936 * @brief Get ADC sequencers scan mode, for all ADC groups
1937 * (group regular, group injected).
1938 * @note According to sequencers scan mode :
1939 * - If disabled: ADC conversion is performed in unitary conversion
1940 * mode (one channel converted, that defined in rank 1).
1941 * Configuration of sequencers of all ADC groups
1942 * (sequencer scan length, ...) is discarded: equivalent to
1943 * scan length of 1 rank.
1944 * - If enabled: ADC conversions are performed in sequence conversions
1945 * mode, according to configuration of sequencers of
1946 * each ADC group (sequencer scan length, ...).
1947 * Refer to function @ref LL_ADC_REG_SetSequencerLength()
1948 * and to function @ref LL_ADC_INJ_SetSequencerLength().
1949 * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode
1950 * @param ADCx ADC instance
1951 * @retval Returned value can be one of the following values:
1952 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
1953 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
1954 */
LL_ADC_GetSequencersScanMode(ADC_TypeDef * ADCx)1955 __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
1956 {
1957 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));
1958 }
1959
1960 /**
1961 * @}
1962 */
1963
1964 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
1965 * @{
1966 */
1967
1968 /**
1969 * @brief Set ADC group regular conversion trigger source:
1970 * internal (SW start) or from external IP (timer event,
1971 * external interrupt line).
1972 * @note On this STM32 series, setting of external trigger edge is performed
1973 * using function @ref LL_ADC_REG_StartConversionExtTrig().
1974 * @note Availability of parameters of trigger sources from timer
1975 * depends on timers availability on the selected device.
1976 * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource\n
1977 * CR2 EXTEN LL_ADC_REG_SetTriggerSource
1978 * @param ADCx ADC instance
1979 * @param TriggerSource This parameter can be one of the following values:
1980 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
1981 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
1982 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
1983 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
1984 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
1985 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3
1986 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4
1987 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
1988 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1
1989 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
1990 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
1991 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1
1992 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH2
1993 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3
1994 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1
1995 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
1996 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
1997 * @retval None
1998 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)1999 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2000 {
2001 /* Note: On this STM32 series, ADC group regular external trigger edge */
2002 /* is used to perform a ADC conversion start. */
2003 /* This function does not set external trigger edge. */
2004 /* This feature is set using function */
2005 /* @ref LL_ADC_REG_StartConversionExtTrig(). */
2006 MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));
2007 }
2008
2009 /**
2010 * @brief Get ADC group regular conversion trigger source:
2011 * internal (SW start) or from external IP (timer event,
2012 * external interrupt line).
2013 * @note To determine whether group regular trigger source is
2014 * internal (SW start) or external, without detail
2015 * of which peripheral is selected as external trigger,
2016 * (equivalent to
2017 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
2018 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
2019 * @note Availability of parameters of trigger sources from timer
2020 * depends on timers availability on the selected device.
2021 * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource\n
2022 * CR2 EXTEN LL_ADC_REG_GetTriggerSource
2023 * @param ADCx ADC instance
2024 * @retval Returned value can be one of the following values:
2025 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2026 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
2027 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
2028 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
2029 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
2030 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3
2031 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4
2032 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
2033 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1
2034 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
2035 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
2036 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1
2037 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH2
2038 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3
2039 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1
2040 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
2041 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2042 */
LL_ADC_REG_GetTriggerSource(ADC_TypeDef * ADCx)2043 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
2044 {
2045 register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN);
2046
2047 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
2048 /* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}. */
2049 register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
2050
2051 /* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL */
2052 /* to match with triggers literals definition. */
2053 return ((TriggerSource
2054 & (ADC_REG_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_EXTSEL)
2055 | ((ADC_REG_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_EXTEN)
2056 );
2057 }
2058
2059 /**
2060 * @brief Get ADC group regular conversion trigger source internal (SW start)
2061 or external.
2062 * @note In case of group regular trigger source set to external trigger,
2063 * to determine which peripheral is selected as external trigger,
2064 * use function @ref LL_ADC_REG_GetTriggerSource().
2065 * @rmtoll CR2 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
2066 * @param ADCx ADC instance
2067 * @retval Value "0" if trigger source external trigger
2068 * Value "1" if trigger source SW start.
2069 */
LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)2070 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
2071 {
2072 return (READ_BIT(ADCx->CR2, ADC_CR2_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN));
2073 }
2074
2075 /**
2076 * @brief Get ADC group regular conversion trigger polarity.
2077 * @note Applicable only for trigger source set to external trigger.
2078 * @note On this STM32 series, setting of external trigger edge is performed
2079 * using function @ref LL_ADC_REG_StartConversionExtTrig().
2080 * @rmtoll CR2 EXTEN LL_ADC_REG_GetTriggerEdge
2081 * @param ADCx ADC instance
2082 * @retval Returned value can be one of the following values:
2083 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
2084 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
2085 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
2086 */
LL_ADC_REG_GetTriggerEdge(ADC_TypeDef * ADCx)2087 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
2088 {
2089 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTEN));
2090 }
2091
2092
2093 /**
2094 * @brief Set ADC group regular sequencer length and scan direction.
2095 * @note Description of ADC group regular sequencer features:
2096 * - For devices with sequencer fully configurable
2097 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2098 * sequencer length and each rank affectation to a channel
2099 * are configurable.
2100 * This function performs configuration of:
2101 * - Sequence length: Number of ranks in the scan sequence.
2102 * - Sequence direction: Unless specified in parameters, sequencer
2103 * scan direction is forward (from rank 1 to rank n).
2104 * Sequencer ranks are selected using
2105 * function "LL_ADC_REG_SetSequencerRanks()".
2106 * - For devices with sequencer not fully configurable
2107 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2108 * sequencer length and each rank affectation to a channel
2109 * are defined by channel number.
2110 * This function performs configuration of:
2111 * - Sequence length: Number of ranks in the scan sequence is
2112 * defined by number of channels set in the sequence,
2113 * rank of each channel is fixed by channel HW number.
2114 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2115 * - Sequence direction: Unless specified in parameters, sequencer
2116 * scan direction is forward (from lowest channel number to
2117 * highest channel number).
2118 * Sequencer ranks are selected using
2119 * function "LL_ADC_REG_SetSequencerChannels()".
2120 * @note On this STM32 series, group regular sequencer configuration
2121 * is conditioned to ADC instance sequencer mode.
2122 * If ADC instance sequencer mode is disabled, sequencers of
2123 * all groups (group regular, group injected) can be configured
2124 * but their execution is disabled (limited to rank 1).
2125 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2126 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2127 * ADC conversion on only 1 channel.
2128 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
2129 * @param ADCx ADC instance
2130 * @param SequencerNbRanks This parameter can be one of the following values:
2131 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2132 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2133 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2134 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2135 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2136 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2137 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2138 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2139 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
2140 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
2141 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
2142 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
2143 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
2144 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
2145 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
2146 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
2147 * @retval None
2148 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)2149 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
2150 {
2151 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
2152 }
2153
2154 /**
2155 * @brief Get ADC group regular sequencer length and scan direction.
2156 * @note Description of ADC group regular sequencer features:
2157 * - For devices with sequencer fully configurable
2158 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2159 * sequencer length and each rank affectation to a channel
2160 * are configurable.
2161 * This function retrieves:
2162 * - Sequence length: Number of ranks in the scan sequence.
2163 * - Sequence direction: Unless specified in parameters, sequencer
2164 * scan direction is forward (from rank 1 to rank n).
2165 * Sequencer ranks are selected using
2166 * function "LL_ADC_REG_SetSequencerRanks()".
2167 * - For devices with sequencer not fully configurable
2168 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2169 * sequencer length and each rank affectation to a channel
2170 * are defined by channel number.
2171 * This function retrieves:
2172 * - Sequence length: Number of ranks in the scan sequence is
2173 * defined by number of channels set in the sequence,
2174 * rank of each channel is fixed by channel HW number.
2175 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2176 * - Sequence direction: Unless specified in parameters, sequencer
2177 * scan direction is forward (from lowest channel number to
2178 * highest channel number).
2179 * Sequencer ranks are selected using
2180 * function "LL_ADC_REG_SetSequencerChannels()".
2181 * @note On this STM32 series, group regular sequencer configuration
2182 * is conditioned to ADC instance sequencer mode.
2183 * If ADC instance sequencer mode is disabled, sequencers of
2184 * all groups (group regular, group injected) can be configured
2185 * but their execution is disabled (limited to rank 1).
2186 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2187 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2188 * ADC conversion on only 1 channel.
2189 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
2190 * @param ADCx ADC instance
2191 * @retval Returned value can be one of the following values:
2192 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2193 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2194 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2195 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2196 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2197 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2198 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2199 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2200 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
2201 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
2202 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
2203 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
2204 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
2205 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
2206 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
2207 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
2208 */
LL_ADC_REG_GetSequencerLength(ADC_TypeDef * ADCx)2209 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
2210 {
2211 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
2212 }
2213
2214 /**
2215 * @brief Set ADC group regular sequencer discontinuous mode:
2216 * sequence subdivided and scan conversions interrupted every selected
2217 * number of ranks.
2218 * @note It is not possible to enable both ADC group regular
2219 * continuous mode and sequencer discontinuous mode.
2220 * @note It is not possible to enable both ADC auto-injected mode
2221 * and ADC group regular sequencer discontinuous mode.
2222 * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
2223 * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont
2224 * @param ADCx ADC instance
2225 * @param SeqDiscont This parameter can be one of the following values:
2226 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2227 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2228 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
2229 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
2230 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
2231 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
2232 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
2233 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
2234 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
2235 * @retval None
2236 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)2237 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2238 {
2239 MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont);
2240 }
2241
2242 /**
2243 * @brief Get ADC group regular sequencer discontinuous mode:
2244 * sequence subdivided and scan conversions interrupted every selected
2245 * number of ranks.
2246 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
2247 * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont
2248 * @param ADCx ADC instance
2249 * @retval Returned value can be one of the following values:
2250 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2251 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2252 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
2253 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
2254 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
2255 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
2256 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
2257 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
2258 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
2259 */
LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef * ADCx)2260 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
2261 {
2262 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM));
2263 }
2264
2265 /**
2266 * @brief Set ADC group regular sequence: channel on the selected
2267 * scan sequence rank.
2268 * @note This function performs configuration of:
2269 * - Channels ordering into each rank of scan sequence:
2270 * whatever channel can be placed into whatever rank.
2271 * @note On this STM32 series, ADC group regular sequencer is
2272 * fully configurable: sequencer length and each rank
2273 * affectation to a channel are configurable.
2274 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
2275 * @note Depending on devices and packages, some channels may not be available.
2276 * Refer to device datasheet for channels availability.
2277 * @note On this STM32 series, to measure internal channels (VrefInt,
2278 * TempSensor, ...), measurement paths to internal channels must be
2279 * enabled separately.
2280 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2281 * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n
2282 * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n
2283 * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n
2284 * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n
2285 * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n
2286 * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n
2287 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
2288 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
2289 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
2290 * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n
2291 * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n
2292 * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n
2293 * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n
2294 * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n
2295 * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n
2296 * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks
2297 * @param ADCx ADC instance
2298 * @param Rank This parameter can be one of the following values:
2299 * @arg @ref LL_ADC_REG_RANK_1
2300 * @arg @ref LL_ADC_REG_RANK_2
2301 * @arg @ref LL_ADC_REG_RANK_3
2302 * @arg @ref LL_ADC_REG_RANK_4
2303 * @arg @ref LL_ADC_REG_RANK_5
2304 * @arg @ref LL_ADC_REG_RANK_6
2305 * @arg @ref LL_ADC_REG_RANK_7
2306 * @arg @ref LL_ADC_REG_RANK_8
2307 * @arg @ref LL_ADC_REG_RANK_9
2308 * @arg @ref LL_ADC_REG_RANK_10
2309 * @arg @ref LL_ADC_REG_RANK_11
2310 * @arg @ref LL_ADC_REG_RANK_12
2311 * @arg @ref LL_ADC_REG_RANK_13
2312 * @arg @ref LL_ADC_REG_RANK_14
2313 * @arg @ref LL_ADC_REG_RANK_15
2314 * @arg @ref LL_ADC_REG_RANK_16
2315 * @param Channel This parameter can be one of the following values:
2316 * @arg @ref LL_ADC_CHANNEL_0
2317 * @arg @ref LL_ADC_CHANNEL_1
2318 * @arg @ref LL_ADC_CHANNEL_2
2319 * @arg @ref LL_ADC_CHANNEL_3
2320 * @arg @ref LL_ADC_CHANNEL_4
2321 * @arg @ref LL_ADC_CHANNEL_5
2322 * @arg @ref LL_ADC_CHANNEL_6
2323 * @arg @ref LL_ADC_CHANNEL_7
2324 * @arg @ref LL_ADC_CHANNEL_8
2325 * @arg @ref LL_ADC_CHANNEL_9
2326 * @arg @ref LL_ADC_CHANNEL_10
2327 * @arg @ref LL_ADC_CHANNEL_11
2328 * @arg @ref LL_ADC_CHANNEL_12
2329 * @arg @ref LL_ADC_CHANNEL_13
2330 * @arg @ref LL_ADC_CHANNEL_14
2331 * @arg @ref LL_ADC_CHANNEL_15
2332 * @arg @ref LL_ADC_CHANNEL_16
2333 * @arg @ref LL_ADC_CHANNEL_17
2334 * @arg @ref LL_ADC_CHANNEL_18
2335 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2336 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2337 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2338 *
2339 * (1) On STM32F2, parameter available only on ADC instance: ADC1.\n
2340 * @retval None
2341 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)2342 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
2343 {
2344 /* Set bits with content of parameter "Channel" with bits position */
2345 /* in register and register position depending on parameter "Rank". */
2346 /* Parameters "Rank" and "Channel" are used with masks because containing */
2347 /* other bits reserved for other purpose. */
2348 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
2349
2350 MODIFY_REG(*preg,
2351 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
2352 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
2353 }
2354
2355 /**
2356 * @brief Get ADC group regular sequence: channel on the selected
2357 * scan sequence rank.
2358 * @note On this STM32 series, ADC group regular sequencer is
2359 * fully configurable: sequencer length and each rank
2360 * affectation to a channel are configurable.
2361 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
2362 * @note Depending on devices and packages, some channels may not be available.
2363 * Refer to device datasheet for channels availability.
2364 * @note Usage of the returned channel number:
2365 * - To reinject this channel into another function LL_ADC_xxx:
2366 * the returned channel number is only partly formatted on definition
2367 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
2368 * with parts of literals LL_ADC_CHANNEL_x or using
2369 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2370 * Then the selected literal LL_ADC_CHANNEL_x can be used
2371 * as parameter for another function.
2372 * - To get the channel number in decimal format:
2373 * process the returned value with the helper macro
2374 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2375 * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n
2376 * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n
2377 * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n
2378 * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n
2379 * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n
2380 * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n
2381 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
2382 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
2383 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
2384 * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n
2385 * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n
2386 * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n
2387 * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n
2388 * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n
2389 * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n
2390 * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks
2391 * @param ADCx ADC instance
2392 * @param Rank This parameter can be one of the following values:
2393 * @arg @ref LL_ADC_REG_RANK_1
2394 * @arg @ref LL_ADC_REG_RANK_2
2395 * @arg @ref LL_ADC_REG_RANK_3
2396 * @arg @ref LL_ADC_REG_RANK_4
2397 * @arg @ref LL_ADC_REG_RANK_5
2398 * @arg @ref LL_ADC_REG_RANK_6
2399 * @arg @ref LL_ADC_REG_RANK_7
2400 * @arg @ref LL_ADC_REG_RANK_8
2401 * @arg @ref LL_ADC_REG_RANK_9
2402 * @arg @ref LL_ADC_REG_RANK_10
2403 * @arg @ref LL_ADC_REG_RANK_11
2404 * @arg @ref LL_ADC_REG_RANK_12
2405 * @arg @ref LL_ADC_REG_RANK_13
2406 * @arg @ref LL_ADC_REG_RANK_14
2407 * @arg @ref LL_ADC_REG_RANK_15
2408 * @arg @ref LL_ADC_REG_RANK_16
2409 * @retval Returned value can be one of the following values:
2410 * @arg @ref LL_ADC_CHANNEL_0
2411 * @arg @ref LL_ADC_CHANNEL_1
2412 * @arg @ref LL_ADC_CHANNEL_2
2413 * @arg @ref LL_ADC_CHANNEL_3
2414 * @arg @ref LL_ADC_CHANNEL_4
2415 * @arg @ref LL_ADC_CHANNEL_5
2416 * @arg @ref LL_ADC_CHANNEL_6
2417 * @arg @ref LL_ADC_CHANNEL_7
2418 * @arg @ref LL_ADC_CHANNEL_8
2419 * @arg @ref LL_ADC_CHANNEL_9
2420 * @arg @ref LL_ADC_CHANNEL_10
2421 * @arg @ref LL_ADC_CHANNEL_11
2422 * @arg @ref LL_ADC_CHANNEL_12
2423 * @arg @ref LL_ADC_CHANNEL_13
2424 * @arg @ref LL_ADC_CHANNEL_14
2425 * @arg @ref LL_ADC_CHANNEL_15
2426 * @arg @ref LL_ADC_CHANNEL_16
2427 * @arg @ref LL_ADC_CHANNEL_17
2428 * @arg @ref LL_ADC_CHANNEL_18
2429 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2430 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2431 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2432 *
2433 * (1) On STM32F2, parameter available only on ADC instance: ADC1.\n
2434 * (1) For ADC channel read back from ADC register,
2435 * comparison with internal channel parameter to be done
2436 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2437 */
LL_ADC_REG_GetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank)2438 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
2439 {
2440 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
2441
2442 return (uint32_t) (READ_BIT(*preg,
2443 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
2444 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
2445 );
2446 }
2447
2448 /**
2449 * @brief Set ADC continuous conversion mode on ADC group regular.
2450 * @note Description of ADC continuous conversion mode:
2451 * - single mode: one conversion per trigger
2452 * - continuous mode: after the first trigger, following
2453 * conversions launched successively automatically.
2454 * @note It is not possible to enable both ADC group regular
2455 * continuous mode and sequencer discontinuous mode.
2456 * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode
2457 * @param ADCx ADC instance
2458 * @param Continuous This parameter can be one of the following values:
2459 * @arg @ref LL_ADC_REG_CONV_SINGLE
2460 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
2461 * @retval None
2462 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)2463 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
2464 {
2465 MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);
2466 }
2467
2468 /**
2469 * @brief Get ADC continuous conversion mode on ADC group regular.
2470 * @note Description of ADC continuous conversion mode:
2471 * - single mode: one conversion per trigger
2472 * - continuous mode: after the first trigger, following
2473 * conversions launched successively automatically.
2474 * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode
2475 * @param ADCx ADC instance
2476 * @retval Returned value can be one of the following values:
2477 * @arg @ref LL_ADC_REG_CONV_SINGLE
2478 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
2479 */
LL_ADC_REG_GetContinuousMode(ADC_TypeDef * ADCx)2480 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
2481 {
2482 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));
2483 }
2484
2485 /**
2486 * @brief Set ADC group regular conversion data transfer: no transfer or
2487 * transfer by DMA, and DMA requests mode.
2488 * @note If transfer by DMA selected, specifies the DMA requests
2489 * mode:
2490 * - Limited mode (One shot mode): DMA transfer requests are stopped
2491 * when number of DMA data transfers (number of
2492 * ADC conversions) is reached.
2493 * This ADC mode is intended to be used with DMA mode non-circular.
2494 * - Unlimited mode: DMA transfer requests are unlimited,
2495 * whatever number of DMA data transfers (number of
2496 * ADC conversions).
2497 * This ADC mode is intended to be used with DMA mode circular.
2498 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
2499 * mode non-circular:
2500 * when DMA transfers size will be reached, DMA will stop transfers of
2501 * ADC conversions data ADC will raise an overrun error
2502 * (overrun flag and interruption if enabled).
2503 * @note For devices with several ADC instances: ADC multimode DMA
2504 * settings are available using function @ref LL_ADC_SetMultiDMATransfer().
2505 * @note To configure DMA source address (peripheral address),
2506 * use function @ref LL_ADC_DMA_GetRegAddr().
2507 * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer\n
2508 * CR2 DDS LL_ADC_REG_SetDMATransfer
2509 * @param ADCx ADC instance
2510 * @param DMATransfer This parameter can be one of the following values:
2511 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
2512 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
2513 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
2514 * @retval None
2515 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)2516 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
2517 {
2518 MODIFY_REG(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS, DMATransfer);
2519 }
2520
2521 /**
2522 * @brief Get ADC group regular conversion data transfer: no transfer or
2523 * transfer by DMA, and DMA requests mode.
2524 * @note If transfer by DMA selected, specifies the DMA requests
2525 * mode:
2526 * - Limited mode (One shot mode): DMA transfer requests are stopped
2527 * when number of DMA data transfers (number of
2528 * ADC conversions) is reached.
2529 * This ADC mode is intended to be used with DMA mode non-circular.
2530 * - Unlimited mode: DMA transfer requests are unlimited,
2531 * whatever number of DMA data transfers (number of
2532 * ADC conversions).
2533 * This ADC mode is intended to be used with DMA mode circular.
2534 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
2535 * mode non-circular:
2536 * when DMA transfers size will be reached, DMA will stop transfers of
2537 * ADC conversions data ADC will raise an overrun error
2538 * (overrun flag and interruption if enabled).
2539 * @note For devices with several ADC instances: ADC multimode DMA
2540 * settings are available using function @ref LL_ADC_GetMultiDMATransfer().
2541 * @note To configure DMA source address (peripheral address),
2542 * use function @ref LL_ADC_DMA_GetRegAddr().
2543 * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer\n
2544 * CR2 DDS LL_ADC_REG_GetDMATransfer
2545 * @param ADCx ADC instance
2546 * @retval Returned value can be one of the following values:
2547 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
2548 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
2549 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
2550 */
LL_ADC_REG_GetDMATransfer(ADC_TypeDef * ADCx)2551 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
2552 {
2553 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS));
2554 }
2555
2556 /**
2557 * @brief Specify which ADC flag between EOC (end of unitary conversion)
2558 * or EOS (end of sequence conversions) is used to indicate
2559 * the end of conversion.
2560 * @note This feature is aimed to be set when using ADC with
2561 * programming model by polling or interruption
2562 * (programming model by DMA usually uses DMA interruptions
2563 * to indicate end of conversion and data transfer).
2564 * @note For ADC group injected, end of conversion (flag&IT) is raised
2565 * only at the end of the sequence.
2566 * @rmtoll CR2 EOCS LL_ADC_REG_SetFlagEndOfConversion
2567 * @param ADCx ADC instance
2568 * @param EocSelection This parameter can be one of the following values:
2569 * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
2570 * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
2571 * @retval None
2572 */
LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef * ADCx,uint32_t EocSelection)2573 __STATIC_INLINE void LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef *ADCx, uint32_t EocSelection)
2574 {
2575 MODIFY_REG(ADCx->CR2, ADC_CR2_EOCS, EocSelection);
2576 }
2577
2578 /**
2579 * @brief Get which ADC flag between EOC (end of unitary conversion)
2580 * or EOS (end of sequence conversions) is used to indicate
2581 * the end of conversion.
2582 * @rmtoll CR2 EOCS LL_ADC_REG_GetFlagEndOfConversion
2583 * @param ADCx ADC instance
2584 * @retval Returned value can be one of the following values:
2585 * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
2586 * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
2587 */
LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef * ADCx)2588 __STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx)
2589 {
2590 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EOCS));
2591 }
2592
2593 /**
2594 * @}
2595 */
2596
2597 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
2598 * @{
2599 */
2600
2601 /**
2602 * @brief Set ADC group injected conversion trigger source:
2603 * internal (SW start) or from external IP (timer event,
2604 * external interrupt line).
2605 * @note On this STM32 series, setting of external trigger edge is performed
2606 * using function @ref LL_ADC_INJ_StartConversionExtTrig().
2607 * @note Availability of parameters of trigger sources from timer
2608 * depends on timers availability on the selected device.
2609 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource\n
2610 * CR2 JEXTEN LL_ADC_INJ_SetTriggerSource
2611 * @param ADCx ADC instance
2612 * @param TriggerSource This parameter can be one of the following values:
2613 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
2614 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
2615 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
2616 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
2617 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
2618 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH2
2619 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
2620 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1
2621 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2
2622 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3
2623 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
2624 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4
2625 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
2626 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2
2627 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH3
2628 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
2629 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
2630 * @retval None
2631 */
LL_ADC_INJ_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)2632 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2633 {
2634 /* Note: On this STM32 series, ADC group injected external trigger edge */
2635 /* is used to perform a ADC conversion start. */
2636 /* This function does not set external trigger edge. */
2637 /* This feature is set using function */
2638 /* @ref LL_ADC_INJ_StartConversionExtTrig(). */
2639 MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));
2640 }
2641
2642 /**
2643 * @brief Get ADC group injected conversion trigger source:
2644 * internal (SW start) or from external IP (timer event,
2645 * external interrupt line).
2646 * @note To determine whether group injected trigger source is
2647 * internal (SW start) or external, without detail
2648 * of which peripheral is selected as external trigger,
2649 * (equivalent to
2650 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
2651 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
2652 * @note Availability of parameters of trigger sources from timer
2653 * depends on timers availability on the selected device.
2654 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource\n
2655 * CR2 JEXTEN LL_ADC_INJ_GetTriggerSource
2656 * @param ADCx ADC instance
2657 * @retval Returned value can be one of the following values:
2658 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
2659 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
2660 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
2661 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
2662 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
2663 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH2
2664 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
2665 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1
2666 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2
2667 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3
2668 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
2669 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4
2670 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
2671 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2
2672 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH3
2673 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
2674 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
2675 */
LL_ADC_INJ_GetTriggerSource(ADC_TypeDef * ADCx)2676 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
2677 {
2678 register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN);
2679
2680 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
2681 /* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}. */
2682 register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));
2683
2684 /* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL */
2685 /* to match with triggers literals definition. */
2686 return ((TriggerSource
2687 & (ADC_INJ_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_JEXTSEL)
2688 | ((ADC_INJ_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_JEXTEN)
2689 );
2690 }
2691
2692 /**
2693 * @brief Get ADC group injected conversion trigger source internal (SW start)
2694 or external
2695 * @note In case of group injected trigger source set to external trigger,
2696 * to determine which peripheral is selected as external trigger,
2697 * use function @ref LL_ADC_INJ_GetTriggerSource.
2698 * @rmtoll CR2 JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
2699 * @param ADCx ADC instance
2700 * @retval Value "0" if trigger source external trigger
2701 * Value "1" if trigger source SW start.
2702 */
LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)2703 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
2704 {
2705 return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN));
2706 }
2707
2708 /**
2709 * @brief Get ADC group injected conversion trigger polarity.
2710 * Applicable only for trigger source set to external trigger.
2711 * @rmtoll CR2 JEXTEN LL_ADC_INJ_GetTriggerEdge
2712 * @param ADCx ADC instance
2713 * @retval Returned value can be one of the following values:
2714 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
2715 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
2716 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
2717 */
LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef * ADCx)2718 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
2719 {
2720 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN));
2721 }
2722
2723 /**
2724 * @brief Set ADC group injected sequencer length and scan direction.
2725 * @note This function performs configuration of:
2726 * - Sequence length: Number of ranks in the scan sequence.
2727 * - Sequence direction: Unless specified in parameters, sequencer
2728 * scan direction is forward (from rank 1 to rank n).
2729 * @note On this STM32 series, group injected sequencer configuration
2730 * is conditioned to ADC instance sequencer mode.
2731 * If ADC instance sequencer mode is disabled, sequencers of
2732 * all groups (group regular, group injected) can be configured
2733 * but their execution is disabled (limited to rank 1).
2734 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2735 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2736 * ADC conversion on only 1 channel.
2737 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
2738 * @param ADCx ADC instance
2739 * @param SequencerNbRanks This parameter can be one of the following values:
2740 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
2741 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
2742 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
2743 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
2744 * @retval None
2745 */
LL_ADC_INJ_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)2746 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
2747 {
2748 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
2749 }
2750
2751 /**
2752 * @brief Get ADC group injected sequencer length and scan direction.
2753 * @note This function retrieves:
2754 * - Sequence length: Number of ranks in the scan sequence.
2755 * - Sequence direction: Unless specified in parameters, sequencer
2756 * scan direction is forward (from rank 1 to rank n).
2757 * @note On this STM32 series, group injected sequencer configuration
2758 * is conditioned to ADC instance sequencer mode.
2759 * If ADC instance sequencer mode is disabled, sequencers of
2760 * all groups (group regular, group injected) can be configured
2761 * but their execution is disabled (limited to rank 1).
2762 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2763 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2764 * ADC conversion on only 1 channel.
2765 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
2766 * @param ADCx ADC instance
2767 * @retval Returned value can be one of the following values:
2768 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
2769 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
2770 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
2771 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
2772 */
LL_ADC_INJ_GetSequencerLength(ADC_TypeDef * ADCx)2773 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
2774 {
2775 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
2776 }
2777
2778 /**
2779 * @brief Set ADC group injected sequencer discontinuous mode:
2780 * sequence subdivided and scan conversions interrupted every selected
2781 * number of ranks.
2782 * @note It is not possible to enable both ADC group injected
2783 * auto-injected mode and sequencer discontinuous mode.
2784 * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont
2785 * @param ADCx ADC instance
2786 * @param SeqDiscont This parameter can be one of the following values:
2787 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
2788 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
2789 * @retval None
2790 */
LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)2791 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2792 {
2793 MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);
2794 }
2795
2796 /**
2797 * @brief Get ADC group injected sequencer discontinuous mode:
2798 * sequence subdivided and scan conversions interrupted every selected
2799 * number of ranks.
2800 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
2801 * @param ADCx ADC instance
2802 * @retval Returned value can be one of the following values:
2803 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
2804 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
2805 */
LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef * ADCx)2806 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
2807 {
2808 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));
2809 }
2810
2811 /**
2812 * @brief Set ADC group injected sequence: channel on the selected
2813 * sequence rank.
2814 * @note Depending on devices and packages, some channels may not be available.
2815 * Refer to device datasheet for channels availability.
2816 * @note On this STM32 series, to measure internal channels (VrefInt,
2817 * TempSensor, ...), measurement paths to internal channels must be
2818 * enabled separately.
2819 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2820 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
2821 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
2822 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
2823 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
2824 * @param ADCx ADC instance
2825 * @param Rank This parameter can be one of the following values:
2826 * @arg @ref LL_ADC_INJ_RANK_1
2827 * @arg @ref LL_ADC_INJ_RANK_2
2828 * @arg @ref LL_ADC_INJ_RANK_3
2829 * @arg @ref LL_ADC_INJ_RANK_4
2830 * @param Channel This parameter can be one of the following values:
2831 * @arg @ref LL_ADC_CHANNEL_0
2832 * @arg @ref LL_ADC_CHANNEL_1
2833 * @arg @ref LL_ADC_CHANNEL_2
2834 * @arg @ref LL_ADC_CHANNEL_3
2835 * @arg @ref LL_ADC_CHANNEL_4
2836 * @arg @ref LL_ADC_CHANNEL_5
2837 * @arg @ref LL_ADC_CHANNEL_6
2838 * @arg @ref LL_ADC_CHANNEL_7
2839 * @arg @ref LL_ADC_CHANNEL_8
2840 * @arg @ref LL_ADC_CHANNEL_9
2841 * @arg @ref LL_ADC_CHANNEL_10
2842 * @arg @ref LL_ADC_CHANNEL_11
2843 * @arg @ref LL_ADC_CHANNEL_12
2844 * @arg @ref LL_ADC_CHANNEL_13
2845 * @arg @ref LL_ADC_CHANNEL_14
2846 * @arg @ref LL_ADC_CHANNEL_15
2847 * @arg @ref LL_ADC_CHANNEL_16
2848 * @arg @ref LL_ADC_CHANNEL_17
2849 * @arg @ref LL_ADC_CHANNEL_18
2850 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2851 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2852 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2853 *
2854 * (1) On STM32F2, parameter available only on ADC instance: ADC1.\n
2855 * @retval None
2856 */
LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)2857 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
2858 {
2859 /* Set bits with content of parameter "Channel" with bits position */
2860 /* in register depending on parameter "Rank". */
2861 /* Parameters "Rank" and "Channel" are used with masks because containing */
2862 /* other bits reserved for other purpose. */
2863 register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
2864
2865 MODIFY_REG(ADCx->JSQR,
2866 ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))),
2867 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))));
2868 }
2869
2870 /**
2871 * @brief Get ADC group injected sequence: channel on the selected
2872 * sequence rank.
2873 * @note Depending on devices and packages, some channels may not be available.
2874 * Refer to device datasheet for channels availability.
2875 * @note Usage of the returned channel number:
2876 * - To reinject this channel into another function LL_ADC_xxx:
2877 * the returned channel number is only partly formatted on definition
2878 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
2879 * with parts of literals LL_ADC_CHANNEL_x or using
2880 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2881 * Then the selected literal LL_ADC_CHANNEL_x can be used
2882 * as parameter for another function.
2883 * - To get the channel number in decimal format:
2884 * process the returned value with the helper macro
2885 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2886 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
2887 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
2888 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
2889 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
2890 * @param ADCx ADC instance
2891 * @param Rank This parameter can be one of the following values:
2892 * @arg @ref LL_ADC_INJ_RANK_1
2893 * @arg @ref LL_ADC_INJ_RANK_2
2894 * @arg @ref LL_ADC_INJ_RANK_3
2895 * @arg @ref LL_ADC_INJ_RANK_4
2896 * @retval Returned value can be one of the following values:
2897 * @arg @ref LL_ADC_CHANNEL_0
2898 * @arg @ref LL_ADC_CHANNEL_1
2899 * @arg @ref LL_ADC_CHANNEL_2
2900 * @arg @ref LL_ADC_CHANNEL_3
2901 * @arg @ref LL_ADC_CHANNEL_4
2902 * @arg @ref LL_ADC_CHANNEL_5
2903 * @arg @ref LL_ADC_CHANNEL_6
2904 * @arg @ref LL_ADC_CHANNEL_7
2905 * @arg @ref LL_ADC_CHANNEL_8
2906 * @arg @ref LL_ADC_CHANNEL_9
2907 * @arg @ref LL_ADC_CHANNEL_10
2908 * @arg @ref LL_ADC_CHANNEL_11
2909 * @arg @ref LL_ADC_CHANNEL_12
2910 * @arg @ref LL_ADC_CHANNEL_13
2911 * @arg @ref LL_ADC_CHANNEL_14
2912 * @arg @ref LL_ADC_CHANNEL_15
2913 * @arg @ref LL_ADC_CHANNEL_16
2914 * @arg @ref LL_ADC_CHANNEL_17
2915 * @arg @ref LL_ADC_CHANNEL_18
2916 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2917 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2918 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2919 *
2920 * (1) On STM32F2, parameter available only on ADC instance: ADC1.\n
2921 * (1) For ADC channel read back from ADC register,
2922 * comparison with internal channel parameter to be done
2923 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2924 */
LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank)2925 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
2926 {
2927 register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
2928
2929 return (uint32_t)(READ_BIT(ADCx->JSQR,
2930 ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))))
2931 >> (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))
2932 );
2933 }
2934
2935 /**
2936 * @brief Set ADC group injected conversion trigger:
2937 * independent or from ADC group regular.
2938 * @note This mode can be used to extend number of data registers
2939 * updated after one ADC conversion trigger and with data
2940 * permanently kept (not erased by successive conversions of scan of
2941 * ADC sequencer ranks), up to 5 data registers:
2942 * 1 data register on ADC group regular, 4 data registers
2943 * on ADC group injected.
2944 * @note If ADC group injected injected trigger source is set to an
2945 * external trigger, this feature must be must be set to
2946 * independent trigger.
2947 * ADC group injected automatic trigger is compliant only with
2948 * group injected trigger source set to SW start, without any
2949 * further action on ADC group injected conversion start or stop:
2950 * in this case, ADC group injected is controlled only
2951 * from ADC group regular.
2952 * @note It is not possible to enable both ADC group injected
2953 * auto-injected mode and sequencer discontinuous mode.
2954 * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto
2955 * @param ADCx ADC instance
2956 * @param TrigAuto This parameter can be one of the following values:
2957 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
2958 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
2959 * @retval None
2960 */
LL_ADC_INJ_SetTrigAuto(ADC_TypeDef * ADCx,uint32_t TrigAuto)2961 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
2962 {
2963 MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);
2964 }
2965
2966 /**
2967 * @brief Get ADC group injected conversion trigger:
2968 * independent or from ADC group regular.
2969 * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto
2970 * @param ADCx ADC instance
2971 * @retval Returned value can be one of the following values:
2972 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
2973 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
2974 */
LL_ADC_INJ_GetTrigAuto(ADC_TypeDef * ADCx)2975 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
2976 {
2977 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));
2978 }
2979
2980 /**
2981 * @brief Set ADC group injected offset.
2982 * @note It sets:
2983 * - ADC group injected rank to which the offset programmed
2984 * will be applied
2985 * - Offset level (offset to be subtracted from the raw
2986 * converted data).
2987 * Caution: Offset format is dependent to ADC resolution:
2988 * offset has to be left-aligned on bit 11, the LSB (right bits)
2989 * are set to 0.
2990 * @note Offset cannot be enabled or disabled.
2991 * To emulate offset disabled, set an offset value equal to 0.
2992 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n
2993 * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n
2994 * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n
2995 * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset
2996 * @param ADCx ADC instance
2997 * @param Rank This parameter can be one of the following values:
2998 * @arg @ref LL_ADC_INJ_RANK_1
2999 * @arg @ref LL_ADC_INJ_RANK_2
3000 * @arg @ref LL_ADC_INJ_RANK_3
3001 * @arg @ref LL_ADC_INJ_RANK_4
3002 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
3003 * @retval None
3004 */
LL_ADC_INJ_SetOffset(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t OffsetLevel)3005 __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
3006 {
3007 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
3008
3009 MODIFY_REG(*preg,
3010 ADC_JOFR1_JOFFSET1,
3011 OffsetLevel);
3012 }
3013
3014 /**
3015 * @brief Get ADC group injected offset.
3016 * @note It gives offset level (offset to be subtracted from the raw converted data).
3017 * Caution: Offset format is dependent to ADC resolution:
3018 * offset has to be left-aligned on bit 11, the LSB (right bits)
3019 * are set to 0.
3020 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n
3021 * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n
3022 * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n
3023 * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset
3024 * @param ADCx ADC instance
3025 * @param Rank This parameter can be one of the following values:
3026 * @arg @ref LL_ADC_INJ_RANK_1
3027 * @arg @ref LL_ADC_INJ_RANK_2
3028 * @arg @ref LL_ADC_INJ_RANK_3
3029 * @arg @ref LL_ADC_INJ_RANK_4
3030 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3031 */
LL_ADC_INJ_GetOffset(ADC_TypeDef * ADCx,uint32_t Rank)3032 __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
3033 {
3034 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
3035
3036 return (uint32_t)(READ_BIT(*preg,
3037 ADC_JOFR1_JOFFSET1)
3038 );
3039 }
3040
3041 /**
3042 * @}
3043 */
3044
3045 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
3046 * @{
3047 */
3048
3049 /**
3050 * @brief Set sampling time of the selected ADC channel
3051 * Unit: ADC clock cycles.
3052 * @note On this device, sampling time is on channel scope: independently
3053 * of channel mapped on ADC group regular or injected.
3054 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
3055 * converted:
3056 * sampling time constraints must be respected (sampling time can be
3057 * adjusted in function of ADC clock frequency and sampling time
3058 * setting).
3059 * Refer to device datasheet for timings values (parameters TS_vrefint,
3060 * TS_temp, ...).
3061 * @note Conversion time is the addition of sampling time and processing time.
3062 * Refer to reference manual for ADC processing time of
3063 * this STM32 series.
3064 * @note In case of ADC conversion of internal channel (VrefInt,
3065 * temperature sensor, ...), a sampling time minimum value
3066 * is required.
3067 * Refer to device datasheet.
3068 * @rmtoll SMPR1 SMP18 LL_ADC_SetChannelSamplingTime\n
3069 * SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n
3070 * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n
3071 * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n
3072 * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n
3073 * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n
3074 * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n
3075 * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n
3076 * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n
3077 * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n
3078 * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n
3079 * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n
3080 * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n
3081 * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n
3082 * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n
3083 * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n
3084 * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n
3085 * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n
3086 * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime
3087 * @param ADCx ADC instance
3088 * @param Channel This parameter can be one of the following values:
3089 * @arg @ref LL_ADC_CHANNEL_0
3090 * @arg @ref LL_ADC_CHANNEL_1
3091 * @arg @ref LL_ADC_CHANNEL_2
3092 * @arg @ref LL_ADC_CHANNEL_3
3093 * @arg @ref LL_ADC_CHANNEL_4
3094 * @arg @ref LL_ADC_CHANNEL_5
3095 * @arg @ref LL_ADC_CHANNEL_6
3096 * @arg @ref LL_ADC_CHANNEL_7
3097 * @arg @ref LL_ADC_CHANNEL_8
3098 * @arg @ref LL_ADC_CHANNEL_9
3099 * @arg @ref LL_ADC_CHANNEL_10
3100 * @arg @ref LL_ADC_CHANNEL_11
3101 * @arg @ref LL_ADC_CHANNEL_12
3102 * @arg @ref LL_ADC_CHANNEL_13
3103 * @arg @ref LL_ADC_CHANNEL_14
3104 * @arg @ref LL_ADC_CHANNEL_15
3105 * @arg @ref LL_ADC_CHANNEL_16
3106 * @arg @ref LL_ADC_CHANNEL_17
3107 * @arg @ref LL_ADC_CHANNEL_18
3108 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3109 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
3110 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3111 *
3112 * (1) On STM32F2, parameter available only on ADC instance: ADC1.\n
3113 * @param SamplingTime This parameter can be one of the following values:
3114 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES
3115 * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES
3116 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES
3117 * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES
3118 * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES
3119 * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES
3120 * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES
3121 * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES
3122 * @retval None
3123 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTime)3124 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
3125 {
3126 /* Set bits with content of parameter "SamplingTime" with bits position */
3127 /* in register and register position depending on parameter "Channel". */
3128 /* Parameter "Channel" is used with masks because containing */
3129 /* other bits reserved for other purpose. */
3130 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
3131
3132 MODIFY_REG(*preg,
3133 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
3134 SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
3135 }
3136
3137 /**
3138 * @brief Get sampling time of the selected ADC channel
3139 * Unit: ADC clock cycles.
3140 * @note On this device, sampling time is on channel scope: independently
3141 * of channel mapped on ADC group regular or injected.
3142 * @note Conversion time is the addition of sampling time and processing time.
3143 * Refer to reference manual for ADC processing time of
3144 * this STM32 series.
3145 * @rmtoll SMPR1 SMP18 LL_ADC_GetChannelSamplingTime\n
3146 * SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n
3147 * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n
3148 * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n
3149 * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n
3150 * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n
3151 * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n
3152 * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n
3153 * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n
3154 * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n
3155 * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n
3156 * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n
3157 * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n
3158 * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n
3159 * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n
3160 * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n
3161 * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n
3162 * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n
3163 * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime
3164 * @param ADCx ADC instance
3165 * @param Channel This parameter can be one of the following values:
3166 * @arg @ref LL_ADC_CHANNEL_0
3167 * @arg @ref LL_ADC_CHANNEL_1
3168 * @arg @ref LL_ADC_CHANNEL_2
3169 * @arg @ref LL_ADC_CHANNEL_3
3170 * @arg @ref LL_ADC_CHANNEL_4
3171 * @arg @ref LL_ADC_CHANNEL_5
3172 * @arg @ref LL_ADC_CHANNEL_6
3173 * @arg @ref LL_ADC_CHANNEL_7
3174 * @arg @ref LL_ADC_CHANNEL_8
3175 * @arg @ref LL_ADC_CHANNEL_9
3176 * @arg @ref LL_ADC_CHANNEL_10
3177 * @arg @ref LL_ADC_CHANNEL_11
3178 * @arg @ref LL_ADC_CHANNEL_12
3179 * @arg @ref LL_ADC_CHANNEL_13
3180 * @arg @ref LL_ADC_CHANNEL_14
3181 * @arg @ref LL_ADC_CHANNEL_15
3182 * @arg @ref LL_ADC_CHANNEL_16
3183 * @arg @ref LL_ADC_CHANNEL_17
3184 * @arg @ref LL_ADC_CHANNEL_18
3185 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3186 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
3187 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3188 *
3189 * (1) On STM32F2, parameter available only on ADC instance: ADC1.\n
3190 * @retval Returned value can be one of the following values:
3191 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES
3192 * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES
3193 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES
3194 * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES
3195 * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES
3196 * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES
3197 * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES
3198 * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES
3199 */
LL_ADC_GetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel)3200 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
3201 {
3202 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
3203
3204 return (uint32_t)(READ_BIT(*preg,
3205 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
3206 >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
3207 );
3208 }
3209
3210 /**
3211 * @}
3212 */
3213
3214 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
3215 * @{
3216 */
3217
3218 /**
3219 * @brief Set ADC analog watchdog monitored channels:
3220 * a single channel or all channels,
3221 * on ADC groups regular and-or injected.
3222 * @note Once monitored channels are selected, analog watchdog
3223 * is enabled.
3224 * @note In case of need to define a single channel to monitor
3225 * with analog watchdog from sequencer channel definition,
3226 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
3227 * @note On this STM32 series, there is only 1 kind of analog watchdog
3228 * instance:
3229 * - AWD standard (instance AWD1):
3230 * - channels monitored: can monitor 1 channel or all channels.
3231 * - groups monitored: ADC groups regular and-or injected.
3232 * - resolution: resolution is not limited (corresponds to
3233 * ADC resolution configured).
3234 * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
3235 * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
3236 * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels
3237 * @param ADCx ADC instance
3238 * @param AWDChannelGroup This parameter can be one of the following values:
3239 * @arg @ref LL_ADC_AWD_DISABLE
3240 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3241 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
3242 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
3243 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3244 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
3245 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
3246 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3247 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
3248 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
3249 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3250 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
3251 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
3252 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3253 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
3254 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
3255 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3256 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
3257 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
3258 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3259 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
3260 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
3261 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3262 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
3263 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
3264 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3265 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
3266 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
3267 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
3268 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
3269 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
3270 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
3271 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
3272 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
3273 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3274 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
3275 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
3276 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3277 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
3278 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
3279 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3280 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
3281 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
3282 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3283 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
3284 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
3285 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
3286 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
3287 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
3288 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
3289 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
3290 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
3291 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
3292 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
3293 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
3294 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
3295 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
3296 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
3297 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
3298 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
3299 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
3300 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
3301 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
3302 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
3303 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)
3304 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)
3305 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
3306 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
3307 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1)
3308 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
3309 *
3310 * (1) On STM32F2, parameter available only on ADC instance: ADC1.\n
3311 * @retval None
3312 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDChannelGroup)3313 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
3314 {
3315 MODIFY_REG(ADCx->CR1,
3316 (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH),
3317 AWDChannelGroup);
3318 }
3319
3320 /**
3321 * @brief Get ADC analog watchdog monitored channel.
3322 * @note Usage of the returned channel number:
3323 * - To reinject this channel into another function LL_ADC_xxx:
3324 * the returned channel number is only partly formatted on definition
3325 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3326 * with parts of literals LL_ADC_CHANNEL_x or using
3327 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3328 * Then the selected literal LL_ADC_CHANNEL_x can be used
3329 * as parameter for another function.
3330 * - To get the channel number in decimal format:
3331 * process the returned value with the helper macro
3332 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3333 * Applicable only when the analog watchdog is set to monitor
3334 * one channel.
3335 * @note On this STM32 series, there is only 1 kind of analog watchdog
3336 * instance:
3337 * - AWD standard (instance AWD1):
3338 * - channels monitored: can monitor 1 channel or all channels.
3339 * - groups monitored: ADC groups regular and-or injected.
3340 * - resolution: resolution is not limited (corresponds to
3341 * ADC resolution configured).
3342 * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
3343 * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
3344 * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels
3345 * @param ADCx ADC instance
3346 * @retval Returned value can be one of the following values:
3347 * @arg @ref LL_ADC_AWD_DISABLE
3348 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3349 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
3350 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
3351 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3352 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
3353 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
3354 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3355 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
3356 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
3357 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3358 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
3359 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
3360 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3361 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
3362 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
3363 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3364 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
3365 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
3366 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3367 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
3368 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
3369 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3370 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
3371 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
3372 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3373 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
3374 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
3375 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
3376 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
3377 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
3378 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
3379 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
3380 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
3381 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3382 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
3383 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
3384 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3385 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
3386 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
3387 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3388 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
3389 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
3390 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3391 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
3392 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
3393 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
3394 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
3395 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
3396 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
3397 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
3398 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
3399 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
3400 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
3401 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
3402 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
3403 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
3404 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
3405 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
3406 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
3407 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
3408 */
LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef * ADCx)3409 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
3410 {
3411 return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH)));
3412 }
3413
3414 /**
3415 * @brief Set ADC analog watchdog threshold value of threshold
3416 * high or low.
3417 * @note In case of ADC resolution different of 12 bits,
3418 * analog watchdog thresholds data require a specific shift.
3419 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
3420 * @note On this STM32 series, there is only 1 kind of analog watchdog
3421 * instance:
3422 * - AWD standard (instance AWD1):
3423 * - channels monitored: can monitor 1 channel or all channels.
3424 * - groups monitored: ADC groups regular and-or injected.
3425 * - resolution: resolution is not limited (corresponds to
3426 * ADC resolution configured).
3427 * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n
3428 * LTR LT LL_ADC_SetAnalogWDThresholds
3429 * @param ADCx ADC instance
3430 * @param AWDThresholdsHighLow This parameter can be one of the following values:
3431 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
3432 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3433 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
3434 * @retval None
3435 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)3436 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
3437 {
3438 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
3439
3440 MODIFY_REG(*preg,
3441 ADC_HTR_HT,
3442 AWDThresholdValue);
3443 }
3444
3445 /**
3446 * @brief Get ADC analog watchdog threshold value of threshold high or
3447 * threshold low.
3448 * @note In case of ADC resolution different of 12 bits,
3449 * analog watchdog thresholds data require a specific shift.
3450 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
3451 * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n
3452 * LTR LT LL_ADC_GetAnalogWDThresholds
3453 * @param ADCx ADC instance
3454 * @param AWDThresholdsHighLow This parameter can be one of the following values:
3455 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
3456 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3457 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3458 */
LL_ADC_GetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDThresholdsHighLow)3459 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
3460 {
3461 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
3462
3463 return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
3464 }
3465
3466 /**
3467 * @}
3468 */
3469
3470 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
3471 * @{
3472 */
3473
3474 /**
3475 * @brief Set ADC multimode configuration to operate in independent mode
3476 * or multimode (for devices with several ADC instances).
3477 * @note If multimode configuration: the selected ADC instance is
3478 * either master or slave depending on hardware.
3479 * Refer to reference manual.
3480 * @rmtoll CCR MULTI LL_ADC_SetMultimode
3481 * @param ADCxy_COMMON ADC common instance
3482 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3483 * @param Multimode This parameter can be one of the following values:
3484 * @arg @ref LL_ADC_MULTI_INDEPENDENT
3485 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
3486 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
3487 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
3488 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
3489 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
3490 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
3491 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
3492 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM
3493 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT
3494 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT
3495 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT
3496 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL
3497 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN
3498 * @retval None
3499 */
LL_ADC_SetMultimode(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t Multimode)3500 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
3501 {
3502 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MULTI, Multimode);
3503 }
3504
3505 /**
3506 * @brief Get ADC multimode configuration to operate in independent mode
3507 * or multimode (for devices with several ADC instances).
3508 * @note If multimode configuration: the selected ADC instance is
3509 * either master or slave depending on hardware.
3510 * Refer to reference manual.
3511 * @rmtoll CCR MULTI LL_ADC_GetMultimode
3512 * @param ADCxy_COMMON ADC common instance
3513 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3514 * @retval Returned value can be one of the following values:
3515 * @arg @ref LL_ADC_MULTI_INDEPENDENT
3516 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
3517 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
3518 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
3519 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
3520 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
3521 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
3522 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
3523 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM
3524 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT
3525 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT
3526 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT
3527 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL
3528 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN
3529 */
LL_ADC_GetMultimode(ADC_Common_TypeDef * ADCxy_COMMON)3530 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
3531 {
3532 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MULTI));
3533 }
3534
3535 /**
3536 * @brief Set ADC multimode conversion data transfer: no transfer
3537 * or transfer by DMA.
3538 * @note If ADC multimode transfer by DMA is not selected:
3539 * each ADC uses its own DMA channel, with its individual
3540 * DMA transfer settings.
3541 * If ADC multimode transfer by DMA is selected:
3542 * One DMA channel is used for both ADC (DMA of ADC master)
3543 * Specifies the DMA requests mode:
3544 * - Limited mode (One shot mode): DMA transfer requests are stopped
3545 * when number of DMA data transfers (number of
3546 * ADC conversions) is reached.
3547 * This ADC mode is intended to be used with DMA mode non-circular.
3548 * - Unlimited mode: DMA transfer requests are unlimited,
3549 * whatever number of DMA data transfers (number of
3550 * ADC conversions).
3551 * This ADC mode is intended to be used with DMA mode circular.
3552 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3553 * mode non-circular:
3554 * when DMA transfers size will be reached, DMA will stop transfers of
3555 * ADC conversions data ADC will raise an overrun error
3556 * (overrun flag and interruption if enabled).
3557 * @note How to retrieve multimode conversion data:
3558 * Whatever multimode transfer by DMA setting: using function
3559 * @ref LL_ADC_REG_ReadMultiConversionData32().
3560 * If ADC multimode transfer by DMA is selected: conversion data
3561 * is a raw data with ADC master and slave concatenated.
3562 * A macro is available to get the conversion data of
3563 * ADC master or ADC slave: see helper macro
3564 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
3565 * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
3566 * CCR DDS LL_ADC_SetMultiDMATransfer
3567 * @param ADCxy_COMMON ADC common instance
3568 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3569 * @param MultiDMATransfer This parameter can be one of the following values:
3570 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
3571 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1
3572 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2
3573 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3
3574 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1
3575 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2
3576 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3
3577 * @retval None
3578 */
LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiDMATransfer)3579 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
3580 {
3581 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS, MultiDMATransfer);
3582 }
3583
3584 /**
3585 * @brief Get ADC multimode conversion data transfer: no transfer
3586 * or transfer by DMA.
3587 * @note If ADC multimode transfer by DMA is not selected:
3588 * each ADC uses its own DMA channel, with its individual
3589 * DMA transfer settings.
3590 * If ADC multimode transfer by DMA is selected:
3591 * One DMA channel is used for both ADC (DMA of ADC master)
3592 * Specifies the DMA requests mode:
3593 * - Limited mode (One shot mode): DMA transfer requests are stopped
3594 * when number of DMA data transfers (number of
3595 * ADC conversions) is reached.
3596 * This ADC mode is intended to be used with DMA mode non-circular.
3597 * - Unlimited mode: DMA transfer requests are unlimited,
3598 * whatever number of DMA data transfers (number of
3599 * ADC conversions).
3600 * This ADC mode is intended to be used with DMA mode circular.
3601 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3602 * mode non-circular:
3603 * when DMA transfers size will be reached, DMA will stop transfers of
3604 * ADC conversions data ADC will raise an overrun error
3605 * (overrun flag and interruption if enabled).
3606 * @note How to retrieve multimode conversion data:
3607 * Whatever multimode transfer by DMA setting: using function
3608 * @ref LL_ADC_REG_ReadMultiConversionData32().
3609 * If ADC multimode transfer by DMA is selected: conversion data
3610 * is a raw data with ADC master and slave concatenated.
3611 * A macro is available to get the conversion data of
3612 * ADC master or ADC slave: see helper macro
3613 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
3614 * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
3615 * CCR DDS LL_ADC_GetMultiDMATransfer
3616 * @param ADCxy_COMMON ADC common instance
3617 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3618 * @retval Returned value can be one of the following values:
3619 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
3620 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1
3621 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2
3622 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3
3623 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1
3624 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2
3625 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3
3626 */
LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON)3627 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
3628 {
3629 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS));
3630 }
3631
3632 /**
3633 * @brief Set ADC multimode delay between 2 sampling phases.
3634 * @note The sampling delay range depends on ADC resolution:
3635 * - ADC resolution 12 bits can have maximum delay of 12 cycles.
3636 * - ADC resolution 10 bits can have maximum delay of 10 cycles.
3637 * - ADC resolution 8 bits can have maximum delay of 8 cycles.
3638 * - ADC resolution 6 bits can have maximum delay of 6 cycles.
3639 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
3640 * @param ADCxy_COMMON ADC common instance
3641 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3642 * @param MultiTwoSamplingDelay This parameter can be one of the following values:
3643 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
3644 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
3645 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
3646 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
3647 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
3648 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
3649 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
3650 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
3651 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
3652 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES
3653 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES
3654 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES
3655 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES
3656 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES
3657 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES
3658 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES
3659 * @retval None
3660 */
LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiTwoSamplingDelay)3661 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
3662 {
3663 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
3664 }
3665
3666 /**
3667 * @brief Get ADC multimode delay between 2 sampling phases.
3668 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
3669 * @param ADCxy_COMMON ADC common instance
3670 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3671 * @retval Returned value can be one of the following values:
3672 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
3673 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
3674 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
3675 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
3676 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
3677 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
3678 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
3679 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
3680 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
3681 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES
3682 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES
3683 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES
3684 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES
3685 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES
3686 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES
3687 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES
3688 */
LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON)3689 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
3690 {
3691 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
3692 }
3693
3694 /**
3695 * @}
3696 */
3697 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
3698 * @{
3699 */
3700
3701 /**
3702 * @brief Enable the selected ADC instance.
3703 * @note On this STM32 series, after ADC enable, a delay for
3704 * ADC internal analog stabilization is required before performing a
3705 * ADC conversion start.
3706 * Refer to device datasheet, parameter tSTAB.
3707 * @rmtoll CR2 ADON LL_ADC_Enable
3708 * @param ADCx ADC instance
3709 * @retval None
3710 */
LL_ADC_Enable(ADC_TypeDef * ADCx)3711 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
3712 {
3713 SET_BIT(ADCx->CR2, ADC_CR2_ADON);
3714 }
3715
3716 /**
3717 * @brief Disable the selected ADC instance.
3718 * @rmtoll CR2 ADON LL_ADC_Disable
3719 * @param ADCx ADC instance
3720 * @retval None
3721 */
LL_ADC_Disable(ADC_TypeDef * ADCx)3722 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
3723 {
3724 CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);
3725 }
3726
3727 /**
3728 * @brief Get the selected ADC instance enable state.
3729 * @rmtoll CR2 ADON LL_ADC_IsEnabled
3730 * @param ADCx ADC instance
3731 * @retval 0: ADC is disabled, 1: ADC is enabled.
3732 */
LL_ADC_IsEnabled(ADC_TypeDef * ADCx)3733 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
3734 {
3735 return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));
3736 }
3737
3738 /**
3739 * @}
3740 */
3741
3742 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
3743 * @{
3744 */
3745
3746 /**
3747 * @brief Start ADC group regular conversion.
3748 * @note On this STM32 series, this function is relevant only for
3749 * internal trigger (SW start), not for external trigger:
3750 * - If ADC trigger has been set to software start, ADC conversion
3751 * starts immediately.
3752 * - If ADC trigger has been set to external trigger, ADC conversion
3753 * start must be performed using function
3754 * @ref LL_ADC_REG_StartConversionExtTrig().
3755 * (if external trigger edge would have been set during ADC other
3756 * settings, ADC conversion would start at trigger event
3757 * as soon as ADC is enabled).
3758 * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart
3759 * @param ADCx ADC instance
3760 * @retval None
3761 */
LL_ADC_REG_StartConversionSWStart(ADC_TypeDef * ADCx)3762 __STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx)
3763 {
3764 SET_BIT(ADCx->CR2, ADC_CR2_SWSTART);
3765 }
3766
3767 /**
3768 * @brief Start ADC group regular conversion from external trigger.
3769 * @note ADC conversion will start at next trigger event (on the selected
3770 * trigger edge) following the ADC start conversion command.
3771 * @note On this STM32 series, this function is relevant for
3772 * ADC conversion start from external trigger.
3773 * If internal trigger (SW start) is needed, perform ADC conversion
3774 * start using function @ref LL_ADC_REG_StartConversionSWStart().
3775 * @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig
3776 * @param ExternalTriggerEdge This parameter can be one of the following values:
3777 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3778 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3779 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3780 * @param ADCx ADC instance
3781 * @retval None
3782 */
LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)3783 __STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3784 {
3785 SET_BIT(ADCx->CR2, ExternalTriggerEdge);
3786 }
3787
3788 /**
3789 * @brief Stop ADC group regular conversion from external trigger.
3790 * @note No more ADC conversion will start at next trigger event
3791 * following the ADC stop conversion command.
3792 * If a conversion is on-going, it will be completed.
3793 * @note On this STM32 series, there is no specific command
3794 * to stop a conversion on-going or to stop ADC converting
3795 * in continuous mode. These actions can be performed
3796 * using function @ref LL_ADC_Disable().
3797 * @rmtoll CR2 EXTEN LL_ADC_REG_StopConversionExtTrig
3798 * @param ADCx ADC instance
3799 * @retval None
3800 */
LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef * ADCx)3801 __STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
3802 {
3803 CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTEN);
3804 }
3805
3806 /**
3807 * @brief Get ADC group regular conversion data, range fit for
3808 * all ADC configurations: all ADC resolutions and
3809 * all oversampling increased data width (for devices
3810 * with feature oversampling).
3811 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
3812 * @param ADCx ADC instance
3813 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
3814 */
LL_ADC_REG_ReadConversionData32(ADC_TypeDef * ADCx)3815 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
3816 {
3817 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3818 }
3819
3820 /**
3821 * @brief Get ADC group regular conversion data, range fit for
3822 * ADC resolution 12 bits.
3823 * @note For devices with feature oversampling: Oversampling
3824 * can increase data width, function for extended range
3825 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3826 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
3827 * @param ADCx ADC instance
3828 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3829 */
LL_ADC_REG_ReadConversionData12(ADC_TypeDef * ADCx)3830 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
3831 {
3832 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3833 }
3834
3835 /**
3836 * @brief Get ADC group regular conversion data, range fit for
3837 * ADC resolution 10 bits.
3838 * @note For devices with feature oversampling: Oversampling
3839 * can increase data width, function for extended range
3840 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3841 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
3842 * @param ADCx ADC instance
3843 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
3844 */
LL_ADC_REG_ReadConversionData10(ADC_TypeDef * ADCx)3845 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
3846 {
3847 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3848 }
3849
3850 /**
3851 * @brief Get ADC group regular conversion data, range fit for
3852 * ADC resolution 8 bits.
3853 * @note For devices with feature oversampling: Oversampling
3854 * can increase data width, function for extended range
3855 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3856 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
3857 * @param ADCx ADC instance
3858 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
3859 */
LL_ADC_REG_ReadConversionData8(ADC_TypeDef * ADCx)3860 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
3861 {
3862 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3863 }
3864
3865 /**
3866 * @brief Get ADC group regular conversion data, range fit for
3867 * ADC resolution 6 bits.
3868 * @note For devices with feature oversampling: Oversampling
3869 * can increase data width, function for extended range
3870 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3871 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
3872 * @param ADCx ADC instance
3873 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
3874 */
LL_ADC_REG_ReadConversionData6(ADC_TypeDef * ADCx)3875 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
3876 {
3877 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3878 }
3879
3880 /**
3881 * @brief Get ADC multimode conversion data of ADC master, ADC slave
3882 * or raw data with ADC master and slave concatenated.
3883 * @note If raw data with ADC master and slave concatenated is retrieved,
3884 * a macro is available to get the conversion data of
3885 * ADC master or ADC slave: see helper macro
3886 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
3887 * (however this macro is mainly intended for multimode
3888 * transfer by DMA, because this function can do the same
3889 * by getting multimode conversion data of ADC master or ADC slave
3890 * separately).
3891 * @rmtoll CDR DATA1 LL_ADC_REG_ReadMultiConversionData32\n
3892 * CDR DATA2 LL_ADC_REG_ReadMultiConversionData32
3893 * @param ADCxy_COMMON ADC common instance
3894 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3895 * @param ConversionData This parameter can be one of the following values:
3896 * @arg @ref LL_ADC_MULTI_MASTER
3897 * @arg @ref LL_ADC_MULTI_SLAVE
3898 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
3899 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
3900 */
LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t ConversionData)3901 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
3902 {
3903 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
3904 ADC_DR_ADC2DATA)
3905 >> POSITION_VAL(ConversionData)
3906 );
3907 }
3908
3909 /**
3910 * @}
3911 */
3912
3913 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
3914 * @{
3915 */
3916
3917 /**
3918 * @brief Start ADC group injected conversion.
3919 * @note On this STM32 series, this function is relevant only for
3920 * internal trigger (SW start), not for external trigger:
3921 * - If ADC trigger has been set to software start, ADC conversion
3922 * starts immediately.
3923 * - If ADC trigger has been set to external trigger, ADC conversion
3924 * start must be performed using function
3925 * @ref LL_ADC_INJ_StartConversionExtTrig().
3926 * (if external trigger edge would have been set during ADC other
3927 * settings, ADC conversion would start at trigger event
3928 * as soon as ADC is enabled).
3929 * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart
3930 * @param ADCx ADC instance
3931 * @retval None
3932 */
LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef * ADCx)3933 __STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx)
3934 {
3935 SET_BIT(ADCx->CR2, ADC_CR2_JSWSTART);
3936 }
3937
3938 /**
3939 * @brief Start ADC group injected conversion from external trigger.
3940 * @note ADC conversion will start at next trigger event (on the selected
3941 * trigger edge) following the ADC start conversion command.
3942 * @note On this STM32 series, this function is relevant for
3943 * ADC conversion start from external trigger.
3944 * If internal trigger (SW start) is needed, perform ADC conversion
3945 * start using function @ref LL_ADC_INJ_StartConversionSWStart().
3946 * @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig
3947 * @param ExternalTriggerEdge This parameter can be one of the following values:
3948 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
3949 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
3950 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
3951 * @param ADCx ADC instance
3952 * @retval None
3953 */
LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)3954 __STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3955 {
3956 SET_BIT(ADCx->CR2, ExternalTriggerEdge);
3957 }
3958
3959 /**
3960 * @brief Stop ADC group injected conversion from external trigger.
3961 * @note No more ADC conversion will start at next trigger event
3962 * following the ADC stop conversion command.
3963 * If a conversion is on-going, it will be completed.
3964 * @note On this STM32 series, there is no specific command
3965 * to stop a conversion on-going or to stop ADC converting
3966 * in continuous mode. These actions can be performed
3967 * using function @ref LL_ADC_Disable().
3968 * @rmtoll CR2 JEXTEN LL_ADC_INJ_StopConversionExtTrig
3969 * @param ADCx ADC instance
3970 * @retval None
3971 */
LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef * ADCx)3972 __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
3973 {
3974 CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTEN);
3975 }
3976
3977 /**
3978 * @brief Get ADC group regular conversion data, range fit for
3979 * all ADC configurations: all ADC resolutions and
3980 * all oversampling increased data width (for devices
3981 * with feature oversampling).
3982 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
3983 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
3984 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
3985 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
3986 * @param ADCx ADC instance
3987 * @param Rank This parameter can be one of the following values:
3988 * @arg @ref LL_ADC_INJ_RANK_1
3989 * @arg @ref LL_ADC_INJ_RANK_2
3990 * @arg @ref LL_ADC_INJ_RANK_3
3991 * @arg @ref LL_ADC_INJ_RANK_4
3992 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
3993 */
LL_ADC_INJ_ReadConversionData32(ADC_TypeDef * ADCx,uint32_t Rank)3994 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
3995 {
3996 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
3997
3998 return (uint32_t)(READ_BIT(*preg,
3999 ADC_JDR1_JDATA)
4000 );
4001 }
4002
4003 /**
4004 * @brief Get ADC group injected conversion data, range fit for
4005 * ADC resolution 12 bits.
4006 * @note For devices with feature oversampling: Oversampling
4007 * can increase data width, function for extended range
4008 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4009 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
4010 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
4011 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
4012 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
4013 * @param ADCx ADC instance
4014 * @param Rank This parameter can be one of the following values:
4015 * @arg @ref LL_ADC_INJ_RANK_1
4016 * @arg @ref LL_ADC_INJ_RANK_2
4017 * @arg @ref LL_ADC_INJ_RANK_3
4018 * @arg @ref LL_ADC_INJ_RANK_4
4019 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
4020 */
LL_ADC_INJ_ReadConversionData12(ADC_TypeDef * ADCx,uint32_t Rank)4021 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
4022 {
4023 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4024
4025 return (uint16_t)(READ_BIT(*preg,
4026 ADC_JDR1_JDATA)
4027 );
4028 }
4029
4030 /**
4031 * @brief Get ADC group injected conversion data, range fit for
4032 * ADC resolution 10 bits.
4033 * @note For devices with feature oversampling: Oversampling
4034 * can increase data width, function for extended range
4035 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4036 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
4037 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
4038 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
4039 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
4040 * @param ADCx ADC instance
4041 * @param Rank This parameter can be one of the following values:
4042 * @arg @ref LL_ADC_INJ_RANK_1
4043 * @arg @ref LL_ADC_INJ_RANK_2
4044 * @arg @ref LL_ADC_INJ_RANK_3
4045 * @arg @ref LL_ADC_INJ_RANK_4
4046 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
4047 */
LL_ADC_INJ_ReadConversionData10(ADC_TypeDef * ADCx,uint32_t Rank)4048 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
4049 {
4050 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4051
4052 return (uint16_t)(READ_BIT(*preg,
4053 ADC_JDR1_JDATA)
4054 );
4055 }
4056
4057 /**
4058 * @brief Get ADC group injected conversion data, range fit for
4059 * ADC resolution 8 bits.
4060 * @note For devices with feature oversampling: Oversampling
4061 * can increase data width, function for extended range
4062 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4063 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
4064 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
4065 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
4066 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
4067 * @param ADCx ADC instance
4068 * @param Rank This parameter can be one of the following values:
4069 * @arg @ref LL_ADC_INJ_RANK_1
4070 * @arg @ref LL_ADC_INJ_RANK_2
4071 * @arg @ref LL_ADC_INJ_RANK_3
4072 * @arg @ref LL_ADC_INJ_RANK_4
4073 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
4074 */
LL_ADC_INJ_ReadConversionData8(ADC_TypeDef * ADCx,uint32_t Rank)4075 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
4076 {
4077 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4078
4079 return (uint8_t)(READ_BIT(*preg,
4080 ADC_JDR1_JDATA)
4081 );
4082 }
4083
4084 /**
4085 * @brief Get ADC group injected conversion data, range fit for
4086 * ADC resolution 6 bits.
4087 * @note For devices with feature oversampling: Oversampling
4088 * can increase data width, function for extended range
4089 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4090 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
4091 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
4092 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
4093 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
4094 * @param ADCx ADC instance
4095 * @param Rank This parameter can be one of the following values:
4096 * @arg @ref LL_ADC_INJ_RANK_1
4097 * @arg @ref LL_ADC_INJ_RANK_2
4098 * @arg @ref LL_ADC_INJ_RANK_3
4099 * @arg @ref LL_ADC_INJ_RANK_4
4100 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
4101 */
LL_ADC_INJ_ReadConversionData6(ADC_TypeDef * ADCx,uint32_t Rank)4102 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
4103 {
4104 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4105
4106 return (uint8_t)(READ_BIT(*preg,
4107 ADC_JDR1_JDATA)
4108 );
4109 }
4110
4111 /**
4112 * @}
4113 */
4114
4115 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
4116 * @{
4117 */
4118
4119 /**
4120 * @brief Get flag ADC group regular end of unitary conversion
4121 * or end of sequence conversions, depending on
4122 * ADC configuration.
4123 * @note To configure flag of end of conversion,
4124 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4125 * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOCS
4126 * @param ADCx ADC instance
4127 * @retval State of bit (1 or 0).
4128 */
LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef * ADCx)4129 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef *ADCx)
4130 {
4131 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));
4132 }
4133
4134 /**
4135 * @brief Get flag ADC group regular overrun.
4136 * @rmtoll SR OVR LL_ADC_IsActiveFlag_OVR
4137 * @param ADCx ADC instance
4138 * @retval State of bit (1 or 0).
4139 */
LL_ADC_IsActiveFlag_OVR(ADC_TypeDef * ADCx)4140 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
4141 {
4142 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
4143 }
4144
4145
4146 /**
4147 * @brief Get flag ADC group injected end of sequence conversions.
4148 * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS
4149 * @param ADCx ADC instance
4150 * @retval State of bit (1 or 0).
4151 */
LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef * ADCx)4152 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
4153 {
4154 /* Note: on this STM32 series, there is no flag ADC group injected */
4155 /* end of unitary conversion. */
4156 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4157 /* in other STM32 families). */
4158 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
4159 }
4160
4161 /**
4162 * @brief Get flag ADC analog watchdog 1 flag
4163 * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1
4164 * @param ADCx ADC instance
4165 * @retval State of bit (1 or 0).
4166 */
LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef * ADCx)4167 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
4168 {
4169 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
4170 }
4171
4172 /**
4173 * @brief Clear flag ADC group regular end of unitary conversion
4174 * or end of sequence conversions, depending on
4175 * ADC configuration.
4176 * @note To configure flag of end of conversion,
4177 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4178 * @rmtoll SR EOC LL_ADC_ClearFlag_EOCS
4179 * @param ADCx ADC instance
4180 * @retval None
4181 */
LL_ADC_ClearFlag_EOCS(ADC_TypeDef * ADCx)4182 __STATIC_INLINE void LL_ADC_ClearFlag_EOCS(ADC_TypeDef *ADCx)
4183 {
4184 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOCS);
4185 }
4186
4187 /**
4188 * @brief Clear flag ADC group regular overrun.
4189 * @rmtoll SR OVR LL_ADC_ClearFlag_OVR
4190 * @param ADCx ADC instance
4191 * @retval None
4192 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)4193 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
4194 {
4195 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_OVR);
4196 }
4197
4198
4199 /**
4200 * @brief Clear flag ADC group injected end of sequence conversions.
4201 * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS
4202 * @param ADCx ADC instance
4203 * @retval None
4204 */
LL_ADC_ClearFlag_JEOS(ADC_TypeDef * ADCx)4205 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
4206 {
4207 /* Note: on this STM32 series, there is no flag ADC group injected */
4208 /* end of unitary conversion. */
4209 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4210 /* in other STM32 families). */
4211 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);
4212 }
4213
4214 /**
4215 * @brief Clear flag ADC analog watchdog 1.
4216 * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1
4217 * @param ADCx ADC instance
4218 * @retval None
4219 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)4220 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
4221 {
4222 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);
4223 }
4224
4225 /**
4226 * @brief Get flag multimode ADC group regular end of unitary conversion
4227 * or end of sequence conversions, depending on
4228 * ADC configuration, of the ADC master.
4229 * @note To configure flag of end of conversion,
4230 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4231 * @rmtoll CSR EOC1 LL_ADC_IsActiveFlag_MST_EOCS
4232 * @param ADCxy_COMMON ADC common instance
4233 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4234 * @retval State of bit (1 or 0).
4235 */
LL_ADC_IsActiveFlag_MST_EOCS(ADC_Common_TypeDef * ADCxy_COMMON)4236 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
4237 {
4238 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_MST) == (LL_ADC_FLAG_EOCS_MST));
4239 }
4240
4241 /**
4242 * @brief Get flag multimode ADC group regular end of unitary conversion
4243 * or end of sequence conversions, depending on
4244 * ADC configuration, of the ADC slave 1.
4245 * @note To configure flag of end of conversion,
4246 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4247 * @rmtoll CSR EOC2 LL_ADC_IsActiveFlag_SLV1_EOCS
4248 * @param ADCxy_COMMON ADC common instance
4249 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4250 * @retval State of bit (1 or 0).
4251 */
LL_ADC_IsActiveFlag_SLV1_EOCS(ADC_Common_TypeDef * ADCxy_COMMON)4252 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
4253 {
4254 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV1) == (LL_ADC_FLAG_EOCS_SLV1));
4255 }
4256
4257 /**
4258 * @brief Get flag multimode ADC group regular end of unitary conversion
4259 * or end of sequence conversions, depending on
4260 * ADC configuration, of the ADC slave 2.
4261 * @note To configure flag of end of conversion,
4262 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4263 * @rmtoll CSR EOC3 LL_ADC_IsActiveFlag_SLV2_EOCS
4264 * @param ADCxy_COMMON ADC common instance
4265 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4266 * @retval State of bit (1 or 0).
4267 */
LL_ADC_IsActiveFlag_SLV2_EOCS(ADC_Common_TypeDef * ADCxy_COMMON)4268 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
4269 {
4270 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV2) == (LL_ADC_FLAG_EOCS_SLV2));
4271 }
4272 /**
4273 * @brief Get flag multimode ADC group regular overrun of the ADC master.
4274 * @rmtoll CSR OVR1 LL_ADC_IsActiveFlag_MST_OVR
4275 * @param ADCxy_COMMON ADC common instance
4276 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4277 * @retval State of bit (1 or 0).
4278 */
LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef * ADCxy_COMMON)4279 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
4280 {
4281 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST));
4282 }
4283
4284 /**
4285 * @brief Get flag multimode ADC group regular overrun of the ADC slave 1.
4286 * @rmtoll CSR OVR2 LL_ADC_IsActiveFlag_SLV1_OVR
4287 * @param ADCxy_COMMON ADC common instance
4288 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4289 * @retval State of bit (1 or 0).
4290 */
LL_ADC_IsActiveFlag_SLV1_OVR(ADC_Common_TypeDef * ADCxy_COMMON)4291 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
4292 {
4293 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV1) == (LL_ADC_FLAG_OVR_SLV1));
4294 }
4295
4296 /**
4297 * @brief Get flag multimode ADC group regular overrun of the ADC slave 2.
4298 * @rmtoll CSR OVR3 LL_ADC_IsActiveFlag_SLV2_OVR
4299 * @param ADCxy_COMMON ADC common instance
4300 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4301 * @retval State of bit (1 or 0).
4302 */
LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef * ADCxy_COMMON)4303 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
4304 {
4305 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV2) == (LL_ADC_FLAG_OVR_SLV2));
4306 }
4307
4308
4309 /**
4310 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
4311 * @rmtoll CSR JEOC LL_ADC_IsActiveFlag_MST_EOCS
4312 * @param ADCxy_COMMON ADC common instance
4313 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4314 * @retval State of bit (1 or 0).
4315 */
LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef * ADCxy_COMMON)4316 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
4317 {
4318 /* Note: on this STM32 series, there is no flag ADC group injected */
4319 /* end of unitary conversion. */
4320 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4321 /* in other STM32 families). */
4322 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC1) == (ADC_CSR_JEOC1));
4323 }
4324
4325 /**
4326 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 1.
4327 * @rmtoll CSR JEOC2 LL_ADC_IsActiveFlag_SLV1_JEOS
4328 * @param ADCxy_COMMON ADC common instance
4329 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4330 * @retval State of bit (1 or 0).
4331 */
LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef * ADCxy_COMMON)4332 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
4333 {
4334 /* Note: on this STM32 series, there is no flag ADC group injected */
4335 /* end of unitary conversion. */
4336 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4337 /* in other STM32 families). */
4338 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC2) == (ADC_CSR_JEOC2));
4339 }
4340
4341 /**
4342 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 2.
4343 * @rmtoll CSR JEOC3 LL_ADC_IsActiveFlag_SLV2_JEOS
4344 * @param ADCxy_COMMON ADC common instance
4345 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4346 * @retval State of bit (1 or 0).
4347 */
LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef * ADCxy_COMMON)4348 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
4349 {
4350 /* Note: on this STM32 series, there is no flag ADC group injected */
4351 /* end of unitary conversion. */
4352 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4353 /* in other STM32 families). */
4354 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC3) == (ADC_CSR_JEOC3));
4355 }
4356
4357 /**
4358 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
4359 * @rmtoll CSR AWD1 LL_ADC_IsActiveFlag_MST_AWD1
4360 * @param ADCxy_COMMON ADC common instance
4361 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4362 * @retval State of bit (1 or 0).
4363 */
LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef * ADCxy_COMMON)4364 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
4365 {
4366 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST));
4367 }
4368
4369 /**
4370 * @brief Get flag multimode analog watchdog 1 of the ADC slave 1.
4371 * @rmtoll CSR AWD2 LL_ADC_IsActiveFlag_SLV1_AWD1
4372 * @param ADCxy_COMMON ADC common instance
4373 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4374 * @retval State of bit (1 or 0).
4375 */
LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef * ADCxy_COMMON)4376 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
4377 {
4378 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV1) == (LL_ADC_FLAG_AWD1_SLV1));
4379 }
4380
4381 /**
4382 * @brief Get flag multimode analog watchdog 1 of the ADC slave 2.
4383 * @rmtoll CSR AWD3 LL_ADC_IsActiveFlag_SLV2_AWD1
4384 * @param ADCxy_COMMON ADC common instance
4385 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4386 * @retval State of bit (1 or 0).
4387 */
LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef * ADCxy_COMMON)4388 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
4389 {
4390 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2));
4391 }
4392
4393
4394 /**
4395 * @}
4396 */
4397
4398 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
4399 * @{
4400 */
4401
4402 /**
4403 * @brief Enable interruption ADC group regular end of unitary conversion
4404 * or end of sequence conversions, depending on
4405 * ADC configuration.
4406 * @note To configure flag of end of conversion,
4407 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4408 * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOCS
4409 * @param ADCx ADC instance
4410 * @retval None
4411 */
LL_ADC_EnableIT_EOCS(ADC_TypeDef * ADCx)4412 __STATIC_INLINE void LL_ADC_EnableIT_EOCS(ADC_TypeDef *ADCx)
4413 {
4414 SET_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
4415 }
4416
4417 /**
4418 * @brief Enable ADC group regular interruption overrun.
4419 * @rmtoll CR1 OVRIE LL_ADC_EnableIT_OVR
4420 * @param ADCx ADC instance
4421 * @retval None
4422 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)4423 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
4424 {
4425 SET_BIT(ADCx->CR1, LL_ADC_IT_OVR);
4426 }
4427
4428
4429 /**
4430 * @brief Enable interruption ADC group injected end of sequence conversions.
4431 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
4432 * @param ADCx ADC instance
4433 * @retval None
4434 */
LL_ADC_EnableIT_JEOS(ADC_TypeDef * ADCx)4435 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
4436 {
4437 /* Note: on this STM32 series, there is no flag ADC group injected */
4438 /* end of unitary conversion. */
4439 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4440 /* in other STM32 families). */
4441 SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
4442 }
4443
4444 /**
4445 * @brief Enable interruption ADC analog watchdog 1.
4446 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
4447 * @param ADCx ADC instance
4448 * @retval None
4449 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)4450 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
4451 {
4452 SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
4453 }
4454
4455 /**
4456 * @brief Disable interruption ADC group regular end of unitary conversion
4457 * or end of sequence conversions, depending on
4458 * ADC configuration.
4459 * @note To configure flag of end of conversion,
4460 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4461 * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOCS
4462 * @param ADCx ADC instance
4463 * @retval None
4464 */
LL_ADC_DisableIT_EOCS(ADC_TypeDef * ADCx)4465 __STATIC_INLINE void LL_ADC_DisableIT_EOCS(ADC_TypeDef *ADCx)
4466 {
4467 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
4468 }
4469
4470 /**
4471 * @brief Disable interruption ADC group regular overrun.
4472 * @rmtoll CR1 OVRIE LL_ADC_DisableIT_OVR
4473 * @param ADCx ADC instance
4474 * @retval None
4475 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)4476 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
4477 {
4478 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_OVR);
4479 }
4480
4481
4482 /**
4483 * @brief Disable interruption ADC group injected end of sequence conversions.
4484 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
4485 * @param ADCx ADC instance
4486 * @retval None
4487 */
LL_ADC_DisableIT_JEOS(ADC_TypeDef * ADCx)4488 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
4489 {
4490 /* Note: on this STM32 series, there is no flag ADC group injected */
4491 /* end of unitary conversion. */
4492 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4493 /* in other STM32 families). */
4494 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
4495 }
4496
4497 /**
4498 * @brief Disable interruption ADC analog watchdog 1.
4499 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
4500 * @param ADCx ADC instance
4501 * @retval None
4502 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)4503 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
4504 {
4505 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
4506 }
4507
4508 /**
4509 * @brief Get state of interruption ADC group regular end of unitary conversion
4510 * or end of sequence conversions, depending on
4511 * ADC configuration.
4512 * @note To configure flag of end of conversion,
4513 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4514 * (0: interrupt disabled, 1: interrupt enabled)
4515 * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOCS
4516 * @param ADCx ADC instance
4517 * @retval State of bit (1 or 0).
4518 */
LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef * ADCx)4519 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef *ADCx)
4520 {
4521 return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOCS) == (LL_ADC_IT_EOCS));
4522 }
4523
4524 /**
4525 * @brief Get state of interruption ADC group regular overrun
4526 * (0: interrupt disabled, 1: interrupt enabled).
4527 * @rmtoll CR1 OVRIE LL_ADC_IsEnabledIT_OVR
4528 * @param ADCx ADC instance
4529 * @retval State of bit (1 or 0).
4530 */
LL_ADC_IsEnabledIT_OVR(ADC_TypeDef * ADCx)4531 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
4532 {
4533 return (READ_BIT(ADCx->CR1, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
4534 }
4535
4536
4537 /**
4538 * @brief Get state of interruption ADC group injected end of sequence conversions
4539 * (0: interrupt disabled, 1: interrupt enabled).
4540 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
4541 * @param ADCx ADC instance
4542 * @retval State of bit (1 or 0).
4543 */
LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef * ADCx)4544 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
4545 {
4546 /* Note: on this STM32 series, there is no flag ADC group injected */
4547 /* end of unitary conversion. */
4548 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4549 /* in other STM32 families). */
4550 return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
4551 }
4552
4553 /**
4554 * @brief Get state of interruption ADC analog watchdog 1
4555 * (0: interrupt disabled, 1: interrupt enabled).
4556 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
4557 * @param ADCx ADC instance
4558 * @retval State of bit (1 or 0).
4559 */
LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef * ADCx)4560 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
4561 {
4562 return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
4563 }
4564
4565 /**
4566 * @}
4567 */
4568
4569 #if defined(USE_FULL_LL_DRIVER)
4570 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
4571 * @{
4572 */
4573
4574 /* Initialization of some features of ADC common parameters and multimode */
4575 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
4576 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
4577 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
4578
4579 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
4580 /* (availability of ADC group injected depends on STM32 families) */
4581 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
4582
4583 /* Initialization of some features of ADC instance */
4584 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
4585 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
4586
4587 /* Initialization of some features of ADC instance and ADC group regular */
4588 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
4589 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
4590
4591 /* Initialization of some features of ADC instance and ADC group injected */
4592 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
4593 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
4594
4595 /**
4596 * @}
4597 */
4598 #endif /* USE_FULL_LL_DRIVER */
4599
4600 /**
4601 * @}
4602 */
4603
4604 /**
4605 * @}
4606 */
4607
4608 #endif /* ADC1 || ADC2 || ADC3 */
4609
4610 /**
4611 * @}
4612 */
4613
4614 #ifdef __cplusplus
4615 }
4616 #endif
4617
4618 #endif /* __STM32F2xx_LL_ADC_H */
4619
4620
