1 /**
2 ******************************************************************************
3 * @file stm32f2xx_hal_pwr.c
4 * @author MCD Application Team
5 * @brief PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller (PWR) peripheral:
8 * + Initialization and de-initialization functions
9 * + Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2017 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file
18 * in the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 *
21 ******************************************************************************
22 */
23
24 /* Includes ------------------------------------------------------------------*/
25 #include "stm32f2xx_hal.h"
26
27 /** @addtogroup STM32F2xx_HAL_Driver
28 * @{
29 */
30
31 /** @defgroup PWR PWR
32 * @brief PWR HAL module driver
33 * @{
34 */
35
36 #ifdef HAL_PWR_MODULE_ENABLED
37
38 /* Private typedef -----------------------------------------------------------*/
39 /* Private define ------------------------------------------------------------*/
40 /** @addtogroup PWR_Private_Constants
41 * @{
42 */
43
44 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
45 * @{
46 */
47 #define PVD_MODE_IT 0x00010000U
48 #define PVD_MODE_EVT 0x00020000U
49 #define PVD_RISING_EDGE 0x00000001U
50 #define PVD_FALLING_EDGE 0x00000002U
51 /**
52 * @}
53 */
54
55 /**
56 * @}
57 */
58 /* Private macro -------------------------------------------------------------*/
59 /* Private variables ---------------------------------------------------------*/
60 /* Private function prototypes -----------------------------------------------*/
61 /* Private functions ---------------------------------------------------------*/
62
63 /** @defgroup PWR_Exported_Functions PWR Exported Functions
64 * @{
65 */
66
67 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
68 * @brief Initialization and de-initialization functions
69 *
70 @verbatim
71 ===============================================================================
72 ##### Initialization and de-initialization functions #####
73 ===============================================================================
74 [..]
75 After reset, the backup domain (RTC registers, RTC backup data
76 registers and backup SRAM) is protected against possible unwanted
77 write accesses.
78 To enable access to the RTC Domain and RTC registers, proceed as follows:
79 (+) Enable the Power Controller (PWR) APB1 interface clock using the
80 __HAL_RCC_PWR_CLK_ENABLE() macro.
81 (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
82
83 @endverbatim
84 * @{
85 */
86
87 /**
88 * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
89 * @retval None
90 */
HAL_PWR_DeInit(void)91 void HAL_PWR_DeInit(void)
92 {
93 __HAL_RCC_PWR_FORCE_RESET();
94 __HAL_RCC_PWR_RELEASE_RESET();
95 }
96
97 /**
98 * @brief Enables access to the backup domain (RTC registers, RTC
99 * backup data registers and backup SRAM).
100 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
101 * Backup Domain Access should be kept enabled.
102 * @retval None
103 */
HAL_PWR_EnableBkUpAccess(void)104 void HAL_PWR_EnableBkUpAccess(void)
105 {
106 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
107 }
108
109 /**
110 * @brief Disables access to the backup domain (RTC registers, RTC
111 * backup data registers and backup SRAM).
112 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
113 * Backup Domain Access should be kept enabled.
114 * @retval None
115 */
HAL_PWR_DisableBkUpAccess(void)116 void HAL_PWR_DisableBkUpAccess(void)
117 {
118 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
119 }
120
121 /**
122 * @}
123 */
124
125 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
126 * @brief Low Power modes configuration functions
127 *
128 @verbatim
129
130 ===============================================================================
131 ##### Peripheral Control functions #####
132 ===============================================================================
133
134 *** PVD configuration ***
135 =========================
136 [..]
137 (+) The PVD is used to monitor the VDD power supply by comparing it to a
138 threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
139 (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
140 than the PVD threshold. This event is internally connected to the EXTI
141 line16 and can generate an interrupt if enabled. This is done through
142 __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
143 (+) The PVD is stopped in Standby mode.
144
145 *** Wake-up pin configuration ***
146 ================================
147 [..]
148 (+) Wake-up pin is used to wake up the system from Standby mode. This pin is
149 forced in input pull-down configuration and is active on rising edges.
150 (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00.
151
152 *** Low Power modes configuration ***
153 =====================================
154 [..]
155 The devices feature 3 low-power modes:
156 (+) Sleep mode: Cortex-M3 core stopped, peripherals kept running.
157 (+) Stop mode: all clocks are stopped, regulator running, regulator
158 in low power mode
159 (+) Standby mode: 1.2V domain powered off.
160
161 *** Sleep mode ***
162 ==================
163 [..]
164 (+) Entry:
165 The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)
166 functions with
167 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
168 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
169
170 -@@- The Regulator parameter is not used for the STM32F2 family
171 and is kept as parameter just to maintain compatibility with the
172 lower power families (STM32L).
173 (+) Exit:
174 Any peripheral interrupt acknowledged by the nested vectored interrupt
175 controller (NVIC) can wake up the device from Sleep mode.
176
177 *** Stop mode ***
178 =================
179 [..]
180 In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
181 and the HSE RC oscillators are disabled. Internal SRAM and register contents
182 are preserved.
183 The voltage regulator can be configured either in normal or low-power mode.
184 To minimize the consumption In Stop mode, FLASH can be powered off before
185 entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
186 It can be switched on again by software after exiting the Stop mode using
187 the HAL_PWREx_DisableFlashPowerDown() function.
188
189 (+) Entry:
190 The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON)
191 function with:
192 (++) Main regulator ON.
193 (++) Low Power regulator ON.
194 (+) Exit:
195 Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
196
197 *** Standby mode ***
198 ====================
199 [..]
200 (+)
201 The Standby mode allows to achieve the lowest power consumption. It is based
202 on the Cortex-M3 deep sleep mode, with the voltage regulator disabled.
203 The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
204 the HSE oscillator are also switched off. SRAM and register contents are lost
205 except for the RTC registers, RTC backup registers, backup SRAM and Standby
206 circuitry.
207
208 The voltage regulator is OFF.
209
210 (++) Entry:
211 (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
212 (++) Exit:
213 (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up,
214 tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
215
216 *** Auto-wake-up (AWU) from low-power mode ***
217 =============================================
218 [..]
219
220 (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
221 Wake-up event, a tamper event or a time-stamp event, without depending on
222 an external interrupt (Auto-wake-up mode).
223
224 (+) RTC auto-wake-up (AWU) from the Stop and Standby modes
225
226 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
227 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
228
229 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
230 is necessary to configure the RTC to detect the tamper or time stamp event using the
231 HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
232
233 (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to
234 configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
235
236 @endverbatim
237 * @{
238 */
239
240 /**
241 * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
242 * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
243 * information for the PVD.
244 * @note Refer to the electrical characteristics of your device datasheet for
245 * more details about the voltage threshold corresponding to each
246 * detection level.
247 * @retval None
248 */
HAL_PWR_ConfigPVD(PWR_PVDTypeDef * sConfigPVD)249 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
250 {
251 /* Check the parameters */
252 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
253 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
254
255 /* Set PLS[7:5] bits according to PVDLevel value */
256 MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
257
258 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
259 __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
260 __HAL_PWR_PVD_EXTI_DISABLE_IT();
261 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
262 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
263
264 /* Configure interrupt mode */
265 if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
266 {
267 __HAL_PWR_PVD_EXTI_ENABLE_IT();
268 }
269
270 /* Configure event mode */
271 if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
272 {
273 __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
274 }
275
276 /* Configure the edge */
277 if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
278 {
279 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
280 }
281
282 if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
283 {
284 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
285 }
286 }
287
288 /**
289 * @brief Enables the Power Voltage Detector(PVD).
290 * @retval None
291 */
HAL_PWR_EnablePVD(void)292 void HAL_PWR_EnablePVD(void)
293 {
294 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
295 }
296
297 /**
298 * @brief Disables the Power Voltage Detector(PVD).
299 * @retval None
300 */
HAL_PWR_DisablePVD(void)301 void HAL_PWR_DisablePVD(void)
302 {
303 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
304 }
305
306 /**
307 * @brief Enables the Wake-up PINx functionality.
308 * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
309 * This parameter can be one of the following values:
310 * @arg PWR_WAKEUP_PIN1
311 * @retval None
312 */
HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)313 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
314 {
315 /* Check the parameter */
316 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
317
318 /* Enable the wake up pin */
319 SET_BIT(PWR->CSR, WakeUpPinx);
320 }
321
322 /**
323 * @brief Disables the Wake-up PINx functionality.
324 * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
325 * This parameter can be one of the following values:
326 * @arg PWR_WAKEUP_PIN1
327 * @retval None
328 */
HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)329 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
330 {
331 /* Check the parameter */
332 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
333
334 /* Disable the wake up pin */
335 CLEAR_BIT(PWR->CSR, WakeUpPinx);
336 }
337
338 /**
339 * @brief Enters Sleep mode.
340 *
341 * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
342 *
343 * @note In Sleep mode, the systick is stopped to avoid exit from this mode with
344 * systick interrupt when used as time base for Timeout
345 *
346 * @param Regulator Specifies the regulator state in SLEEP mode.
347 * This parameter can be one of the following values:
348 * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
349 * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
350 * @note This parameter is not used for the STM32F2 family and is kept as parameter
351 * just to maintain compatibility with the lower power families.
352 * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction.
353 * This parameter can be one of the following values:
354 * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
355 * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
356 * @retval None
357 */
HAL_PWR_EnterSLEEPMode(uint32_t Regulator,uint8_t SLEEPEntry)358 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
359 {
360 /* Prevent unused argument(s) compilation warning */
361 UNUSED(Regulator);
362
363 /* Check the parameters */
364 assert_param(IS_PWR_REGULATOR(Regulator));
365 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
366
367 /* Clear SLEEPDEEP bit of Cortex System Control Register */
368 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
369
370 /* Select SLEEP mode entry -------------------------------------------------*/
371 if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
372 {
373 /* Request Wait For Interrupt */
374 __WFI();
375 }
376 else
377 {
378 /* Request Wait For Event */
379 __SEV();
380 __WFE();
381 __WFE();
382 }
383 }
384
385 /**
386 * @brief Enters Stop mode.
387 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
388 * @note When exiting Stop mode by issuing an interrupt or a wake-up event,
389 * the HSI RC oscillator is selected as system clock.
390 * @note When the voltage regulator operates in low power mode, an additional
391 * startup delay is incurred when waking up from Stop mode.
392 * By keeping the internal regulator ON during Stop mode, the consumption
393 * is higher although the startup time is reduced.
394 * @param Regulator Specifies the regulator state in Stop mode.
395 * This parameter can be one of the following values:
396 * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
397 * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
398 * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction.
399 * This parameter can be one of the following values:
400 * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
401 * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
402 * @retval None
403 */
HAL_PWR_EnterSTOPMode(uint32_t Regulator,uint8_t STOPEntry)404 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
405 {
406 /* Check the parameters */
407 assert_param(IS_PWR_REGULATOR(Regulator));
408 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
409
410 /* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator value */
411 MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator);
412
413 /* Set SLEEPDEEP bit of Cortex System Control Register */
414 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
415
416 /* Select Stop mode entry --------------------------------------------------*/
417 if(STOPEntry == PWR_STOPENTRY_WFI)
418 {
419 /* Request Wait For Interrupt */
420 __WFI();
421 }
422 else
423 {
424 /* Request Wait For Event */
425 __SEV();
426 __WFE();
427 __WFE();
428 }
429 /* Reset SLEEPDEEP bit of Cortex System Control Register */
430 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
431 }
432
433 /**
434 * @brief Enters Standby mode.
435 * @note In Standby mode, all I/O pins are high impedance except for:
436 * - Reset pad (still available)
437 * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
438 * Alarm out, or RTC clock calibration out.
439 * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
440 * - WKUP pin 1 (PA0) if enabled.
441 * @retval None
442 */
HAL_PWR_EnterSTANDBYMode(void)443 void HAL_PWR_EnterSTANDBYMode(void)
444 {
445 /* Select Standby mode */
446 SET_BIT(PWR->CR, PWR_CR_PDDS);
447
448 /* Set SLEEPDEEP bit of Cortex System Control Register */
449 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
450
451 /* This option is used to ensure that store operations are completed */
452 #if defined ( __CC_ARM)
453 __force_stores();
454 #endif
455 /* Request Wait For Interrupt */
456 __WFI();
457 }
458
459 /**
460 * @brief This function handles the PWR PVD interrupt request.
461 * @note This API should be called under the PVD_IRQHandler().
462 * @retval None
463 */
HAL_PWR_PVD_IRQHandler(void)464 void HAL_PWR_PVD_IRQHandler(void)
465 {
466 /* Check PWR Exti flag */
467 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
468 {
469 /* PWR PVD interrupt user callback */
470 HAL_PWR_PVDCallback();
471
472 /* Clear PWR Exti pending bit */
473 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
474 }
475 }
476
477 /**
478 * @brief PWR PVD interrupt callback
479 * @retval None
480 */
HAL_PWR_PVDCallback(void)481 __weak void HAL_PWR_PVDCallback(void)
482 {
483 /* NOTE : This function Should not be modified, when the callback is needed,
484 the HAL_PWR_PVDCallback could be implemented in the user file
485 */
486 }
487
488 /**
489 * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
490 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
491 * re-enters SLEEP mode when an interruption handling is over.
492 * Setting this bit is useful when the processor is expected to run only on
493 * interruptions handling.
494 * @retval None
495 */
HAL_PWR_EnableSleepOnExit(void)496 void HAL_PWR_EnableSleepOnExit(void)
497 {
498 /* Set SLEEPONEXIT bit of Cortex System Control Register */
499 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
500 }
501
502 /**
503 * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
504 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
505 * re-enters SLEEP mode when an interruption handling is over.
506 * @retval None
507 */
HAL_PWR_DisableSleepOnExit(void)508 void HAL_PWR_DisableSleepOnExit(void)
509 {
510 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
511 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
512 }
513
514 /**
515 * @brief Enables CORTEX M3 SEVONPEND bit.
516 * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
517 * WFE to wake up when an interrupt moves from inactive to pended.
518 * @retval None
519 */
HAL_PWR_EnableSEVOnPend(void)520 void HAL_PWR_EnableSEVOnPend(void)
521 {
522 /* Set SEVONPEND bit of Cortex System Control Register */
523 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
524 }
525
526 /**
527 * @brief Disables CORTEX M3 SEVONPEND bit.
528 * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
529 * WFE to wake up when an interrupt moves from inactive to pended.
530 * @retval None
531 */
HAL_PWR_DisableSEVOnPend(void)532 void HAL_PWR_DisableSEVOnPend(void)
533 {
534 /* Clear SEVONPEND bit of Cortex System Control Register */
535 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
536 }
537
538 /**
539 * @}
540 */
541
542 /**
543 * @}
544 */
545
546 #endif /* HAL_PWR_MODULE_ENABLED */
547 /**
548 * @}
549 */
550
551 /**
552 * @}
553 */
554
