1 /** 2 ****************************************************************************** 3 * @file stm32f217xx.h 4 * @author MCD Application Team 5 * @brief CMSIS STM32F217xx Device Peripheral Access Layer Header File. 6 * 7 * This file contains : 8 * - Data structures and the address mapping for all peripherals 9 * - Peripherals registers declarations and bits definition 10 * - Macros to access peripheral's registers hardware 11 * 12 ****************************************************************************** 13 * @attention 14 * 15 * Copyright (c) 2017-2021 STMicroelectronics. 16 * All rights reserved. 17 * 18 * This software is licensed under terms that can be found in the LICENSE file 19 * in the root directory of this software component. 20 * If no LICENSE file comes with this software, it is provided AS-IS. 21 * 22 ****************************************************************************** 23 */ 24 25 /** @addtogroup CMSIS_Device 26 * @{ 27 */ 28 29 /** @addtogroup stm32f217xx 30 * @{ 31 */ 32 33 #ifndef __STM32F217xx_H 34 #define __STM32F217xx_H 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif /* __cplusplus */ 39 40 /** @addtogroup Configuration_section_for_CMSIS 41 * @{ 42 */ 43 44 /** 45 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 46 */ 47 #define __CM3_REV 0x0200U /*!< Core revision r0p1 */ 48 #define __MPU_PRESENT 1U /*!< STM32F2XX provides an MPU */ 49 #define __NVIC_PRIO_BITS 4U /*!< STM32F2XX uses 4 Bits for the Priority Levels */ 50 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ 51 52 /** 53 * @} 54 */ 55 56 /** @addtogroup Peripheral_interrupt_number_definition 57 * @{ 58 */ 59 60 /** 61 * @brief STM32F2XX Interrupt Number Definition, according to the selected device 62 * in @ref Library_configuration_section 63 */ 64 typedef enum 65 { 66 /****** Cortex-M3 Processor Exceptions Numbers ****************************************************************/ 67 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 68 HardFault_IRQn = -13, /*!< 3 Hard Fault Interrupt */ 69 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ 70 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ 71 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ 72 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ 73 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ 74 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ 75 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ 76 /****** STM32 specific Interrupt Numbers **********************************************************************/ 77 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 78 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ 79 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ 80 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ 81 FLASH_IRQn = 4, /*!< FLASH global Interrupt */ 82 RCC_IRQn = 5, /*!< RCC global Interrupt */ 83 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ 84 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ 85 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ 86 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ 87 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ 88 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ 89 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ 90 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ 91 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ 92 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ 93 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ 94 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ 95 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ 96 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ 97 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ 98 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ 99 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ 100 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ 101 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ 102 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ 103 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ 104 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ 105 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ 106 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ 107 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ 108 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ 109 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ 110 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ 111 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ 112 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ 113 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ 114 USART1_IRQn = 37, /*!< USART1 global Interrupt */ 115 USART2_IRQn = 38, /*!< USART2 global Interrupt */ 116 USART3_IRQn = 39, /*!< USART3 global Interrupt */ 117 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ 118 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ 119 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ 120 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ 121 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ 122 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ 123 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ 124 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ 125 FSMC_IRQn = 48, /*!< FSMC global Interrupt */ 126 SDIO_IRQn = 49, /*!< SDIO global Interrupt */ 127 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ 128 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ 129 UART4_IRQn = 52, /*!< UART4 global Interrupt */ 130 UART5_IRQn = 53, /*!< UART5 global Interrupt */ 131 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ 132 TIM7_IRQn = 55, /*!< TIM7 global interrupt */ 133 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ 134 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ 135 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ 136 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ 137 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ 138 ETH_IRQn = 61, /*!< Ethernet global Interrupt */ 139 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ 140 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ 141 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ 142 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ 143 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ 144 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ 145 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ 146 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ 147 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ 148 USART6_IRQn = 71, /*!< USART6 global interrupt */ 149 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ 150 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ 151 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ 152 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ 153 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ 154 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ 155 DCMI_IRQn = 78, /*!< DCMI global interrupt */ 156 CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ 157 HASH_RNG_IRQn = 80 /*!< Hash and Rng global interrupt */ 158 } IRQn_Type; 159 160 /** 161 * @} 162 */ 163 164 #include "core_cm3.h" 165 #include "system_stm32f2xx.h" 166 #include <stdint.h> 167 168 /** @addtogroup Peripheral_registers_structures 169 * @{ 170 */ 171 172 /** 173 * @brief Analog to Digital Converter 174 */ 175 176 typedef struct 177 { 178 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ 179 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ 180 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ 181 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ 182 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ 183 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ 184 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ 185 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ 186 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ 187 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ 188 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ 189 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ 190 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ 191 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ 192 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38 */ 193 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ 194 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ 195 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ 196 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ 197 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ 198 } ADC_TypeDef; 199 200 typedef struct 201 { 202 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ 203 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ 204 __IO uint32_t CDR; /*!< ADC common regular data register for dual 205 AND triple modes, Address offset: ADC1 base address + 0x308 */ 206 } ADC_Common_TypeDef; 207 208 209 /** 210 * @brief Controller Area Network TxMailBox 211 */ 212 213 typedef struct 214 { 215 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ 216 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ 217 __IO uint32_t TDLR; /*!< CAN mailbox data low register */ 218 __IO uint32_t TDHR; /*!< CAN mailbox data high register */ 219 } CAN_TxMailBox_TypeDef; 220 221 /** 222 * @brief Controller Area Network FIFOMailBox 223 */ 224 225 typedef struct 226 { 227 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ 228 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ 229 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ 230 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ 231 } CAN_FIFOMailBox_TypeDef; 232 233 /** 234 * @brief Controller Area Network FilterRegister 235 */ 236 237 typedef struct 238 { 239 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ 240 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ 241 } CAN_FilterRegister_TypeDef; 242 243 /** 244 * @brief Controller Area Network 245 */ 246 247 typedef struct 248 { 249 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ 250 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ 251 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ 252 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ 253 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ 254 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ 255 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ 256 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ 257 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ 258 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ 259 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ 260 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ 261 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ 262 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ 263 uint32_t RESERVED2; /*!< Reserved, 0x208 */ 264 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ 265 uint32_t RESERVED3; /*!< Reserved, 0x210 */ 266 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ 267 uint32_t RESERVED4; /*!< Reserved, 0x218 */ 268 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ 269 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ 270 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ 271 } CAN_TypeDef; 272 273 /** 274 * @brief CRC calculation unit 275 */ 276 277 typedef struct 278 { 279 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ 280 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ 281 uint8_t RESERVED0; /*!< Reserved, 0x05 */ 282 uint16_t RESERVED1; /*!< Reserved, 0x06 */ 283 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ 284 } CRC_TypeDef; 285 286 /** 287 * @brief Digital to Analog Converter 288 */ 289 290 typedef struct 291 { 292 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ 293 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ 294 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ 295 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ 296 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ 297 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ 298 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ 299 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ 300 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ 301 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ 302 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ 303 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ 304 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ 305 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ 306 } DAC_TypeDef; 307 308 /** 309 * @brief Debug MCU 310 */ 311 312 typedef struct 313 { 314 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ 315 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ 316 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ 317 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ 318 }DBGMCU_TypeDef; 319 320 /** 321 * @brief DCMI 322 */ 323 324 typedef struct 325 { 326 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ 327 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ 328 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ 329 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ 330 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ 331 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ 332 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ 333 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ 334 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ 335 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ 336 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ 337 } DCMI_TypeDef; 338 339 /** 340 * @brief DMA Controller 341 */ 342 343 typedef struct 344 { 345 __IO uint32_t CR; /*!< DMA stream x configuration register */ 346 __IO uint32_t NDTR; /*!< DMA stream x number of data register */ 347 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ 348 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ 349 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ 350 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ 351 } DMA_Stream_TypeDef; 352 353 typedef struct 354 { 355 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ 356 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ 357 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ 358 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ 359 } DMA_TypeDef; 360 361 362 /** 363 * @brief Ethernet MAC 364 */ 365 366 typedef struct 367 { 368 __IO uint32_t MACCR; 369 __IO uint32_t MACFFR; 370 __IO uint32_t MACHTHR; 371 __IO uint32_t MACHTLR; 372 __IO uint32_t MACMIIAR; 373 __IO uint32_t MACMIIDR; 374 __IO uint32_t MACFCR; 375 __IO uint32_t MACVLANTR; /* 8 */ 376 uint32_t RESERVED0[2]; 377 __IO uint32_t MACRWUFFR; /* 11 */ 378 __IO uint32_t MACPMTCSR; 379 uint32_t RESERVED1; 380 __IO uint32_t MACDBGR; 381 __IO uint32_t MACSR; /* 15 */ 382 __IO uint32_t MACIMR; 383 __IO uint32_t MACA0HR; 384 __IO uint32_t MACA0LR; 385 __IO uint32_t MACA1HR; 386 __IO uint32_t MACA1LR; 387 __IO uint32_t MACA2HR; 388 __IO uint32_t MACA2LR; 389 __IO uint32_t MACA3HR; 390 __IO uint32_t MACA3LR; /* 24 */ 391 uint32_t RESERVED2[40]; 392 __IO uint32_t MMCCR; /* 65 */ 393 __IO uint32_t MMCRIR; 394 __IO uint32_t MMCTIR; 395 __IO uint32_t MMCRIMR; 396 __IO uint32_t MMCTIMR; /* 69 */ 397 uint32_t RESERVED3[14]; 398 __IO uint32_t MMCTGFSCCR; /* 84 */ 399 __IO uint32_t MMCTGFMSCCR; 400 uint32_t RESERVED4[5]; 401 __IO uint32_t MMCTGFCR; 402 uint32_t RESERVED5[10]; 403 __IO uint32_t MMCRFCECR; 404 __IO uint32_t MMCRFAECR; 405 uint32_t RESERVED6[10]; 406 __IO uint32_t MMCRGUFCR; 407 uint32_t RESERVED7[334]; 408 __IO uint32_t PTPTSCR; 409 __IO uint32_t PTPSSIR; 410 __IO uint32_t PTPTSHR; 411 __IO uint32_t PTPTSLR; 412 __IO uint32_t PTPTSHUR; 413 __IO uint32_t PTPTSLUR; 414 __IO uint32_t PTPTSAR; 415 __IO uint32_t PTPTTHR; 416 __IO uint32_t PTPTTLR; 417 __IO uint32_t RESERVED8; 418 __IO uint32_t PTPTSSR; 419 uint32_t RESERVED9[565]; 420 __IO uint32_t DMABMR; 421 __IO uint32_t DMATPDR; 422 __IO uint32_t DMARPDR; 423 __IO uint32_t DMARDLAR; 424 __IO uint32_t DMATDLAR; 425 __IO uint32_t DMASR; 426 __IO uint32_t DMAOMR; 427 __IO uint32_t DMAIER; 428 __IO uint32_t DMAMFBOCR; 429 __IO uint32_t DMARSWTR; 430 uint32_t RESERVED10[8]; 431 __IO uint32_t DMACHTDR; 432 __IO uint32_t DMACHRDR; 433 __IO uint32_t DMACHTBAR; 434 __IO uint32_t DMACHRBAR; 435 } ETH_TypeDef; 436 437 /** 438 * @brief External Interrupt/Event Controller 439 */ 440 441 typedef struct 442 { 443 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ 444 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ 445 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ 446 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ 447 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ 448 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ 449 } EXTI_TypeDef; 450 451 /** 452 * @brief FLASH Registers 453 */ 454 455 typedef struct 456 { 457 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ 458 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ 459 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ 460 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ 461 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ 462 __IO uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x14 */ 463 } FLASH_TypeDef; 464 465 466 /** 467 * @brief Flexible Static Memory Controller 468 */ 469 470 typedef struct 471 { 472 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ 473 } FSMC_Bank1_TypeDef; 474 475 /** 476 * @brief Flexible Static Memory Controller Bank1E 477 */ 478 479 typedef struct 480 { 481 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ 482 } FSMC_Bank1E_TypeDef; 483 484 /** 485 * @brief Flexible Static Memory Controller Bank2 486 */ 487 488 typedef struct 489 { 490 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ 491 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ 492 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ 493 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ 494 uint32_t RESERVED0; /*!< Reserved, 0x70 */ 495 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ 496 uint32_t RESERVED1; /*!< Reserved, 0x78 */ 497 uint32_t RESERVED2; /*!< Reserved, 0x7C */ 498 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ 499 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ 500 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ 501 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ 502 uint32_t RESERVED3; /*!< Reserved, 0x90 */ 503 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ 504 } FSMC_Bank2_3_TypeDef; 505 506 /** 507 * @brief Flexible Static Memory Controller Bank4 508 */ 509 510 typedef struct 511 { 512 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ 513 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ 514 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ 515 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ 516 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ 517 } FSMC_Bank4_TypeDef; 518 519 520 /** 521 * @brief General Purpose I/O 522 */ 523 524 typedef struct 525 { 526 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ 527 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ 528 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ 529 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ 530 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ 531 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ 532 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ 533 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ 534 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ 535 } GPIO_TypeDef; 536 537 /** 538 * @brief System configuration controller 539 */ 540 541 typedef struct 542 { 543 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ 544 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ 545 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ 546 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ 547 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ 548 } SYSCFG_TypeDef; 549 550 /** 551 * @brief Inter-integrated Circuit Interface 552 */ 553 554 typedef struct 555 { 556 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ 557 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ 558 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ 559 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ 560 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ 561 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ 562 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ 563 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ 564 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ 565 } I2C_TypeDef; 566 567 /** 568 * @brief Independent WATCHDOG 569 */ 570 571 typedef struct 572 { 573 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ 574 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ 575 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ 576 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ 577 } IWDG_TypeDef; 578 579 /** 580 * @brief Power Control 581 */ 582 583 typedef struct 584 { 585 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ 586 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ 587 } PWR_TypeDef; 588 589 /** 590 * @brief Reset and Clock Control 591 */ 592 593 typedef struct 594 { 595 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ 596 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ 597 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ 598 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ 599 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ 600 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ 601 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ 602 uint32_t RESERVED0; /*!< Reserved, 0x1C */ 603 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ 604 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ 605 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ 606 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ 607 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ 608 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ 609 uint32_t RESERVED2; /*!< Reserved, 0x3C */ 610 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ 611 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ 612 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ 613 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ 614 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ 615 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ 616 uint32_t RESERVED4; /*!< Reserved, 0x5C */ 617 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ 618 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ 619 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ 620 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ 621 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ 622 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ 623 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ 624 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ 625 626 } RCC_TypeDef; 627 628 /** 629 * @brief Real-Time Clock 630 */ 631 632 typedef struct 633 { 634 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ 635 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ 636 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ 637 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ 638 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ 639 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ 640 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ 641 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ 642 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ 643 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ 644 uint32_t RESERVED1; /*!< Reserved, 0x28 */ 645 uint32_t RESERVED2; /*!< Reserved, 0x2C */ 646 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ 647 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ 648 uint32_t RESERVED3; /*!< Reserved, 0x38 */ 649 uint32_t RESERVED4; /*!< Reserved, 0x3C */ 650 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ 651 uint32_t RESERVED5; /*!< Reserved, 0x44 */ 652 uint32_t RESERVED6; /*!< Reserved, 0x48 */ 653 uint32_t RESERVED7; /*!< Reserved, 0x4C */ 654 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ 655 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ 656 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ 657 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ 658 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ 659 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ 660 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ 661 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ 662 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ 663 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ 664 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ 665 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ 666 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ 667 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ 668 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ 669 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ 670 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ 671 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ 672 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ 673 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ 674 } RTC_TypeDef; 675 676 677 /** 678 * @brief SD host Interface 679 */ 680 681 typedef struct 682 { 683 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ 684 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ 685 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ 686 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ 687 __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ 688 __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ 689 __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ 690 __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ 691 __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ 692 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ 693 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ 694 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ 695 __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ 696 __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ 697 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ 698 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ 699 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ 700 __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ 701 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ 702 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ 703 } SDIO_TypeDef; 704 705 /** 706 * @brief Serial Peripheral Interface 707 */ 708 709 typedef struct 710 { 711 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ 712 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ 713 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ 714 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ 715 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ 716 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ 717 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ 718 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ 719 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ 720 } SPI_TypeDef; 721 722 /** 723 * @brief TIM 724 */ 725 726 typedef struct 727 { 728 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ 729 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ 730 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ 731 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 732 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ 733 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 734 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 735 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 736 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 737 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ 738 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ 739 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 740 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ 741 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 742 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 743 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 744 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 745 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ 746 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ 747 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ 748 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ 749 } TIM_TypeDef; 750 751 /** 752 * @brief Universal Synchronous Asynchronous Receiver Transmitter 753 */ 754 755 typedef struct 756 { 757 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ 758 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ 759 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ 760 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ 761 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ 762 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ 763 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ 764 } USART_TypeDef; 765 766 /** 767 * @brief Window WATCHDOG 768 */ 769 770 typedef struct 771 { 772 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ 773 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ 774 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ 775 } WWDG_TypeDef; 776 777 778 /** 779 * @brief Crypto Processor 780 */ 781 782 typedef struct 783 { 784 __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ 785 __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ 786 __IO uint32_t DIN; /*!< CRYP data input register, Address offset: 0x08 */ 787 __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ 788 __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ 789 __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ 790 __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ 791 __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ 792 __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ 793 __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ 794 __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ 795 __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ 796 __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ 797 __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ 798 __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ 799 __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ 800 __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ 801 __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ 802 __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ 803 __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ 804 } CRYP_TypeDef; 805 806 /** 807 * @brief HASH 808 */ 809 810 typedef struct 811 { 812 __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ 813 __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ 814 __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ 815 __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ 816 __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ 817 __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ 818 uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ 819 __IO uint32_t CSR[51]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1C0 */ 820 } HASH_TypeDef; 821 822 /** 823 * @brief RNG 824 */ 825 826 typedef struct 827 { 828 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ 829 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ 830 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ 831 } RNG_TypeDef; 832 833 834 835 /** 836 * @brief __USB_OTG_Core_register 837 */ 838 typedef struct 839 { 840 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */ 841 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */ 842 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */ 843 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */ 844 __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */ 845 __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */ 846 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */ 847 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */ 848 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */ 849 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */ 850 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */ 851 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */ 852 uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */ 853 __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */ 854 __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */ 855 uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */ 856 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */ 857 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ 858 } 859 USB_OTG_GlobalTypeDef; 860 861 862 863 /** 864 * @brief __device_Registers 865 */ 866 typedef struct 867 { 868 __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */ 869 __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */ 870 __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */ 871 uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */ 872 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask Address offset : 0x810 */ 873 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */ 874 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */ 875 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */ 876 uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */ 877 uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */ 878 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */ 879 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */ 880 __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */ 881 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */ 882 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */ 883 __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */ 884 uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */ 885 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */ 886 uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */ 887 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */ 888 } 889 USB_OTG_DeviceTypeDef; 890 891 892 /** 893 * @brief __IN_Endpoint-Specific_Register 894 */ 895 typedef struct 896 { 897 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ 898 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */ 899 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ 900 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */ 901 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ 902 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ 903 __IO uint32_t DTXFSTS; /* IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ 904 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ 905 } 906 USB_OTG_INEndpointTypeDef; 907 908 909 /** 910 * @brief __OUT_Endpoint-Specific_Registers 911 */ 912 typedef struct 913 { 914 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ 915 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ 916 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ 917 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ 918 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ 919 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ 920 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ 921 } 922 USB_OTG_OUTEndpointTypeDef; 923 924 925 /** 926 * @brief __Host_Mode_Register_Structures 927 */ 928 typedef struct 929 { 930 __IO uint32_t HCFG; /* Host Configuration Register 400h*/ 931 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ 932 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ 933 uint32_t Reserved40C; /* Reserved 40Ch*/ 934 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ 935 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ 936 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ 937 } 938 USB_OTG_HostTypeDef; 939 940 941 /** 942 * @brief __Host_Channel_Specific_Registers 943 */ 944 typedef struct 945 { 946 __IO uint32_t HCCHAR; 947 __IO uint32_t HCSPLT; 948 __IO uint32_t HCINT; 949 __IO uint32_t HCINTMSK; 950 __IO uint32_t HCTSIZ; 951 __IO uint32_t HCDMA; 952 uint32_t Reserved[2]; 953 } 954 USB_OTG_HostChannelTypeDef; 955 956 957 /** 958 * @brief Peripheral_memory_map 959 */ 960 #define FLASH_BASE 0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region */ 961 #define SRAM1_BASE 0x20000000UL /*!< SRAM1(112 KB) base address in the alias region */ 962 #define SRAM2_BASE 0x2001C000UL /*!< SRAM2(16 KB) base address in the alias region */ 963 #define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */ 964 #define BKPSRAM_BASE 0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region */ 965 #define FSMC_R_BASE 0xA0000000UL /*!< FSMC registers base address */ 966 #define SRAM1_BB_BASE 0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region */ 967 #define SRAM2_BB_BASE 0x22380000UL /*!< SRAM2(16 KB) base address in the bit-band region */ 968 #define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */ 969 #define BKPSRAM_BB_BASE 0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region */ 970 #define FLASH_END 0x080FFFFFUL /*!< FLASH end address */ 971 #define FLASH_OTP_BASE 0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */ 972 #define FLASH_OTP_END 0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */ 973 974 /* Legacy defines */ 975 #define SRAM_BASE SRAM1_BASE 976 #define SRAM_BB_BASE SRAM1_BB_BASE 977 978 979 /*!< Peripheral memory map */ 980 #define APB1PERIPH_BASE PERIPH_BASE 981 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) 982 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) 983 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL) 984 985 /*!< APB1 peripherals */ 986 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) 987 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) 988 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) 989 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) 990 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) 991 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) 992 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL) 993 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL) 994 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL) 995 #define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) 996 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) 997 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) 998 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) 999 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) 1000 #define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) 1001 #define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) 1002 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) 1003 #define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) 1004 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) 1005 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) 1006 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) 1007 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) 1008 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL) 1009 #define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) 1010 #define DAC_BASE (APB1PERIPH_BASE + 0x7400UL) 1011 1012 /*!< APB2 peripherals */ 1013 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL) 1014 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL) 1015 #define USART1_BASE (APB2PERIPH_BASE + 0x1000UL) 1016 #define USART6_BASE (APB2PERIPH_BASE + 0x1400UL) 1017 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL) 1018 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL) 1019 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL) 1020 #define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL) 1021 /* Legacy define */ 1022 #define ADC_BASE ADC123_COMMON_BASE 1023 1024 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL) 1025 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) 1026 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL) 1027 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL) 1028 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL) 1029 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL) 1030 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL) 1031 1032 /*!< AHB1 peripherals */ 1033 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL) 1034 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL) 1035 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL) 1036 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL) 1037 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL) 1038 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL) 1039 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL) 1040 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL) 1041 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL) 1042 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) 1043 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL) 1044 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL) 1045 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL) 1046 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) 1047 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) 1048 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) 1049 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) 1050 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) 1051 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) 1052 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) 1053 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) 1054 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL) 1055 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) 1056 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) 1057 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) 1058 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) 1059 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) 1060 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) 1061 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) 1062 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) 1063 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL) 1064 #define ETH_MAC_BASE (ETH_BASE) 1065 #define ETH_MMC_BASE (ETH_BASE + 0x0100UL) 1066 #define ETH_PTP_BASE (ETH_BASE + 0x0700UL) 1067 #define ETH_DMA_BASE (ETH_BASE + 0x1000UL) 1068 1069 /*!< AHB2 peripherals */ 1070 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL) 1071 #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000UL) 1072 #define HASH_BASE (AHB2PERIPH_BASE + 0x60400UL) 1073 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL) 1074 1075 /*!< FSMC Bankx registers base address */ 1076 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000UL) 1077 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104UL) 1078 #define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060UL) 1079 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0UL) 1080 1081 /* Debug MCU registers base address */ 1082 #define DBGMCU_BASE 0xE0042000UL 1083 1084 /*!< USB registers base address */ 1085 #define USB_OTG_HS_PERIPH_BASE 0x40040000UL 1086 #define USB_OTG_FS_PERIPH_BASE 0x50000000UL 1087 1088 #define USB_OTG_GLOBAL_BASE 0x000UL 1089 #define USB_OTG_DEVICE_BASE 0x800UL 1090 #define USB_OTG_IN_ENDPOINT_BASE 0x900UL 1091 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL 1092 #define USB_OTG_EP_REG_SIZE 0x20UL 1093 #define USB_OTG_HOST_BASE 0x400UL 1094 #define USB_OTG_HOST_PORT_BASE 0x440UL 1095 #define USB_OTG_HOST_CHANNEL_BASE 0x500UL 1096 #define USB_OTG_HOST_CHANNEL_SIZE 0x20UL 1097 #define USB_OTG_PCGCCTL_BASE 0xE00UL 1098 #define USB_OTG_FIFO_BASE 0x1000UL 1099 #define USB_OTG_FIFO_SIZE 0x1000UL 1100 1101 /******************* Device electronic signature ***************/ 1102 #define UID_BASE 0x1FFF7A10UL /*!< Unique device ID register base address */ 1103 #define FLASHSIZE_BASE 0x1FFF7A22UL /*!< FLASH Size register base address */ 1104 1105 /** 1106 * @} 1107 */ 1108 1109 /** @addtogroup Peripheral_declaration 1110 * @{ 1111 */ 1112 #define TIM2 ((TIM_TypeDef *) TIM2_BASE) 1113 #define TIM3 ((TIM_TypeDef *) TIM3_BASE) 1114 #define TIM4 ((TIM_TypeDef *) TIM4_BASE) 1115 #define TIM5 ((TIM_TypeDef *) TIM5_BASE) 1116 #define TIM6 ((TIM_TypeDef *) TIM6_BASE) 1117 #define TIM7 ((TIM_TypeDef *) TIM7_BASE) 1118 #define TIM12 ((TIM_TypeDef *) TIM12_BASE) 1119 #define TIM13 ((TIM_TypeDef *) TIM13_BASE) 1120 #define TIM14 ((TIM_TypeDef *) TIM14_BASE) 1121 #define RTC ((RTC_TypeDef *) RTC_BASE) 1122 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 1123 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 1124 #define SPI2 ((SPI_TypeDef *) SPI2_BASE) 1125 #define SPI3 ((SPI_TypeDef *) SPI3_BASE) 1126 #define USART2 ((USART_TypeDef *) USART2_BASE) 1127 #define USART3 ((USART_TypeDef *) USART3_BASE) 1128 #define UART4 ((USART_TypeDef *) UART4_BASE) 1129 #define UART5 ((USART_TypeDef *) UART5_BASE) 1130 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 1131 #define I2C2 ((I2C_TypeDef *) I2C2_BASE) 1132 #define I2C3 ((I2C_TypeDef *) I2C3_BASE) 1133 #define CAN1 ((CAN_TypeDef *) CAN1_BASE) 1134 #define CAN2 ((CAN_TypeDef *) CAN2_BASE) 1135 #define PWR ((PWR_TypeDef *) PWR_BASE) 1136 #define DAC1 ((DAC_TypeDef *) DAC_BASE) 1137 #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */ 1138 #define TIM1 ((TIM_TypeDef *) TIM1_BASE) 1139 #define TIM8 ((TIM_TypeDef *) TIM8_BASE) 1140 #define USART1 ((USART_TypeDef *) USART1_BASE) 1141 #define USART6 ((USART_TypeDef *) USART6_BASE) 1142 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 1143 #define ADC2 ((ADC_TypeDef *) ADC2_BASE) 1144 #define ADC3 ((ADC_TypeDef *) ADC3_BASE) 1145 #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE) 1146 /* Legacy define */ 1147 #define ADC ADC123_COMMON 1148 #define SDIO ((SDIO_TypeDef *) SDIO_BASE) 1149 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 1150 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 1151 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 1152 #define TIM9 ((TIM_TypeDef *) TIM9_BASE) 1153 #define TIM10 ((TIM_TypeDef *) TIM10_BASE) 1154 #define TIM11 ((TIM_TypeDef *) TIM11_BASE) 1155 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 1156 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 1157 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 1158 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) 1159 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) 1160 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) 1161 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) 1162 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) 1163 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) 1164 #define CRC ((CRC_TypeDef *) CRC_BASE) 1165 #define RCC ((RCC_TypeDef *) RCC_BASE) 1166 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 1167 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 1168 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) 1169 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) 1170 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) 1171 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) 1172 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) 1173 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) 1174 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) 1175 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) 1176 #define DMA2 ((DMA_TypeDef *) DMA2_BASE) 1177 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) 1178 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) 1179 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) 1180 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) 1181 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) 1182 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) 1183 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) 1184 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) 1185 #define ETH ((ETH_TypeDef *) ETH_BASE) 1186 #define DCMI ((DCMI_TypeDef *) DCMI_BASE) 1187 #define CRYP ((CRYP_TypeDef *) CRYP_BASE) 1188 #define HASH ((HASH_TypeDef *) HASH_BASE) 1189 #define RNG ((RNG_TypeDef *) RNG_BASE) 1190 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) 1191 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) 1192 #define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE) 1193 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) 1194 1195 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 1196 1197 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) 1198 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) 1199 1200 /** 1201 * @} 1202 */ 1203 1204 /** @addtogroup Exported_constants 1205 * @{ 1206 */ 1207 1208 /** @addtogroup Hardware_Constant_Definition 1209 * @{ 1210 */ 1211 #define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ 1212 /** 1213 * @} 1214 */ 1215 1216 /** @addtogroup Peripheral_Registers_Bits_Definition 1217 * @{ 1218 */ 1219 1220 /******************************************************************************/ 1221 /* Peripheral Registers_Bits_Definition */ 1222 /******************************************************************************/ 1223 1224 /******************************************************************************/ 1225 /* */ 1226 /* Analog to Digital Converter */ 1227 /* */ 1228 /******************************************************************************/ 1229 /******************** Bit definition for ADC_SR register ********************/ 1230 #define ADC_SR_AWD_Pos (0U) 1231 #define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */ 1232 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */ 1233 #define ADC_SR_EOC_Pos (1U) 1234 #define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos) /*!< 0x00000002 */ 1235 #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */ 1236 #define ADC_SR_JEOC_Pos (2U) 1237 #define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos) /*!< 0x00000004 */ 1238 #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */ 1239 #define ADC_SR_JSTRT_Pos (3U) 1240 #define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ 1241 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */ 1242 #define ADC_SR_STRT_Pos (4U) 1243 #define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */ 1244 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */ 1245 #define ADC_SR_OVR_Pos (5U) 1246 #define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos) /*!< 0x00000020 */ 1247 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */ 1248 1249 /******************* Bit definition for ADC_CR1 register ********************/ 1250 #define ADC_CR1_AWDCH_Pos (0U) 1251 #define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ 1252 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */ 1253 #define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ 1254 #define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ 1255 #define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ 1256 #define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ 1257 #define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ 1258 #define ADC_CR1_EOCIE_Pos (5U) 1259 #define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */ 1260 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */ 1261 #define ADC_CR1_AWDIE_Pos (6U) 1262 #define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ 1263 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */ 1264 #define ADC_CR1_JEOCIE_Pos (7U) 1265 #define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */ 1266 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */ 1267 #define ADC_CR1_SCAN_Pos (8U) 1268 #define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ 1269 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */ 1270 #define ADC_CR1_AWDSGL_Pos (9U) 1271 #define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ 1272 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */ 1273 #define ADC_CR1_JAUTO_Pos (10U) 1274 #define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ 1275 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */ 1276 #define ADC_CR1_DISCEN_Pos (11U) 1277 #define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ 1278 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */ 1279 #define ADC_CR1_JDISCEN_Pos (12U) 1280 #define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ 1281 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */ 1282 #define ADC_CR1_DISCNUM_Pos (13U) 1283 #define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ 1284 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */ 1285 #define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ 1286 #define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ 1287 #define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ 1288 #define ADC_CR1_JAWDEN_Pos (22U) 1289 #define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ 1290 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */ 1291 #define ADC_CR1_AWDEN_Pos (23U) 1292 #define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ 1293 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */ 1294 #define ADC_CR1_RES_Pos (24U) 1295 #define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos) /*!< 0x03000000 */ 1296 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */ 1297 #define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos) /*!< 0x01000000 */ 1298 #define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos) /*!< 0x02000000 */ 1299 #define ADC_CR1_OVRIE_Pos (26U) 1300 #define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */ 1301 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */ 1302 1303 /******************* Bit definition for ADC_CR2 register ********************/ 1304 #define ADC_CR2_ADON_Pos (0U) 1305 #define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ 1306 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */ 1307 #define ADC_CR2_CONT_Pos (1U) 1308 #define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ 1309 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */ 1310 #define ADC_CR2_DMA_Pos (8U) 1311 #define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ 1312 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */ 1313 #define ADC_CR2_DDS_Pos (9U) 1314 #define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos) /*!< 0x00000200 */ 1315 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */ 1316 #define ADC_CR2_EOCS_Pos (10U) 1317 #define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */ 1318 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */ 1319 #define ADC_CR2_ALIGN_Pos (11U) 1320 #define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ 1321 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */ 1322 #define ADC_CR2_JEXTSEL_Pos (16U) 1323 #define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */ 1324 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */ 1325 #define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */ 1326 #define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */ 1327 #define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */ 1328 #define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */ 1329 #define ADC_CR2_JEXTEN_Pos (20U) 1330 #define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */ 1331 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */ 1332 #define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */ 1333 #define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */ 1334 #define ADC_CR2_JSWSTART_Pos (22U) 1335 #define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */ 1336 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */ 1337 #define ADC_CR2_EXTSEL_Pos (24U) 1338 #define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */ 1339 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */ 1340 #define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */ 1341 #define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */ 1342 #define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */ 1343 #define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */ 1344 #define ADC_CR2_EXTEN_Pos (28U) 1345 #define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */ 1346 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */ 1347 #define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */ 1348 #define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */ 1349 #define ADC_CR2_SWSTART_Pos (30U) 1350 #define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */ 1351 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */ 1352 1353 /****************** Bit definition for ADC_SMPR1 register *******************/ 1354 #define ADC_SMPR1_SMP10_Pos (0U) 1355 #define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */ 1356 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */ 1357 #define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */ 1358 #define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */ 1359 #define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */ 1360 #define ADC_SMPR1_SMP11_Pos (3U) 1361 #define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */ 1362 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */ 1363 #define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */ 1364 #define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */ 1365 #define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */ 1366 #define ADC_SMPR1_SMP12_Pos (6U) 1367 #define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */ 1368 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */ 1369 #define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */ 1370 #define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */ 1371 #define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */ 1372 #define ADC_SMPR1_SMP13_Pos (9U) 1373 #define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */ 1374 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */ 1375 #define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */ 1376 #define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */ 1377 #define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */ 1378 #define ADC_SMPR1_SMP14_Pos (12U) 1379 #define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */ 1380 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */ 1381 #define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */ 1382 #define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */ 1383 #define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */ 1384 #define ADC_SMPR1_SMP15_Pos (15U) 1385 #define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */ 1386 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */ 1387 #define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */ 1388 #define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */ 1389 #define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */ 1390 #define ADC_SMPR1_SMP16_Pos (18U) 1391 #define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */ 1392 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */ 1393 #define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */ 1394 #define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */ 1395 #define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */ 1396 #define ADC_SMPR1_SMP17_Pos (21U) 1397 #define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */ 1398 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */ 1399 #define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */ 1400 #define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */ 1401 #define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */ 1402 #define ADC_SMPR1_SMP18_Pos (24U) 1403 #define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */ 1404 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */ 1405 #define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */ 1406 #define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */ 1407 #define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */ 1408 1409 /****************** Bit definition for ADC_SMPR2 register *******************/ 1410 #define ADC_SMPR2_SMP0_Pos (0U) 1411 #define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */ 1412 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */ 1413 #define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */ 1414 #define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */ 1415 #define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */ 1416 #define ADC_SMPR2_SMP1_Pos (3U) 1417 #define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */ 1418 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */ 1419 #define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */ 1420 #define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */ 1421 #define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */ 1422 #define ADC_SMPR2_SMP2_Pos (6U) 1423 #define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */ 1424 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */ 1425 #define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */ 1426 #define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */ 1427 #define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */ 1428 #define ADC_SMPR2_SMP3_Pos (9U) 1429 #define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */ 1430 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */ 1431 #define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */ 1432 #define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */ 1433 #define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */ 1434 #define ADC_SMPR2_SMP4_Pos (12U) 1435 #define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */ 1436 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */ 1437 #define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */ 1438 #define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */ 1439 #define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */ 1440 #define ADC_SMPR2_SMP5_Pos (15U) 1441 #define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */ 1442 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */ 1443 #define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */ 1444 #define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */ 1445 #define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */ 1446 #define ADC_SMPR2_SMP6_Pos (18U) 1447 #define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */ 1448 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */ 1449 #define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */ 1450 #define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */ 1451 #define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */ 1452 #define ADC_SMPR2_SMP7_Pos (21U) 1453 #define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */ 1454 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */ 1455 #define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */ 1456 #define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */ 1457 #define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */ 1458 #define ADC_SMPR2_SMP8_Pos (24U) 1459 #define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */ 1460 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */ 1461 #define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */ 1462 #define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */ 1463 #define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */ 1464 #define ADC_SMPR2_SMP9_Pos (27U) 1465 #define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */ 1466 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */ 1467 #define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */ 1468 #define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */ 1469 #define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */ 1470 1471 /****************** Bit definition for ADC_JOFR1 register *******************/ 1472 #define ADC_JOFR1_JOFFSET1_Pos (0U) 1473 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ 1474 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */ 1475 1476 /****************** Bit definition for ADC_JOFR2 register *******************/ 1477 #define ADC_JOFR2_JOFFSET2_Pos (0U) 1478 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ 1479 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */ 1480 1481 /****************** Bit definition for ADC_JOFR3 register *******************/ 1482 #define ADC_JOFR3_JOFFSET3_Pos (0U) 1483 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ 1484 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */ 1485 1486 /****************** Bit definition for ADC_JOFR4 register *******************/ 1487 #define ADC_JOFR4_JOFFSET4_Pos (0U) 1488 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ 1489 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */ 1490 1491 /******************* Bit definition for ADC_HTR register ********************/ 1492 #define ADC_HTR_HT_Pos (0U) 1493 #define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ 1494 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */ 1495 1496 /******************* Bit definition for ADC_LTR register ********************/ 1497 #define ADC_LTR_LT_Pos (0U) 1498 #define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ 1499 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */ 1500 1501 /******************* Bit definition for ADC_SQR1 register *******************/ 1502 #define ADC_SQR1_SQ13_Pos (0U) 1503 #define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ 1504 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */ 1505 #define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ 1506 #define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */ 1507 #define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */ 1508 #define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ 1509 #define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ 1510 #define ADC_SQR1_SQ14_Pos (5U) 1511 #define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ 1512 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */ 1513 #define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ 1514 #define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */ 1515 #define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */ 1516 #define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ 1517 #define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ 1518 #define ADC_SQR1_SQ15_Pos (10U) 1519 #define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ 1520 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */ 1521 #define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ 1522 #define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */ 1523 #define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */ 1524 #define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ 1525 #define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ 1526 #define ADC_SQR1_SQ16_Pos (15U) 1527 #define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ 1528 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */ 1529 #define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ 1530 #define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */ 1531 #define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */ 1532 #define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ 1533 #define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ 1534 #define ADC_SQR1_L_Pos (20U) 1535 #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ 1536 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */ 1537 #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */ 1538 #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */ 1539 #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */ 1540 #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */ 1541 1542 /******************* Bit definition for ADC_SQR2 register *******************/ 1543 #define ADC_SQR2_SQ7_Pos (0U) 1544 #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ 1545 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */ 1546 #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ 1547 #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */ 1548 #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */ 1549 #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ 1550 #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ 1551 #define ADC_SQR2_SQ8_Pos (5U) 1552 #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ 1553 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */ 1554 #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ 1555 #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */ 1556 #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */ 1557 #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ 1558 #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ 1559 #define ADC_SQR2_SQ9_Pos (10U) 1560 #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ 1561 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */ 1562 #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ 1563 #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */ 1564 #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */ 1565 #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ 1566 #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ 1567 #define ADC_SQR2_SQ10_Pos (15U) 1568 #define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ 1569 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */ 1570 #define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ 1571 #define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */ 1572 #define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */ 1573 #define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ 1574 #define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ 1575 #define ADC_SQR2_SQ11_Pos (20U) 1576 #define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ 1577 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */ 1578 #define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ 1579 #define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */ 1580 #define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */ 1581 #define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ 1582 #define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ 1583 #define ADC_SQR2_SQ12_Pos (25U) 1584 #define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ 1585 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */ 1586 #define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ 1587 #define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */ 1588 #define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */ 1589 #define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */ 1590 #define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ 1591 1592 /******************* Bit definition for ADC_SQR3 register *******************/ 1593 #define ADC_SQR3_SQ1_Pos (0U) 1594 #define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ 1595 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */ 1596 #define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ 1597 #define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */ 1598 #define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */ 1599 #define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ 1600 #define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ 1601 #define ADC_SQR3_SQ2_Pos (5U) 1602 #define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ 1603 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */ 1604 #define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ 1605 #define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */ 1606 #define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */ 1607 #define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ 1608 #define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ 1609 #define ADC_SQR3_SQ3_Pos (10U) 1610 #define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ 1611 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */ 1612 #define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ 1613 #define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */ 1614 #define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */ 1615 #define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ 1616 #define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ 1617 #define ADC_SQR3_SQ4_Pos (15U) 1618 #define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ 1619 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */ 1620 #define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ 1621 #define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */ 1622 #define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */ 1623 #define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ 1624 #define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */ 1625 #define ADC_SQR3_SQ5_Pos (20U) 1626 #define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */ 1627 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */ 1628 #define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */ 1629 #define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */ 1630 #define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */ 1631 #define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */ 1632 #define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ 1633 #define ADC_SQR3_SQ6_Pos (25U) 1634 #define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ 1635 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */ 1636 #define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ 1637 #define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */ 1638 #define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */ 1639 #define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */ 1640 #define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */ 1641 1642 /******************* Bit definition for ADC_JSQR register *******************/ 1643 #define ADC_JSQR_JSQ1_Pos (0U) 1644 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ 1645 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */ 1646 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ 1647 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ 1648 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ 1649 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ 1650 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ 1651 #define ADC_JSQR_JSQ2_Pos (5U) 1652 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ 1653 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */ 1654 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ 1655 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ 1656 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ 1657 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ 1658 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ 1659 #define ADC_JSQR_JSQ3_Pos (10U) 1660 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ 1661 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */ 1662 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ 1663 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ 1664 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ 1665 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ 1666 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ 1667 #define ADC_JSQR_JSQ4_Pos (15U) 1668 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ 1669 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */ 1670 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ 1671 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ 1672 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ 1673 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ 1674 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ 1675 #define ADC_JSQR_JL_Pos (20U) 1676 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ 1677 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */ 1678 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ 1679 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ 1680 1681 /******************* Bit definition for ADC_JDR1 register *******************/ 1682 #define ADC_JDR1_JDATA_Pos (0U) 1683 #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ 1684 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */ 1685 1686 /******************* Bit definition for ADC_JDR2 register *******************/ 1687 #define ADC_JDR2_JDATA_Pos (0U) 1688 #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ 1689 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */ 1690 1691 /******************* Bit definition for ADC_JDR3 register *******************/ 1692 #define ADC_JDR3_JDATA_Pos (0U) 1693 #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ 1694 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */ 1695 1696 /******************* Bit definition for ADC_JDR4 register *******************/ 1697 #define ADC_JDR4_JDATA_Pos (0U) 1698 #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ 1699 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */ 1700 1701 /******************** Bit definition for ADC_DR register ********************/ 1702 #define ADC_DR_DATA_Pos (0U) 1703 #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ 1704 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */ 1705 #define ADC_DR_ADC2DATA_Pos (16U) 1706 #define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */ 1707 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */ 1708 1709 /******************* Bit definition for ADC_CSR register ********************/ 1710 #define ADC_CSR_AWD1_Pos (0U) 1711 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */ 1712 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */ 1713 #define ADC_CSR_EOC1_Pos (1U) 1714 #define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */ 1715 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */ 1716 #define ADC_CSR_JEOC1_Pos (2U) 1717 #define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */ 1718 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */ 1719 #define ADC_CSR_JSTRT1_Pos (3U) 1720 #define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */ 1721 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */ 1722 #define ADC_CSR_STRT1_Pos (4U) 1723 #define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */ 1724 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */ 1725 #define ADC_CSR_OVR1_Pos (5U) 1726 #define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */ 1727 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */ 1728 #define ADC_CSR_AWD2_Pos (8U) 1729 #define ADC_CSR_AWD2_Msk (0x1UL << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */ 1730 #define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */ 1731 #define ADC_CSR_EOC2_Pos (9U) 1732 #define ADC_CSR_EOC2_Msk (0x1UL << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */ 1733 #define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */ 1734 #define ADC_CSR_JEOC2_Pos (10U) 1735 #define ADC_CSR_JEOC2_Msk (0x1UL << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */ 1736 #define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */ 1737 #define ADC_CSR_JSTRT2_Pos (11U) 1738 #define ADC_CSR_JSTRT2_Msk (0x1UL << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */ 1739 #define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */ 1740 #define ADC_CSR_STRT2_Pos (12U) 1741 #define ADC_CSR_STRT2_Msk (0x1UL << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */ 1742 #define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */ 1743 #define ADC_CSR_OVR2_Pos (13U) 1744 #define ADC_CSR_OVR2_Msk (0x1UL << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */ 1745 #define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 DMA overrun flag */ 1746 #define ADC_CSR_AWD3_Pos (16U) 1747 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */ 1748 #define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */ 1749 #define ADC_CSR_EOC3_Pos (17U) 1750 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */ 1751 #define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */ 1752 #define ADC_CSR_JEOC3_Pos (18U) 1753 #define ADC_CSR_JEOC3_Msk (0x1UL << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */ 1754 #define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */ 1755 #define ADC_CSR_JSTRT3_Pos (19U) 1756 #define ADC_CSR_JSTRT3_Msk (0x1UL << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */ 1757 #define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */ 1758 #define ADC_CSR_STRT3_Pos (20U) 1759 #define ADC_CSR_STRT3_Msk (0x1UL << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */ 1760 #define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */ 1761 #define ADC_CSR_OVR3_Pos (21U) 1762 #define ADC_CSR_OVR3_Msk (0x1UL << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */ 1763 #define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 DMA overrun flag */ 1764 1765 /* Legacy defines */ 1766 #define ADC_CSR_DOVR1 ADC_CSR_OVR1 1767 #define ADC_CSR_DOVR2 ADC_CSR_OVR2 1768 #define ADC_CSR_DOVR3 ADC_CSR_OVR3 1769 1770 /******************* Bit definition for ADC_CCR register ********************/ 1771 #define ADC_CCR_MULTI_Pos (0U) 1772 #define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */ 1773 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */ 1774 #define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */ 1775 #define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */ 1776 #define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */ 1777 #define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */ 1778 #define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */ 1779 #define ADC_CCR_DELAY_Pos (8U) 1780 #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ 1781 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */ 1782 #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ 1783 #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ 1784 #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ 1785 #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ 1786 #define ADC_CCR_DDS_Pos (13U) 1787 #define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos) /*!< 0x00002000 */ 1788 #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */ 1789 #define ADC_CCR_DMA_Pos (14U) 1790 #define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */ 1791 #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */ 1792 #define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos) /*!< 0x00004000 */ 1793 #define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos) /*!< 0x00008000 */ 1794 #define ADC_CCR_ADCPRE_Pos (16U) 1795 #define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */ 1796 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */ 1797 #define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */ 1798 #define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */ 1799 #define ADC_CCR_VBATE_Pos (22U) 1800 #define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */ 1801 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */ 1802 #define ADC_CCR_TSVREFE_Pos (23U) 1803 #define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */ 1804 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */ 1805 1806 /******************* Bit definition for ADC_CDR register ********************/ 1807 #define ADC_CDR_DATA1_Pos (0U) 1808 #define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */ 1809 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */ 1810 #define ADC_CDR_DATA2_Pos (16U) 1811 #define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */ 1812 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */ 1813 1814 /* Legacy defines */ 1815 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1 1816 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2 1817 1818 /******************************************************************************/ 1819 /* */ 1820 /* Controller Area Network */ 1821 /* */ 1822 /******************************************************************************/ 1823 /*!<CAN control and status registers */ 1824 /******************* Bit definition for CAN_MCR register ********************/ 1825 #define CAN_MCR_INRQ_Pos (0U) 1826 #define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */ 1827 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */ 1828 #define CAN_MCR_SLEEP_Pos (1U) 1829 #define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */ 1830 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */ 1831 #define CAN_MCR_TXFP_Pos (2U) 1832 #define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */ 1833 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */ 1834 #define CAN_MCR_RFLM_Pos (3U) 1835 #define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */ 1836 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */ 1837 #define CAN_MCR_NART_Pos (4U) 1838 #define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos) /*!< 0x00000010 */ 1839 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */ 1840 #define CAN_MCR_AWUM_Pos (5U) 1841 #define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */ 1842 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */ 1843 #define CAN_MCR_ABOM_Pos (6U) 1844 #define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */ 1845 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */ 1846 #define CAN_MCR_TTCM_Pos (7U) 1847 #define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */ 1848 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */ 1849 #define CAN_MCR_RESET_Pos (15U) 1850 #define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos) /*!< 0x00008000 */ 1851 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */ 1852 #define CAN_MCR_DBF_Pos (16U) 1853 #define CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos) /*!< 0x00010000 */ 1854 #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */ 1855 /******************* Bit definition for CAN_MSR register ********************/ 1856 #define CAN_MSR_INAK_Pos (0U) 1857 #define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos) /*!< 0x00000001 */ 1858 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */ 1859 #define CAN_MSR_SLAK_Pos (1U) 1860 #define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */ 1861 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */ 1862 #define CAN_MSR_ERRI_Pos (2U) 1863 #define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */ 1864 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */ 1865 #define CAN_MSR_WKUI_Pos (3U) 1866 #define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */ 1867 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */ 1868 #define CAN_MSR_SLAKI_Pos (4U) 1869 #define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */ 1870 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */ 1871 #define CAN_MSR_TXM_Pos (8U) 1872 #define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos) /*!< 0x00000100 */ 1873 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */ 1874 #define CAN_MSR_RXM_Pos (9U) 1875 #define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos) /*!< 0x00000200 */ 1876 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */ 1877 #define CAN_MSR_SAMP_Pos (10U) 1878 #define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */ 1879 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */ 1880 #define CAN_MSR_RX_Pos (11U) 1881 #define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos) /*!< 0x00000800 */ 1882 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */ 1883 1884 /******************* Bit definition for CAN_TSR register ********************/ 1885 #define CAN_TSR_RQCP0_Pos (0U) 1886 #define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */ 1887 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */ 1888 #define CAN_TSR_TXOK0_Pos (1U) 1889 #define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */ 1890 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */ 1891 #define CAN_TSR_ALST0_Pos (2U) 1892 #define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */ 1893 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */ 1894 #define CAN_TSR_TERR0_Pos (3U) 1895 #define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */ 1896 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */ 1897 #define CAN_TSR_ABRQ0_Pos (7U) 1898 #define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */ 1899 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */ 1900 #define CAN_TSR_RQCP1_Pos (8U) 1901 #define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */ 1902 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */ 1903 #define CAN_TSR_TXOK1_Pos (9U) 1904 #define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */ 1905 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */ 1906 #define CAN_TSR_ALST1_Pos (10U) 1907 #define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */ 1908 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */ 1909 #define CAN_TSR_TERR1_Pos (11U) 1910 #define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */ 1911 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */ 1912 #define CAN_TSR_ABRQ1_Pos (15U) 1913 #define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */ 1914 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */ 1915 #define CAN_TSR_RQCP2_Pos (16U) 1916 #define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */ 1917 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */ 1918 #define CAN_TSR_TXOK2_Pos (17U) 1919 #define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */ 1920 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */ 1921 #define CAN_TSR_ALST2_Pos (18U) 1922 #define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */ 1923 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */ 1924 #define CAN_TSR_TERR2_Pos (19U) 1925 #define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */ 1926 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */ 1927 #define CAN_TSR_ABRQ2_Pos (23U) 1928 #define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */ 1929 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */ 1930 #define CAN_TSR_CODE_Pos (24U) 1931 #define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos) /*!< 0x03000000 */ 1932 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */ 1933 1934 #define CAN_TSR_TME_Pos (26U) 1935 #define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos) /*!< 0x1C000000 */ 1936 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */ 1937 #define CAN_TSR_TME0_Pos (26U) 1938 #define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos) /*!< 0x04000000 */ 1939 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */ 1940 #define CAN_TSR_TME1_Pos (27U) 1941 #define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos) /*!< 0x08000000 */ 1942 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */ 1943 #define CAN_TSR_TME2_Pos (28U) 1944 #define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos) /*!< 0x10000000 */ 1945 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */ 1946 1947 #define CAN_TSR_LOW_Pos (29U) 1948 #define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */ 1949 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */ 1950 #define CAN_TSR_LOW0_Pos (29U) 1951 #define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */ 1952 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */ 1953 #define CAN_TSR_LOW1_Pos (30U) 1954 #define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */ 1955 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */ 1956 #define CAN_TSR_LOW2_Pos (31U) 1957 #define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */ 1958 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */ 1959 1960 /******************* Bit definition for CAN_RF0R register *******************/ 1961 #define CAN_RF0R_FMP0_Pos (0U) 1962 #define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */ 1963 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */ 1964 #define CAN_RF0R_FULL0_Pos (3U) 1965 #define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */ 1966 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */ 1967 #define CAN_RF0R_FOVR0_Pos (4U) 1968 #define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */ 1969 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */ 1970 #define CAN_RF0R_RFOM0_Pos (5U) 1971 #define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */ 1972 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */ 1973 1974 /******************* Bit definition for CAN_RF1R register *******************/ 1975 #define CAN_RF1R_FMP1_Pos (0U) 1976 #define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */ 1977 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */ 1978 #define CAN_RF1R_FULL1_Pos (3U) 1979 #define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */ 1980 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */ 1981 #define CAN_RF1R_FOVR1_Pos (4U) 1982 #define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */ 1983 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */ 1984 #define CAN_RF1R_RFOM1_Pos (5U) 1985 #define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */ 1986 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */ 1987 1988 /******************** Bit definition for CAN_IER register *******************/ 1989 #define CAN_IER_TMEIE_Pos (0U) 1990 #define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */ 1991 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */ 1992 #define CAN_IER_FMPIE0_Pos (1U) 1993 #define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */ 1994 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */ 1995 #define CAN_IER_FFIE0_Pos (2U) 1996 #define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */ 1997 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */ 1998 #define CAN_IER_FOVIE0_Pos (3U) 1999 #define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */ 2000 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */ 2001 #define CAN_IER_FMPIE1_Pos (4U) 2002 #define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */ 2003 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */ 2004 #define CAN_IER_FFIE1_Pos (5U) 2005 #define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */ 2006 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */ 2007 #define CAN_IER_FOVIE1_Pos (6U) 2008 #define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */ 2009 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */ 2010 #define CAN_IER_EWGIE_Pos (8U) 2011 #define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */ 2012 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */ 2013 #define CAN_IER_EPVIE_Pos (9U) 2014 #define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */ 2015 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */ 2016 #define CAN_IER_BOFIE_Pos (10U) 2017 #define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */ 2018 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */ 2019 #define CAN_IER_LECIE_Pos (11U) 2020 #define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos) /*!< 0x00000800 */ 2021 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */ 2022 #define CAN_IER_ERRIE_Pos (15U) 2023 #define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */ 2024 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */ 2025 #define CAN_IER_WKUIE_Pos (16U) 2026 #define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */ 2027 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */ 2028 #define CAN_IER_SLKIE_Pos (17U) 2029 #define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */ 2030 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */ 2031 2032 /******************** Bit definition for CAN_ESR register *******************/ 2033 #define CAN_ESR_EWGF_Pos (0U) 2034 #define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */ 2035 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */ 2036 #define CAN_ESR_EPVF_Pos (1U) 2037 #define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */ 2038 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */ 2039 #define CAN_ESR_BOFF_Pos (2U) 2040 #define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */ 2041 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */ 2042 2043 #define CAN_ESR_LEC_Pos (4U) 2044 #define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos) /*!< 0x00000070 */ 2045 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */ 2046 #define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos) /*!< 0x00000010 */ 2047 #define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos) /*!< 0x00000020 */ 2048 #define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos) /*!< 0x00000040 */ 2049 2050 #define CAN_ESR_TEC_Pos (16U) 2051 #define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */ 2052 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */ 2053 #define CAN_ESR_REC_Pos (24U) 2054 #define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos) /*!< 0xFF000000 */ 2055 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */ 2056 2057 /******************* Bit definition for CAN_BTR register ********************/ 2058 #define CAN_BTR_BRP_Pos (0U) 2059 #define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos) /*!< 0x000003FF */ 2060 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */ 2061 #define CAN_BTR_TS1_Pos (16U) 2062 #define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */ 2063 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */ 2064 #define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos) /*!< 0x00010000 */ 2065 #define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos) /*!< 0x00020000 */ 2066 #define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos) /*!< 0x00040000 */ 2067 #define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos) /*!< 0x00080000 */ 2068 #define CAN_BTR_TS2_Pos (20U) 2069 #define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos) /*!< 0x00700000 */ 2070 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */ 2071 #define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos) /*!< 0x00100000 */ 2072 #define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos) /*!< 0x00200000 */ 2073 #define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos) /*!< 0x00400000 */ 2074 #define CAN_BTR_SJW_Pos (24U) 2075 #define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos) /*!< 0x03000000 */ 2076 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */ 2077 #define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos) /*!< 0x01000000 */ 2078 #define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos) /*!< 0x02000000 */ 2079 #define CAN_BTR_LBKM_Pos (30U) 2080 #define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */ 2081 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */ 2082 #define CAN_BTR_SILM_Pos (31U) 2083 #define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos) /*!< 0x80000000 */ 2084 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */ 2085 2086 2087 /*!<Mailbox registers */ 2088 /****************** Bit definition for CAN_TI0R register ********************/ 2089 #define CAN_TI0R_TXRQ_Pos (0U) 2090 #define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */ 2091 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */ 2092 #define CAN_TI0R_RTR_Pos (1U) 2093 #define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */ 2094 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */ 2095 #define CAN_TI0R_IDE_Pos (2U) 2096 #define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */ 2097 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */ 2098 #define CAN_TI0R_EXID_Pos (3U) 2099 #define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */ 2100 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */ 2101 #define CAN_TI0R_STID_Pos (21U) 2102 #define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */ 2103 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */ 2104 2105 /****************** Bit definition for CAN_TDT0R register *******************/ 2106 #define CAN_TDT0R_DLC_Pos (0U) 2107 #define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */ 2108 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */ 2109 #define CAN_TDT0R_TGT_Pos (8U) 2110 #define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */ 2111 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */ 2112 #define CAN_TDT0R_TIME_Pos (16U) 2113 #define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */ 2114 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */ 2115 2116 /****************** Bit definition for CAN_TDL0R register *******************/ 2117 #define CAN_TDL0R_DATA0_Pos (0U) 2118 #define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */ 2119 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */ 2120 #define CAN_TDL0R_DATA1_Pos (8U) 2121 #define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */ 2122 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */ 2123 #define CAN_TDL0R_DATA2_Pos (16U) 2124 #define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */ 2125 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */ 2126 #define CAN_TDL0R_DATA3_Pos (24U) 2127 #define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */ 2128 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */ 2129 2130 /****************** Bit definition for CAN_TDH0R register *******************/ 2131 #define CAN_TDH0R_DATA4_Pos (0U) 2132 #define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */ 2133 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */ 2134 #define CAN_TDH0R_DATA5_Pos (8U) 2135 #define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */ 2136 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */ 2137 #define CAN_TDH0R_DATA6_Pos (16U) 2138 #define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */ 2139 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */ 2140 #define CAN_TDH0R_DATA7_Pos (24U) 2141 #define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */ 2142 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */ 2143 2144 /******************* Bit definition for CAN_TI1R register *******************/ 2145 #define CAN_TI1R_TXRQ_Pos (0U) 2146 #define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */ 2147 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */ 2148 #define CAN_TI1R_RTR_Pos (1U) 2149 #define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */ 2150 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */ 2151 #define CAN_TI1R_IDE_Pos (2U) 2152 #define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */ 2153 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */ 2154 #define CAN_TI1R_EXID_Pos (3U) 2155 #define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */ 2156 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */ 2157 #define CAN_TI1R_STID_Pos (21U) 2158 #define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */ 2159 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */ 2160 2161 /******************* Bit definition for CAN_TDT1R register ******************/ 2162 #define CAN_TDT1R_DLC_Pos (0U) 2163 #define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */ 2164 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */ 2165 #define CAN_TDT1R_TGT_Pos (8U) 2166 #define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */ 2167 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */ 2168 #define CAN_TDT1R_TIME_Pos (16U) 2169 #define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */ 2170 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */ 2171 2172 /******************* Bit definition for CAN_TDL1R register ******************/ 2173 #define CAN_TDL1R_DATA0_Pos (0U) 2174 #define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */ 2175 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */ 2176 #define CAN_TDL1R_DATA1_Pos (8U) 2177 #define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */ 2178 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */ 2179 #define CAN_TDL1R_DATA2_Pos (16U) 2180 #define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */ 2181 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */ 2182 #define CAN_TDL1R_DATA3_Pos (24U) 2183 #define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */ 2184 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */ 2185 2186 /******************* Bit definition for CAN_TDH1R register ******************/ 2187 #define CAN_TDH1R_DATA4_Pos (0U) 2188 #define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */ 2189 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */ 2190 #define CAN_TDH1R_DATA5_Pos (8U) 2191 #define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */ 2192 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */ 2193 #define CAN_TDH1R_DATA6_Pos (16U) 2194 #define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */ 2195 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */ 2196 #define CAN_TDH1R_DATA7_Pos (24U) 2197 #define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */ 2198 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */ 2199 2200 /******************* Bit definition for CAN_TI2R register *******************/ 2201 #define CAN_TI2R_TXRQ_Pos (0U) 2202 #define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */ 2203 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */ 2204 #define CAN_TI2R_RTR_Pos (1U) 2205 #define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */ 2206 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */ 2207 #define CAN_TI2R_IDE_Pos (2U) 2208 #define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */ 2209 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */ 2210 #define CAN_TI2R_EXID_Pos (3U) 2211 #define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */ 2212 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */ 2213 #define CAN_TI2R_STID_Pos (21U) 2214 #define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */ 2215 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */ 2216 2217 /******************* Bit definition for CAN_TDT2R register ******************/ 2218 #define CAN_TDT2R_DLC_Pos (0U) 2219 #define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */ 2220 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */ 2221 #define CAN_TDT2R_TGT_Pos (8U) 2222 #define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */ 2223 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */ 2224 #define CAN_TDT2R_TIME_Pos (16U) 2225 #define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */ 2226 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */ 2227 2228 /******************* Bit definition for CAN_TDL2R register ******************/ 2229 #define CAN_TDL2R_DATA0_Pos (0U) 2230 #define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */ 2231 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */ 2232 #define CAN_TDL2R_DATA1_Pos (8U) 2233 #define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */ 2234 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */ 2235 #define CAN_TDL2R_DATA2_Pos (16U) 2236 #define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */ 2237 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */ 2238 #define CAN_TDL2R_DATA3_Pos (24U) 2239 #define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */ 2240 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */ 2241 2242 /******************* Bit definition for CAN_TDH2R register ******************/ 2243 #define CAN_TDH2R_DATA4_Pos (0U) 2244 #define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */ 2245 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */ 2246 #define CAN_TDH2R_DATA5_Pos (8U) 2247 #define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */ 2248 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */ 2249 #define CAN_TDH2R_DATA6_Pos (16U) 2250 #define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */ 2251 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */ 2252 #define CAN_TDH2R_DATA7_Pos (24U) 2253 #define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */ 2254 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */ 2255 2256 /******************* Bit definition for CAN_RI0R register *******************/ 2257 #define CAN_RI0R_RTR_Pos (1U) 2258 #define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */ 2259 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */ 2260 #define CAN_RI0R_IDE_Pos (2U) 2261 #define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */ 2262 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */ 2263 #define CAN_RI0R_EXID_Pos (3U) 2264 #define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */ 2265 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */ 2266 #define CAN_RI0R_STID_Pos (21U) 2267 #define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */ 2268 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */ 2269 2270 /******************* Bit definition for CAN_RDT0R register ******************/ 2271 #define CAN_RDT0R_DLC_Pos (0U) 2272 #define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */ 2273 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */ 2274 #define CAN_RDT0R_FMI_Pos (8U) 2275 #define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */ 2276 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */ 2277 #define CAN_RDT0R_TIME_Pos (16U) 2278 #define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */ 2279 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */ 2280 2281 /******************* Bit definition for CAN_RDL0R register ******************/ 2282 #define CAN_RDL0R_DATA0_Pos (0U) 2283 #define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */ 2284 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */ 2285 #define CAN_RDL0R_DATA1_Pos (8U) 2286 #define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */ 2287 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */ 2288 #define CAN_RDL0R_DATA2_Pos (16U) 2289 #define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */ 2290 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */ 2291 #define CAN_RDL0R_DATA3_Pos (24U) 2292 #define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */ 2293 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */ 2294 2295 /******************* Bit definition for CAN_RDH0R register ******************/ 2296 #define CAN_RDH0R_DATA4_Pos (0U) 2297 #define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */ 2298 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */ 2299 #define CAN_RDH0R_DATA5_Pos (8U) 2300 #define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */ 2301 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */ 2302 #define CAN_RDH0R_DATA6_Pos (16U) 2303 #define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */ 2304 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */ 2305 #define CAN_RDH0R_DATA7_Pos (24U) 2306 #define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */ 2307 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */ 2308 2309 /******************* Bit definition for CAN_RI1R register *******************/ 2310 #define CAN_RI1R_RTR_Pos (1U) 2311 #define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */ 2312 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */ 2313 #define CAN_RI1R_IDE_Pos (2U) 2314 #define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */ 2315 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */ 2316 #define CAN_RI1R_EXID_Pos (3U) 2317 #define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */ 2318 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */ 2319 #define CAN_RI1R_STID_Pos (21U) 2320 #define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */ 2321 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */ 2322 2323 /******************* Bit definition for CAN_RDT1R register ******************/ 2324 #define CAN_RDT1R_DLC_Pos (0U) 2325 #define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */ 2326 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */ 2327 #define CAN_RDT1R_FMI_Pos (8U) 2328 #define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */ 2329 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */ 2330 #define CAN_RDT1R_TIME_Pos (16U) 2331 #define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */ 2332 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */ 2333 2334 /******************* Bit definition for CAN_RDL1R register ******************/ 2335 #define CAN_RDL1R_DATA0_Pos (0U) 2336 #define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */ 2337 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */ 2338 #define CAN_RDL1R_DATA1_Pos (8U) 2339 #define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */ 2340 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */ 2341 #define CAN_RDL1R_DATA2_Pos (16U) 2342 #define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */ 2343 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */ 2344 #define CAN_RDL1R_DATA3_Pos (24U) 2345 #define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */ 2346 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */ 2347 2348 /******************* Bit definition for CAN_RDH1R register ******************/ 2349 #define CAN_RDH1R_DATA4_Pos (0U) 2350 #define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */ 2351 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */ 2352 #define CAN_RDH1R_DATA5_Pos (8U) 2353 #define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */ 2354 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */ 2355 #define CAN_RDH1R_DATA6_Pos (16U) 2356 #define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */ 2357 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */ 2358 #define CAN_RDH1R_DATA7_Pos (24U) 2359 #define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */ 2360 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */ 2361 2362 /*!<CAN filter registers */ 2363 /******************* Bit definition for CAN_FMR register ********************/ 2364 #define CAN_FMR_FINIT_Pos (0U) 2365 #define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */ 2366 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */ 2367 #define CAN_FMR_CAN2SB_Pos (8U) 2368 #define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */ 2369 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */ 2370 2371 /************* Bit definition for CAN_FM1R register *******************/ 2372 #define CAN_FM1R_FBM_Pos (0U) 2373 #define CAN_FM1R_FBM_Msk (0xFFFFFFFUL << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */ 2374 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */ 2375 #define CAN_FM1R_FBM0_Pos (0U) 2376 #define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */ 2377 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */ 2378 #define CAN_FM1R_FBM1_Pos (1U) 2379 #define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */ 2380 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */ 2381 #define CAN_FM1R_FBM2_Pos (2U) 2382 #define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */ 2383 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */ 2384 #define CAN_FM1R_FBM3_Pos (3U) 2385 #define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */ 2386 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */ 2387 #define CAN_FM1R_FBM4_Pos (4U) 2388 #define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */ 2389 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */ 2390 #define CAN_FM1R_FBM5_Pos (5U) 2391 #define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */ 2392 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */ 2393 #define CAN_FM1R_FBM6_Pos (6U) 2394 #define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */ 2395 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */ 2396 #define CAN_FM1R_FBM7_Pos (7U) 2397 #define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */ 2398 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */ 2399 #define CAN_FM1R_FBM8_Pos (8U) 2400 #define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */ 2401 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */ 2402 #define CAN_FM1R_FBM9_Pos (9U) 2403 #define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */ 2404 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */ 2405 #define CAN_FM1R_FBM10_Pos (10U) 2406 #define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */ 2407 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */ 2408 #define CAN_FM1R_FBM11_Pos (11U) 2409 #define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */ 2410 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */ 2411 #define CAN_FM1R_FBM12_Pos (12U) 2412 #define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */ 2413 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */ 2414 #define CAN_FM1R_FBM13_Pos (13U) 2415 #define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */ 2416 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */ 2417 #define CAN_FM1R_FBM14_Pos (14U) 2418 #define CAN_FM1R_FBM14_Msk (0x1UL << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */ 2419 #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */ 2420 #define CAN_FM1R_FBM15_Pos (15U) 2421 #define CAN_FM1R_FBM15_Msk (0x1UL << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */ 2422 #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */ 2423 #define CAN_FM1R_FBM16_Pos (16U) 2424 #define CAN_FM1R_FBM16_Msk (0x1UL << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */ 2425 #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */ 2426 #define CAN_FM1R_FBM17_Pos (17U) 2427 #define CAN_FM1R_FBM17_Msk (0x1UL << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */ 2428 #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */ 2429 #define CAN_FM1R_FBM18_Pos (18U) 2430 #define CAN_FM1R_FBM18_Msk (0x1UL << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */ 2431 #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */ 2432 #define CAN_FM1R_FBM19_Pos (19U) 2433 #define CAN_FM1R_FBM19_Msk (0x1UL << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */ 2434 #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */ 2435 #define CAN_FM1R_FBM20_Pos (20U) 2436 #define CAN_FM1R_FBM20_Msk (0x1UL << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */ 2437 #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */ 2438 #define CAN_FM1R_FBM21_Pos (21U) 2439 #define CAN_FM1R_FBM21_Msk (0x1UL << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */ 2440 #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */ 2441 #define CAN_FM1R_FBM22_Pos (22U) 2442 #define CAN_FM1R_FBM22_Msk (0x1UL << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */ 2443 #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */ 2444 #define CAN_FM1R_FBM23_Pos (23U) 2445 #define CAN_FM1R_FBM23_Msk (0x1UL << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */ 2446 #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */ 2447 #define CAN_FM1R_FBM24_Pos (24U) 2448 #define CAN_FM1R_FBM24_Msk (0x1UL << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */ 2449 #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */ 2450 #define CAN_FM1R_FBM25_Pos (25U) 2451 #define CAN_FM1R_FBM25_Msk (0x1UL << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */ 2452 #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */ 2453 #define CAN_FM1R_FBM26_Pos (26U) 2454 #define CAN_FM1R_FBM26_Msk (0x1UL << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */ 2455 #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */ 2456 #define CAN_FM1R_FBM27_Pos (27U) 2457 #define CAN_FM1R_FBM27_Msk (0x1UL << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */ 2458 #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */ 2459 2460 /******************* Bit definition for CAN_FS1R register *******************/ 2461 #define CAN_FS1R_FSC_Pos (0U) 2462 #define CAN_FS1R_FSC_Msk (0xFFFFFFFUL << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */ 2463 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */ 2464 #define CAN_FS1R_FSC0_Pos (0U) 2465 #define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */ 2466 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */ 2467 #define CAN_FS1R_FSC1_Pos (1U) 2468 #define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */ 2469 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */ 2470 #define CAN_FS1R_FSC2_Pos (2U) 2471 #define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */ 2472 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */ 2473 #define CAN_FS1R_FSC3_Pos (3U) 2474 #define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */ 2475 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */ 2476 #define CAN_FS1R_FSC4_Pos (4U) 2477 #define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */ 2478 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */ 2479 #define CAN_FS1R_FSC5_Pos (5U) 2480 #define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */ 2481 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */ 2482 #define CAN_FS1R_FSC6_Pos (6U) 2483 #define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */ 2484 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */ 2485 #define CAN_FS1R_FSC7_Pos (7U) 2486 #define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */ 2487 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */ 2488 #define CAN_FS1R_FSC8_Pos (8U) 2489 #define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */ 2490 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */ 2491 #define CAN_FS1R_FSC9_Pos (9U) 2492 #define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */ 2493 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */ 2494 #define CAN_FS1R_FSC10_Pos (10U) 2495 #define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */ 2496 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */ 2497 #define CAN_FS1R_FSC11_Pos (11U) 2498 #define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */ 2499 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */ 2500 #define CAN_FS1R_FSC12_Pos (12U) 2501 #define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */ 2502 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */ 2503 #define CAN_FS1R_FSC13_Pos (13U) 2504 #define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */ 2505 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */ 2506 #define CAN_FS1R_FSC14_Pos (14U) 2507 #define CAN_FS1R_FSC14_Msk (0x1UL << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */ 2508 #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */ 2509 #define CAN_FS1R_FSC15_Pos (15U) 2510 #define CAN_FS1R_FSC15_Msk (0x1UL << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */ 2511 #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */ 2512 #define CAN_FS1R_FSC16_Pos (16U) 2513 #define CAN_FS1R_FSC16_Msk (0x1UL << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */ 2514 #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */ 2515 #define CAN_FS1R_FSC17_Pos (17U) 2516 #define CAN_FS1R_FSC17_Msk (0x1UL << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */ 2517 #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */ 2518 #define CAN_FS1R_FSC18_Pos (18U) 2519 #define CAN_FS1R_FSC18_Msk (0x1UL << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */ 2520 #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */ 2521 #define CAN_FS1R_FSC19_Pos (19U) 2522 #define CAN_FS1R_FSC19_Msk (0x1UL << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */ 2523 #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */ 2524 #define CAN_FS1R_FSC20_Pos (20U) 2525 #define CAN_FS1R_FSC20_Msk (0x1UL << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */ 2526 #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */ 2527 #define CAN_FS1R_FSC21_Pos (21U) 2528 #define CAN_FS1R_FSC21_Msk (0x1UL << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */ 2529 #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */ 2530 #define CAN_FS1R_FSC22_Pos (22U) 2531 #define CAN_FS1R_FSC22_Msk (0x1UL << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */ 2532 #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */ 2533 #define CAN_FS1R_FSC23_Pos (23U) 2534 #define CAN_FS1R_FSC23_Msk (0x1UL << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */ 2535 #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */ 2536 #define CAN_FS1R_FSC24_Pos (24U) 2537 #define CAN_FS1R_FSC24_Msk (0x1UL << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */ 2538 #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */ 2539 #define CAN_FS1R_FSC25_Pos (25U) 2540 #define CAN_FS1R_FSC25_Msk (0x1UL << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */ 2541 #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */ 2542 #define CAN_FS1R_FSC26_Pos (26U) 2543 #define CAN_FS1R_FSC26_Msk (0x1UL << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */ 2544 #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */ 2545 #define CAN_FS1R_FSC27_Pos (27U) 2546 #define CAN_FS1R_FSC27_Msk (0x1UL << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */ 2547 #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */ 2548 2549 /****************** Bit definition for CAN_FFA1R register *******************/ 2550 #define CAN_FFA1R_FFA_Pos (0U) 2551 #define CAN_FFA1R_FFA_Msk (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */ 2552 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */ 2553 #define CAN_FFA1R_FFA0_Pos (0U) 2554 #define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */ 2555 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */ 2556 #define CAN_FFA1R_FFA1_Pos (1U) 2557 #define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */ 2558 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */ 2559 #define CAN_FFA1R_FFA2_Pos (2U) 2560 #define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */ 2561 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */ 2562 #define CAN_FFA1R_FFA3_Pos (3U) 2563 #define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */ 2564 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */ 2565 #define CAN_FFA1R_FFA4_Pos (4U) 2566 #define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */ 2567 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */ 2568 #define CAN_FFA1R_FFA5_Pos (5U) 2569 #define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */ 2570 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */ 2571 #define CAN_FFA1R_FFA6_Pos (6U) 2572 #define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */ 2573 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */ 2574 #define CAN_FFA1R_FFA7_Pos (7U) 2575 #define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */ 2576 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */ 2577 #define CAN_FFA1R_FFA8_Pos (8U) 2578 #define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */ 2579 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */ 2580 #define CAN_FFA1R_FFA9_Pos (9U) 2581 #define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */ 2582 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */ 2583 #define CAN_FFA1R_FFA10_Pos (10U) 2584 #define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */ 2585 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */ 2586 #define CAN_FFA1R_FFA11_Pos (11U) 2587 #define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */ 2588 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */ 2589 #define CAN_FFA1R_FFA12_Pos (12U) 2590 #define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */ 2591 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */ 2592 #define CAN_FFA1R_FFA13_Pos (13U) 2593 #define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */ 2594 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */ 2595 #define CAN_FFA1R_FFA14_Pos (14U) 2596 #define CAN_FFA1R_FFA14_Msk (0x1UL << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */ 2597 #define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */ 2598 #define CAN_FFA1R_FFA15_Pos (15U) 2599 #define CAN_FFA1R_FFA15_Msk (0x1UL << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */ 2600 #define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */ 2601 #define CAN_FFA1R_FFA16_Pos (16U) 2602 #define CAN_FFA1R_FFA16_Msk (0x1UL << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */ 2603 #define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */ 2604 #define CAN_FFA1R_FFA17_Pos (17U) 2605 #define CAN_FFA1R_FFA17_Msk (0x1UL << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */ 2606 #define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */ 2607 #define CAN_FFA1R_FFA18_Pos (18U) 2608 #define CAN_FFA1R_FFA18_Msk (0x1UL << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */ 2609 #define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */ 2610 #define CAN_FFA1R_FFA19_Pos (19U) 2611 #define CAN_FFA1R_FFA19_Msk (0x1UL << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */ 2612 #define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */ 2613 #define CAN_FFA1R_FFA20_Pos (20U) 2614 #define CAN_FFA1R_FFA20_Msk (0x1UL << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */ 2615 #define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */ 2616 #define CAN_FFA1R_FFA21_Pos (21U) 2617 #define CAN_FFA1R_FFA21_Msk (0x1UL << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */ 2618 #define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */ 2619 #define CAN_FFA1R_FFA22_Pos (22U) 2620 #define CAN_FFA1R_FFA22_Msk (0x1UL << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */ 2621 #define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */ 2622 #define CAN_FFA1R_FFA23_Pos (23U) 2623 #define CAN_FFA1R_FFA23_Msk (0x1UL << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */ 2624 #define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */ 2625 #define CAN_FFA1R_FFA24_Pos (24U) 2626 #define CAN_FFA1R_FFA24_Msk (0x1UL << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */ 2627 #define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */ 2628 #define CAN_FFA1R_FFA25_Pos (25U) 2629 #define CAN_FFA1R_FFA25_Msk (0x1UL << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */ 2630 #define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */ 2631 #define CAN_FFA1R_FFA26_Pos (26U) 2632 #define CAN_FFA1R_FFA26_Msk (0x1UL << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */ 2633 #define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */ 2634 #define CAN_FFA1R_FFA27_Pos (27U) 2635 #define CAN_FFA1R_FFA27_Msk (0x1UL << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */ 2636 #define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */ 2637 2638 /******************* Bit definition for CAN_FA1R register *******************/ 2639 #define CAN_FA1R_FACT_Pos (0U) 2640 #define CAN_FA1R_FACT_Msk (0xFFFFFFFUL << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */ 2641 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */ 2642 #define CAN_FA1R_FACT0_Pos (0U) 2643 #define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */ 2644 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */ 2645 #define CAN_FA1R_FACT1_Pos (1U) 2646 #define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */ 2647 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */ 2648 #define CAN_FA1R_FACT2_Pos (2U) 2649 #define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */ 2650 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */ 2651 #define CAN_FA1R_FACT3_Pos (3U) 2652 #define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */ 2653 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */ 2654 #define CAN_FA1R_FACT4_Pos (4U) 2655 #define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */ 2656 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */ 2657 #define CAN_FA1R_FACT5_Pos (5U) 2658 #define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */ 2659 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */ 2660 #define CAN_FA1R_FACT6_Pos (6U) 2661 #define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */ 2662 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */ 2663 #define CAN_FA1R_FACT7_Pos (7U) 2664 #define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */ 2665 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */ 2666 #define CAN_FA1R_FACT8_Pos (8U) 2667 #define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */ 2668 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */ 2669 #define CAN_FA1R_FACT9_Pos (9U) 2670 #define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */ 2671 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */ 2672 #define CAN_FA1R_FACT10_Pos (10U) 2673 #define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */ 2674 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */ 2675 #define CAN_FA1R_FACT11_Pos (11U) 2676 #define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */ 2677 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */ 2678 #define CAN_FA1R_FACT12_Pos (12U) 2679 #define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */ 2680 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */ 2681 #define CAN_FA1R_FACT13_Pos (13U) 2682 #define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */ 2683 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */ 2684 #define CAN_FA1R_FACT14_Pos (14U) 2685 #define CAN_FA1R_FACT14_Msk (0x1UL << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */ 2686 #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */ 2687 #define CAN_FA1R_FACT15_Pos (15U) 2688 #define CAN_FA1R_FACT15_Msk (0x1UL << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */ 2689 #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */ 2690 #define CAN_FA1R_FACT16_Pos (16U) 2691 #define CAN_FA1R_FACT16_Msk (0x1UL << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */ 2692 #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */ 2693 #define CAN_FA1R_FACT17_Pos (17U) 2694 #define CAN_FA1R_FACT17_Msk (0x1UL << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */ 2695 #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */ 2696 #define CAN_FA1R_FACT18_Pos (18U) 2697 #define CAN_FA1R_FACT18_Msk (0x1UL << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */ 2698 #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */ 2699 #define CAN_FA1R_FACT19_Pos (19U) 2700 #define CAN_FA1R_FACT19_Msk (0x1UL << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */ 2701 #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */ 2702 #define CAN_FA1R_FACT20_Pos (20U) 2703 #define CAN_FA1R_FACT20_Msk (0x1UL << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */ 2704 #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */ 2705 #define CAN_FA1R_FACT21_Pos (21U) 2706 #define CAN_FA1R_FACT21_Msk (0x1UL << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */ 2707 #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */ 2708 #define CAN_FA1R_FACT22_Pos (22U) 2709 #define CAN_FA1R_FACT22_Msk (0x1UL << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */ 2710 #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */ 2711 #define CAN_FA1R_FACT23_Pos (23U) 2712 #define CAN_FA1R_FACT23_Msk (0x1UL << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */ 2713 #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */ 2714 #define CAN_FA1R_FACT24_Pos (24U) 2715 #define CAN_FA1R_FACT24_Msk (0x1UL << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */ 2716 #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */ 2717 #define CAN_FA1R_FACT25_Pos (25U) 2718 #define CAN_FA1R_FACT25_Msk (0x1UL << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */ 2719 #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */ 2720 #define CAN_FA1R_FACT26_Pos (26U) 2721 #define CAN_FA1R_FACT26_Msk (0x1UL << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */ 2722 #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */ 2723 #define CAN_FA1R_FACT27_Pos (27U) 2724 #define CAN_FA1R_FACT27_Msk (0x1UL << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */ 2725 #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */ 2726 2727 /******************* Bit definition for CAN_F0R1 register *******************/ 2728 #define CAN_F0R1_FB0_Pos (0U) 2729 #define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */ 2730 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */ 2731 #define CAN_F0R1_FB1_Pos (1U) 2732 #define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */ 2733 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */ 2734 #define CAN_F0R1_FB2_Pos (2U) 2735 #define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */ 2736 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */ 2737 #define CAN_F0R1_FB3_Pos (3U) 2738 #define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */ 2739 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */ 2740 #define CAN_F0R1_FB4_Pos (4U) 2741 #define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */ 2742 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */ 2743 #define CAN_F0R1_FB5_Pos (5U) 2744 #define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */ 2745 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */ 2746 #define CAN_F0R1_FB6_Pos (6U) 2747 #define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */ 2748 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */ 2749 #define CAN_F0R1_FB7_Pos (7U) 2750 #define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */ 2751 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */ 2752 #define CAN_F0R1_FB8_Pos (8U) 2753 #define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */ 2754 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */ 2755 #define CAN_F0R1_FB9_Pos (9U) 2756 #define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */ 2757 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */ 2758 #define CAN_F0R1_FB10_Pos (10U) 2759 #define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */ 2760 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */ 2761 #define CAN_F0R1_FB11_Pos (11U) 2762 #define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */ 2763 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */ 2764 #define CAN_F0R1_FB12_Pos (12U) 2765 #define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */ 2766 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */ 2767 #define CAN_F0R1_FB13_Pos (13U) 2768 #define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */ 2769 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */ 2770 #define CAN_F0R1_FB14_Pos (14U) 2771 #define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */ 2772 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */ 2773 #define CAN_F0R1_FB15_Pos (15U) 2774 #define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */ 2775 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */ 2776 #define CAN_F0R1_FB16_Pos (16U) 2777 #define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */ 2778 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */ 2779 #define CAN_F0R1_FB17_Pos (17U) 2780 #define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */ 2781 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */ 2782 #define CAN_F0R1_FB18_Pos (18U) 2783 #define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */ 2784 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */ 2785 #define CAN_F0R1_FB19_Pos (19U) 2786 #define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */ 2787 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */ 2788 #define CAN_F0R1_FB20_Pos (20U) 2789 #define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */ 2790 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */ 2791 #define CAN_F0R1_FB21_Pos (21U) 2792 #define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */ 2793 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */ 2794 #define CAN_F0R1_FB22_Pos (22U) 2795 #define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */ 2796 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */ 2797 #define CAN_F0R1_FB23_Pos (23U) 2798 #define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */ 2799 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */ 2800 #define CAN_F0R1_FB24_Pos (24U) 2801 #define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */ 2802 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */ 2803 #define CAN_F0R1_FB25_Pos (25U) 2804 #define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */ 2805 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */ 2806 #define CAN_F0R1_FB26_Pos (26U) 2807 #define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */ 2808 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */ 2809 #define CAN_F0R1_FB27_Pos (27U) 2810 #define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */ 2811 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */ 2812 #define CAN_F0R1_FB28_Pos (28U) 2813 #define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */ 2814 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */ 2815 #define CAN_F0R1_FB29_Pos (29U) 2816 #define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */ 2817 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */ 2818 #define CAN_F0R1_FB30_Pos (30U) 2819 #define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */ 2820 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */ 2821 #define CAN_F0R1_FB31_Pos (31U) 2822 #define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */ 2823 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */ 2824 2825 /******************* Bit definition for CAN_F1R1 register *******************/ 2826 #define CAN_F1R1_FB0_Pos (0U) 2827 #define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */ 2828 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */ 2829 #define CAN_F1R1_FB1_Pos (1U) 2830 #define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */ 2831 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */ 2832 #define CAN_F1R1_FB2_Pos (2U) 2833 #define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */ 2834 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */ 2835 #define CAN_F1R1_FB3_Pos (3U) 2836 #define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */ 2837 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */ 2838 #define CAN_F1R1_FB4_Pos (4U) 2839 #define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */ 2840 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */ 2841 #define CAN_F1R1_FB5_Pos (5U) 2842 #define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */ 2843 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */ 2844 #define CAN_F1R1_FB6_Pos (6U) 2845 #define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */ 2846 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */ 2847 #define CAN_F1R1_FB7_Pos (7U) 2848 #define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */ 2849 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */ 2850 #define CAN_F1R1_FB8_Pos (8U) 2851 #define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */ 2852 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */ 2853 #define CAN_F1R1_FB9_Pos (9U) 2854 #define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */ 2855 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */ 2856 #define CAN_F1R1_FB10_Pos (10U) 2857 #define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */ 2858 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */ 2859 #define CAN_F1R1_FB11_Pos (11U) 2860 #define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */ 2861 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */ 2862 #define CAN_F1R1_FB12_Pos (12U) 2863 #define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */ 2864 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */ 2865 #define CAN_F1R1_FB13_Pos (13U) 2866 #define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */ 2867 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */ 2868 #define CAN_F1R1_FB14_Pos (14U) 2869 #define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */ 2870 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */ 2871 #define CAN_F1R1_FB15_Pos (15U) 2872 #define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */ 2873 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */ 2874 #define CAN_F1R1_FB16_Pos (16U) 2875 #define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */ 2876 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */ 2877 #define CAN_F1R1_FB17_Pos (17U) 2878 #define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */ 2879 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */ 2880 #define CAN_F1R1_FB18_Pos (18U) 2881 #define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */ 2882 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */ 2883 #define CAN_F1R1_FB19_Pos (19U) 2884 #define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */ 2885 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */ 2886 #define CAN_F1R1_FB20_Pos (20U) 2887 #define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */ 2888 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */ 2889 #define CAN_F1R1_FB21_Pos (21U) 2890 #define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */ 2891 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */ 2892 #define CAN_F1R1_FB22_Pos (22U) 2893 #define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */ 2894 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */ 2895 #define CAN_F1R1_FB23_Pos (23U) 2896 #define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */ 2897 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */ 2898 #define CAN_F1R1_FB24_Pos (24U) 2899 #define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */ 2900 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */ 2901 #define CAN_F1R1_FB25_Pos (25U) 2902 #define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */ 2903 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */ 2904 #define CAN_F1R1_FB26_Pos (26U) 2905 #define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */ 2906 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */ 2907 #define CAN_F1R1_FB27_Pos (27U) 2908 #define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */ 2909 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */ 2910 #define CAN_F1R1_FB28_Pos (28U) 2911 #define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */ 2912 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */ 2913 #define CAN_F1R1_FB29_Pos (29U) 2914 #define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */ 2915 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */ 2916 #define CAN_F1R1_FB30_Pos (30U) 2917 #define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */ 2918 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */ 2919 #define CAN_F1R1_FB31_Pos (31U) 2920 #define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */ 2921 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */ 2922 2923 /******************* Bit definition for CAN_F2R1 register *******************/ 2924 #define CAN_F2R1_FB0_Pos (0U) 2925 #define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */ 2926 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */ 2927 #define CAN_F2R1_FB1_Pos (1U) 2928 #define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */ 2929 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */ 2930 #define CAN_F2R1_FB2_Pos (2U) 2931 #define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */ 2932 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */ 2933 #define CAN_F2R1_FB3_Pos (3U) 2934 #define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */ 2935 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */ 2936 #define CAN_F2R1_FB4_Pos (4U) 2937 #define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */ 2938 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */ 2939 #define CAN_F2R1_FB5_Pos (5U) 2940 #define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */ 2941 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */ 2942 #define CAN_F2R1_FB6_Pos (6U) 2943 #define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */ 2944 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */ 2945 #define CAN_F2R1_FB7_Pos (7U) 2946 #define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */ 2947 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */ 2948 #define CAN_F2R1_FB8_Pos (8U) 2949 #define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */ 2950 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */ 2951 #define CAN_F2R1_FB9_Pos (9U) 2952 #define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */ 2953 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */ 2954 #define CAN_F2R1_FB10_Pos (10U) 2955 #define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */ 2956 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */ 2957 #define CAN_F2R1_FB11_Pos (11U) 2958 #define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */ 2959 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */ 2960 #define CAN_F2R1_FB12_Pos (12U) 2961 #define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */ 2962 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */ 2963 #define CAN_F2R1_FB13_Pos (13U) 2964 #define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */ 2965 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */ 2966 #define CAN_F2R1_FB14_Pos (14U) 2967 #define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */ 2968 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */ 2969 #define CAN_F2R1_FB15_Pos (15U) 2970 #define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */ 2971 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */ 2972 #define CAN_F2R1_FB16_Pos (16U) 2973 #define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */ 2974 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */ 2975 #define CAN_F2R1_FB17_Pos (17U) 2976 #define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */ 2977 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */ 2978 #define CAN_F2R1_FB18_Pos (18U) 2979 #define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */ 2980 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */ 2981 #define CAN_F2R1_FB19_Pos (19U) 2982 #define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */ 2983 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */ 2984 #define CAN_F2R1_FB20_Pos (20U) 2985 #define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */ 2986 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */ 2987 #define CAN_F2R1_FB21_Pos (21U) 2988 #define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */ 2989 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */ 2990 #define CAN_F2R1_FB22_Pos (22U) 2991 #define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */ 2992 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */ 2993 #define CAN_F2R1_FB23_Pos (23U) 2994 #define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */ 2995 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */ 2996 #define CAN_F2R1_FB24_Pos (24U) 2997 #define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */ 2998 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */ 2999 #define CAN_F2R1_FB25_Pos (25U) 3000 #define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */ 3001 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */ 3002 #define CAN_F2R1_FB26_Pos (26U) 3003 #define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */ 3004 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */ 3005 #define CAN_F2R1_FB27_Pos (27U) 3006 #define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */ 3007 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */ 3008 #define CAN_F2R1_FB28_Pos (28U) 3009 #define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */ 3010 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */ 3011 #define CAN_F2R1_FB29_Pos (29U) 3012 #define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */ 3013 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */ 3014 #define CAN_F2R1_FB30_Pos (30U) 3015 #define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */ 3016 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */ 3017 #define CAN_F2R1_FB31_Pos (31U) 3018 #define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */ 3019 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */ 3020 3021 /******************* Bit definition for CAN_F3R1 register *******************/ 3022 #define CAN_F3R1_FB0_Pos (0U) 3023 #define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */ 3024 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */ 3025 #define CAN_F3R1_FB1_Pos (1U) 3026 #define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */ 3027 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */ 3028 #define CAN_F3R1_FB2_Pos (2U) 3029 #define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */ 3030 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */ 3031 #define CAN_F3R1_FB3_Pos (3U) 3032 #define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */ 3033 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */ 3034 #define CAN_F3R1_FB4_Pos (4U) 3035 #define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */ 3036 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */ 3037 #define CAN_F3R1_FB5_Pos (5U) 3038 #define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */ 3039 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */ 3040 #define CAN_F3R1_FB6_Pos (6U) 3041 #define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */ 3042 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */ 3043 #define CAN_F3R1_FB7_Pos (7U) 3044 #define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */ 3045 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */ 3046 #define CAN_F3R1_FB8_Pos (8U) 3047 #define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */ 3048 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */ 3049 #define CAN_F3R1_FB9_Pos (9U) 3050 #define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */ 3051 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */ 3052 #define CAN_F3R1_FB10_Pos (10U) 3053 #define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */ 3054 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */ 3055 #define CAN_F3R1_FB11_Pos (11U) 3056 #define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */ 3057 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */ 3058 #define CAN_F3R1_FB12_Pos (12U) 3059 #define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */ 3060 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */ 3061 #define CAN_F3R1_FB13_Pos (13U) 3062 #define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */ 3063 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */ 3064 #define CAN_F3R1_FB14_Pos (14U) 3065 #define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */ 3066 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */ 3067 #define CAN_F3R1_FB15_Pos (15U) 3068 #define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */ 3069 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */ 3070 #define CAN_F3R1_FB16_Pos (16U) 3071 #define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */ 3072 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */ 3073 #define CAN_F3R1_FB17_Pos (17U) 3074 #define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */ 3075 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */ 3076 #define CAN_F3R1_FB18_Pos (18U) 3077 #define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */ 3078 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */ 3079 #define CAN_F3R1_FB19_Pos (19U) 3080 #define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */ 3081 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */ 3082 #define CAN_F3R1_FB20_Pos (20U) 3083 #define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */ 3084 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */ 3085 #define CAN_F3R1_FB21_Pos (21U) 3086 #define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */ 3087 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */ 3088 #define CAN_F3R1_FB22_Pos (22U) 3089 #define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */ 3090 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */ 3091 #define CAN_F3R1_FB23_Pos (23U) 3092 #define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */ 3093 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */ 3094 #define CAN_F3R1_FB24_Pos (24U) 3095 #define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */ 3096 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */ 3097 #define CAN_F3R1_FB25_Pos (25U) 3098 #define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */ 3099 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */ 3100 #define CAN_F3R1_FB26_Pos (26U) 3101 #define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */ 3102 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */ 3103 #define CAN_F3R1_FB27_Pos (27U) 3104 #define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */ 3105 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */ 3106 #define CAN_F3R1_FB28_Pos (28U) 3107 #define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */ 3108 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */ 3109 #define CAN_F3R1_FB29_Pos (29U) 3110 #define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */ 3111 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */ 3112 #define CAN_F3R1_FB30_Pos (30U) 3113 #define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */ 3114 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */ 3115 #define CAN_F3R1_FB31_Pos (31U) 3116 #define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */ 3117 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */ 3118 3119 /******************* Bit definition for CAN_F4R1 register *******************/ 3120 #define CAN_F4R1_FB0_Pos (0U) 3121 #define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */ 3122 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */ 3123 #define CAN_F4R1_FB1_Pos (1U) 3124 #define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */ 3125 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */ 3126 #define CAN_F4R1_FB2_Pos (2U) 3127 #define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */ 3128 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */ 3129 #define CAN_F4R1_FB3_Pos (3U) 3130 #define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */ 3131 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */ 3132 #define CAN_F4R1_FB4_Pos (4U) 3133 #define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */ 3134 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */ 3135 #define CAN_F4R1_FB5_Pos (5U) 3136 #define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */ 3137 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */ 3138 #define CAN_F4R1_FB6_Pos (6U) 3139 #define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */ 3140 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */ 3141 #define CAN_F4R1_FB7_Pos (7U) 3142 #define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */ 3143 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */ 3144 #define CAN_F4R1_FB8_Pos (8U) 3145 #define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */ 3146 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */ 3147 #define CAN_F4R1_FB9_Pos (9U) 3148 #define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */ 3149 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */ 3150 #define CAN_F4R1_FB10_Pos (10U) 3151 #define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */ 3152 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */ 3153 #define CAN_F4R1_FB11_Pos (11U) 3154 #define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */ 3155 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */ 3156 #define CAN_F4R1_FB12_Pos (12U) 3157 #define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */ 3158 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */ 3159 #define CAN_F4R1_FB13_Pos (13U) 3160 #define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */ 3161 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */ 3162 #define CAN_F4R1_FB14_Pos (14U) 3163 #define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */ 3164 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */ 3165 #define CAN_F4R1_FB15_Pos (15U) 3166 #define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */ 3167 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */ 3168 #define CAN_F4R1_FB16_Pos (16U) 3169 #define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */ 3170 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */ 3171 #define CAN_F4R1_FB17_Pos (17U) 3172 #define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */ 3173 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */ 3174 #define CAN_F4R1_FB18_Pos (18U) 3175 #define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */ 3176 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */ 3177 #define CAN_F4R1_FB19_Pos (19U) 3178 #define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */ 3179 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */ 3180 #define CAN_F4R1_FB20_Pos (20U) 3181 #define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */ 3182 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */ 3183 #define CAN_F4R1_FB21_Pos (21U) 3184 #define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */ 3185 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */ 3186 #define CAN_F4R1_FB22_Pos (22U) 3187 #define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */ 3188 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */ 3189 #define CAN_F4R1_FB23_Pos (23U) 3190 #define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */ 3191 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */ 3192 #define CAN_F4R1_FB24_Pos (24U) 3193 #define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */ 3194 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */ 3195 #define CAN_F4R1_FB25_Pos (25U) 3196 #define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */ 3197 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */ 3198 #define CAN_F4R1_FB26_Pos (26U) 3199 #define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */ 3200 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */ 3201 #define CAN_F4R1_FB27_Pos (27U) 3202 #define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */ 3203 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */ 3204 #define CAN_F4R1_FB28_Pos (28U) 3205 #define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */ 3206 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */ 3207 #define CAN_F4R1_FB29_Pos (29U) 3208 #define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */ 3209 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */ 3210 #define CAN_F4R1_FB30_Pos (30U) 3211 #define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */ 3212 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */ 3213 #define CAN_F4R1_FB31_Pos (31U) 3214 #define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */ 3215 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */ 3216 3217 /******************* Bit definition for CAN_F5R1 register *******************/ 3218 #define CAN_F5R1_FB0_Pos (0U) 3219 #define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */ 3220 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */ 3221 #define CAN_F5R1_FB1_Pos (1U) 3222 #define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */ 3223 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */ 3224 #define CAN_F5R1_FB2_Pos (2U) 3225 #define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */ 3226 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */ 3227 #define CAN_F5R1_FB3_Pos (3U) 3228 #define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */ 3229 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */ 3230 #define CAN_F5R1_FB4_Pos (4U) 3231 #define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */ 3232 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */ 3233 #define CAN_F5R1_FB5_Pos (5U) 3234 #define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */ 3235 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */ 3236 #define CAN_F5R1_FB6_Pos (6U) 3237 #define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */ 3238 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */ 3239 #define CAN_F5R1_FB7_Pos (7U) 3240 #define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */ 3241 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */ 3242 #define CAN_F5R1_FB8_Pos (8U) 3243 #define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */ 3244 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */ 3245 #define CAN_F5R1_FB9_Pos (9U) 3246 #define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */ 3247 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */ 3248 #define CAN_F5R1_FB10_Pos (10U) 3249 #define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */ 3250 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */ 3251 #define CAN_F5R1_FB11_Pos (11U) 3252 #define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */ 3253 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */ 3254 #define CAN_F5R1_FB12_Pos (12U) 3255 #define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */ 3256 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */ 3257 #define CAN_F5R1_FB13_Pos (13U) 3258 #define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */ 3259 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */ 3260 #define CAN_F5R1_FB14_Pos (14U) 3261 #define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */ 3262 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */ 3263 #define CAN_F5R1_FB15_Pos (15U) 3264 #define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */ 3265 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */ 3266 #define CAN_F5R1_FB16_Pos (16U) 3267 #define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */ 3268 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */ 3269 #define CAN_F5R1_FB17_Pos (17U) 3270 #define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */ 3271 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */ 3272 #define CAN_F5R1_FB18_Pos (18U) 3273 #define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */ 3274 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */ 3275 #define CAN_F5R1_FB19_Pos (19U) 3276 #define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */ 3277 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */ 3278 #define CAN_F5R1_FB20_Pos (20U) 3279 #define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */ 3280 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */ 3281 #define CAN_F5R1_FB21_Pos (21U) 3282 #define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */ 3283 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */ 3284 #define CAN_F5R1_FB22_Pos (22U) 3285 #define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */ 3286 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */ 3287 #define CAN_F5R1_FB23_Pos (23U) 3288 #define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */ 3289 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */ 3290 #define CAN_F5R1_FB24_Pos (24U) 3291 #define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */ 3292 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */ 3293 #define CAN_F5R1_FB25_Pos (25U) 3294 #define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */ 3295 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */ 3296 #define CAN_F5R1_FB26_Pos (26U) 3297 #define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */ 3298 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */ 3299 #define CAN_F5R1_FB27_Pos (27U) 3300 #define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */ 3301 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */ 3302 #define CAN_F5R1_FB28_Pos (28U) 3303 #define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */ 3304 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */ 3305 #define CAN_F5R1_FB29_Pos (29U) 3306 #define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */ 3307 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */ 3308 #define CAN_F5R1_FB30_Pos (30U) 3309 #define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */ 3310 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */ 3311 #define CAN_F5R1_FB31_Pos (31U) 3312 #define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */ 3313 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */ 3314 3315 /******************* Bit definition for CAN_F6R1 register *******************/ 3316 #define CAN_F6R1_FB0_Pos (0U) 3317 #define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */ 3318 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */ 3319 #define CAN_F6R1_FB1_Pos (1U) 3320 #define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */ 3321 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */ 3322 #define CAN_F6R1_FB2_Pos (2U) 3323 #define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */ 3324 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */ 3325 #define CAN_F6R1_FB3_Pos (3U) 3326 #define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */ 3327 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */ 3328 #define CAN_F6R1_FB4_Pos (4U) 3329 #define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */ 3330 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */ 3331 #define CAN_F6R1_FB5_Pos (5U) 3332 #define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */ 3333 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */ 3334 #define CAN_F6R1_FB6_Pos (6U) 3335 #define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */ 3336 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */ 3337 #define CAN_F6R1_FB7_Pos (7U) 3338 #define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */ 3339 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */ 3340 #define CAN_F6R1_FB8_Pos (8U) 3341 #define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */ 3342 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */ 3343 #define CAN_F6R1_FB9_Pos (9U) 3344 #define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */ 3345 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */ 3346 #define CAN_F6R1_FB10_Pos (10U) 3347 #define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */ 3348 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */ 3349 #define CAN_F6R1_FB11_Pos (11U) 3350 #define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */ 3351 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */ 3352 #define CAN_F6R1_FB12_Pos (12U) 3353 #define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */ 3354 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */ 3355 #define CAN_F6R1_FB13_Pos (13U) 3356 #define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */ 3357 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */ 3358 #define CAN_F6R1_FB14_Pos (14U) 3359 #define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */ 3360 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */ 3361 #define CAN_F6R1_FB15_Pos (15U) 3362 #define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */ 3363 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */ 3364 #define CAN_F6R1_FB16_Pos (16U) 3365 #define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */ 3366 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */ 3367 #define CAN_F6R1_FB17_Pos (17U) 3368 #define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */ 3369 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */ 3370 #define CAN_F6R1_FB18_Pos (18U) 3371 #define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */ 3372 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */ 3373 #define CAN_F6R1_FB19_Pos (19U) 3374 #define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */ 3375 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */ 3376 #define CAN_F6R1_FB20_Pos (20U) 3377 #define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */ 3378 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */ 3379 #define CAN_F6R1_FB21_Pos (21U) 3380 #define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */ 3381 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */ 3382 #define CAN_F6R1_FB22_Pos (22U) 3383 #define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */ 3384 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */ 3385 #define CAN_F6R1_FB23_Pos (23U) 3386 #define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */ 3387 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */ 3388 #define CAN_F6R1_FB24_Pos (24U) 3389 #define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */ 3390 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */ 3391 #define CAN_F6R1_FB25_Pos (25U) 3392 #define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */ 3393 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */ 3394 #define CAN_F6R1_FB26_Pos (26U) 3395 #define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */ 3396 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */ 3397 #define CAN_F6R1_FB27_Pos (27U) 3398 #define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */ 3399 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */ 3400 #define CAN_F6R1_FB28_Pos (28U) 3401 #define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */ 3402 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */ 3403 #define CAN_F6R1_FB29_Pos (29U) 3404 #define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */ 3405 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */ 3406 #define CAN_F6R1_FB30_Pos (30U) 3407 #define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */ 3408 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */ 3409 #define CAN_F6R1_FB31_Pos (31U) 3410 #define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */ 3411 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */ 3412 3413 /******************* Bit definition for CAN_F7R1 register *******************/ 3414 #define CAN_F7R1_FB0_Pos (0U) 3415 #define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */ 3416 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */ 3417 #define CAN_F7R1_FB1_Pos (1U) 3418 #define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */ 3419 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */ 3420 #define CAN_F7R1_FB2_Pos (2U) 3421 #define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */ 3422 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */ 3423 #define CAN_F7R1_FB3_Pos (3U) 3424 #define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */ 3425 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */ 3426 #define CAN_F7R1_FB4_Pos (4U) 3427 #define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */ 3428 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */ 3429 #define CAN_F7R1_FB5_Pos (5U) 3430 #define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */ 3431 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */ 3432 #define CAN_F7R1_FB6_Pos (6U) 3433 #define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */ 3434 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */ 3435 #define CAN_F7R1_FB7_Pos (7U) 3436 #define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */ 3437 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */ 3438 #define CAN_F7R1_FB8_Pos (8U) 3439 #define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */ 3440 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */ 3441 #define CAN_F7R1_FB9_Pos (9U) 3442 #define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */ 3443 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */ 3444 #define CAN_F7R1_FB10_Pos (10U) 3445 #define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */ 3446 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */ 3447 #define CAN_F7R1_FB11_Pos (11U) 3448 #define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */ 3449 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */ 3450 #define CAN_F7R1_FB12_Pos (12U) 3451 #define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */ 3452 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */ 3453 #define CAN_F7R1_FB13_Pos (13U) 3454 #define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */ 3455 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */ 3456 #define CAN_F7R1_FB14_Pos (14U) 3457 #define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */ 3458 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */ 3459 #define CAN_F7R1_FB15_Pos (15U) 3460 #define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */ 3461 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */ 3462 #define CAN_F7R1_FB16_Pos (16U) 3463 #define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */ 3464 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */ 3465 #define CAN_F7R1_FB17_Pos (17U) 3466 #define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */ 3467 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */ 3468 #define CAN_F7R1_FB18_Pos (18U) 3469 #define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */ 3470 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */ 3471 #define CAN_F7R1_FB19_Pos (19U) 3472 #define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */ 3473 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */ 3474 #define CAN_F7R1_FB20_Pos (20U) 3475 #define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */ 3476 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */ 3477 #define CAN_F7R1_FB21_Pos (21U) 3478 #define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */ 3479 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */ 3480 #define CAN_F7R1_FB22_Pos (22U) 3481 #define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */ 3482 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */ 3483 #define CAN_F7R1_FB23_Pos (23U) 3484 #define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */ 3485 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */ 3486 #define CAN_F7R1_FB24_Pos (24U) 3487 #define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */ 3488 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */ 3489 #define CAN_F7R1_FB25_Pos (25U) 3490 #define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */ 3491 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */ 3492 #define CAN_F7R1_FB26_Pos (26U) 3493 #define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */ 3494 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */ 3495 #define CAN_F7R1_FB27_Pos (27U) 3496 #define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */ 3497 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */ 3498 #define CAN_F7R1_FB28_Pos (28U) 3499 #define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */ 3500 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */ 3501 #define CAN_F7R1_FB29_Pos (29U) 3502 #define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */ 3503 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */ 3504 #define CAN_F7R1_FB30_Pos (30U) 3505 #define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */ 3506 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */ 3507 #define CAN_F7R1_FB31_Pos (31U) 3508 #define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */ 3509 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */ 3510 3511 /******************* Bit definition for CAN_F8R1 register *******************/ 3512 #define CAN_F8R1_FB0_Pos (0U) 3513 #define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */ 3514 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */ 3515 #define CAN_F8R1_FB1_Pos (1U) 3516 #define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */ 3517 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */ 3518 #define CAN_F8R1_FB2_Pos (2U) 3519 #define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */ 3520 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */ 3521 #define CAN_F8R1_FB3_Pos (3U) 3522 #define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */ 3523 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */ 3524 #define CAN_F8R1_FB4_Pos (4U) 3525 #define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */ 3526 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */ 3527 #define CAN_F8R1_FB5_Pos (5U) 3528 #define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */ 3529 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */ 3530 #define CAN_F8R1_FB6_Pos (6U) 3531 #define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */ 3532 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */ 3533 #define CAN_F8R1_FB7_Pos (7U) 3534 #define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */ 3535 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */ 3536 #define CAN_F8R1_FB8_Pos (8U) 3537 #define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */ 3538 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */ 3539 #define CAN_F8R1_FB9_Pos (9U) 3540 #define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */ 3541 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */ 3542 #define CAN_F8R1_FB10_Pos (10U) 3543 #define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */ 3544 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */ 3545 #define CAN_F8R1_FB11_Pos (11U) 3546 #define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */ 3547 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */ 3548 #define CAN_F8R1_FB12_Pos (12U) 3549 #define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */ 3550 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */ 3551 #define CAN_F8R1_FB13_Pos (13U) 3552 #define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */ 3553 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */ 3554 #define CAN_F8R1_FB14_Pos (14U) 3555 #define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */ 3556 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */ 3557 #define CAN_F8R1_FB15_Pos (15U) 3558 #define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */ 3559 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */ 3560 #define CAN_F8R1_FB16_Pos (16U) 3561 #define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */ 3562 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */ 3563 #define CAN_F8R1_FB17_Pos (17U) 3564 #define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */ 3565 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */ 3566 #define CAN_F8R1_FB18_Pos (18U) 3567 #define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */ 3568 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */ 3569 #define CAN_F8R1_FB19_Pos (19U) 3570 #define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */ 3571 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */ 3572 #define CAN_F8R1_FB20_Pos (20U) 3573 #define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */ 3574 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */ 3575 #define CAN_F8R1_FB21_Pos (21U) 3576 #define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */ 3577 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */ 3578 #define CAN_F8R1_FB22_Pos (22U) 3579 #define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */ 3580 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */ 3581 #define CAN_F8R1_FB23_Pos (23U) 3582 #define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */ 3583 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */ 3584 #define CAN_F8R1_FB24_Pos (24U) 3585 #define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */ 3586 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */ 3587 #define CAN_F8R1_FB25_Pos (25U) 3588 #define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */ 3589 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */ 3590 #define CAN_F8R1_FB26_Pos (26U) 3591 #define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */ 3592 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */ 3593 #define CAN_F8R1_FB27_Pos (27U) 3594 #define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */ 3595 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */ 3596 #define CAN_F8R1_FB28_Pos (28U) 3597 #define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */ 3598 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */ 3599 #define CAN_F8R1_FB29_Pos (29U) 3600 #define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */ 3601 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */ 3602 #define CAN_F8R1_FB30_Pos (30U) 3603 #define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */ 3604 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */ 3605 #define CAN_F8R1_FB31_Pos (31U) 3606 #define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */ 3607 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */ 3608 3609 /******************* Bit definition for CAN_F9R1 register *******************/ 3610 #define CAN_F9R1_FB0_Pos (0U) 3611 #define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */ 3612 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */ 3613 #define CAN_F9R1_FB1_Pos (1U) 3614 #define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */ 3615 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */ 3616 #define CAN_F9R1_FB2_Pos (2U) 3617 #define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */ 3618 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */ 3619 #define CAN_F9R1_FB3_Pos (3U) 3620 #define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */ 3621 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */ 3622 #define CAN_F9R1_FB4_Pos (4U) 3623 #define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */ 3624 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */ 3625 #define CAN_F9R1_FB5_Pos (5U) 3626 #define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */ 3627 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */ 3628 #define CAN_F9R1_FB6_Pos (6U) 3629 #define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */ 3630 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */ 3631 #define CAN_F9R1_FB7_Pos (7U) 3632 #define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */ 3633 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */ 3634 #define CAN_F9R1_FB8_Pos (8U) 3635 #define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */ 3636 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */ 3637 #define CAN_F9R1_FB9_Pos (9U) 3638 #define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */ 3639 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */ 3640 #define CAN_F9R1_FB10_Pos (10U) 3641 #define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */ 3642 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */ 3643 #define CAN_F9R1_FB11_Pos (11U) 3644 #define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */ 3645 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */ 3646 #define CAN_F9R1_FB12_Pos (12U) 3647 #define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */ 3648 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */ 3649 #define CAN_F9R1_FB13_Pos (13U) 3650 #define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */ 3651 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */ 3652 #define CAN_F9R1_FB14_Pos (14U) 3653 #define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */ 3654 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */ 3655 #define CAN_F9R1_FB15_Pos (15U) 3656 #define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */ 3657 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */ 3658 #define CAN_F9R1_FB16_Pos (16U) 3659 #define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */ 3660 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */ 3661 #define CAN_F9R1_FB17_Pos (17U) 3662 #define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */ 3663 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */ 3664 #define CAN_F9R1_FB18_Pos (18U) 3665 #define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */ 3666 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */ 3667 #define CAN_F9R1_FB19_Pos (19U) 3668 #define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */ 3669 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */ 3670 #define CAN_F9R1_FB20_Pos (20U) 3671 #define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */ 3672 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */ 3673 #define CAN_F9R1_FB21_Pos (21U) 3674 #define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */ 3675 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */ 3676 #define CAN_F9R1_FB22_Pos (22U) 3677 #define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */ 3678 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */ 3679 #define CAN_F9R1_FB23_Pos (23U) 3680 #define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */ 3681 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */ 3682 #define CAN_F9R1_FB24_Pos (24U) 3683 #define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */ 3684 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */ 3685 #define CAN_F9R1_FB25_Pos (25U) 3686 #define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */ 3687 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */ 3688 #define CAN_F9R1_FB26_Pos (26U) 3689 #define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */ 3690 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */ 3691 #define CAN_F9R1_FB27_Pos (27U) 3692 #define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */ 3693 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */ 3694 #define CAN_F9R1_FB28_Pos (28U) 3695 #define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */ 3696 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */ 3697 #define CAN_F9R1_FB29_Pos (29U) 3698 #define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */ 3699 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */ 3700 #define CAN_F9R1_FB30_Pos (30U) 3701 #define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */ 3702 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */ 3703 #define CAN_F9R1_FB31_Pos (31U) 3704 #define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */ 3705 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */ 3706 3707 /******************* Bit definition for CAN_F10R1 register ******************/ 3708 #define CAN_F10R1_FB0_Pos (0U) 3709 #define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */ 3710 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */ 3711 #define CAN_F10R1_FB1_Pos (1U) 3712 #define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */ 3713 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */ 3714 #define CAN_F10R1_FB2_Pos (2U) 3715 #define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */ 3716 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */ 3717 #define CAN_F10R1_FB3_Pos (3U) 3718 #define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */ 3719 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */ 3720 #define CAN_F10R1_FB4_Pos (4U) 3721 #define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */ 3722 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */ 3723 #define CAN_F10R1_FB5_Pos (5U) 3724 #define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */ 3725 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */ 3726 #define CAN_F10R1_FB6_Pos (6U) 3727 #define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */ 3728 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */ 3729 #define CAN_F10R1_FB7_Pos (7U) 3730 #define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */ 3731 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */ 3732 #define CAN_F10R1_FB8_Pos (8U) 3733 #define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */ 3734 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */ 3735 #define CAN_F10R1_FB9_Pos (9U) 3736 #define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */ 3737 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */ 3738 #define CAN_F10R1_FB10_Pos (10U) 3739 #define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */ 3740 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */ 3741 #define CAN_F10R1_FB11_Pos (11U) 3742 #define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */ 3743 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */ 3744 #define CAN_F10R1_FB12_Pos (12U) 3745 #define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */ 3746 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */ 3747 #define CAN_F10R1_FB13_Pos (13U) 3748 #define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */ 3749 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */ 3750 #define CAN_F10R1_FB14_Pos (14U) 3751 #define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */ 3752 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */ 3753 #define CAN_F10R1_FB15_Pos (15U) 3754 #define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */ 3755 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */ 3756 #define CAN_F10R1_FB16_Pos (16U) 3757 #define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */ 3758 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */ 3759 #define CAN_F10R1_FB17_Pos (17U) 3760 #define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */ 3761 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */ 3762 #define CAN_F10R1_FB18_Pos (18U) 3763 #define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */ 3764 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */ 3765 #define CAN_F10R1_FB19_Pos (19U) 3766 #define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */ 3767 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */ 3768 #define CAN_F10R1_FB20_Pos (20U) 3769 #define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */ 3770 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */ 3771 #define CAN_F10R1_FB21_Pos (21U) 3772 #define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */ 3773 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */ 3774 #define CAN_F10R1_FB22_Pos (22U) 3775 #define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */ 3776 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */ 3777 #define CAN_F10R1_FB23_Pos (23U) 3778 #define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */ 3779 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */ 3780 #define CAN_F10R1_FB24_Pos (24U) 3781 #define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */ 3782 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */ 3783 #define CAN_F10R1_FB25_Pos (25U) 3784 #define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */ 3785 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */ 3786 #define CAN_F10R1_FB26_Pos (26U) 3787 #define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */ 3788 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */ 3789 #define CAN_F10R1_FB27_Pos (27U) 3790 #define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */ 3791 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */ 3792 #define CAN_F10R1_FB28_Pos (28U) 3793 #define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */ 3794 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */ 3795 #define CAN_F10R1_FB29_Pos (29U) 3796 #define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */ 3797 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */ 3798 #define CAN_F10R1_FB30_Pos (30U) 3799 #define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */ 3800 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */ 3801 #define CAN_F10R1_FB31_Pos (31U) 3802 #define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */ 3803 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */ 3804 3805 /******************* Bit definition for CAN_F11R1 register ******************/ 3806 #define CAN_F11R1_FB0_Pos (0U) 3807 #define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */ 3808 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */ 3809 #define CAN_F11R1_FB1_Pos (1U) 3810 #define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */ 3811 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */ 3812 #define CAN_F11R1_FB2_Pos (2U) 3813 #define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */ 3814 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */ 3815 #define CAN_F11R1_FB3_Pos (3U) 3816 #define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */ 3817 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */ 3818 #define CAN_F11R1_FB4_Pos (4U) 3819 #define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */ 3820 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */ 3821 #define CAN_F11R1_FB5_Pos (5U) 3822 #define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */ 3823 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */ 3824 #define CAN_F11R1_FB6_Pos (6U) 3825 #define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */ 3826 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */ 3827 #define CAN_F11R1_FB7_Pos (7U) 3828 #define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */ 3829 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */ 3830 #define CAN_F11R1_FB8_Pos (8U) 3831 #define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */ 3832 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */ 3833 #define CAN_F11R1_FB9_Pos (9U) 3834 #define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */ 3835 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */ 3836 #define CAN_F11R1_FB10_Pos (10U) 3837 #define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */ 3838 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */ 3839 #define CAN_F11R1_FB11_Pos (11U) 3840 #define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */ 3841 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */ 3842 #define CAN_F11R1_FB12_Pos (12U) 3843 #define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */ 3844 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */ 3845 #define CAN_F11R1_FB13_Pos (13U) 3846 #define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */ 3847 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */ 3848 #define CAN_F11R1_FB14_Pos (14U) 3849 #define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */ 3850 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */ 3851 #define CAN_F11R1_FB15_Pos (15U) 3852 #define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */ 3853 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */ 3854 #define CAN_F11R1_FB16_Pos (16U) 3855 #define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */ 3856 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */ 3857 #define CAN_F11R1_FB17_Pos (17U) 3858 #define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */ 3859 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */ 3860 #define CAN_F11R1_FB18_Pos (18U) 3861 #define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */ 3862 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */ 3863 #define CAN_F11R1_FB19_Pos (19U) 3864 #define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */ 3865 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */ 3866 #define CAN_F11R1_FB20_Pos (20U) 3867 #define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */ 3868 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */ 3869 #define CAN_F11R1_FB21_Pos (21U) 3870 #define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */ 3871 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */ 3872 #define CAN_F11R1_FB22_Pos (22U) 3873 #define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */ 3874 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */ 3875 #define CAN_F11R1_FB23_Pos (23U) 3876 #define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */ 3877 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */ 3878 #define CAN_F11R1_FB24_Pos (24U) 3879 #define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */ 3880 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */ 3881 #define CAN_F11R1_FB25_Pos (25U) 3882 #define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */ 3883 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */ 3884 #define CAN_F11R1_FB26_Pos (26U) 3885 #define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */ 3886 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */ 3887 #define CAN_F11R1_FB27_Pos (27U) 3888 #define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */ 3889 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */ 3890 #define CAN_F11R1_FB28_Pos (28U) 3891 #define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */ 3892 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */ 3893 #define CAN_F11R1_FB29_Pos (29U) 3894 #define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */ 3895 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */ 3896 #define CAN_F11R1_FB30_Pos (30U) 3897 #define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */ 3898 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */ 3899 #define CAN_F11R1_FB31_Pos (31U) 3900 #define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */ 3901 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */ 3902 3903 /******************* Bit definition for CAN_F12R1 register ******************/ 3904 #define CAN_F12R1_FB0_Pos (0U) 3905 #define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */ 3906 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */ 3907 #define CAN_F12R1_FB1_Pos (1U) 3908 #define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */ 3909 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */ 3910 #define CAN_F12R1_FB2_Pos (2U) 3911 #define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */ 3912 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */ 3913 #define CAN_F12R1_FB3_Pos (3U) 3914 #define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */ 3915 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */ 3916 #define CAN_F12R1_FB4_Pos (4U) 3917 #define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */ 3918 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */ 3919 #define CAN_F12R1_FB5_Pos (5U) 3920 #define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */ 3921 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */ 3922 #define CAN_F12R1_FB6_Pos (6U) 3923 #define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */ 3924 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */ 3925 #define CAN_F12R1_FB7_Pos (7U) 3926 #define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */ 3927 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */ 3928 #define CAN_F12R1_FB8_Pos (8U) 3929 #define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */ 3930 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */ 3931 #define CAN_F12R1_FB9_Pos (9U) 3932 #define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */ 3933 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */ 3934 #define CAN_F12R1_FB10_Pos (10U) 3935 #define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */ 3936 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */ 3937 #define CAN_F12R1_FB11_Pos (11U) 3938 #define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */ 3939 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */ 3940 #define CAN_F12R1_FB12_Pos (12U) 3941 #define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */ 3942 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */ 3943 #define CAN_F12R1_FB13_Pos (13U) 3944 #define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */ 3945 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */ 3946 #define CAN_F12R1_FB14_Pos (14U) 3947 #define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */ 3948 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */ 3949 #define CAN_F12R1_FB15_Pos (15U) 3950 #define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */ 3951 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */ 3952 #define CAN_F12R1_FB16_Pos (16U) 3953 #define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */ 3954 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */ 3955 #define CAN_F12R1_FB17_Pos (17U) 3956 #define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */ 3957 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */ 3958 #define CAN_F12R1_FB18_Pos (18U) 3959 #define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */ 3960 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */ 3961 #define CAN_F12R1_FB19_Pos (19U) 3962 #define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */ 3963 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */ 3964 #define CAN_F12R1_FB20_Pos (20U) 3965 #define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */ 3966 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */ 3967 #define CAN_F12R1_FB21_Pos (21U) 3968 #define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */ 3969 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */ 3970 #define CAN_F12R1_FB22_Pos (22U) 3971 #define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */ 3972 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */ 3973 #define CAN_F12R1_FB23_Pos (23U) 3974 #define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */ 3975 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */ 3976 #define CAN_F12R1_FB24_Pos (24U) 3977 #define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */ 3978 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */ 3979 #define CAN_F12R1_FB25_Pos (25U) 3980 #define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */ 3981 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */ 3982 #define CAN_F12R1_FB26_Pos (26U) 3983 #define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */ 3984 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */ 3985 #define CAN_F12R1_FB27_Pos (27U) 3986 #define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */ 3987 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */ 3988 #define CAN_F12R1_FB28_Pos (28U) 3989 #define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */ 3990 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */ 3991 #define CAN_F12R1_FB29_Pos (29U) 3992 #define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */ 3993 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */ 3994 #define CAN_F12R1_FB30_Pos (30U) 3995 #define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */ 3996 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */ 3997 #define CAN_F12R1_FB31_Pos (31U) 3998 #define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */ 3999 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */ 4000 4001 /******************* Bit definition for CAN_F13R1 register ******************/ 4002 #define CAN_F13R1_FB0_Pos (0U) 4003 #define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */ 4004 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */ 4005 #define CAN_F13R1_FB1_Pos (1U) 4006 #define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */ 4007 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */ 4008 #define CAN_F13R1_FB2_Pos (2U) 4009 #define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */ 4010 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */ 4011 #define CAN_F13R1_FB3_Pos (3U) 4012 #define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */ 4013 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */ 4014 #define CAN_F13R1_FB4_Pos (4U) 4015 #define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */ 4016 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */ 4017 #define CAN_F13R1_FB5_Pos (5U) 4018 #define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */ 4019 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */ 4020 #define CAN_F13R1_FB6_Pos (6U) 4021 #define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */ 4022 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */ 4023 #define CAN_F13R1_FB7_Pos (7U) 4024 #define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */ 4025 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */ 4026 #define CAN_F13R1_FB8_Pos (8U) 4027 #define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */ 4028 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */ 4029 #define CAN_F13R1_FB9_Pos (9U) 4030 #define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */ 4031 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */ 4032 #define CAN_F13R1_FB10_Pos (10U) 4033 #define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */ 4034 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */ 4035 #define CAN_F13R1_FB11_Pos (11U) 4036 #define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */ 4037 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */ 4038 #define CAN_F13R1_FB12_Pos (12U) 4039 #define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */ 4040 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */ 4041 #define CAN_F13R1_FB13_Pos (13U) 4042 #define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */ 4043 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */ 4044 #define CAN_F13R1_FB14_Pos (14U) 4045 #define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */ 4046 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */ 4047 #define CAN_F13R1_FB15_Pos (15U) 4048 #define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */ 4049 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */ 4050 #define CAN_F13R1_FB16_Pos (16U) 4051 #define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */ 4052 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */ 4053 #define CAN_F13R1_FB17_Pos (17U) 4054 #define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */ 4055 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */ 4056 #define CAN_F13R1_FB18_Pos (18U) 4057 #define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */ 4058 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */ 4059 #define CAN_F13R1_FB19_Pos (19U) 4060 #define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */ 4061 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */ 4062 #define CAN_F13R1_FB20_Pos (20U) 4063 #define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */ 4064 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */ 4065 #define CAN_F13R1_FB21_Pos (21U) 4066 #define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */ 4067 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */ 4068 #define CAN_F13R1_FB22_Pos (22U) 4069 #define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */ 4070 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */ 4071 #define CAN_F13R1_FB23_Pos (23U) 4072 #define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */ 4073 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */ 4074 #define CAN_F13R1_FB24_Pos (24U) 4075 #define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */ 4076 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */ 4077 #define CAN_F13R1_FB25_Pos (25U) 4078 #define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */ 4079 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */ 4080 #define CAN_F13R1_FB26_Pos (26U) 4081 #define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */ 4082 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */ 4083 #define CAN_F13R1_FB27_Pos (27U) 4084 #define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */ 4085 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */ 4086 #define CAN_F13R1_FB28_Pos (28U) 4087 #define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */ 4088 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */ 4089 #define CAN_F13R1_FB29_Pos (29U) 4090 #define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */ 4091 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */ 4092 #define CAN_F13R1_FB30_Pos (30U) 4093 #define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */ 4094 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */ 4095 #define CAN_F13R1_FB31_Pos (31U) 4096 #define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */ 4097 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */ 4098 4099 /******************* Bit definition for CAN_F0R2 register *******************/ 4100 #define CAN_F0R2_FB0_Pos (0U) 4101 #define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */ 4102 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */ 4103 #define CAN_F0R2_FB1_Pos (1U) 4104 #define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */ 4105 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */ 4106 #define CAN_F0R2_FB2_Pos (2U) 4107 #define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */ 4108 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */ 4109 #define CAN_F0R2_FB3_Pos (3U) 4110 #define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */ 4111 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */ 4112 #define CAN_F0R2_FB4_Pos (4U) 4113 #define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */ 4114 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */ 4115 #define CAN_F0R2_FB5_Pos (5U) 4116 #define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */ 4117 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */ 4118 #define CAN_F0R2_FB6_Pos (6U) 4119 #define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */ 4120 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */ 4121 #define CAN_F0R2_FB7_Pos (7U) 4122 #define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */ 4123 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */ 4124 #define CAN_F0R2_FB8_Pos (8U) 4125 #define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */ 4126 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */ 4127 #define CAN_F0R2_FB9_Pos (9U) 4128 #define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */ 4129 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */ 4130 #define CAN_F0R2_FB10_Pos (10U) 4131 #define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */ 4132 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */ 4133 #define CAN_F0R2_FB11_Pos (11U) 4134 #define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */ 4135 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */ 4136 #define CAN_F0R2_FB12_Pos (12U) 4137 #define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */ 4138 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */ 4139 #define CAN_F0R2_FB13_Pos (13U) 4140 #define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */ 4141 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */ 4142 #define CAN_F0R2_FB14_Pos (14U) 4143 #define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */ 4144 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */ 4145 #define CAN_F0R2_FB15_Pos (15U) 4146 #define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */ 4147 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */ 4148 #define CAN_F0R2_FB16_Pos (16U) 4149 #define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */ 4150 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */ 4151 #define CAN_F0R2_FB17_Pos (17U) 4152 #define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */ 4153 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */ 4154 #define CAN_F0R2_FB18_Pos (18U) 4155 #define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */ 4156 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */ 4157 #define CAN_F0R2_FB19_Pos (19U) 4158 #define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */ 4159 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */ 4160 #define CAN_F0R2_FB20_Pos (20U) 4161 #define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */ 4162 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */ 4163 #define CAN_F0R2_FB21_Pos (21U) 4164 #define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */ 4165 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */ 4166 #define CAN_F0R2_FB22_Pos (22U) 4167 #define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */ 4168 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */ 4169 #define CAN_F0R2_FB23_Pos (23U) 4170 #define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */ 4171 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */ 4172 #define CAN_F0R2_FB24_Pos (24U) 4173 #define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */ 4174 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */ 4175 #define CAN_F0R2_FB25_Pos (25U) 4176 #define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */ 4177 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */ 4178 #define CAN_F0R2_FB26_Pos (26U) 4179 #define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */ 4180 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */ 4181 #define CAN_F0R2_FB27_Pos (27U) 4182 #define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */ 4183 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */ 4184 #define CAN_F0R2_FB28_Pos (28U) 4185 #define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */ 4186 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */ 4187 #define CAN_F0R2_FB29_Pos (29U) 4188 #define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */ 4189 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */ 4190 #define CAN_F0R2_FB30_Pos (30U) 4191 #define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */ 4192 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */ 4193 #define CAN_F0R2_FB31_Pos (31U) 4194 #define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */ 4195 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */ 4196 4197 /******************* Bit definition for CAN_F1R2 register *******************/ 4198 #define CAN_F1R2_FB0_Pos (0U) 4199 #define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */ 4200 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */ 4201 #define CAN_F1R2_FB1_Pos (1U) 4202 #define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */ 4203 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */ 4204 #define CAN_F1R2_FB2_Pos (2U) 4205 #define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */ 4206 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */ 4207 #define CAN_F1R2_FB3_Pos (3U) 4208 #define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */ 4209 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */ 4210 #define CAN_F1R2_FB4_Pos (4U) 4211 #define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */ 4212 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */ 4213 #define CAN_F1R2_FB5_Pos (5U) 4214 #define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */ 4215 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */ 4216 #define CAN_F1R2_FB6_Pos (6U) 4217 #define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */ 4218 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */ 4219 #define CAN_F1R2_FB7_Pos (7U) 4220 #define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */ 4221 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */ 4222 #define CAN_F1R2_FB8_Pos (8U) 4223 #define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */ 4224 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */ 4225 #define CAN_F1R2_FB9_Pos (9U) 4226 #define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */ 4227 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */ 4228 #define CAN_F1R2_FB10_Pos (10U) 4229 #define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */ 4230 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */ 4231 #define CAN_F1R2_FB11_Pos (11U) 4232 #define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */ 4233 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */ 4234 #define CAN_F1R2_FB12_Pos (12U) 4235 #define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */ 4236 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */ 4237 #define CAN_F1R2_FB13_Pos (13U) 4238 #define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */ 4239 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */ 4240 #define CAN_F1R2_FB14_Pos (14U) 4241 #define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */ 4242 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */ 4243 #define CAN_F1R2_FB15_Pos (15U) 4244 #define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */ 4245 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */ 4246 #define CAN_F1R2_FB16_Pos (16U) 4247 #define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */ 4248 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */ 4249 #define CAN_F1R2_FB17_Pos (17U) 4250 #define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */ 4251 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */ 4252 #define CAN_F1R2_FB18_Pos (18U) 4253 #define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */ 4254 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */ 4255 #define CAN_F1R2_FB19_Pos (19U) 4256 #define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */ 4257 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */ 4258 #define CAN_F1R2_FB20_Pos (20U) 4259 #define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */ 4260 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */ 4261 #define CAN_F1R2_FB21_Pos (21U) 4262 #define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */ 4263 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */ 4264 #define CAN_F1R2_FB22_Pos (22U) 4265 #define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */ 4266 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */ 4267 #define CAN_F1R2_FB23_Pos (23U) 4268 #define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */ 4269 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */ 4270 #define CAN_F1R2_FB24_Pos (24U) 4271 #define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */ 4272 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */ 4273 #define CAN_F1R2_FB25_Pos (25U) 4274 #define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */ 4275 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */ 4276 #define CAN_F1R2_FB26_Pos (26U) 4277 #define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */ 4278 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */ 4279 #define CAN_F1R2_FB27_Pos (27U) 4280 #define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */ 4281 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */ 4282 #define CAN_F1R2_FB28_Pos (28U) 4283 #define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */ 4284 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */ 4285 #define CAN_F1R2_FB29_Pos (29U) 4286 #define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */ 4287 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */ 4288 #define CAN_F1R2_FB30_Pos (30U) 4289 #define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */ 4290 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */ 4291 #define CAN_F1R2_FB31_Pos (31U) 4292 #define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */ 4293 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */ 4294 4295 /******************* Bit definition for CAN_F2R2 register *******************/ 4296 #define CAN_F2R2_FB0_Pos (0U) 4297 #define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */ 4298 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */ 4299 #define CAN_F2R2_FB1_Pos (1U) 4300 #define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */ 4301 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */ 4302 #define CAN_F2R2_FB2_Pos (2U) 4303 #define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */ 4304 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */ 4305 #define CAN_F2R2_FB3_Pos (3U) 4306 #define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */ 4307 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */ 4308 #define CAN_F2R2_FB4_Pos (4U) 4309 #define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */ 4310 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */ 4311 #define CAN_F2R2_FB5_Pos (5U) 4312 #define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */ 4313 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */ 4314 #define CAN_F2R2_FB6_Pos (6U) 4315 #define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */ 4316 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */ 4317 #define CAN_F2R2_FB7_Pos (7U) 4318 #define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */ 4319 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */ 4320 #define CAN_F2R2_FB8_Pos (8U) 4321 #define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */ 4322 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */ 4323 #define CAN_F2R2_FB9_Pos (9U) 4324 #define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */ 4325 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */ 4326 #define CAN_F2R2_FB10_Pos (10U) 4327 #define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */ 4328 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */ 4329 #define CAN_F2R2_FB11_Pos (11U) 4330 #define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */ 4331 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */ 4332 #define CAN_F2R2_FB12_Pos (12U) 4333 #define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */ 4334 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */ 4335 #define CAN_F2R2_FB13_Pos (13U) 4336 #define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */ 4337 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */ 4338 #define CAN_F2R2_FB14_Pos (14U) 4339 #define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */ 4340 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */ 4341 #define CAN_F2R2_FB15_Pos (15U) 4342 #define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */ 4343 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */ 4344 #define CAN_F2R2_FB16_Pos (16U) 4345 #define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */ 4346 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */ 4347 #define CAN_F2R2_FB17_Pos (17U) 4348 #define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */ 4349 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */ 4350 #define CAN_F2R2_FB18_Pos (18U) 4351 #define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */ 4352 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */ 4353 #define CAN_F2R2_FB19_Pos (19U) 4354 #define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */ 4355 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */ 4356 #define CAN_F2R2_FB20_Pos (20U) 4357 #define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */ 4358 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */ 4359 #define CAN_F2R2_FB21_Pos (21U) 4360 #define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */ 4361 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */ 4362 #define CAN_F2R2_FB22_Pos (22U) 4363 #define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */ 4364 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */ 4365 #define CAN_F2R2_FB23_Pos (23U) 4366 #define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */ 4367 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */ 4368 #define CAN_F2R2_FB24_Pos (24U) 4369 #define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */ 4370 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */ 4371 #define CAN_F2R2_FB25_Pos (25U) 4372 #define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */ 4373 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */ 4374 #define CAN_F2R2_FB26_Pos (26U) 4375 #define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */ 4376 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */ 4377 #define CAN_F2R2_FB27_Pos (27U) 4378 #define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */ 4379 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */ 4380 #define CAN_F2R2_FB28_Pos (28U) 4381 #define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */ 4382 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */ 4383 #define CAN_F2R2_FB29_Pos (29U) 4384 #define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */ 4385 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */ 4386 #define CAN_F2R2_FB30_Pos (30U) 4387 #define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */ 4388 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */ 4389 #define CAN_F2R2_FB31_Pos (31U) 4390 #define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */ 4391 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */ 4392 4393 /******************* Bit definition for CAN_F3R2 register *******************/ 4394 #define CAN_F3R2_FB0_Pos (0U) 4395 #define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */ 4396 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */ 4397 #define CAN_F3R2_FB1_Pos (1U) 4398 #define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */ 4399 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */ 4400 #define CAN_F3R2_FB2_Pos (2U) 4401 #define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */ 4402 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */ 4403 #define CAN_F3R2_FB3_Pos (3U) 4404 #define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */ 4405 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */ 4406 #define CAN_F3R2_FB4_Pos (4U) 4407 #define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */ 4408 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */ 4409 #define CAN_F3R2_FB5_Pos (5U) 4410 #define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */ 4411 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */ 4412 #define CAN_F3R2_FB6_Pos (6U) 4413 #define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */ 4414 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */ 4415 #define CAN_F3R2_FB7_Pos (7U) 4416 #define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */ 4417 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */ 4418 #define CAN_F3R2_FB8_Pos (8U) 4419 #define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */ 4420 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */ 4421 #define CAN_F3R2_FB9_Pos (9U) 4422 #define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */ 4423 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */ 4424 #define CAN_F3R2_FB10_Pos (10U) 4425 #define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */ 4426 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */ 4427 #define CAN_F3R2_FB11_Pos (11U) 4428 #define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */ 4429 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */ 4430 #define CAN_F3R2_FB12_Pos (12U) 4431 #define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */ 4432 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */ 4433 #define CAN_F3R2_FB13_Pos (13U) 4434 #define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */ 4435 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */ 4436 #define CAN_F3R2_FB14_Pos (14U) 4437 #define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */ 4438 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */ 4439 #define CAN_F3R2_FB15_Pos (15U) 4440 #define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */ 4441 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */ 4442 #define CAN_F3R2_FB16_Pos (16U) 4443 #define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */ 4444 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */ 4445 #define CAN_F3R2_FB17_Pos (17U) 4446 #define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */ 4447 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */ 4448 #define CAN_F3R2_FB18_Pos (18U) 4449 #define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */ 4450 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */ 4451 #define CAN_F3R2_FB19_Pos (19U) 4452 #define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */ 4453 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */ 4454 #define CAN_F3R2_FB20_Pos (20U) 4455 #define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */ 4456 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */ 4457 #define CAN_F3R2_FB21_Pos (21U) 4458 #define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */ 4459 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */ 4460 #define CAN_F3R2_FB22_Pos (22U) 4461 #define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */ 4462 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */ 4463 #define CAN_F3R2_FB23_Pos (23U) 4464 #define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */ 4465 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */ 4466 #define CAN_F3R2_FB24_Pos (24U) 4467 #define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */ 4468 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */ 4469 #define CAN_F3R2_FB25_Pos (25U) 4470 #define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */ 4471 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */ 4472 #define CAN_F3R2_FB26_Pos (26U) 4473 #define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */ 4474 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */ 4475 #define CAN_F3R2_FB27_Pos (27U) 4476 #define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */ 4477 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */ 4478 #define CAN_F3R2_FB28_Pos (28U) 4479 #define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */ 4480 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */ 4481 #define CAN_F3R2_FB29_Pos (29U) 4482 #define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */ 4483 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */ 4484 #define CAN_F3R2_FB30_Pos (30U) 4485 #define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */ 4486 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */ 4487 #define CAN_F3R2_FB31_Pos (31U) 4488 #define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */ 4489 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */ 4490 4491 /******************* Bit definition for CAN_F4R2 register *******************/ 4492 #define CAN_F4R2_FB0_Pos (0U) 4493 #define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */ 4494 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */ 4495 #define CAN_F4R2_FB1_Pos (1U) 4496 #define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */ 4497 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */ 4498 #define CAN_F4R2_FB2_Pos (2U) 4499 #define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */ 4500 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */ 4501 #define CAN_F4R2_FB3_Pos (3U) 4502 #define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */ 4503 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */ 4504 #define CAN_F4R2_FB4_Pos (4U) 4505 #define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */ 4506 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */ 4507 #define CAN_F4R2_FB5_Pos (5U) 4508 #define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */ 4509 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */ 4510 #define CAN_F4R2_FB6_Pos (6U) 4511 #define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */ 4512 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */ 4513 #define CAN_F4R2_FB7_Pos (7U) 4514 #define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */ 4515 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */ 4516 #define CAN_F4R2_FB8_Pos (8U) 4517 #define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */ 4518 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */ 4519 #define CAN_F4R2_FB9_Pos (9U) 4520 #define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */ 4521 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */ 4522 #define CAN_F4R2_FB10_Pos (10U) 4523 #define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */ 4524 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */ 4525 #define CAN_F4R2_FB11_Pos (11U) 4526 #define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */ 4527 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */ 4528 #define CAN_F4R2_FB12_Pos (12U) 4529 #define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */ 4530 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */ 4531 #define CAN_F4R2_FB13_Pos (13U) 4532 #define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */ 4533 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */ 4534 #define CAN_F4R2_FB14_Pos (14U) 4535 #define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */ 4536 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */ 4537 #define CAN_F4R2_FB15_Pos (15U) 4538 #define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */ 4539 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */ 4540 #define CAN_F4R2_FB16_Pos (16U) 4541 #define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */ 4542 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */ 4543 #define CAN_F4R2_FB17_Pos (17U) 4544 #define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */ 4545 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */ 4546 #define CAN_F4R2_FB18_Pos (18U) 4547 #define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */ 4548 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */ 4549 #define CAN_F4R2_FB19_Pos (19U) 4550 #define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */ 4551 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */ 4552 #define CAN_F4R2_FB20_Pos (20U) 4553 #define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */ 4554 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */ 4555 #define CAN_F4R2_FB21_Pos (21U) 4556 #define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */ 4557 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */ 4558 #define CAN_F4R2_FB22_Pos (22U) 4559 #define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */ 4560 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */ 4561 #define CAN_F4R2_FB23_Pos (23U) 4562 #define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */ 4563 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */ 4564 #define CAN_F4R2_FB24_Pos (24U) 4565 #define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */ 4566 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */ 4567 #define CAN_F4R2_FB25_Pos (25U) 4568 #define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */ 4569 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */ 4570 #define CAN_F4R2_FB26_Pos (26U) 4571 #define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */ 4572 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */ 4573 #define CAN_F4R2_FB27_Pos (27U) 4574 #define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */ 4575 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */ 4576 #define CAN_F4R2_FB28_Pos (28U) 4577 #define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */ 4578 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */ 4579 #define CAN_F4R2_FB29_Pos (29U) 4580 #define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */ 4581 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */ 4582 #define CAN_F4R2_FB30_Pos (30U) 4583 #define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */ 4584 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */ 4585 #define CAN_F4R2_FB31_Pos (31U) 4586 #define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */ 4587 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */ 4588 4589 /******************* Bit definition for CAN_F5R2 register *******************/ 4590 #define CAN_F5R2_FB0_Pos (0U) 4591 #define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */ 4592 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */ 4593 #define CAN_F5R2_FB1_Pos (1U) 4594 #define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */ 4595 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */ 4596 #define CAN_F5R2_FB2_Pos (2U) 4597 #define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */ 4598 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */ 4599 #define CAN_F5R2_FB3_Pos (3U) 4600 #define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */ 4601 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */ 4602 #define CAN_F5R2_FB4_Pos (4U) 4603 #define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */ 4604 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */ 4605 #define CAN_F5R2_FB5_Pos (5U) 4606 #define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */ 4607 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */ 4608 #define CAN_F5R2_FB6_Pos (6U) 4609 #define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */ 4610 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */ 4611 #define CAN_F5R2_FB7_Pos (7U) 4612 #define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */ 4613 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */ 4614 #define CAN_F5R2_FB8_Pos (8U) 4615 #define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */ 4616 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */ 4617 #define CAN_F5R2_FB9_Pos (9U) 4618 #define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */ 4619 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */ 4620 #define CAN_F5R2_FB10_Pos (10U) 4621 #define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */ 4622 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */ 4623 #define CAN_F5R2_FB11_Pos (11U) 4624 #define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */ 4625 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */ 4626 #define CAN_F5R2_FB12_Pos (12U) 4627 #define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */ 4628 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */ 4629 #define CAN_F5R2_FB13_Pos (13U) 4630 #define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */ 4631 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */ 4632 #define CAN_F5R2_FB14_Pos (14U) 4633 #define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */ 4634 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */ 4635 #define CAN_F5R2_FB15_Pos (15U) 4636 #define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */ 4637 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */ 4638 #define CAN_F5R2_FB16_Pos (16U) 4639 #define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */ 4640 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */ 4641 #define CAN_F5R2_FB17_Pos (17U) 4642 #define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */ 4643 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */ 4644 #define CAN_F5R2_FB18_Pos (18U) 4645 #define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */ 4646 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */ 4647 #define CAN_F5R2_FB19_Pos (19U) 4648 #define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */ 4649 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */ 4650 #define CAN_F5R2_FB20_Pos (20U) 4651 #define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */ 4652 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */ 4653 #define CAN_F5R2_FB21_Pos (21U) 4654 #define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */ 4655 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */ 4656 #define CAN_F5R2_FB22_Pos (22U) 4657 #define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */ 4658 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */ 4659 #define CAN_F5R2_FB23_Pos (23U) 4660 #define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */ 4661 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */ 4662 #define CAN_F5R2_FB24_Pos (24U) 4663 #define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */ 4664 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */ 4665 #define CAN_F5R2_FB25_Pos (25U) 4666 #define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */ 4667 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */ 4668 #define CAN_F5R2_FB26_Pos (26U) 4669 #define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */ 4670 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */ 4671 #define CAN_F5R2_FB27_Pos (27U) 4672 #define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */ 4673 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */ 4674 #define CAN_F5R2_FB28_Pos (28U) 4675 #define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */ 4676 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */ 4677 #define CAN_F5R2_FB29_Pos (29U) 4678 #define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */ 4679 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */ 4680 #define CAN_F5R2_FB30_Pos (30U) 4681 #define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */ 4682 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */ 4683 #define CAN_F5R2_FB31_Pos (31U) 4684 #define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */ 4685 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */ 4686 4687 /******************* Bit definition for CAN_F6R2 register *******************/ 4688 #define CAN_F6R2_FB0_Pos (0U) 4689 #define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */ 4690 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */ 4691 #define CAN_F6R2_FB1_Pos (1U) 4692 #define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */ 4693 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */ 4694 #define CAN_F6R2_FB2_Pos (2U) 4695 #define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */ 4696 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */ 4697 #define CAN_F6R2_FB3_Pos (3U) 4698 #define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */ 4699 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */ 4700 #define CAN_F6R2_FB4_Pos (4U) 4701 #define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */ 4702 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */ 4703 #define CAN_F6R2_FB5_Pos (5U) 4704 #define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */ 4705 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */ 4706 #define CAN_F6R2_FB6_Pos (6U) 4707 #define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */ 4708 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */ 4709 #define CAN_F6R2_FB7_Pos (7U) 4710 #define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */ 4711 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */ 4712 #define CAN_F6R2_FB8_Pos (8U) 4713 #define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */ 4714 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */ 4715 #define CAN_F6R2_FB9_Pos (9U) 4716 #define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */ 4717 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */ 4718 #define CAN_F6R2_FB10_Pos (10U) 4719 #define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */ 4720 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */ 4721 #define CAN_F6R2_FB11_Pos (11U) 4722 #define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */ 4723 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */ 4724 #define CAN_F6R2_FB12_Pos (12U) 4725 #define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */ 4726 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */ 4727 #define CAN_F6R2_FB13_Pos (13U) 4728 #define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */ 4729 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */ 4730 #define CAN_F6R2_FB14_Pos (14U) 4731 #define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */ 4732 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */ 4733 #define CAN_F6R2_FB15_Pos (15U) 4734 #define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */ 4735 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */ 4736 #define CAN_F6R2_FB16_Pos (16U) 4737 #define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */ 4738 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */ 4739 #define CAN_F6R2_FB17_Pos (17U) 4740 #define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */ 4741 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */ 4742 #define CAN_F6R2_FB18_Pos (18U) 4743 #define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */ 4744 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */ 4745 #define CAN_F6R2_FB19_Pos (19U) 4746 #define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */ 4747 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */ 4748 #define CAN_F6R2_FB20_Pos (20U) 4749 #define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */ 4750 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */ 4751 #define CAN_F6R2_FB21_Pos (21U) 4752 #define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */ 4753 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */ 4754 #define CAN_F6R2_FB22_Pos (22U) 4755 #define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */ 4756 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */ 4757 #define CAN_F6R2_FB23_Pos (23U) 4758 #define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */ 4759 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */ 4760 #define CAN_F6R2_FB24_Pos (24U) 4761 #define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */ 4762 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */ 4763 #define CAN_F6R2_FB25_Pos (25U) 4764 #define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */ 4765 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */ 4766 #define CAN_F6R2_FB26_Pos (26U) 4767 #define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */ 4768 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */ 4769 #define CAN_F6R2_FB27_Pos (27U) 4770 #define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */ 4771 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */ 4772 #define CAN_F6R2_FB28_Pos (28U) 4773 #define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */ 4774 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */ 4775 #define CAN_F6R2_FB29_Pos (29U) 4776 #define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */ 4777 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */ 4778 #define CAN_F6R2_FB30_Pos (30U) 4779 #define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */ 4780 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */ 4781 #define CAN_F6R2_FB31_Pos (31U) 4782 #define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */ 4783 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */ 4784 4785 /******************* Bit definition for CAN_F7R2 register *******************/ 4786 #define CAN_F7R2_FB0_Pos (0U) 4787 #define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */ 4788 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */ 4789 #define CAN_F7R2_FB1_Pos (1U) 4790 #define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */ 4791 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */ 4792 #define CAN_F7R2_FB2_Pos (2U) 4793 #define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */ 4794 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */ 4795 #define CAN_F7R2_FB3_Pos (3U) 4796 #define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */ 4797 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */ 4798 #define CAN_F7R2_FB4_Pos (4U) 4799 #define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */ 4800 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */ 4801 #define CAN_F7R2_FB5_Pos (5U) 4802 #define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */ 4803 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */ 4804 #define CAN_F7R2_FB6_Pos (6U) 4805 #define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */ 4806 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */ 4807 #define CAN_F7R2_FB7_Pos (7U) 4808 #define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */ 4809 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */ 4810 #define CAN_F7R2_FB8_Pos (8U) 4811 #define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */ 4812 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */ 4813 #define CAN_F7R2_FB9_Pos (9U) 4814 #define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */ 4815 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */ 4816 #define CAN_F7R2_FB10_Pos (10U) 4817 #define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */ 4818 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */ 4819 #define CAN_F7R2_FB11_Pos (11U) 4820 #define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */ 4821 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */ 4822 #define CAN_F7R2_FB12_Pos (12U) 4823 #define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */ 4824 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */ 4825 #define CAN_F7R2_FB13_Pos (13U) 4826 #define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */ 4827 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */ 4828 #define CAN_F7R2_FB14_Pos (14U) 4829 #define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */ 4830 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */ 4831 #define CAN_F7R2_FB15_Pos (15U) 4832 #define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */ 4833 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */ 4834 #define CAN_F7R2_FB16_Pos (16U) 4835 #define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */ 4836 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */ 4837 #define CAN_F7R2_FB17_Pos (17U) 4838 #define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */ 4839 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */ 4840 #define CAN_F7R2_FB18_Pos (18U) 4841 #define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */ 4842 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */ 4843 #define CAN_F7R2_FB19_Pos (19U) 4844 #define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */ 4845 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */ 4846 #define CAN_F7R2_FB20_Pos (20U) 4847 #define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */ 4848 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */ 4849 #define CAN_F7R2_FB21_Pos (21U) 4850 #define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */ 4851 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */ 4852 #define CAN_F7R2_FB22_Pos (22U) 4853 #define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */ 4854 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */ 4855 #define CAN_F7R2_FB23_Pos (23U) 4856 #define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */ 4857 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */ 4858 #define CAN_F7R2_FB24_Pos (24U) 4859 #define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */ 4860 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */ 4861 #define CAN_F7R2_FB25_Pos (25U) 4862 #define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */ 4863 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */ 4864 #define CAN_F7R2_FB26_Pos (26U) 4865 #define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */ 4866 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */ 4867 #define CAN_F7R2_FB27_Pos (27U) 4868 #define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */ 4869 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */ 4870 #define CAN_F7R2_FB28_Pos (28U) 4871 #define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */ 4872 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */ 4873 #define CAN_F7R2_FB29_Pos (29U) 4874 #define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */ 4875 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */ 4876 #define CAN_F7R2_FB30_Pos (30U) 4877 #define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */ 4878 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */ 4879 #define CAN_F7R2_FB31_Pos (31U) 4880 #define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */ 4881 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */ 4882 4883 /******************* Bit definition for CAN_F8R2 register *******************/ 4884 #define CAN_F8R2_FB0_Pos (0U) 4885 #define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */ 4886 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */ 4887 #define CAN_F8R2_FB1_Pos (1U) 4888 #define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */ 4889 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */ 4890 #define CAN_F8R2_FB2_Pos (2U) 4891 #define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */ 4892 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */ 4893 #define CAN_F8R2_FB3_Pos (3U) 4894 #define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */ 4895 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */ 4896 #define CAN_F8R2_FB4_Pos (4U) 4897 #define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */ 4898 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */ 4899 #define CAN_F8R2_FB5_Pos (5U) 4900 #define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */ 4901 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */ 4902 #define CAN_F8R2_FB6_Pos (6U) 4903 #define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */ 4904 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */ 4905 #define CAN_F8R2_FB7_Pos (7U) 4906 #define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */ 4907 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */ 4908 #define CAN_F8R2_FB8_Pos (8U) 4909 #define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */ 4910 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */ 4911 #define CAN_F8R2_FB9_Pos (9U) 4912 #define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */ 4913 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */ 4914 #define CAN_F8R2_FB10_Pos (10U) 4915 #define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */ 4916 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */ 4917 #define CAN_F8R2_FB11_Pos (11U) 4918 #define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */ 4919 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */ 4920 #define CAN_F8R2_FB12_Pos (12U) 4921 #define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */ 4922 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */ 4923 #define CAN_F8R2_FB13_Pos (13U) 4924 #define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */ 4925 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */ 4926 #define CAN_F8R2_FB14_Pos (14U) 4927 #define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */ 4928 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */ 4929 #define CAN_F8R2_FB15_Pos (15U) 4930 #define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */ 4931 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */ 4932 #define CAN_F8R2_FB16_Pos (16U) 4933 #define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */ 4934 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */ 4935 #define CAN_F8R2_FB17_Pos (17U) 4936 #define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */ 4937 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */ 4938 #define CAN_F8R2_FB18_Pos (18U) 4939 #define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */ 4940 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */ 4941 #define CAN_F8R2_FB19_Pos (19U) 4942 #define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */ 4943 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */ 4944 #define CAN_F8R2_FB20_Pos (20U) 4945 #define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */ 4946 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */ 4947 #define CAN_F8R2_FB21_Pos (21U) 4948 #define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */ 4949 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */ 4950 #define CAN_F8R2_FB22_Pos (22U) 4951 #define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */ 4952 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */ 4953 #define CAN_F8R2_FB23_Pos (23U) 4954 #define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */ 4955 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */ 4956 #define CAN_F8R2_FB24_Pos (24U) 4957 #define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */ 4958 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */ 4959 #define CAN_F8R2_FB25_Pos (25U) 4960 #define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */ 4961 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */ 4962 #define CAN_F8R2_FB26_Pos (26U) 4963 #define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */ 4964 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */ 4965 #define CAN_F8R2_FB27_Pos (27U) 4966 #define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */ 4967 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */ 4968 #define CAN_F8R2_FB28_Pos (28U) 4969 #define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */ 4970 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */ 4971 #define CAN_F8R2_FB29_Pos (29U) 4972 #define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */ 4973 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */ 4974 #define CAN_F8R2_FB30_Pos (30U) 4975 #define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */ 4976 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */ 4977 #define CAN_F8R2_FB31_Pos (31U) 4978 #define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */ 4979 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */ 4980 4981 /******************* Bit definition for CAN_F9R2 register *******************/ 4982 #define CAN_F9R2_FB0_Pos (0U) 4983 #define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */ 4984 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */ 4985 #define CAN_F9R2_FB1_Pos (1U) 4986 #define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */ 4987 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */ 4988 #define CAN_F9R2_FB2_Pos (2U) 4989 #define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */ 4990 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */ 4991 #define CAN_F9R2_FB3_Pos (3U) 4992 #define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */ 4993 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */ 4994 #define CAN_F9R2_FB4_Pos (4U) 4995 #define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */ 4996 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */ 4997 #define CAN_F9R2_FB5_Pos (5U) 4998 #define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */ 4999 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */ 5000 #define CAN_F9R2_FB6_Pos (6U) 5001 #define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */ 5002 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */ 5003 #define CAN_F9R2_FB7_Pos (7U) 5004 #define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */ 5005 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */ 5006 #define CAN_F9R2_FB8_Pos (8U) 5007 #define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */ 5008 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */ 5009 #define CAN_F9R2_FB9_Pos (9U) 5010 #define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */ 5011 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */ 5012 #define CAN_F9R2_FB10_Pos (10U) 5013 #define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */ 5014 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */ 5015 #define CAN_F9R2_FB11_Pos (11U) 5016 #define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */ 5017 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */ 5018 #define CAN_F9R2_FB12_Pos (12U) 5019 #define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */ 5020 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */ 5021 #define CAN_F9R2_FB13_Pos (13U) 5022 #define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */ 5023 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */ 5024 #define CAN_F9R2_FB14_Pos (14U) 5025 #define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */ 5026 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */ 5027 #define CAN_F9R2_FB15_Pos (15U) 5028 #define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */ 5029 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */ 5030 #define CAN_F9R2_FB16_Pos (16U) 5031 #define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */ 5032 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */ 5033 #define CAN_F9R2_FB17_Pos (17U) 5034 #define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */ 5035 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */ 5036 #define CAN_F9R2_FB18_Pos (18U) 5037 #define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */ 5038 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */ 5039 #define CAN_F9R2_FB19_Pos (19U) 5040 #define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */ 5041 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */ 5042 #define CAN_F9R2_FB20_Pos (20U) 5043 #define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */ 5044 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */ 5045 #define CAN_F9R2_FB21_Pos (21U) 5046 #define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */ 5047 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */ 5048 #define CAN_F9R2_FB22_Pos (22U) 5049 #define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */ 5050 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */ 5051 #define CAN_F9R2_FB23_Pos (23U) 5052 #define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */ 5053 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */ 5054 #define CAN_F9R2_FB24_Pos (24U) 5055 #define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */ 5056 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */ 5057 #define CAN_F9R2_FB25_Pos (25U) 5058 #define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */ 5059 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */ 5060 #define CAN_F9R2_FB26_Pos (26U) 5061 #define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */ 5062 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */ 5063 #define CAN_F9R2_FB27_Pos (27U) 5064 #define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */ 5065 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */ 5066 #define CAN_F9R2_FB28_Pos (28U) 5067 #define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */ 5068 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */ 5069 #define CAN_F9R2_FB29_Pos (29U) 5070 #define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */ 5071 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */ 5072 #define CAN_F9R2_FB30_Pos (30U) 5073 #define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */ 5074 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */ 5075 #define CAN_F9R2_FB31_Pos (31U) 5076 #define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */ 5077 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */ 5078 5079 /******************* Bit definition for CAN_F10R2 register ******************/ 5080 #define CAN_F10R2_FB0_Pos (0U) 5081 #define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */ 5082 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */ 5083 #define CAN_F10R2_FB1_Pos (1U) 5084 #define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */ 5085 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */ 5086 #define CAN_F10R2_FB2_Pos (2U) 5087 #define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */ 5088 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */ 5089 #define CAN_F10R2_FB3_Pos (3U) 5090 #define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */ 5091 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */ 5092 #define CAN_F10R2_FB4_Pos (4U) 5093 #define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */ 5094 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */ 5095 #define CAN_F10R2_FB5_Pos (5U) 5096 #define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */ 5097 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */ 5098 #define CAN_F10R2_FB6_Pos (6U) 5099 #define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */ 5100 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */ 5101 #define CAN_F10R2_FB7_Pos (7U) 5102 #define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */ 5103 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */ 5104 #define CAN_F10R2_FB8_Pos (8U) 5105 #define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */ 5106 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */ 5107 #define CAN_F10R2_FB9_Pos (9U) 5108 #define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */ 5109 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */ 5110 #define CAN_F10R2_FB10_Pos (10U) 5111 #define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */ 5112 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */ 5113 #define CAN_F10R2_FB11_Pos (11U) 5114 #define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */ 5115 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */ 5116 #define CAN_F10R2_FB12_Pos (12U) 5117 #define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */ 5118 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */ 5119 #define CAN_F10R2_FB13_Pos (13U) 5120 #define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */ 5121 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */ 5122 #define CAN_F10R2_FB14_Pos (14U) 5123 #define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */ 5124 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */ 5125 #define CAN_F10R2_FB15_Pos (15U) 5126 #define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */ 5127 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */ 5128 #define CAN_F10R2_FB16_Pos (16U) 5129 #define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */ 5130 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */ 5131 #define CAN_F10R2_FB17_Pos (17U) 5132 #define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */ 5133 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */ 5134 #define CAN_F10R2_FB18_Pos (18U) 5135 #define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */ 5136 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */ 5137 #define CAN_F10R2_FB19_Pos (19U) 5138 #define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */ 5139 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */ 5140 #define CAN_F10R2_FB20_Pos (20U) 5141 #define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */ 5142 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */ 5143 #define CAN_F10R2_FB21_Pos (21U) 5144 #define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */ 5145 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */ 5146 #define CAN_F10R2_FB22_Pos (22U) 5147 #define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */ 5148 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */ 5149 #define CAN_F10R2_FB23_Pos (23U) 5150 #define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */ 5151 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */ 5152 #define CAN_F10R2_FB24_Pos (24U) 5153 #define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */ 5154 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */ 5155 #define CAN_F10R2_FB25_Pos (25U) 5156 #define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */ 5157 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */ 5158 #define CAN_F10R2_FB26_Pos (26U) 5159 #define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */ 5160 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */ 5161 #define CAN_F10R2_FB27_Pos (27U) 5162 #define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */ 5163 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */ 5164 #define CAN_F10R2_FB28_Pos (28U) 5165 #define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */ 5166 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */ 5167 #define CAN_F10R2_FB29_Pos (29U) 5168 #define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */ 5169 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */ 5170 #define CAN_F10R2_FB30_Pos (30U) 5171 #define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */ 5172 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */ 5173 #define CAN_F10R2_FB31_Pos (31U) 5174 #define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */ 5175 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */ 5176 5177 /******************* Bit definition for CAN_F11R2 register ******************/ 5178 #define CAN_F11R2_FB0_Pos (0U) 5179 #define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */ 5180 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */ 5181 #define CAN_F11R2_FB1_Pos (1U) 5182 #define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */ 5183 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */ 5184 #define CAN_F11R2_FB2_Pos (2U) 5185 #define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */ 5186 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */ 5187 #define CAN_F11R2_FB3_Pos (3U) 5188 #define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */ 5189 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */ 5190 #define CAN_F11R2_FB4_Pos (4U) 5191 #define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */ 5192 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */ 5193 #define CAN_F11R2_FB5_Pos (5U) 5194 #define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */ 5195 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */ 5196 #define CAN_F11R2_FB6_Pos (6U) 5197 #define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */ 5198 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */ 5199 #define CAN_F11R2_FB7_Pos (7U) 5200 #define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */ 5201 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */ 5202 #define CAN_F11R2_FB8_Pos (8U) 5203 #define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */ 5204 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */ 5205 #define CAN_F11R2_FB9_Pos (9U) 5206 #define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */ 5207 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */ 5208 #define CAN_F11R2_FB10_Pos (10U) 5209 #define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */ 5210 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */ 5211 #define CAN_F11R2_FB11_Pos (11U) 5212 #define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */ 5213 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */ 5214 #define CAN_F11R2_FB12_Pos (12U) 5215 #define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */ 5216 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */ 5217 #define CAN_F11R2_FB13_Pos (13U) 5218 #define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */ 5219 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */ 5220 #define CAN_F11R2_FB14_Pos (14U) 5221 #define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */ 5222 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */ 5223 #define CAN_F11R2_FB15_Pos (15U) 5224 #define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */ 5225 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */ 5226 #define CAN_F11R2_FB16_Pos (16U) 5227 #define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */ 5228 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */ 5229 #define CAN_F11R2_FB17_Pos (17U) 5230 #define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */ 5231 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */ 5232 #define CAN_F11R2_FB18_Pos (18U) 5233 #define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */ 5234 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */ 5235 #define CAN_F11R2_FB19_Pos (19U) 5236 #define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */ 5237 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */ 5238 #define CAN_F11R2_FB20_Pos (20U) 5239 #define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */ 5240 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */ 5241 #define CAN_F11R2_FB21_Pos (21U) 5242 #define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */ 5243 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */ 5244 #define CAN_F11R2_FB22_Pos (22U) 5245 #define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */ 5246 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */ 5247 #define CAN_F11R2_FB23_Pos (23U) 5248 #define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */ 5249 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */ 5250 #define CAN_F11R2_FB24_Pos (24U) 5251 #define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */ 5252 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */ 5253 #define CAN_F11R2_FB25_Pos (25U) 5254 #define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */ 5255 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */ 5256 #define CAN_F11R2_FB26_Pos (26U) 5257 #define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */ 5258 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */ 5259 #define CAN_F11R2_FB27_Pos (27U) 5260 #define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */ 5261 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */ 5262 #define CAN_F11R2_FB28_Pos (28U) 5263 #define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */ 5264 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */ 5265 #define CAN_F11R2_FB29_Pos (29U) 5266 #define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */ 5267 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */ 5268 #define CAN_F11R2_FB30_Pos (30U) 5269 #define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */ 5270 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */ 5271 #define CAN_F11R2_FB31_Pos (31U) 5272 #define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */ 5273 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */ 5274 5275 /******************* Bit definition for CAN_F12R2 register ******************/ 5276 #define CAN_F12R2_FB0_Pos (0U) 5277 #define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */ 5278 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */ 5279 #define CAN_F12R2_FB1_Pos (1U) 5280 #define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */ 5281 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */ 5282 #define CAN_F12R2_FB2_Pos (2U) 5283 #define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */ 5284 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */ 5285 #define CAN_F12R2_FB3_Pos (3U) 5286 #define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */ 5287 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */ 5288 #define CAN_F12R2_FB4_Pos (4U) 5289 #define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */ 5290 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */ 5291 #define CAN_F12R2_FB5_Pos (5U) 5292 #define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */ 5293 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */ 5294 #define CAN_F12R2_FB6_Pos (6U) 5295 #define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */ 5296 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */ 5297 #define CAN_F12R2_FB7_Pos (7U) 5298 #define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */ 5299 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */ 5300 #define CAN_F12R2_FB8_Pos (8U) 5301 #define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */ 5302 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */ 5303 #define CAN_F12R2_FB9_Pos (9U) 5304 #define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */ 5305 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */ 5306 #define CAN_F12R2_FB10_Pos (10U) 5307 #define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */ 5308 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */ 5309 #define CAN_F12R2_FB11_Pos (11U) 5310 #define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */ 5311 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */ 5312 #define CAN_F12R2_FB12_Pos (12U) 5313 #define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */ 5314 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */ 5315 #define CAN_F12R2_FB13_Pos (13U) 5316 #define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */ 5317 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */ 5318 #define CAN_F12R2_FB14_Pos (14U) 5319 #define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */ 5320 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */ 5321 #define CAN_F12R2_FB15_Pos (15U) 5322 #define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */ 5323 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */ 5324 #define CAN_F12R2_FB16_Pos (16U) 5325 #define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */ 5326 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */ 5327 #define CAN_F12R2_FB17_Pos (17U) 5328 #define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */ 5329 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */ 5330 #define CAN_F12R2_FB18_Pos (18U) 5331 #define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */ 5332 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */ 5333 #define CAN_F12R2_FB19_Pos (19U) 5334 #define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */ 5335 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */ 5336 #define CAN_F12R2_FB20_Pos (20U) 5337 #define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */ 5338 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */ 5339 #define CAN_F12R2_FB21_Pos (21U) 5340 #define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */ 5341 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */ 5342 #define CAN_F12R2_FB22_Pos (22U) 5343 #define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */ 5344 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */ 5345 #define CAN_F12R2_FB23_Pos (23U) 5346 #define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */ 5347 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */ 5348 #define CAN_F12R2_FB24_Pos (24U) 5349 #define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */ 5350 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */ 5351 #define CAN_F12R2_FB25_Pos (25U) 5352 #define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */ 5353 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */ 5354 #define CAN_F12R2_FB26_Pos (26U) 5355 #define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */ 5356 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */ 5357 #define CAN_F12R2_FB27_Pos (27U) 5358 #define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */ 5359 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */ 5360 #define CAN_F12R2_FB28_Pos (28U) 5361 #define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */ 5362 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */ 5363 #define CAN_F12R2_FB29_Pos (29U) 5364 #define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */ 5365 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */ 5366 #define CAN_F12R2_FB30_Pos (30U) 5367 #define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */ 5368 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */ 5369 #define CAN_F12R2_FB31_Pos (31U) 5370 #define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */ 5371 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */ 5372 5373 /******************* Bit definition for CAN_F13R2 register ******************/ 5374 #define CAN_F13R2_FB0_Pos (0U) 5375 #define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */ 5376 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */ 5377 #define CAN_F13R2_FB1_Pos (1U) 5378 #define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */ 5379 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */ 5380 #define CAN_F13R2_FB2_Pos (2U) 5381 #define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */ 5382 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */ 5383 #define CAN_F13R2_FB3_Pos (3U) 5384 #define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */ 5385 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */ 5386 #define CAN_F13R2_FB4_Pos (4U) 5387 #define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */ 5388 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */ 5389 #define CAN_F13R2_FB5_Pos (5U) 5390 #define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */ 5391 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */ 5392 #define CAN_F13R2_FB6_Pos (6U) 5393 #define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */ 5394 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */ 5395 #define CAN_F13R2_FB7_Pos (7U) 5396 #define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */ 5397 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */ 5398 #define CAN_F13R2_FB8_Pos (8U) 5399 #define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */ 5400 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */ 5401 #define CAN_F13R2_FB9_Pos (9U) 5402 #define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */ 5403 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */ 5404 #define CAN_F13R2_FB10_Pos (10U) 5405 #define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */ 5406 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */ 5407 #define CAN_F13R2_FB11_Pos (11U) 5408 #define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */ 5409 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */ 5410 #define CAN_F13R2_FB12_Pos (12U) 5411 #define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */ 5412 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */ 5413 #define CAN_F13R2_FB13_Pos (13U) 5414 #define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */ 5415 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */ 5416 #define CAN_F13R2_FB14_Pos (14U) 5417 #define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */ 5418 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */ 5419 #define CAN_F13R2_FB15_Pos (15U) 5420 #define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */ 5421 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */ 5422 #define CAN_F13R2_FB16_Pos (16U) 5423 #define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */ 5424 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */ 5425 #define CAN_F13R2_FB17_Pos (17U) 5426 #define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */ 5427 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */ 5428 #define CAN_F13R2_FB18_Pos (18U) 5429 #define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */ 5430 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */ 5431 #define CAN_F13R2_FB19_Pos (19U) 5432 #define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */ 5433 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */ 5434 #define CAN_F13R2_FB20_Pos (20U) 5435 #define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */ 5436 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */ 5437 #define CAN_F13R2_FB21_Pos (21U) 5438 #define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */ 5439 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */ 5440 #define CAN_F13R2_FB22_Pos (22U) 5441 #define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */ 5442 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */ 5443 #define CAN_F13R2_FB23_Pos (23U) 5444 #define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */ 5445 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */ 5446 #define CAN_F13R2_FB24_Pos (24U) 5447 #define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */ 5448 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */ 5449 #define CAN_F13R2_FB25_Pos (25U) 5450 #define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */ 5451 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */ 5452 #define CAN_F13R2_FB26_Pos (26U) 5453 #define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */ 5454 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */ 5455 #define CAN_F13R2_FB27_Pos (27U) 5456 #define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */ 5457 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */ 5458 #define CAN_F13R2_FB28_Pos (28U) 5459 #define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */ 5460 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */ 5461 #define CAN_F13R2_FB29_Pos (29U) 5462 #define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */ 5463 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */ 5464 #define CAN_F13R2_FB30_Pos (30U) 5465 #define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */ 5466 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */ 5467 #define CAN_F13R2_FB31_Pos (31U) 5468 #define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */ 5469 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */ 5470 5471 /******************************************************************************/ 5472 /* */ 5473 /* CRC calculation unit */ 5474 /* */ 5475 /******************************************************************************/ 5476 /******************* Bit definition for CRC_DR register *********************/ 5477 #define CRC_DR_DR_Pos (0U) 5478 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ 5479 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ 5480 5481 5482 /******************* Bit definition for CRC_IDR register ********************/ 5483 #define CRC_IDR_IDR_Pos (0U) 5484 #define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ 5485 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ 5486 5487 5488 /******************** Bit definition for CRC_CR register ********************/ 5489 #define CRC_CR_RESET_Pos (0U) 5490 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ 5491 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ 5492 5493 /******************************************************************************/ 5494 /* */ 5495 /* Crypto Processor */ 5496 /* */ 5497 /******************************************************************************/ 5498 /******************* Bits definition for CRYP_CR register ********************/ 5499 #define CRYP_CR_ALGODIR_Pos (2U) 5500 #define CRYP_CR_ALGODIR_Msk (0x1UL << CRYP_CR_ALGODIR_Pos) /*!< 0x00000004 */ 5501 #define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk 5502 5503 #define CRYP_CR_ALGOMODE_Pos (3U) 5504 #define CRYP_CR_ALGOMODE_Msk (0x7UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000038 */ 5505 #define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk 5506 #define CRYP_CR_ALGOMODE_0 (0x1UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */ 5507 #define CRYP_CR_ALGOMODE_1 (0x2UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */ 5508 #define CRYP_CR_ALGOMODE_2 (0x4UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */ 5509 #define CRYP_CR_ALGOMODE_TDES_ECB 0x00000000U 5510 #define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U) 5511 #define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */ 5512 #define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk 5513 #define CRYP_CR_ALGOMODE_DES_ECB_Pos (4U) 5514 #define CRYP_CR_ALGOMODE_DES_ECB_Msk (0x1UL << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */ 5515 #define CRYP_CR_ALGOMODE_DES_ECB CRYP_CR_ALGOMODE_DES_ECB_Msk 5516 #define CRYP_CR_ALGOMODE_DES_CBC_Pos (3U) 5517 #define CRYP_CR_ALGOMODE_DES_CBC_Msk (0x3UL << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */ 5518 #define CRYP_CR_ALGOMODE_DES_CBC CRYP_CR_ALGOMODE_DES_CBC_Msk 5519 #define CRYP_CR_ALGOMODE_AES_ECB_Pos (5U) 5520 #define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */ 5521 #define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk 5522 #define CRYP_CR_ALGOMODE_AES_CBC_Pos (3U) 5523 #define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */ 5524 #define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk 5525 #define CRYP_CR_ALGOMODE_AES_CTR_Pos (4U) 5526 #define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */ 5527 #define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk 5528 #define CRYP_CR_ALGOMODE_AES_KEY_Pos (3U) 5529 #define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */ 5530 #define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk 5531 5532 #define CRYP_CR_DATATYPE_Pos (6U) 5533 #define CRYP_CR_DATATYPE_Msk (0x3UL << CRYP_CR_DATATYPE_Pos) /*!< 0x000000C0 */ 5534 #define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk 5535 #define CRYP_CR_DATATYPE_0 (0x1UL << CRYP_CR_DATATYPE_Pos) /*!< 0x00000040 */ 5536 #define CRYP_CR_DATATYPE_1 (0x2UL << CRYP_CR_DATATYPE_Pos) /*!< 0x00000080 */ 5537 #define CRYP_CR_KEYSIZE_Pos (8U) 5538 #define CRYP_CR_KEYSIZE_Msk (0x3UL << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000300 */ 5539 #define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk 5540 #define CRYP_CR_KEYSIZE_0 (0x1UL << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000100 */ 5541 #define CRYP_CR_KEYSIZE_1 (0x2UL << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000200 */ 5542 #define CRYP_CR_FFLUSH_Pos (14U) 5543 #define CRYP_CR_FFLUSH_Msk (0x1UL << CRYP_CR_FFLUSH_Pos) /*!< 0x00004000 */ 5544 #define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk 5545 #define CRYP_CR_CRYPEN_Pos (15U) 5546 #define CRYP_CR_CRYPEN_Msk (0x1UL << CRYP_CR_CRYPEN_Pos) /*!< 0x00008000 */ 5547 #define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk 5548 /****************** Bits definition for CRYP_SR register *********************/ 5549 #define CRYP_SR_IFEM_Pos (0U) 5550 #define CRYP_SR_IFEM_Msk (0x1UL << CRYP_SR_IFEM_Pos) /*!< 0x00000001 */ 5551 #define CRYP_SR_IFEM CRYP_SR_IFEM_Msk 5552 #define CRYP_SR_IFNF_Pos (1U) 5553 #define CRYP_SR_IFNF_Msk (0x1UL << CRYP_SR_IFNF_Pos) /*!< 0x00000002 */ 5554 #define CRYP_SR_IFNF CRYP_SR_IFNF_Msk 5555 #define CRYP_SR_OFNE_Pos (2U) 5556 #define CRYP_SR_OFNE_Msk (0x1UL << CRYP_SR_OFNE_Pos) /*!< 0x00000004 */ 5557 #define CRYP_SR_OFNE CRYP_SR_OFNE_Msk 5558 #define CRYP_SR_OFFU_Pos (3U) 5559 #define CRYP_SR_OFFU_Msk (0x1UL << CRYP_SR_OFFU_Pos) /*!< 0x00000008 */ 5560 #define CRYP_SR_OFFU CRYP_SR_OFFU_Msk 5561 #define CRYP_SR_BUSY_Pos (4U) 5562 #define CRYP_SR_BUSY_Msk (0x1UL << CRYP_SR_BUSY_Pos) /*!< 0x00000010 */ 5563 #define CRYP_SR_BUSY CRYP_SR_BUSY_Msk 5564 /****************** Bits definition for CRYP_DMACR register ******************/ 5565 #define CRYP_DMACR_DIEN_Pos (0U) 5566 #define CRYP_DMACR_DIEN_Msk (0x1UL << CRYP_DMACR_DIEN_Pos) /*!< 0x00000001 */ 5567 #define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk 5568 #define CRYP_DMACR_DOEN_Pos (1U) 5569 #define CRYP_DMACR_DOEN_Msk (0x1UL << CRYP_DMACR_DOEN_Pos) /*!< 0x00000002 */ 5570 #define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk 5571 /***************** Bits definition for CRYP_IMSCR register ******************/ 5572 #define CRYP_IMSCR_INIM_Pos (0U) 5573 #define CRYP_IMSCR_INIM_Msk (0x1UL << CRYP_IMSCR_INIM_Pos) /*!< 0x00000001 */ 5574 #define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk 5575 #define CRYP_IMSCR_OUTIM_Pos (1U) 5576 #define CRYP_IMSCR_OUTIM_Msk (0x1UL << CRYP_IMSCR_OUTIM_Pos) /*!< 0x00000002 */ 5577 #define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk 5578 /****************** Bits definition for CRYP_RISR register *******************/ 5579 #define CRYP_RISR_OUTRIS_Pos (0U) 5580 #define CRYP_RISR_OUTRIS_Msk (0x1UL << CRYP_RISR_OUTRIS_Pos) /*!< 0x00000001 */ 5581 #define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk 5582 #define CRYP_RISR_INRIS_Pos (1U) 5583 #define CRYP_RISR_INRIS_Msk (0x1UL << CRYP_RISR_INRIS_Pos) /*!< 0x00000002 */ 5584 #define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk 5585 /****************** Bits definition for CRYP_MISR register *******************/ 5586 #define CRYP_MISR_INMIS_Pos (0U) 5587 #define CRYP_MISR_INMIS_Msk (0x1UL << CRYP_MISR_INMIS_Pos) /*!< 0x00000001 */ 5588 #define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk 5589 #define CRYP_MISR_OUTMIS_Pos (1U) 5590 #define CRYP_MISR_OUTMIS_Msk (0x1UL << CRYP_MISR_OUTMIS_Pos) /*!< 0x00000002 */ 5591 #define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk 5592 5593 /******************************************************************************/ 5594 /* */ 5595 /* Digital to Analog Converter */ 5596 /* */ 5597 /******************************************************************************/ 5598 /******************** Bit definition for DAC_CR register ********************/ 5599 #define DAC_CR_EN1_Pos (0U) 5600 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ 5601 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */ 5602 #define DAC_CR_BOFF1_Pos (1U) 5603 #define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ 5604 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */ 5605 #define DAC_CR_TEN1_Pos (2U) 5606 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ 5607 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */ 5608 5609 #define DAC_CR_TSEL1_Pos (3U) 5610 #define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ 5611 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */ 5612 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ 5613 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ 5614 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ 5615 5616 #define DAC_CR_WAVE1_Pos (6U) 5617 #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ 5618 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ 5619 #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ 5620 #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ 5621 5622 #define DAC_CR_MAMP1_Pos (8U) 5623 #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ 5624 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ 5625 #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ 5626 #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ 5627 #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ 5628 #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ 5629 5630 #define DAC_CR_DMAEN1_Pos (12U) 5631 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ 5632 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */ 5633 #define DAC_CR_DMAUDRIE1_Pos (13U) 5634 #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ 5635 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/ 5636 #define DAC_CR_EN2_Pos (16U) 5637 #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ 5638 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */ 5639 #define DAC_CR_BOFF2_Pos (17U) 5640 #define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */ 5641 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */ 5642 #define DAC_CR_TEN2_Pos (18U) 5643 #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00040000 */ 5644 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */ 5645 5646 #define DAC_CR_TSEL2_Pos (19U) 5647 #define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */ 5648 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */ 5649 #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ 5650 #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ 5651 #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ 5652 5653 #define DAC_CR_WAVE2_Pos (22U) 5654 #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ 5655 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ 5656 #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */ 5657 #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */ 5658 5659 #define DAC_CR_MAMP2_Pos (24U) 5660 #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ 5661 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ 5662 #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ 5663 #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ 5664 #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ 5665 #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ 5666 5667 #define DAC_CR_DMAEN2_Pos (28U) 5668 #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ 5669 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */ 5670 #define DAC_CR_DMAUDRIE2_Pos (29U) 5671 #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */ 5672 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/ 5673 5674 /***************** Bit definition for DAC_SWTRIGR register ******************/ 5675 #define DAC_SWTRIGR_SWTRIG1_Pos (0U) 5676 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ 5677 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */ 5678 #define DAC_SWTRIGR_SWTRIG2_Pos (1U) 5679 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */ 5680 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */ 5681 5682 /***************** Bit definition for DAC_DHR12R1 register ******************/ 5683 #define DAC_DHR12R1_DACC1DHR_Pos (0U) 5684 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ 5685 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */ 5686 5687 /***************** Bit definition for DAC_DHR12L1 register ******************/ 5688 #define DAC_DHR12L1_DACC1DHR_Pos (4U) 5689 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ 5690 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */ 5691 5692 /****************** Bit definition for DAC_DHR8R1 register ******************/ 5693 #define DAC_DHR8R1_DACC1DHR_Pos (0U) 5694 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ 5695 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */ 5696 5697 /***************** Bit definition for DAC_DHR12R2 register ******************/ 5698 #define DAC_DHR12R2_DACC2DHR_Pos (0U) 5699 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ 5700 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */ 5701 5702 /***************** Bit definition for DAC_DHR12L2 register ******************/ 5703 #define DAC_DHR12L2_DACC2DHR_Pos (4U) 5704 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ 5705 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */ 5706 5707 /****************** Bit definition for DAC_DHR8R2 register ******************/ 5708 #define DAC_DHR8R2_DACC2DHR_Pos (0U) 5709 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ 5710 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */ 5711 5712 /***************** Bit definition for DAC_DHR12RD register ******************/ 5713 #define DAC_DHR12RD_DACC1DHR_Pos (0U) 5714 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ 5715 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */ 5716 #define DAC_DHR12RD_DACC2DHR_Pos (16U) 5717 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ 5718 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */ 5719 5720 /***************** Bit definition for DAC_DHR12LD register ******************/ 5721 #define DAC_DHR12LD_DACC1DHR_Pos (4U) 5722 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ 5723 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */ 5724 #define DAC_DHR12LD_DACC2DHR_Pos (20U) 5725 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ 5726 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */ 5727 5728 /****************** Bit definition for DAC_DHR8RD register ******************/ 5729 #define DAC_DHR8RD_DACC1DHR_Pos (0U) 5730 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ 5731 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */ 5732 #define DAC_DHR8RD_DACC2DHR_Pos (8U) 5733 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ 5734 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */ 5735 5736 /******************* Bit definition for DAC_DOR1 register *******************/ 5737 #define DAC_DOR1_DACC1DOR_Pos (0U) 5738 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ 5739 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */ 5740 5741 /******************* Bit definition for DAC_DOR2 register *******************/ 5742 #define DAC_DOR2_DACC2DOR_Pos (0U) 5743 #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ 5744 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */ 5745 5746 /******************** Bit definition for DAC_SR register ********************/ 5747 #define DAC_SR_DMAUDR1_Pos (13U) 5748 #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ 5749 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */ 5750 #define DAC_SR_DMAUDR2_Pos (29U) 5751 #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */ 5752 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */ 5753 5754 /******************************************************************************/ 5755 /* */ 5756 /* Debug MCU */ 5757 /* */ 5758 /******************************************************************************/ 5759 5760 /******************************************************************************/ 5761 /* */ 5762 /* DCMI */ 5763 /* */ 5764 /******************************************************************************/ 5765 /******************** Bits definition for DCMI_CR register ******************/ 5766 #define DCMI_CR_CAPTURE_Pos (0U) 5767 #define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */ 5768 #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk 5769 #define DCMI_CR_CM_Pos (1U) 5770 #define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) /*!< 0x00000002 */ 5771 #define DCMI_CR_CM DCMI_CR_CM_Msk 5772 #define DCMI_CR_CROP_Pos (2U) 5773 #define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) /*!< 0x00000004 */ 5774 #define DCMI_CR_CROP DCMI_CR_CROP_Msk 5775 #define DCMI_CR_JPEG_Pos (3U) 5776 #define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */ 5777 #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk 5778 #define DCMI_CR_ESS_Pos (4U) 5779 #define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) /*!< 0x00000010 */ 5780 #define DCMI_CR_ESS DCMI_CR_ESS_Msk 5781 #define DCMI_CR_PCKPOL_Pos (5U) 5782 #define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */ 5783 #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk 5784 #define DCMI_CR_HSPOL_Pos (6U) 5785 #define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */ 5786 #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk 5787 #define DCMI_CR_VSPOL_Pos (7U) 5788 #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ 5789 #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk 5790 #define DCMI_CR_FCRC_0 0x00000100U 5791 #define DCMI_CR_FCRC_1 0x00000200U 5792 #define DCMI_CR_EDM_0 0x00000400U 5793 #define DCMI_CR_EDM_1 0x00000800U 5794 #define DCMI_CR_CRE_Pos (12U) 5795 #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */ 5796 #define DCMI_CR_CRE DCMI_CR_CRE_Msk 5797 #define DCMI_CR_ENABLE_Pos (14U) 5798 #define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */ 5799 #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk 5800 5801 /******************** Bits definition for DCMI_SR register ******************/ 5802 #define DCMI_SR_HSYNC_Pos (0U) 5803 #define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */ 5804 #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk 5805 #define DCMI_SR_VSYNC_Pos (1U) 5806 #define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */ 5807 #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk 5808 #define DCMI_SR_FNE_Pos (2U) 5809 #define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) /*!< 0x00000004 */ 5810 #define DCMI_SR_FNE DCMI_SR_FNE_Msk 5811 5812 /******************** Bits definition for DCMI_RIS register *****************/ 5813 #define DCMI_RIS_FRAME_RIS_Pos (0U) 5814 #define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */ 5815 #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk 5816 #define DCMI_RIS_OVR_RIS_Pos (1U) 5817 #define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */ 5818 #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk 5819 #define DCMI_RIS_ERR_RIS_Pos (2U) 5820 #define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */ 5821 #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk 5822 #define DCMI_RIS_VSYNC_RIS_Pos (3U) 5823 #define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */ 5824 #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk 5825 #define DCMI_RIS_LINE_RIS_Pos (4U) 5826 #define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */ 5827 #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk 5828 /* Legacy defines */ 5829 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS 5830 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS 5831 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS 5832 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS 5833 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS 5834 5835 /******************** Bits definition for DCMI_IER register *****************/ 5836 #define DCMI_IER_FRAME_IE_Pos (0U) 5837 #define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */ 5838 #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk 5839 #define DCMI_IER_OVR_IE_Pos (1U) 5840 #define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */ 5841 #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk 5842 #define DCMI_IER_ERR_IE_Pos (2U) 5843 #define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */ 5844 #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk 5845 #define DCMI_IER_VSYNC_IE_Pos (3U) 5846 #define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */ 5847 #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk 5848 #define DCMI_IER_LINE_IE_Pos (4U) 5849 #define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */ 5850 #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk 5851 /* Legacy defines */ 5852 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE 5853 5854 /******************** Bits definition for DCMI_MIS register *****************/ 5855 #define DCMI_MIS_FRAME_MIS_Pos (0U) 5856 #define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */ 5857 #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk 5858 #define DCMI_MIS_OVR_MIS_Pos (1U) 5859 #define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */ 5860 #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk 5861 #define DCMI_MIS_ERR_MIS_Pos (2U) 5862 #define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */ 5863 #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk 5864 #define DCMI_MIS_VSYNC_MIS_Pos (3U) 5865 #define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */ 5866 #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk 5867 #define DCMI_MIS_LINE_MIS_Pos (4U) 5868 #define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */ 5869 #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk 5870 5871 /* Legacy defines */ 5872 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS 5873 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS 5874 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS 5875 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS 5876 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS 5877 5878 /******************** Bits definition for DCMI_ICR register *****************/ 5879 #define DCMI_ICR_FRAME_ISC_Pos (0U) 5880 #define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */ 5881 #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk 5882 #define DCMI_ICR_OVR_ISC_Pos (1U) 5883 #define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */ 5884 #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk 5885 #define DCMI_ICR_ERR_ISC_Pos (2U) 5886 #define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */ 5887 #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk 5888 #define DCMI_ICR_VSYNC_ISC_Pos (3U) 5889 #define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */ 5890 #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk 5891 #define DCMI_ICR_LINE_ISC_Pos (4U) 5892 #define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */ 5893 #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk 5894 5895 /* Legacy defines */ 5896 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC 5897 5898 /******************** Bits definition for DCMI_ESCR register ******************/ 5899 #define DCMI_ESCR_FSC_Pos (0U) 5900 #define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */ 5901 #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk 5902 #define DCMI_ESCR_LSC_Pos (8U) 5903 #define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */ 5904 #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk 5905 #define DCMI_ESCR_LEC_Pos (16U) 5906 #define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */ 5907 #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk 5908 #define DCMI_ESCR_FEC_Pos (24U) 5909 #define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */ 5910 #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk 5911 5912 /******************** Bits definition for DCMI_ESUR register ******************/ 5913 #define DCMI_ESUR_FSU_Pos (0U) 5914 #define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */ 5915 #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk 5916 #define DCMI_ESUR_LSU_Pos (8U) 5917 #define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */ 5918 #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk 5919 #define DCMI_ESUR_LEU_Pos (16U) 5920 #define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */ 5921 #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk 5922 #define DCMI_ESUR_FEU_Pos (24U) 5923 #define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */ 5924 #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk 5925 5926 /******************** Bits definition for DCMI_CWSTRT register ******************/ 5927 #define DCMI_CWSTRT_HOFFCNT_Pos (0U) 5928 #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */ 5929 #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk 5930 #define DCMI_CWSTRT_VST_Pos (16U) 5931 #define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */ 5932 #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk 5933 5934 /******************** Bits definition for DCMI_CWSIZE register ******************/ 5935 #define DCMI_CWSIZE_CAPCNT_Pos (0U) 5936 #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */ 5937 #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk 5938 #define DCMI_CWSIZE_VLINE_Pos (16U) 5939 #define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */ 5940 #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk 5941 5942 /******************** Bits definition for DCMI_DR register ******************/ 5943 #define DCMI_DR_BYTE0_Pos (0U) 5944 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */ 5945 #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk 5946 #define DCMI_DR_BYTE1_Pos (8U) 5947 #define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */ 5948 #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk 5949 #define DCMI_DR_BYTE2_Pos (16U) 5950 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */ 5951 #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk 5952 #define DCMI_DR_BYTE3_Pos (24U) 5953 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ 5954 #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk 5955 5956 /******************************************************************************/ 5957 /* */ 5958 /* DMA Controller */ 5959 /* */ 5960 /******************************************************************************/ 5961 /******************** Bits definition for DMA_SxCR register *****************/ 5962 #define DMA_SxCR_CHSEL_Pos (25U) 5963 #define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */ 5964 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk 5965 #define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */ 5966 #define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */ 5967 #define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */ 5968 #define DMA_SxCR_MBURST_Pos (23U) 5969 #define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */ 5970 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk 5971 #define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */ 5972 #define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */ 5973 #define DMA_SxCR_PBURST_Pos (21U) 5974 #define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */ 5975 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk 5976 #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ 5977 #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ 5978 #define DMA_SxCR_CT_Pos (19U) 5979 #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ 5980 #define DMA_SxCR_CT DMA_SxCR_CT_Msk 5981 #define DMA_SxCR_DBM_Pos (18U) 5982 #define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */ 5983 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk 5984 #define DMA_SxCR_PL_Pos (16U) 5985 #define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos) /*!< 0x00030000 */ 5986 #define DMA_SxCR_PL DMA_SxCR_PL_Msk 5987 #define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos) /*!< 0x00010000 */ 5988 #define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos) /*!< 0x00020000 */ 5989 #define DMA_SxCR_PINCOS_Pos (15U) 5990 #define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */ 5991 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk 5992 #define DMA_SxCR_MSIZE_Pos (13U) 5993 #define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */ 5994 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk 5995 #define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */ 5996 #define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */ 5997 #define DMA_SxCR_PSIZE_Pos (11U) 5998 #define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */ 5999 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk 6000 #define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */ 6001 #define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */ 6002 #define DMA_SxCR_MINC_Pos (10U) 6003 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */ 6004 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk 6005 #define DMA_SxCR_PINC_Pos (9U) 6006 #define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */ 6007 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk 6008 #define DMA_SxCR_CIRC_Pos (8U) 6009 #define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */ 6010 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk 6011 #define DMA_SxCR_DIR_Pos (6U) 6012 #define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */ 6013 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk 6014 #define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */ 6015 #define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */ 6016 #define DMA_SxCR_PFCTRL_Pos (5U) 6017 #define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */ 6018 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk 6019 #define DMA_SxCR_TCIE_Pos (4U) 6020 #define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */ 6021 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk 6022 #define DMA_SxCR_HTIE_Pos (3U) 6023 #define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */ 6024 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk 6025 #define DMA_SxCR_TEIE_Pos (2U) 6026 #define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */ 6027 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk 6028 #define DMA_SxCR_DMEIE_Pos (1U) 6029 #define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */ 6030 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk 6031 #define DMA_SxCR_EN_Pos (0U) 6032 #define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos) /*!< 0x00000001 */ 6033 #define DMA_SxCR_EN DMA_SxCR_EN_Msk 6034 6035 /* Legacy defines */ 6036 #define DMA_SxCR_ACK_Pos (20U) 6037 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ 6038 #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk 6039 6040 /******************** Bits definition for DMA_SxCNDTR register **************/ 6041 #define DMA_SxNDT_Pos (0U) 6042 #define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos) /*!< 0x0000FFFF */ 6043 #define DMA_SxNDT DMA_SxNDT_Msk 6044 #define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos) /*!< 0x00000001 */ 6045 #define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos) /*!< 0x00000002 */ 6046 #define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos) /*!< 0x00000004 */ 6047 #define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos) /*!< 0x00000008 */ 6048 #define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos) /*!< 0x00000010 */ 6049 #define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos) /*!< 0x00000020 */ 6050 #define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos) /*!< 0x00000040 */ 6051 #define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos) /*!< 0x00000080 */ 6052 #define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos) /*!< 0x00000100 */ 6053 #define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos) /*!< 0x00000200 */ 6054 #define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos) /*!< 0x00000400 */ 6055 #define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos) /*!< 0x00000800 */ 6056 #define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos) /*!< 0x00001000 */ 6057 #define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos) /*!< 0x00002000 */ 6058 #define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos) /*!< 0x00004000 */ 6059 #define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos) /*!< 0x00008000 */ 6060 6061 /******************** Bits definition for DMA_SxFCR register ****************/ 6062 #define DMA_SxFCR_FEIE_Pos (7U) 6063 #define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */ 6064 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk 6065 #define DMA_SxFCR_FS_Pos (3U) 6066 #define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */ 6067 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk 6068 #define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */ 6069 #define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */ 6070 #define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */ 6071 #define DMA_SxFCR_DMDIS_Pos (2U) 6072 #define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */ 6073 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk 6074 #define DMA_SxFCR_FTH_Pos (0U) 6075 #define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */ 6076 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk 6077 #define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */ 6078 #define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */ 6079 6080 /******************** Bits definition for DMA_LISR register *****************/ 6081 #define DMA_LISR_TCIF3_Pos (27U) 6082 #define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */ 6083 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk 6084 #define DMA_LISR_HTIF3_Pos (26U) 6085 #define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */ 6086 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk 6087 #define DMA_LISR_TEIF3_Pos (25U) 6088 #define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */ 6089 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk 6090 #define DMA_LISR_DMEIF3_Pos (24U) 6091 #define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */ 6092 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk 6093 #define DMA_LISR_FEIF3_Pos (22U) 6094 #define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */ 6095 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk 6096 #define DMA_LISR_TCIF2_Pos (21U) 6097 #define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */ 6098 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk 6099 #define DMA_LISR_HTIF2_Pos (20U) 6100 #define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */ 6101 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk 6102 #define DMA_LISR_TEIF2_Pos (19U) 6103 #define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */ 6104 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk 6105 #define DMA_LISR_DMEIF2_Pos (18U) 6106 #define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */ 6107 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk 6108 #define DMA_LISR_FEIF2_Pos (16U) 6109 #define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */ 6110 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk 6111 #define DMA_LISR_TCIF1_Pos (11U) 6112 #define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */ 6113 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk 6114 #define DMA_LISR_HTIF1_Pos (10U) 6115 #define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */ 6116 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk 6117 #define DMA_LISR_TEIF1_Pos (9U) 6118 #define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */ 6119 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk 6120 #define DMA_LISR_DMEIF1_Pos (8U) 6121 #define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */ 6122 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk 6123 #define DMA_LISR_FEIF1_Pos (6U) 6124 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */ 6125 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk 6126 #define DMA_LISR_TCIF0_Pos (5U) 6127 #define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */ 6128 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk 6129 #define DMA_LISR_HTIF0_Pos (4U) 6130 #define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */ 6131 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk 6132 #define DMA_LISR_TEIF0_Pos (3U) 6133 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */ 6134 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk 6135 #define DMA_LISR_DMEIF0_Pos (2U) 6136 #define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */ 6137 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk 6138 #define DMA_LISR_FEIF0_Pos (0U) 6139 #define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */ 6140 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk 6141 6142 /******************** Bits definition for DMA_HISR register *****************/ 6143 #define DMA_HISR_TCIF7_Pos (27U) 6144 #define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */ 6145 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk 6146 #define DMA_HISR_HTIF7_Pos (26U) 6147 #define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */ 6148 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk 6149 #define DMA_HISR_TEIF7_Pos (25U) 6150 #define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */ 6151 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk 6152 #define DMA_HISR_DMEIF7_Pos (24U) 6153 #define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */ 6154 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk 6155 #define DMA_HISR_FEIF7_Pos (22U) 6156 #define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */ 6157 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk 6158 #define DMA_HISR_TCIF6_Pos (21U) 6159 #define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */ 6160 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk 6161 #define DMA_HISR_HTIF6_Pos (20U) 6162 #define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */ 6163 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk 6164 #define DMA_HISR_TEIF6_Pos (19U) 6165 #define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */ 6166 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk 6167 #define DMA_HISR_DMEIF6_Pos (18U) 6168 #define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */ 6169 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk 6170 #define DMA_HISR_FEIF6_Pos (16U) 6171 #define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */ 6172 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk 6173 #define DMA_HISR_TCIF5_Pos (11U) 6174 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ 6175 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk 6176 #define DMA_HISR_HTIF5_Pos (10U) 6177 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */ 6178 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk 6179 #define DMA_HISR_TEIF5_Pos (9U) 6180 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */ 6181 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk 6182 #define DMA_HISR_DMEIF5_Pos (8U) 6183 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */ 6184 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk 6185 #define DMA_HISR_FEIF5_Pos (6U) 6186 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */ 6187 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk 6188 #define DMA_HISR_TCIF4_Pos (5U) 6189 #define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */ 6190 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk 6191 #define DMA_HISR_HTIF4_Pos (4U) 6192 #define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */ 6193 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk 6194 #define DMA_HISR_TEIF4_Pos (3U) 6195 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */ 6196 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk 6197 #define DMA_HISR_DMEIF4_Pos (2U) 6198 #define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */ 6199 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk 6200 #define DMA_HISR_FEIF4_Pos (0U) 6201 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */ 6202 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk 6203 6204 /******************** Bits definition for DMA_LIFCR register ****************/ 6205 #define DMA_LIFCR_CTCIF3_Pos (27U) 6206 #define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */ 6207 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk 6208 #define DMA_LIFCR_CHTIF3_Pos (26U) 6209 #define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */ 6210 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk 6211 #define DMA_LIFCR_CTEIF3_Pos (25U) 6212 #define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */ 6213 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk 6214 #define DMA_LIFCR_CDMEIF3_Pos (24U) 6215 #define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */ 6216 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk 6217 #define DMA_LIFCR_CFEIF3_Pos (22U) 6218 #define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */ 6219 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk 6220 #define DMA_LIFCR_CTCIF2_Pos (21U) 6221 #define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */ 6222 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk 6223 #define DMA_LIFCR_CHTIF2_Pos (20U) 6224 #define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */ 6225 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk 6226 #define DMA_LIFCR_CTEIF2_Pos (19U) 6227 #define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */ 6228 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk 6229 #define DMA_LIFCR_CDMEIF2_Pos (18U) 6230 #define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */ 6231 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk 6232 #define DMA_LIFCR_CFEIF2_Pos (16U) 6233 #define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */ 6234 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk 6235 #define DMA_LIFCR_CTCIF1_Pos (11U) 6236 #define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */ 6237 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk 6238 #define DMA_LIFCR_CHTIF1_Pos (10U) 6239 #define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */ 6240 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk 6241 #define DMA_LIFCR_CTEIF1_Pos (9U) 6242 #define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */ 6243 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk 6244 #define DMA_LIFCR_CDMEIF1_Pos (8U) 6245 #define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */ 6246 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk 6247 #define DMA_LIFCR_CFEIF1_Pos (6U) 6248 #define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */ 6249 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk 6250 #define DMA_LIFCR_CTCIF0_Pos (5U) 6251 #define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */ 6252 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk 6253 #define DMA_LIFCR_CHTIF0_Pos (4U) 6254 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */ 6255 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk 6256 #define DMA_LIFCR_CTEIF0_Pos (3U) 6257 #define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */ 6258 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk 6259 #define DMA_LIFCR_CDMEIF0_Pos (2U) 6260 #define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */ 6261 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk 6262 #define DMA_LIFCR_CFEIF0_Pos (0U) 6263 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */ 6264 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk 6265 6266 /******************** Bits definition for DMA_HIFCR register ****************/ 6267 #define DMA_HIFCR_CTCIF7_Pos (27U) 6268 #define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */ 6269 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk 6270 #define DMA_HIFCR_CHTIF7_Pos (26U) 6271 #define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */ 6272 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk 6273 #define DMA_HIFCR_CTEIF7_Pos (25U) 6274 #define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */ 6275 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk 6276 #define DMA_HIFCR_CDMEIF7_Pos (24U) 6277 #define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */ 6278 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk 6279 #define DMA_HIFCR_CFEIF7_Pos (22U) 6280 #define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */ 6281 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk 6282 #define DMA_HIFCR_CTCIF6_Pos (21U) 6283 #define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */ 6284 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk 6285 #define DMA_HIFCR_CHTIF6_Pos (20U) 6286 #define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */ 6287 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk 6288 #define DMA_HIFCR_CTEIF6_Pos (19U) 6289 #define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */ 6290 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk 6291 #define DMA_HIFCR_CDMEIF6_Pos (18U) 6292 #define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */ 6293 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk 6294 #define DMA_HIFCR_CFEIF6_Pos (16U) 6295 #define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */ 6296 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk 6297 #define DMA_HIFCR_CTCIF5_Pos (11U) 6298 #define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */ 6299 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk 6300 #define DMA_HIFCR_CHTIF5_Pos (10U) 6301 #define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */ 6302 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk 6303 #define DMA_HIFCR_CTEIF5_Pos (9U) 6304 #define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */ 6305 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk 6306 #define DMA_HIFCR_CDMEIF5_Pos (8U) 6307 #define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */ 6308 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk 6309 #define DMA_HIFCR_CFEIF5_Pos (6U) 6310 #define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */ 6311 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk 6312 #define DMA_HIFCR_CTCIF4_Pos (5U) 6313 #define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */ 6314 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk 6315 #define DMA_HIFCR_CHTIF4_Pos (4U) 6316 #define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */ 6317 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk 6318 #define DMA_HIFCR_CTEIF4_Pos (3U) 6319 #define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */ 6320 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk 6321 #define DMA_HIFCR_CDMEIF4_Pos (2U) 6322 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */ 6323 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk 6324 #define DMA_HIFCR_CFEIF4_Pos (0U) 6325 #define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */ 6326 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk 6327 6328 /****************** Bit definition for DMA_SxPAR register ********************/ 6329 #define DMA_SxPAR_PA_Pos (0U) 6330 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */ 6331 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */ 6332 6333 /****************** Bit definition for DMA_SxM0AR register ********************/ 6334 #define DMA_SxM0AR_M0A_Pos (0U) 6335 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */ 6336 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */ 6337 6338 /****************** Bit definition for DMA_SxM1AR register ********************/ 6339 #define DMA_SxM1AR_M1A_Pos (0U) 6340 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */ 6341 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */ 6342 6343 /******************************************************************************/ 6344 /* */ 6345 /* External Interrupt/Event Controller */ 6346 /* */ 6347 /******************************************************************************/ 6348 /******************* Bit definition for EXTI_IMR register *******************/ 6349 #define EXTI_IMR_MR0_Pos (0U) 6350 #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ 6351 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ 6352 #define EXTI_IMR_MR1_Pos (1U) 6353 #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ 6354 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ 6355 #define EXTI_IMR_MR2_Pos (2U) 6356 #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ 6357 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ 6358 #define EXTI_IMR_MR3_Pos (3U) 6359 #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ 6360 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ 6361 #define EXTI_IMR_MR4_Pos (4U) 6362 #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ 6363 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ 6364 #define EXTI_IMR_MR5_Pos (5U) 6365 #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ 6366 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ 6367 #define EXTI_IMR_MR6_Pos (6U) 6368 #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ 6369 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ 6370 #define EXTI_IMR_MR7_Pos (7U) 6371 #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ 6372 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ 6373 #define EXTI_IMR_MR8_Pos (8U) 6374 #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ 6375 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ 6376 #define EXTI_IMR_MR9_Pos (9U) 6377 #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ 6378 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ 6379 #define EXTI_IMR_MR10_Pos (10U) 6380 #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ 6381 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ 6382 #define EXTI_IMR_MR11_Pos (11U) 6383 #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ 6384 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ 6385 #define EXTI_IMR_MR12_Pos (12U) 6386 #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ 6387 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ 6388 #define EXTI_IMR_MR13_Pos (13U) 6389 #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ 6390 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ 6391 #define EXTI_IMR_MR14_Pos (14U) 6392 #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ 6393 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ 6394 #define EXTI_IMR_MR15_Pos (15U) 6395 #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ 6396 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ 6397 #define EXTI_IMR_MR16_Pos (16U) 6398 #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ 6399 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ 6400 #define EXTI_IMR_MR17_Pos (17U) 6401 #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ 6402 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ 6403 #define EXTI_IMR_MR18_Pos (18U) 6404 #define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ 6405 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ 6406 #define EXTI_IMR_MR19_Pos (19U) 6407 #define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ 6408 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ 6409 #define EXTI_IMR_MR20_Pos (20U) 6410 #define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */ 6411 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */ 6412 #define EXTI_IMR_MR21_Pos (21U) 6413 #define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */ 6414 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */ 6415 #define EXTI_IMR_MR22_Pos (22U) 6416 #define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */ 6417 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */ 6418 6419 /* Reference Defines */ 6420 #define EXTI_IMR_IM0 EXTI_IMR_MR0 6421 #define EXTI_IMR_IM1 EXTI_IMR_MR1 6422 #define EXTI_IMR_IM2 EXTI_IMR_MR2 6423 #define EXTI_IMR_IM3 EXTI_IMR_MR3 6424 #define EXTI_IMR_IM4 EXTI_IMR_MR4 6425 #define EXTI_IMR_IM5 EXTI_IMR_MR5 6426 #define EXTI_IMR_IM6 EXTI_IMR_MR6 6427 #define EXTI_IMR_IM7 EXTI_IMR_MR7 6428 #define EXTI_IMR_IM8 EXTI_IMR_MR8 6429 #define EXTI_IMR_IM9 EXTI_IMR_MR9 6430 #define EXTI_IMR_IM10 EXTI_IMR_MR10 6431 #define EXTI_IMR_IM11 EXTI_IMR_MR11 6432 #define EXTI_IMR_IM12 EXTI_IMR_MR12 6433 #define EXTI_IMR_IM13 EXTI_IMR_MR13 6434 #define EXTI_IMR_IM14 EXTI_IMR_MR14 6435 #define EXTI_IMR_IM15 EXTI_IMR_MR15 6436 #define EXTI_IMR_IM16 EXTI_IMR_MR16 6437 #define EXTI_IMR_IM17 EXTI_IMR_MR17 6438 #define EXTI_IMR_IM18 EXTI_IMR_MR18 6439 #define EXTI_IMR_IM19 EXTI_IMR_MR19 6440 #define EXTI_IMR_IM20 EXTI_IMR_MR20 6441 #define EXTI_IMR_IM21 EXTI_IMR_MR21 6442 #define EXTI_IMR_IM22 EXTI_IMR_MR22 6443 #define EXTI_IMR_IM_Pos (0U) 6444 #define EXTI_IMR_IM_Msk (0x7FFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */ 6445 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ 6446 6447 /******************* Bit definition for EXTI_EMR register *******************/ 6448 #define EXTI_EMR_MR0_Pos (0U) 6449 #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ 6450 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ 6451 #define EXTI_EMR_MR1_Pos (1U) 6452 #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ 6453 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ 6454 #define EXTI_EMR_MR2_Pos (2U) 6455 #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ 6456 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ 6457 #define EXTI_EMR_MR3_Pos (3U) 6458 #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ 6459 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ 6460 #define EXTI_EMR_MR4_Pos (4U) 6461 #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ 6462 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ 6463 #define EXTI_EMR_MR5_Pos (5U) 6464 #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ 6465 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ 6466 #define EXTI_EMR_MR6_Pos (6U) 6467 #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ 6468 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ 6469 #define EXTI_EMR_MR7_Pos (7U) 6470 #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ 6471 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ 6472 #define EXTI_EMR_MR8_Pos (8U) 6473 #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ 6474 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ 6475 #define EXTI_EMR_MR9_Pos (9U) 6476 #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ 6477 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ 6478 #define EXTI_EMR_MR10_Pos (10U) 6479 #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ 6480 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ 6481 #define EXTI_EMR_MR11_Pos (11U) 6482 #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ 6483 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ 6484 #define EXTI_EMR_MR12_Pos (12U) 6485 #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ 6486 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ 6487 #define EXTI_EMR_MR13_Pos (13U) 6488 #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ 6489 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ 6490 #define EXTI_EMR_MR14_Pos (14U) 6491 #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ 6492 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ 6493 #define EXTI_EMR_MR15_Pos (15U) 6494 #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ 6495 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ 6496 #define EXTI_EMR_MR16_Pos (16U) 6497 #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ 6498 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ 6499 #define EXTI_EMR_MR17_Pos (17U) 6500 #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ 6501 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ 6502 #define EXTI_EMR_MR18_Pos (18U) 6503 #define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ 6504 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ 6505 #define EXTI_EMR_MR19_Pos (19U) 6506 #define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ 6507 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ 6508 #define EXTI_EMR_MR20_Pos (20U) 6509 #define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */ 6510 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */ 6511 #define EXTI_EMR_MR21_Pos (21U) 6512 #define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */ 6513 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */ 6514 #define EXTI_EMR_MR22_Pos (22U) 6515 #define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */ 6516 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */ 6517 6518 /* Reference Defines */ 6519 #define EXTI_EMR_EM0 EXTI_EMR_MR0 6520 #define EXTI_EMR_EM1 EXTI_EMR_MR1 6521 #define EXTI_EMR_EM2 EXTI_EMR_MR2 6522 #define EXTI_EMR_EM3 EXTI_EMR_MR3 6523 #define EXTI_EMR_EM4 EXTI_EMR_MR4 6524 #define EXTI_EMR_EM5 EXTI_EMR_MR5 6525 #define EXTI_EMR_EM6 EXTI_EMR_MR6 6526 #define EXTI_EMR_EM7 EXTI_EMR_MR7 6527 #define EXTI_EMR_EM8 EXTI_EMR_MR8 6528 #define EXTI_EMR_EM9 EXTI_EMR_MR9 6529 #define EXTI_EMR_EM10 EXTI_EMR_MR10 6530 #define EXTI_EMR_EM11 EXTI_EMR_MR11 6531 #define EXTI_EMR_EM12 EXTI_EMR_MR12 6532 #define EXTI_EMR_EM13 EXTI_EMR_MR13 6533 #define EXTI_EMR_EM14 EXTI_EMR_MR14 6534 #define EXTI_EMR_EM15 EXTI_EMR_MR15 6535 #define EXTI_EMR_EM16 EXTI_EMR_MR16 6536 #define EXTI_EMR_EM17 EXTI_EMR_MR17 6537 #define EXTI_EMR_EM18 EXTI_EMR_MR18 6538 #define EXTI_EMR_EM19 EXTI_EMR_MR19 6539 #define EXTI_EMR_EM20 EXTI_EMR_MR20 6540 #define EXTI_EMR_EM21 EXTI_EMR_MR21 6541 #define EXTI_EMR_EM22 EXTI_EMR_MR22 6542 6543 /****************** Bit definition for EXTI_RTSR register *******************/ 6544 #define EXTI_RTSR_TR0_Pos (0U) 6545 #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ 6546 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ 6547 #define EXTI_RTSR_TR1_Pos (1U) 6548 #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ 6549 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ 6550 #define EXTI_RTSR_TR2_Pos (2U) 6551 #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ 6552 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ 6553 #define EXTI_RTSR_TR3_Pos (3U) 6554 #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ 6555 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ 6556 #define EXTI_RTSR_TR4_Pos (4U) 6557 #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ 6558 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ 6559 #define EXTI_RTSR_TR5_Pos (5U) 6560 #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ 6561 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ 6562 #define EXTI_RTSR_TR6_Pos (6U) 6563 #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ 6564 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ 6565 #define EXTI_RTSR_TR7_Pos (7U) 6566 #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ 6567 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ 6568 #define EXTI_RTSR_TR8_Pos (8U) 6569 #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ 6570 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ 6571 #define EXTI_RTSR_TR9_Pos (9U) 6572 #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ 6573 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ 6574 #define EXTI_RTSR_TR10_Pos (10U) 6575 #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ 6576 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ 6577 #define EXTI_RTSR_TR11_Pos (11U) 6578 #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ 6579 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ 6580 #define EXTI_RTSR_TR12_Pos (12U) 6581 #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ 6582 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ 6583 #define EXTI_RTSR_TR13_Pos (13U) 6584 #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ 6585 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ 6586 #define EXTI_RTSR_TR14_Pos (14U) 6587 #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ 6588 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ 6589 #define EXTI_RTSR_TR15_Pos (15U) 6590 #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ 6591 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ 6592 #define EXTI_RTSR_TR16_Pos (16U) 6593 #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ 6594 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ 6595 #define EXTI_RTSR_TR17_Pos (17U) 6596 #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ 6597 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ 6598 #define EXTI_RTSR_TR18_Pos (18U) 6599 #define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ 6600 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ 6601 #define EXTI_RTSR_TR19_Pos (19U) 6602 #define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ 6603 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ 6604 #define EXTI_RTSR_TR20_Pos (20U) 6605 #define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */ 6606 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */ 6607 #define EXTI_RTSR_TR21_Pos (21U) 6608 #define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */ 6609 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */ 6610 #define EXTI_RTSR_TR22_Pos (22U) 6611 #define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */ 6612 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */ 6613 6614 /****************** Bit definition for EXTI_FTSR register *******************/ 6615 #define EXTI_FTSR_TR0_Pos (0U) 6616 #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ 6617 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ 6618 #define EXTI_FTSR_TR1_Pos (1U) 6619 #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ 6620 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ 6621 #define EXTI_FTSR_TR2_Pos (2U) 6622 #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ 6623 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ 6624 #define EXTI_FTSR_TR3_Pos (3U) 6625 #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ 6626 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ 6627 #define EXTI_FTSR_TR4_Pos (4U) 6628 #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ 6629 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ 6630 #define EXTI_FTSR_TR5_Pos (5U) 6631 #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ 6632 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ 6633 #define EXTI_FTSR_TR6_Pos (6U) 6634 #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ 6635 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ 6636 #define EXTI_FTSR_TR7_Pos (7U) 6637 #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ 6638 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ 6639 #define EXTI_FTSR_TR8_Pos (8U) 6640 #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ 6641 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ 6642 #define EXTI_FTSR_TR9_Pos (9U) 6643 #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ 6644 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ 6645 #define EXTI_FTSR_TR10_Pos (10U) 6646 #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ 6647 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ 6648 #define EXTI_FTSR_TR11_Pos (11U) 6649 #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ 6650 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ 6651 #define EXTI_FTSR_TR12_Pos (12U) 6652 #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ 6653 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ 6654 #define EXTI_FTSR_TR13_Pos (13U) 6655 #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ 6656 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ 6657 #define EXTI_FTSR_TR14_Pos (14U) 6658 #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ 6659 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ 6660 #define EXTI_FTSR_TR15_Pos (15U) 6661 #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ 6662 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ 6663 #define EXTI_FTSR_TR16_Pos (16U) 6664 #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ 6665 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ 6666 #define EXTI_FTSR_TR17_Pos (17U) 6667 #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ 6668 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ 6669 #define EXTI_FTSR_TR18_Pos (18U) 6670 #define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ 6671 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ 6672 #define EXTI_FTSR_TR19_Pos (19U) 6673 #define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ 6674 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ 6675 #define EXTI_FTSR_TR20_Pos (20U) 6676 #define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */ 6677 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */ 6678 #define EXTI_FTSR_TR21_Pos (21U) 6679 #define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */ 6680 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */ 6681 #define EXTI_FTSR_TR22_Pos (22U) 6682 #define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */ 6683 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */ 6684 6685 /****************** Bit definition for EXTI_SWIER register ******************/ 6686 #define EXTI_SWIER_SWIER0_Pos (0U) 6687 #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ 6688 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ 6689 #define EXTI_SWIER_SWIER1_Pos (1U) 6690 #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ 6691 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ 6692 #define EXTI_SWIER_SWIER2_Pos (2U) 6693 #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ 6694 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ 6695 #define EXTI_SWIER_SWIER3_Pos (3U) 6696 #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ 6697 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ 6698 #define EXTI_SWIER_SWIER4_Pos (4U) 6699 #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ 6700 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ 6701 #define EXTI_SWIER_SWIER5_Pos (5U) 6702 #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ 6703 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ 6704 #define EXTI_SWIER_SWIER6_Pos (6U) 6705 #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ 6706 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ 6707 #define EXTI_SWIER_SWIER7_Pos (7U) 6708 #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ 6709 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ 6710 #define EXTI_SWIER_SWIER8_Pos (8U) 6711 #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ 6712 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ 6713 #define EXTI_SWIER_SWIER9_Pos (9U) 6714 #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ 6715 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ 6716 #define EXTI_SWIER_SWIER10_Pos (10U) 6717 #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ 6718 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ 6719 #define EXTI_SWIER_SWIER11_Pos (11U) 6720 #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ 6721 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ 6722 #define EXTI_SWIER_SWIER12_Pos (12U) 6723 #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ 6724 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ 6725 #define EXTI_SWIER_SWIER13_Pos (13U) 6726 #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ 6727 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ 6728 #define EXTI_SWIER_SWIER14_Pos (14U) 6729 #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ 6730 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ 6731 #define EXTI_SWIER_SWIER15_Pos (15U) 6732 #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ 6733 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ 6734 #define EXTI_SWIER_SWIER16_Pos (16U) 6735 #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ 6736 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ 6737 #define EXTI_SWIER_SWIER17_Pos (17U) 6738 #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ 6739 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ 6740 #define EXTI_SWIER_SWIER18_Pos (18U) 6741 #define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ 6742 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ 6743 #define EXTI_SWIER_SWIER19_Pos (19U) 6744 #define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ 6745 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ 6746 #define EXTI_SWIER_SWIER20_Pos (20U) 6747 #define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */ 6748 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */ 6749 #define EXTI_SWIER_SWIER21_Pos (21U) 6750 #define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */ 6751 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */ 6752 #define EXTI_SWIER_SWIER22_Pos (22U) 6753 #define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */ 6754 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */ 6755 6756 /******************* Bit definition for EXTI_PR register ********************/ 6757 #define EXTI_PR_PR0_Pos (0U) 6758 #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ 6759 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ 6760 #define EXTI_PR_PR1_Pos (1U) 6761 #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ 6762 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ 6763 #define EXTI_PR_PR2_Pos (2U) 6764 #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ 6765 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ 6766 #define EXTI_PR_PR3_Pos (3U) 6767 #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ 6768 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ 6769 #define EXTI_PR_PR4_Pos (4U) 6770 #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ 6771 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ 6772 #define EXTI_PR_PR5_Pos (5U) 6773 #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ 6774 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ 6775 #define EXTI_PR_PR6_Pos (6U) 6776 #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ 6777 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ 6778 #define EXTI_PR_PR7_Pos (7U) 6779 #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ 6780 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ 6781 #define EXTI_PR_PR8_Pos (8U) 6782 #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ 6783 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ 6784 #define EXTI_PR_PR9_Pos (9U) 6785 #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ 6786 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ 6787 #define EXTI_PR_PR10_Pos (10U) 6788 #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ 6789 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ 6790 #define EXTI_PR_PR11_Pos (11U) 6791 #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ 6792 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ 6793 #define EXTI_PR_PR12_Pos (12U) 6794 #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ 6795 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ 6796 #define EXTI_PR_PR13_Pos (13U) 6797 #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ 6798 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ 6799 #define EXTI_PR_PR14_Pos (14U) 6800 #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ 6801 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ 6802 #define EXTI_PR_PR15_Pos (15U) 6803 #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ 6804 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ 6805 #define EXTI_PR_PR16_Pos (16U) 6806 #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ 6807 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ 6808 #define EXTI_PR_PR17_Pos (17U) 6809 #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ 6810 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ 6811 #define EXTI_PR_PR18_Pos (18U) 6812 #define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ 6813 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ 6814 #define EXTI_PR_PR19_Pos (19U) 6815 #define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ 6816 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */ 6817 #define EXTI_PR_PR20_Pos (20U) 6818 #define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos) /*!< 0x00100000 */ 6819 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */ 6820 #define EXTI_PR_PR21_Pos (21U) 6821 #define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos) /*!< 0x00200000 */ 6822 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */ 6823 #define EXTI_PR_PR22_Pos (22U) 6824 #define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos) /*!< 0x00400000 */ 6825 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */ 6826 6827 /******************************************************************************/ 6828 /* */ 6829 /* FLASH */ 6830 /* */ 6831 /******************************************************************************/ 6832 /******************* Bits definition for FLASH_ACR register *****************/ 6833 #define FLASH_ACR_LATENCY_Pos (0U) 6834 #define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ 6835 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk 6836 #define FLASH_ACR_LATENCY_0WS 0x00000000U 6837 #define FLASH_ACR_LATENCY_1WS 0x00000001U 6838 #define FLASH_ACR_LATENCY_2WS 0x00000002U 6839 #define FLASH_ACR_LATENCY_3WS 0x00000003U 6840 #define FLASH_ACR_LATENCY_4WS 0x00000004U 6841 #define FLASH_ACR_LATENCY_5WS 0x00000005U 6842 #define FLASH_ACR_LATENCY_6WS 0x00000006U 6843 #define FLASH_ACR_LATENCY_7WS 0x00000007U 6844 6845 #define FLASH_ACR_PRFTEN_Pos (8U) 6846 #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ 6847 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk 6848 #define FLASH_ACR_ICEN_Pos (9U) 6849 #define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ 6850 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk 6851 #define FLASH_ACR_DCEN_Pos (10U) 6852 #define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */ 6853 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk 6854 #define FLASH_ACR_ICRST_Pos (11U) 6855 #define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ 6856 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk 6857 #define FLASH_ACR_DCRST_Pos (12U) 6858 #define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */ 6859 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk 6860 #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U) 6861 #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */ 6862 #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk 6863 #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U) 6864 #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */ 6865 #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk 6866 6867 /******************* Bits definition for FLASH_SR register ******************/ 6868 #define FLASH_SR_EOP_Pos (0U) 6869 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ 6870 #define FLASH_SR_EOP FLASH_SR_EOP_Msk 6871 #define FLASH_SR_SOP_Pos (1U) 6872 #define FLASH_SR_SOP_Msk (0x1UL << FLASH_SR_SOP_Pos) /*!< 0x00000002 */ 6873 #define FLASH_SR_SOP FLASH_SR_SOP_Msk 6874 #define FLASH_SR_WRPERR_Pos (4U) 6875 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ 6876 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk 6877 #define FLASH_SR_PGAERR_Pos (5U) 6878 #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ 6879 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk 6880 #define FLASH_SR_PGPERR_Pos (6U) 6881 #define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */ 6882 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk 6883 #define FLASH_SR_PGSERR_Pos (7U) 6884 #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ 6885 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk 6886 #define FLASH_SR_BSY_Pos (16U) 6887 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */ 6888 #define FLASH_SR_BSY FLASH_SR_BSY_Msk 6889 6890 /******************* Bits definition for FLASH_CR register ******************/ 6891 #define FLASH_CR_PG_Pos (0U) 6892 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ 6893 #define FLASH_CR_PG FLASH_CR_PG_Msk 6894 #define FLASH_CR_SER_Pos (1U) 6895 #define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000002 */ 6896 #define FLASH_CR_SER FLASH_CR_SER_Msk 6897 #define FLASH_CR_MER_Pos (2U) 6898 #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */ 6899 #define FLASH_CR_MER FLASH_CR_MER_Msk 6900 #define FLASH_CR_SNB_Pos (3U) 6901 #define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */ 6902 #define FLASH_CR_SNB FLASH_CR_SNB_Msk 6903 #define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) /*!< 0x00000008 */ 6904 #define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) /*!< 0x00000010 */ 6905 #define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) /*!< 0x00000020 */ 6906 #define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) /*!< 0x00000040 */ 6907 #define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) /*!< 0x00000080 */ 6908 #define FLASH_CR_PSIZE_Pos (8U) 6909 #define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */ 6910 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk 6911 #define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */ 6912 #define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */ 6913 #define FLASH_CR_STRT_Pos (16U) 6914 #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ 6915 #define FLASH_CR_STRT FLASH_CR_STRT_Msk 6916 #define FLASH_CR_EOPIE_Pos (24U) 6917 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ 6918 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk 6919 #define FLASH_CR_LOCK_Pos (31U) 6920 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ 6921 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk 6922 6923 /******************* Bits definition for FLASH_OPTCR register ***************/ 6924 #define FLASH_OPTCR_OPTLOCK_Pos (0U) 6925 #define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ 6926 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk 6927 #define FLASH_OPTCR_OPTSTRT_Pos (1U) 6928 #define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */ 6929 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk 6930 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U 6931 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U 6932 #define FLASH_OPTCR_BOR_LEV_Pos (2U) 6933 #define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */ 6934 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk 6935 6936 #define FLASH_OPTCR_WDG_SW_Pos (5U) 6937 #define FLASH_OPTCR_WDG_SW_Msk (0x1UL << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */ 6938 #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk 6939 #define FLASH_OPTCR_nRST_STOP_Pos (6U) 6940 #define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */ 6941 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk 6942 #define FLASH_OPTCR_nRST_STDBY_Pos (7U) 6943 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */ 6944 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk 6945 #define FLASH_OPTCR_RDP_Pos (8U) 6946 #define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */ 6947 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk 6948 #define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */ 6949 #define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */ 6950 #define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */ 6951 #define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */ 6952 #define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */ 6953 #define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */ 6954 #define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */ 6955 #define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */ 6956 #define FLASH_OPTCR_nWRP_Pos (16U) 6957 #define FLASH_OPTCR_nWRP_Msk (0xFFFUL << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */ 6958 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk 6959 #define FLASH_OPTCR_nWRP_0 (0x001UL << FLASH_OPTCR_nWRP_Pos) /*!< 0x00010000 */ 6960 #define FLASH_OPTCR_nWRP_1 (0x002UL << FLASH_OPTCR_nWRP_Pos) /*!< 0x00020000 */ 6961 #define FLASH_OPTCR_nWRP_2 (0x004UL << FLASH_OPTCR_nWRP_Pos) /*!< 0x00040000 */ 6962 #define FLASH_OPTCR_nWRP_3 (0x008UL << FLASH_OPTCR_nWRP_Pos) /*!< 0x00080000 */ 6963 #define FLASH_OPTCR_nWRP_4 (0x010UL << FLASH_OPTCR_nWRP_Pos) /*!< 0x00100000 */ 6964 #define FLASH_OPTCR_nWRP_5 (0x020UL << FLASH_OPTCR_nWRP_Pos) /*!< 0x00200000 */ 6965 #define FLASH_OPTCR_nWRP_6 (0x040UL << FLASH_OPTCR_nWRP_Pos) /*!< 0x00400000 */ 6966 #define FLASH_OPTCR_nWRP_7 (0x080UL << FLASH_OPTCR_nWRP_Pos) /*!< 0x00800000 */ 6967 #define FLASH_OPTCR_nWRP_8 (0x100UL << FLASH_OPTCR_nWRP_Pos) /*!< 0x01000000 */ 6968 #define FLASH_OPTCR_nWRP_9 (0x200UL << FLASH_OPTCR_nWRP_Pos) /*!< 0x02000000 */ 6969 #define FLASH_OPTCR_nWRP_10 (0x400UL << FLASH_OPTCR_nWRP_Pos) /*!< 0x04000000 */ 6970 #define FLASH_OPTCR_nWRP_11 (0x800UL << FLASH_OPTCR_nWRP_Pos) /*!< 0x08000000 */ 6971 6972 /******************************************************************************/ 6973 /* */ 6974 /* Flexible Static Memory Controller */ 6975 /* */ 6976 /******************************************************************************/ 6977 /****************** Bit definition for FSMC_BCR1 register *******************/ 6978 #define FSMC_BCR1_MBKEN_Pos (0U) 6979 #define FSMC_BCR1_MBKEN_Msk (0x1UL << FSMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */ 6980 #define FSMC_BCR1_MBKEN FSMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */ 6981 #define FSMC_BCR1_MUXEN_Pos (1U) 6982 #define FSMC_BCR1_MUXEN_Msk (0x1UL << FSMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */ 6983 #define FSMC_BCR1_MUXEN FSMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */ 6984 6985 #define FSMC_BCR1_MTYP_Pos (2U) 6986 #define FSMC_BCR1_MTYP_Msk (0x3UL << FSMC_BCR1_MTYP_Pos) /*!< 0x0000000C */ 6987 #define FSMC_BCR1_MTYP FSMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */ 6988 #define FSMC_BCR1_MTYP_0 (0x1UL << FSMC_BCR1_MTYP_Pos) /*!< 0x00000004 */ 6989 #define FSMC_BCR1_MTYP_1 (0x2UL << FSMC_BCR1_MTYP_Pos) /*!< 0x00000008 */ 6990 6991 #define FSMC_BCR1_MWID_Pos (4U) 6992 #define FSMC_BCR1_MWID_Msk (0x3UL << FSMC_BCR1_MWID_Pos) /*!< 0x00000030 */ 6993 #define FSMC_BCR1_MWID FSMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */ 6994 #define FSMC_BCR1_MWID_0 (0x1UL << FSMC_BCR1_MWID_Pos) /*!< 0x00000010 */ 6995 #define FSMC_BCR1_MWID_1 (0x2UL << FSMC_BCR1_MWID_Pos) /*!< 0x00000020 */ 6996 6997 #define FSMC_BCR1_FACCEN_Pos (6U) 6998 #define FSMC_BCR1_FACCEN_Msk (0x1UL << FSMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */ 6999 #define FSMC_BCR1_FACCEN FSMC_BCR1_FACCEN_Msk /*!<Flash access enable */ 7000 #define FSMC_BCR1_BURSTEN_Pos (8U) 7001 #define FSMC_BCR1_BURSTEN_Msk (0x1UL << FSMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */ 7002 #define FSMC_BCR1_BURSTEN FSMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */ 7003 #define FSMC_BCR1_WAITPOL_Pos (9U) 7004 #define FSMC_BCR1_WAITPOL_Msk (0x1UL << FSMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */ 7005 #define FSMC_BCR1_WAITPOL FSMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */ 7006 #define FSMC_BCR1_WRAPMOD_Pos (10U) 7007 #define FSMC_BCR1_WRAPMOD_Msk (0x1UL << FSMC_BCR1_WRAPMOD_Pos) /*!< 0x00000400 */ 7008 #define FSMC_BCR1_WRAPMOD FSMC_BCR1_WRAPMOD_Msk /*!<Wrapped burst mode support */ 7009 #define FSMC_BCR1_WAITCFG_Pos (11U) 7010 #define FSMC_BCR1_WAITCFG_Msk (0x1UL << FSMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */ 7011 #define FSMC_BCR1_WAITCFG FSMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */ 7012 #define FSMC_BCR1_WREN_Pos (12U) 7013 #define FSMC_BCR1_WREN_Msk (0x1UL << FSMC_BCR1_WREN_Pos) /*!< 0x00001000 */ 7014 #define FSMC_BCR1_WREN FSMC_BCR1_WREN_Msk /*!<Write enable bit */ 7015 #define FSMC_BCR1_WAITEN_Pos (13U) 7016 #define FSMC_BCR1_WAITEN_Msk (0x1UL << FSMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */ 7017 #define FSMC_BCR1_WAITEN FSMC_BCR1_WAITEN_Msk /*!<Wait enable bit */ 7018 #define FSMC_BCR1_EXTMOD_Pos (14U) 7019 #define FSMC_BCR1_EXTMOD_Msk (0x1UL << FSMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */ 7020 #define FSMC_BCR1_EXTMOD FSMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */ 7021 #define FSMC_BCR1_ASYNCWAIT_Pos (15U) 7022 #define FSMC_BCR1_ASYNCWAIT_Msk (0x1UL << FSMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */ 7023 #define FSMC_BCR1_ASYNCWAIT FSMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */ 7024 #define FSMC_BCR1_CBURSTRW_Pos (19U) 7025 #define FSMC_BCR1_CBURSTRW_Msk (0x1UL << FSMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */ 7026 #define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */ 7027 7028 /****************** Bit definition for FSMC_BCR2 register *******************/ 7029 #define FSMC_BCR2_MBKEN_Pos (0U) 7030 #define FSMC_BCR2_MBKEN_Msk (0x1UL << FSMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */ 7031 #define FSMC_BCR2_MBKEN FSMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */ 7032 #define FSMC_BCR2_MUXEN_Pos (1U) 7033 #define FSMC_BCR2_MUXEN_Msk (0x1UL << FSMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */ 7034 #define FSMC_BCR2_MUXEN FSMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */ 7035 7036 #define FSMC_BCR2_MTYP_Pos (2U) 7037 #define FSMC_BCR2_MTYP_Msk (0x3UL << FSMC_BCR2_MTYP_Pos) /*!< 0x0000000C */ 7038 #define FSMC_BCR2_MTYP FSMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */ 7039 #define FSMC_BCR2_MTYP_0 (0x1UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000004 */ 7040 #define FSMC_BCR2_MTYP_1 (0x2UL << FSMC_BCR2_MTYP_Pos) /*!< 0x00000008 */ 7041 7042 #define FSMC_BCR2_MWID_Pos (4U) 7043 #define FSMC_BCR2_MWID_Msk (0x3UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000030 */ 7044 #define FSMC_BCR2_MWID FSMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */ 7045 #define FSMC_BCR2_MWID_0 (0x1UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000010 */ 7046 #define FSMC_BCR2_MWID_1 (0x2UL << FSMC_BCR2_MWID_Pos) /*!< 0x00000020 */ 7047 7048 #define FSMC_BCR2_FACCEN_Pos (6U) 7049 #define FSMC_BCR2_FACCEN_Msk (0x1UL << FSMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */ 7050 #define FSMC_BCR2_FACCEN FSMC_BCR2_FACCEN_Msk /*!<Flash access enable */ 7051 #define FSMC_BCR2_BURSTEN_Pos (8U) 7052 #define FSMC_BCR2_BURSTEN_Msk (0x1UL << FSMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */ 7053 #define FSMC_BCR2_BURSTEN FSMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */ 7054 #define FSMC_BCR2_WAITPOL_Pos (9U) 7055 #define FSMC_BCR2_WAITPOL_Msk (0x1UL << FSMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */ 7056 #define FSMC_BCR2_WAITPOL FSMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */ 7057 #define FSMC_BCR2_WRAPMOD_Pos (10U) 7058 #define FSMC_BCR2_WRAPMOD_Msk (0x1UL << FSMC_BCR2_WRAPMOD_Pos) /*!< 0x00000400 */ 7059 #define FSMC_BCR2_WRAPMOD FSMC_BCR2_WRAPMOD_Msk /*!<Wrapped burst mode support */ 7060 #define FSMC_BCR2_WAITCFG_Pos (11U) 7061 #define FSMC_BCR2_WAITCFG_Msk (0x1UL << FSMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */ 7062 #define FSMC_BCR2_WAITCFG FSMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */ 7063 #define FSMC_BCR2_WREN_Pos (12U) 7064 #define FSMC_BCR2_WREN_Msk (0x1UL << FSMC_BCR2_WREN_Pos) /*!< 0x00001000 */ 7065 #define FSMC_BCR2_WREN FSMC_BCR2_WREN_Msk /*!<Write enable bit */ 7066 #define FSMC_BCR2_WAITEN_Pos (13U) 7067 #define FSMC_BCR2_WAITEN_Msk (0x1UL << FSMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */ 7068 #define FSMC_BCR2_WAITEN FSMC_BCR2_WAITEN_Msk /*!<Wait enable bit */ 7069 #define FSMC_BCR2_EXTMOD_Pos (14U) 7070 #define FSMC_BCR2_EXTMOD_Msk (0x1UL << FSMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */ 7071 #define FSMC_BCR2_EXTMOD FSMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */ 7072 #define FSMC_BCR2_ASYNCWAIT_Pos (15U) 7073 #define FSMC_BCR2_ASYNCWAIT_Msk (0x1UL << FSMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */ 7074 #define FSMC_BCR2_ASYNCWAIT FSMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */ 7075 #define FSMC_BCR2_CBURSTRW_Pos (19U) 7076 #define FSMC_BCR2_CBURSTRW_Msk (0x1UL << FSMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */ 7077 #define FSMC_BCR2_CBURSTRW FSMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */ 7078 7079 /****************** Bit definition for FSMC_BCR3 register *******************/ 7080 #define FSMC_BCR3_MBKEN_Pos (0U) 7081 #define FSMC_BCR3_MBKEN_Msk (0x1UL << FSMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */ 7082 #define FSMC_BCR3_MBKEN FSMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */ 7083 #define FSMC_BCR3_MUXEN_Pos (1U) 7084 #define FSMC_BCR3_MUXEN_Msk (0x1UL << FSMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */ 7085 #define FSMC_BCR3_MUXEN FSMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */ 7086 7087 #define FSMC_BCR3_MTYP_Pos (2U) 7088 #define FSMC_BCR3_MTYP_Msk (0x3UL << FSMC_BCR3_MTYP_Pos) /*!< 0x0000000C */ 7089 #define FSMC_BCR3_MTYP FSMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */ 7090 #define FSMC_BCR3_MTYP_0 (0x1UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000004 */ 7091 #define FSMC_BCR3_MTYP_1 (0x2UL << FSMC_BCR3_MTYP_Pos) /*!< 0x00000008 */ 7092 7093 #define FSMC_BCR3_MWID_Pos (4U) 7094 #define FSMC_BCR3_MWID_Msk (0x3UL << FSMC_BCR3_MWID_Pos) /*!< 0x00000030 */ 7095 #define FSMC_BCR3_MWID FSMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */ 7096 #define FSMC_BCR3_MWID_0 (0x1UL << FSMC_BCR3_MWID_Pos) /*!< 0x00000010 */ 7097 #define FSMC_BCR3_MWID_1 (0x2UL << FSMC_BCR3_MWID_Pos) /*!< 0x00000020 */ 7098 7099 #define FSMC_BCR3_FACCEN_Pos (6U) 7100 #define FSMC_BCR3_FACCEN_Msk (0x1UL << FSMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */ 7101 #define FSMC_BCR3_FACCEN FSMC_BCR3_FACCEN_Msk /*!<Flash access enable */ 7102 #define FSMC_BCR3_BURSTEN_Pos (8U) 7103 #define FSMC_BCR3_BURSTEN_Msk (0x1UL << FSMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */ 7104 #define FSMC_BCR3_BURSTEN FSMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */ 7105 #define FSMC_BCR3_WAITPOL_Pos (9U) 7106 #define FSMC_BCR3_WAITPOL_Msk (0x1UL << FSMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */ 7107 #define FSMC_BCR3_WAITPOL FSMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */ 7108 #define FSMC_BCR3_WRAPMOD_Pos (10U) 7109 #define FSMC_BCR3_WRAPMOD_Msk (0x1UL << FSMC_BCR3_WRAPMOD_Pos) /*!< 0x00000400 */ 7110 #define FSMC_BCR3_WRAPMOD FSMC_BCR3_WRAPMOD_Msk /*!<Wrapped burst mode support */ 7111 #define FSMC_BCR3_WAITCFG_Pos (11U) 7112 #define FSMC_BCR3_WAITCFG_Msk (0x1UL << FSMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */ 7113 #define FSMC_BCR3_WAITCFG FSMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */ 7114 #define FSMC_BCR3_WREN_Pos (12U) 7115 #define FSMC_BCR3_WREN_Msk (0x1UL << FSMC_BCR3_WREN_Pos) /*!< 0x00001000 */ 7116 #define FSMC_BCR3_WREN FSMC_BCR3_WREN_Msk /*!<Write enable bit */ 7117 #define FSMC_BCR3_WAITEN_Pos (13U) 7118 #define FSMC_BCR3_WAITEN_Msk (0x1UL << FSMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */ 7119 #define FSMC_BCR3_WAITEN FSMC_BCR3_WAITEN_Msk /*!<Wait enable bit */ 7120 #define FSMC_BCR3_EXTMOD_Pos (14U) 7121 #define FSMC_BCR3_EXTMOD_Msk (0x1UL << FSMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */ 7122 #define FSMC_BCR3_EXTMOD FSMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */ 7123 #define FSMC_BCR3_ASYNCWAIT_Pos (15U) 7124 #define FSMC_BCR3_ASYNCWAIT_Msk (0x1UL << FSMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */ 7125 #define FSMC_BCR3_ASYNCWAIT FSMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */ 7126 #define FSMC_BCR3_CBURSTRW_Pos (19U) 7127 #define FSMC_BCR3_CBURSTRW_Msk (0x1UL << FSMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */ 7128 #define FSMC_BCR3_CBURSTRW FSMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */ 7129 7130 /****************** Bit definition for FSMC_BCR4 register *******************/ 7131 #define FSMC_BCR4_MBKEN_Pos (0U) 7132 #define FSMC_BCR4_MBKEN_Msk (0x1UL << FSMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */ 7133 #define FSMC_BCR4_MBKEN FSMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */ 7134 #define FSMC_BCR4_MUXEN_Pos (1U) 7135 #define FSMC_BCR4_MUXEN_Msk (0x1UL << FSMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */ 7136 #define FSMC_BCR4_MUXEN FSMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */ 7137 7138 #define FSMC_BCR4_MTYP_Pos (2U) 7139 #define FSMC_BCR4_MTYP_Msk (0x3UL << FSMC_BCR4_MTYP_Pos) /*!< 0x0000000C */ 7140 #define FSMC_BCR4_MTYP FSMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */ 7141 #define FSMC_BCR4_MTYP_0 (0x1UL << FSMC_BCR4_MTYP_Pos) /*!< 0x00000004 */ 7142 #define FSMC_BCR4_MTYP_1 (0x2UL << FSMC_BCR4_MTYP_Pos) /*!< 0x00000008 */ 7143 7144 #define FSMC_BCR4_MWID_Pos (4U) 7145 #define FSMC_BCR4_MWID_Msk (0x3UL << FSMC_BCR4_MWID_Pos) /*!< 0x00000030 */ 7146 #define FSMC_BCR4_MWID FSMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */ 7147 #define FSMC_BCR4_MWID_0 (0x1UL << FSMC_BCR4_MWID_Pos) /*!< 0x00000010 */ 7148 #define FSMC_BCR4_MWID_1 (0x2UL << FSMC_BCR4_MWID_Pos) /*!< 0x00000020 */ 7149 7150 #define FSMC_BCR4_FACCEN_Pos (6U) 7151 #define FSMC_BCR4_FACCEN_Msk (0x1UL << FSMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */ 7152 #define FSMC_BCR4_FACCEN FSMC_BCR4_FACCEN_Msk /*!<Flash access enable */ 7153 #define FSMC_BCR4_BURSTEN_Pos (8U) 7154 #define FSMC_BCR4_BURSTEN_Msk (0x1UL << FSMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */ 7155 #define FSMC_BCR4_BURSTEN FSMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */ 7156 #define FSMC_BCR4_WAITPOL_Pos (9U) 7157 #define FSMC_BCR4_WAITPOL_Msk (0x1UL << FSMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */ 7158 #define FSMC_BCR4_WAITPOL FSMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */ 7159 #define FSMC_BCR4_WRAPMOD_Pos (10U) 7160 #define FSMC_BCR4_WRAPMOD_Msk (0x1UL << FSMC_BCR4_WRAPMOD_Pos) /*!< 0x00000400 */ 7161 #define FSMC_BCR4_WRAPMOD FSMC_BCR4_WRAPMOD_Msk /*!<Wrapped burst mode support */ 7162 #define FSMC_BCR4_WAITCFG_Pos (11U) 7163 #define FSMC_BCR4_WAITCFG_Msk (0x1UL << FSMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */ 7164 #define FSMC_BCR4_WAITCFG FSMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */ 7165 #define FSMC_BCR4_WREN_Pos (12U) 7166 #define FSMC_BCR4_WREN_Msk (0x1UL << FSMC_BCR4_WREN_Pos) /*!< 0x00001000 */ 7167 #define FSMC_BCR4_WREN FSMC_BCR4_WREN_Msk /*!<Write enable bit */ 7168 #define FSMC_BCR4_WAITEN_Pos (13U) 7169 #define FSMC_BCR4_WAITEN_Msk (0x1UL << FSMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */ 7170 #define FSMC_BCR4_WAITEN FSMC_BCR4_WAITEN_Msk /*!<Wait enable bit */ 7171 #define FSMC_BCR4_EXTMOD_Pos (14U) 7172 #define FSMC_BCR4_EXTMOD_Msk (0x1UL << FSMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */ 7173 #define FSMC_BCR4_EXTMOD FSMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */ 7174 #define FSMC_BCR4_ASYNCWAIT_Pos (15U) 7175 #define FSMC_BCR4_ASYNCWAIT_Msk (0x1UL << FSMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */ 7176 #define FSMC_BCR4_ASYNCWAIT FSMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */ 7177 #define FSMC_BCR4_CBURSTRW_Pos (19U) 7178 #define FSMC_BCR4_CBURSTRW_Msk (0x1UL << FSMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */ 7179 #define FSMC_BCR4_CBURSTRW FSMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */ 7180 7181 /****************** Bit definition for FSMC_BTR1 register ******************/ 7182 #define FSMC_BTR1_ADDSET_Pos (0U) 7183 #define FSMC_BTR1_ADDSET_Msk (0xFUL << FSMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */ 7184 #define FSMC_BTR1_ADDSET FSMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */ 7185 #define FSMC_BTR1_ADDSET_0 (0x1UL << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */ 7186 #define FSMC_BTR1_ADDSET_1 (0x2UL << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */ 7187 #define FSMC_BTR1_ADDSET_2 (0x4UL << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */ 7188 #define FSMC_BTR1_ADDSET_3 (0x8UL << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */ 7189 7190 #define FSMC_BTR1_ADDHLD_Pos (4U) 7191 #define FSMC_BTR1_ADDHLD_Msk (0xFUL << FSMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */ 7192 #define FSMC_BTR1_ADDHLD FSMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ 7193 #define FSMC_BTR1_ADDHLD_0 (0x1UL << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */ 7194 #define FSMC_BTR1_ADDHLD_1 (0x2UL << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */ 7195 #define FSMC_BTR1_ADDHLD_2 (0x4UL << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */ 7196 #define FSMC_BTR1_ADDHLD_3 (0x8UL << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */ 7197 7198 #define FSMC_BTR1_DATAST_Pos (8U) 7199 #define FSMC_BTR1_DATAST_Msk (0xFFUL << FSMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */ 7200 #define FSMC_BTR1_DATAST FSMC_BTR1_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */ 7201 #define FSMC_BTR1_DATAST_0 (0x01UL << FSMC_BTR1_DATAST_Pos) /*!< 0x00000100 */ 7202 #define FSMC_BTR1_DATAST_1 (0x02UL << FSMC_BTR1_DATAST_Pos) /*!< 0x00000200 */ 7203 #define FSMC_BTR1_DATAST_2 (0x04UL << FSMC_BTR1_DATAST_Pos) /*!< 0x00000400 */ 7204 #define FSMC_BTR1_DATAST_3 (0x08UL << FSMC_BTR1_DATAST_Pos) /*!< 0x00000800 */ 7205 #define FSMC_BTR1_DATAST_4 (0x10UL << FSMC_BTR1_DATAST_Pos) /*!< 0x00001000 */ 7206 #define FSMC_BTR1_DATAST_5 (0x20UL << FSMC_BTR1_DATAST_Pos) /*!< 0x00002000 */ 7207 #define FSMC_BTR1_DATAST_6 (0x40UL << FSMC_BTR1_DATAST_Pos) /*!< 0x00004000 */ 7208 #define FSMC_BTR1_DATAST_7 (0x80UL << FSMC_BTR1_DATAST_Pos) /*!< 0x00008000 */ 7209 7210 #define FSMC_BTR1_BUSTURN_Pos (16U) 7211 #define FSMC_BTR1_BUSTURN_Msk (0xFUL << FSMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */ 7212 #define FSMC_BTR1_BUSTURN FSMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ 7213 #define FSMC_BTR1_BUSTURN_0 (0x1UL << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */ 7214 #define FSMC_BTR1_BUSTURN_1 (0x2UL << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */ 7215 #define FSMC_BTR1_BUSTURN_2 (0x4UL << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */ 7216 #define FSMC_BTR1_BUSTURN_3 (0x8UL << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */ 7217 7218 #define FSMC_BTR1_CLKDIV_Pos (20U) 7219 #define FSMC_BTR1_CLKDIV_Msk (0xFUL << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */ 7220 #define FSMC_BTR1_CLKDIV FSMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */ 7221 #define FSMC_BTR1_CLKDIV_0 (0x1UL << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */ 7222 #define FSMC_BTR1_CLKDIV_1 (0x2UL << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */ 7223 #define FSMC_BTR1_CLKDIV_2 (0x4UL << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */ 7224 #define FSMC_BTR1_CLKDIV_3 (0x8UL << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */ 7225 7226 #define FSMC_BTR1_DATLAT_Pos (24U) 7227 #define FSMC_BTR1_DATLAT_Msk (0xFUL << FSMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */ 7228 #define FSMC_BTR1_DATLAT FSMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */ 7229 #define FSMC_BTR1_DATLAT_0 (0x1UL << FSMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */ 7230 #define FSMC_BTR1_DATLAT_1 (0x2UL << FSMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */ 7231 #define FSMC_BTR1_DATLAT_2 (0x4UL << FSMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */ 7232 #define FSMC_BTR1_DATLAT_3 (0x8UL << FSMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */ 7233 7234 #define FSMC_BTR1_ACCMOD_Pos (28U) 7235 #define FSMC_BTR1_ACCMOD_Msk (0x3UL << FSMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */ 7236 #define FSMC_BTR1_ACCMOD FSMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */ 7237 #define FSMC_BTR1_ACCMOD_0 (0x1UL << FSMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */ 7238 #define FSMC_BTR1_ACCMOD_1 (0x2UL << FSMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */ 7239 7240 /****************** Bit definition for FSMC_BTR2 register *******************/ 7241 #define FSMC_BTR2_ADDSET_Pos (0U) 7242 #define FSMC_BTR2_ADDSET_Msk (0xFUL << FSMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */ 7243 #define FSMC_BTR2_ADDSET FSMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */ 7244 #define FSMC_BTR2_ADDSET_0 (0x1UL << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */ 7245 #define FSMC_BTR2_ADDSET_1 (0x2UL << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */ 7246 #define FSMC_BTR2_ADDSET_2 (0x4UL << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */ 7247 #define FSMC_BTR2_ADDSET_3 (0x8UL << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */ 7248 7249 #define FSMC_BTR2_ADDHLD_Pos (4U) 7250 #define FSMC_BTR2_ADDHLD_Msk (0xFUL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */ 7251 #define FSMC_BTR2_ADDHLD FSMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ 7252 #define FSMC_BTR2_ADDHLD_0 (0x1UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */ 7253 #define FSMC_BTR2_ADDHLD_1 (0x2UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */ 7254 #define FSMC_BTR2_ADDHLD_2 (0x4UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */ 7255 #define FSMC_BTR2_ADDHLD_3 (0x8UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */ 7256 7257 #define FSMC_BTR2_DATAST_Pos (8U) 7258 #define FSMC_BTR2_DATAST_Msk (0xFFUL << FSMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */ 7259 #define FSMC_BTR2_DATAST FSMC_BTR2_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */ 7260 #define FSMC_BTR2_DATAST_0 (0x01UL << FSMC_BTR2_DATAST_Pos) /*!< 0x00000100 */ 7261 #define FSMC_BTR2_DATAST_1 (0x02UL << FSMC_BTR2_DATAST_Pos) /*!< 0x00000200 */ 7262 #define FSMC_BTR2_DATAST_2 (0x04UL << FSMC_BTR2_DATAST_Pos) /*!< 0x00000400 */ 7263 #define FSMC_BTR2_DATAST_3 (0x08UL << FSMC_BTR2_DATAST_Pos) /*!< 0x00000800 */ 7264 #define FSMC_BTR2_DATAST_4 (0x10UL << FSMC_BTR2_DATAST_Pos) /*!< 0x00001000 */ 7265 #define FSMC_BTR2_DATAST_5 (0x20UL << FSMC_BTR2_DATAST_Pos) /*!< 0x00002000 */ 7266 #define FSMC_BTR2_DATAST_6 (0x40UL << FSMC_BTR2_DATAST_Pos) /*!< 0x00004000 */ 7267 #define FSMC_BTR2_DATAST_7 (0x80UL << FSMC_BTR2_DATAST_Pos) /*!< 0x00008000 */ 7268 7269 #define FSMC_BTR2_BUSTURN_Pos (16U) 7270 #define FSMC_BTR2_BUSTURN_Msk (0xFUL << FSMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */ 7271 #define FSMC_BTR2_BUSTURN FSMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ 7272 #define FSMC_BTR2_BUSTURN_0 (0x1UL << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */ 7273 #define FSMC_BTR2_BUSTURN_1 (0x2UL << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */ 7274 #define FSMC_BTR2_BUSTURN_2 (0x4UL << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */ 7275 #define FSMC_BTR2_BUSTURN_3 (0x8UL << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */ 7276 7277 #define FSMC_BTR2_CLKDIV_Pos (20U) 7278 #define FSMC_BTR2_CLKDIV_Msk (0xFUL << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */ 7279 #define FSMC_BTR2_CLKDIV FSMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */ 7280 #define FSMC_BTR2_CLKDIV_0 (0x1UL << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */ 7281 #define FSMC_BTR2_CLKDIV_1 (0x2UL << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */ 7282 #define FSMC_BTR2_CLKDIV_2 (0x4UL << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */ 7283 #define FSMC_BTR2_CLKDIV_3 (0x8UL << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */ 7284 7285 #define FSMC_BTR2_DATLAT_Pos (24U) 7286 #define FSMC_BTR2_DATLAT_Msk (0xFUL << FSMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */ 7287 #define FSMC_BTR2_DATLAT FSMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */ 7288 #define FSMC_BTR2_DATLAT_0 (0x1UL << FSMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */ 7289 #define FSMC_BTR2_DATLAT_1 (0x2UL << FSMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */ 7290 #define FSMC_BTR2_DATLAT_2 (0x4UL << FSMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */ 7291 #define FSMC_BTR2_DATLAT_3 (0x8UL << FSMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */ 7292 7293 #define FSMC_BTR2_ACCMOD_Pos (28U) 7294 #define FSMC_BTR2_ACCMOD_Msk (0x3UL << FSMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */ 7295 #define FSMC_BTR2_ACCMOD FSMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */ 7296 #define FSMC_BTR2_ACCMOD_0 (0x1UL << FSMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */ 7297 #define FSMC_BTR2_ACCMOD_1 (0x2UL << FSMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */ 7298 7299 /******************* Bit definition for FSMC_BTR3 register *******************/ 7300 #define FSMC_BTR3_ADDSET_Pos (0U) 7301 #define FSMC_BTR3_ADDSET_Msk (0xFUL << FSMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */ 7302 #define FSMC_BTR3_ADDSET FSMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */ 7303 #define FSMC_BTR3_ADDSET_0 (0x1UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */ 7304 #define FSMC_BTR3_ADDSET_1 (0x2UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */ 7305 #define FSMC_BTR3_ADDSET_2 (0x4UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */ 7306 #define FSMC_BTR3_ADDSET_3 (0x8UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */ 7307 7308 #define FSMC_BTR3_ADDHLD_Pos (4U) 7309 #define FSMC_BTR3_ADDHLD_Msk (0xFUL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */ 7310 #define FSMC_BTR3_ADDHLD FSMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ 7311 #define FSMC_BTR3_ADDHLD_0 (0x1UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */ 7312 #define FSMC_BTR3_ADDHLD_1 (0x2UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */ 7313 #define FSMC_BTR3_ADDHLD_2 (0x4UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */ 7314 #define FSMC_BTR3_ADDHLD_3 (0x8UL << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */ 7315 7316 #define FSMC_BTR3_DATAST_Pos (8U) 7317 #define FSMC_BTR3_DATAST_Msk (0xFFUL << FSMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */ 7318 #define FSMC_BTR3_DATAST FSMC_BTR3_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */ 7319 #define FSMC_BTR3_DATAST_0 (0x01UL << FSMC_BTR3_DATAST_Pos) /*!< 0x00000100 */ 7320 #define FSMC_BTR3_DATAST_1 (0x02UL << FSMC_BTR3_DATAST_Pos) /*!< 0x00000200 */ 7321 #define FSMC_BTR3_DATAST_2 (0x04UL << FSMC_BTR3_DATAST_Pos) /*!< 0x00000400 */ 7322 #define FSMC_BTR3_DATAST_3 (0x08UL << FSMC_BTR3_DATAST_Pos) /*!< 0x00000800 */ 7323 #define FSMC_BTR3_DATAST_4 (0x10UL << FSMC_BTR3_DATAST_Pos) /*!< 0x00001000 */ 7324 #define FSMC_BTR3_DATAST_5 (0x20UL << FSMC_BTR3_DATAST_Pos) /*!< 0x00002000 */ 7325 #define FSMC_BTR3_DATAST_6 (0x40UL << FSMC_BTR3_DATAST_Pos) /*!< 0x00004000 */ 7326 #define FSMC_BTR3_DATAST_7 (0x80UL << FSMC_BTR3_DATAST_Pos) /*!< 0x00008000 */ 7327 7328 #define FSMC_BTR3_BUSTURN_Pos (16U) 7329 #define FSMC_BTR3_BUSTURN_Msk (0xFUL << FSMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */ 7330 #define FSMC_BTR3_BUSTURN FSMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ 7331 #define FSMC_BTR3_BUSTURN_0 (0x1UL << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */ 7332 #define FSMC_BTR3_BUSTURN_1 (0x2UL << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */ 7333 #define FSMC_BTR3_BUSTURN_2 (0x4UL << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */ 7334 #define FSMC_BTR3_BUSTURN_3 (0x8UL << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */ 7335 7336 #define FSMC_BTR3_CLKDIV_Pos (20U) 7337 #define FSMC_BTR3_CLKDIV_Msk (0xFUL << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */ 7338 #define FSMC_BTR3_CLKDIV FSMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */ 7339 #define FSMC_BTR3_CLKDIV_0 (0x1UL << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */ 7340 #define FSMC_BTR3_CLKDIV_1 (0x2UL << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */ 7341 #define FSMC_BTR3_CLKDIV_2 (0x4UL << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */ 7342 #define FSMC_BTR3_CLKDIV_3 (0x8UL << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */ 7343 7344 #define FSMC_BTR3_DATLAT_Pos (24U) 7345 #define FSMC_BTR3_DATLAT_Msk (0xFUL << FSMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */ 7346 #define FSMC_BTR3_DATLAT FSMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */ 7347 #define FSMC_BTR3_DATLAT_0 (0x1UL << FSMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */ 7348 #define FSMC_BTR3_DATLAT_1 (0x2UL << FSMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */ 7349 #define FSMC_BTR3_DATLAT_2 (0x4UL << FSMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */ 7350 #define FSMC_BTR3_DATLAT_3 (0x8UL << FSMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */ 7351 7352 #define FSMC_BTR3_ACCMOD_Pos (28U) 7353 #define FSMC_BTR3_ACCMOD_Msk (0x3UL << FSMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */ 7354 #define FSMC_BTR3_ACCMOD FSMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */ 7355 #define FSMC_BTR3_ACCMOD_0 (0x1UL << FSMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */ 7356 #define FSMC_BTR3_ACCMOD_1 (0x2UL << FSMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */ 7357 7358 /****************** Bit definition for FSMC_BTR4 register *******************/ 7359 #define FSMC_BTR4_ADDSET_Pos (0U) 7360 #define FSMC_BTR4_ADDSET_Msk (0xFUL << FSMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */ 7361 #define FSMC_BTR4_ADDSET FSMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */ 7362 #define FSMC_BTR4_ADDSET_0 (0x1UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */ 7363 #define FSMC_BTR4_ADDSET_1 (0x2UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */ 7364 #define FSMC_BTR4_ADDSET_2 (0x4UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */ 7365 #define FSMC_BTR4_ADDSET_3 (0x8UL << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */ 7366 7367 #define FSMC_BTR4_ADDHLD_Pos (4U) 7368 #define FSMC_BTR4_ADDHLD_Msk (0xFUL << FSMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */ 7369 #define FSMC_BTR4_ADDHLD FSMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ 7370 #define FSMC_BTR4_ADDHLD_0 (0x1UL << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */ 7371 #define FSMC_BTR4_ADDHLD_1 (0x2UL << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */ 7372 #define FSMC_BTR4_ADDHLD_2 (0x4UL << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */ 7373 #define FSMC_BTR4_ADDHLD_3 (0x8UL << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */ 7374 7375 #define FSMC_BTR4_DATAST_Pos (8U) 7376 #define FSMC_BTR4_DATAST_Msk (0xFFUL << FSMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */ 7377 #define FSMC_BTR4_DATAST FSMC_BTR4_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */ 7378 #define FSMC_BTR4_DATAST_0 (0x01UL << FSMC_BTR4_DATAST_Pos) /*!< 0x00000100 */ 7379 #define FSMC_BTR4_DATAST_1 (0x02UL << FSMC_BTR4_DATAST_Pos) /*!< 0x00000200 */ 7380 #define FSMC_BTR4_DATAST_2 (0x04UL << FSMC_BTR4_DATAST_Pos) /*!< 0x00000400 */ 7381 #define FSMC_BTR4_DATAST_3 (0x08UL << FSMC_BTR4_DATAST_Pos) /*!< 0x00000800 */ 7382 #define FSMC_BTR4_DATAST_4 (0x10UL << FSMC_BTR4_DATAST_Pos) /*!< 0x00001000 */ 7383 #define FSMC_BTR4_DATAST_5 (0x20UL << FSMC_BTR4_DATAST_Pos) /*!< 0x00002000 */ 7384 #define FSMC_BTR4_DATAST_6 (0x40UL << FSMC_BTR4_DATAST_Pos) /*!< 0x00004000 */ 7385 #define FSMC_BTR4_DATAST_7 (0x80UL << FSMC_BTR4_DATAST_Pos) /*!< 0x00008000 */ 7386 7387 #define FSMC_BTR4_BUSTURN_Pos (16U) 7388 #define FSMC_BTR4_BUSTURN_Msk (0xFUL << FSMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */ 7389 #define FSMC_BTR4_BUSTURN FSMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ 7390 #define FSMC_BTR4_BUSTURN_0 (0x1UL << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */ 7391 #define FSMC_BTR4_BUSTURN_1 (0x2UL << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */ 7392 #define FSMC_BTR4_BUSTURN_2 (0x4UL << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */ 7393 #define FSMC_BTR4_BUSTURN_3 (0x8UL << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */ 7394 7395 #define FSMC_BTR4_CLKDIV_Pos (20U) 7396 #define FSMC_BTR4_CLKDIV_Msk (0xFUL << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */ 7397 #define FSMC_BTR4_CLKDIV FSMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */ 7398 #define FSMC_BTR4_CLKDIV_0 (0x1UL << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */ 7399 #define FSMC_BTR4_CLKDIV_1 (0x2UL << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */ 7400 #define FSMC_BTR4_CLKDIV_2 (0x4UL << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */ 7401 #define FSMC_BTR4_CLKDIV_3 (0x8UL << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */ 7402 7403 #define FSMC_BTR4_DATLAT_Pos (24U) 7404 #define FSMC_BTR4_DATLAT_Msk (0xFUL << FSMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */ 7405 #define FSMC_BTR4_DATLAT FSMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */ 7406 #define FSMC_BTR4_DATLAT_0 (0x1UL << FSMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */ 7407 #define FSMC_BTR4_DATLAT_1 (0x2UL << FSMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */ 7408 #define FSMC_BTR4_DATLAT_2 (0x4UL << FSMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */ 7409 #define FSMC_BTR4_DATLAT_3 (0x8UL << FSMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */ 7410 7411 #define FSMC_BTR4_ACCMOD_Pos (28U) 7412 #define FSMC_BTR4_ACCMOD_Msk (0x3UL << FSMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */ 7413 #define FSMC_BTR4_ACCMOD FSMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */ 7414 #define FSMC_BTR4_ACCMOD_0 (0x1UL << FSMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */ 7415 #define FSMC_BTR4_ACCMOD_1 (0x2UL << FSMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */ 7416 7417 /****************** Bit definition for FSMC_BWTR1 register ******************/ 7418 #define FSMC_BWTR1_ADDSET_Pos (0U) 7419 #define FSMC_BWTR1_ADDSET_Msk (0xFUL << FSMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */ 7420 #define FSMC_BWTR1_ADDSET FSMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */ 7421 #define FSMC_BWTR1_ADDSET_0 (0x1UL << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */ 7422 #define FSMC_BWTR1_ADDSET_1 (0x2UL << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */ 7423 #define FSMC_BWTR1_ADDSET_2 (0x4UL << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */ 7424 #define FSMC_BWTR1_ADDSET_3 (0x8UL << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */ 7425 7426 #define FSMC_BWTR1_ADDHLD_Pos (4U) 7427 #define FSMC_BWTR1_ADDHLD_Msk (0xFUL << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */ 7428 #define FSMC_BWTR1_ADDHLD FSMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ 7429 #define FSMC_BWTR1_ADDHLD_0 (0x1UL << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */ 7430 #define FSMC_BWTR1_ADDHLD_1 (0x2UL << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */ 7431 #define FSMC_BWTR1_ADDHLD_2 (0x4UL << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */ 7432 #define FSMC_BWTR1_ADDHLD_3 (0x8UL << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */ 7433 7434 #define FSMC_BWTR1_DATAST_Pos (8U) 7435 #define FSMC_BWTR1_DATAST_Msk (0xFFUL << FSMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */ 7436 #define FSMC_BWTR1_DATAST FSMC_BWTR1_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */ 7437 #define FSMC_BWTR1_DATAST_0 (0x01UL << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */ 7438 #define FSMC_BWTR1_DATAST_1 (0x02UL << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */ 7439 #define FSMC_BWTR1_DATAST_2 (0x04UL << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */ 7440 #define FSMC_BWTR1_DATAST_3 (0x08UL << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */ 7441 #define FSMC_BWTR1_DATAST_4 (0x10UL << FSMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */ 7442 #define FSMC_BWTR1_DATAST_5 (0x20UL << FSMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */ 7443 #define FSMC_BWTR1_DATAST_6 (0x40UL << FSMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */ 7444 #define FSMC_BWTR1_DATAST_7 (0x80UL << FSMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */ 7445 7446 #define FSMC_BWTR1_BUSTURN_Pos (16U) 7447 #define FSMC_BWTR1_BUSTURN_Msk (0xFUL << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */ 7448 #define FSMC_BWTR1_BUSTURN FSMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */ 7449 #define FSMC_BWTR1_BUSTURN_0 (0x1UL << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */ 7450 #define FSMC_BWTR1_BUSTURN_1 (0x2UL << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */ 7451 #define FSMC_BWTR1_BUSTURN_2 (0x4UL << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */ 7452 #define FSMC_BWTR1_BUSTURN_3 (0x8UL << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */ 7453 7454 #define FSMC_BWTR1_ACCMOD_Pos (28U) 7455 #define FSMC_BWTR1_ACCMOD_Msk (0x3UL << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */ 7456 #define FSMC_BWTR1_ACCMOD FSMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */ 7457 #define FSMC_BWTR1_ACCMOD_0 (0x1UL << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */ 7458 #define FSMC_BWTR1_ACCMOD_1 (0x2UL << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */ 7459 7460 /****************** Bit definition for FSMC_BWTR2 register ******************/ 7461 #define FSMC_BWTR2_ADDSET_Pos (0U) 7462 #define FSMC_BWTR2_ADDSET_Msk (0xFUL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */ 7463 #define FSMC_BWTR2_ADDSET FSMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */ 7464 #define FSMC_BWTR2_ADDSET_0 (0x1UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */ 7465 #define FSMC_BWTR2_ADDSET_1 (0x2UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */ 7466 #define FSMC_BWTR2_ADDSET_2 (0x4UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */ 7467 #define FSMC_BWTR2_ADDSET_3 (0x8UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */ 7468 7469 #define FSMC_BWTR2_ADDHLD_Pos (4U) 7470 #define FSMC_BWTR2_ADDHLD_Msk (0xFUL << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */ 7471 #define FSMC_BWTR2_ADDHLD FSMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ 7472 #define FSMC_BWTR2_ADDHLD_0 (0x1UL << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */ 7473 #define FSMC_BWTR2_ADDHLD_1 (0x2UL << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */ 7474 #define FSMC_BWTR2_ADDHLD_2 (0x4UL << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */ 7475 #define FSMC_BWTR2_ADDHLD_3 (0x8UL << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */ 7476 7477 #define FSMC_BWTR2_DATAST_Pos (8U) 7478 #define FSMC_BWTR2_DATAST_Msk (0xFFUL << FSMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */ 7479 #define FSMC_BWTR2_DATAST FSMC_BWTR2_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */ 7480 #define FSMC_BWTR2_DATAST_0 (0x01UL << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */ 7481 #define FSMC_BWTR2_DATAST_1 (0x02UL << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */ 7482 #define FSMC_BWTR2_DATAST_2 (0x04UL << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */ 7483 #define FSMC_BWTR2_DATAST_3 (0x08UL << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */ 7484 #define FSMC_BWTR2_DATAST_4 (0x10UL << FSMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */ 7485 #define FSMC_BWTR2_DATAST_5 (0x20UL << FSMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */ 7486 #define FSMC_BWTR2_DATAST_6 (0x40UL << FSMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */ 7487 #define FSMC_BWTR2_DATAST_7 (0x80UL << FSMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */ 7488 7489 #define FSMC_BWTR2_BUSTURN_Pos (16U) 7490 #define FSMC_BWTR2_BUSTURN_Msk (0xFUL << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */ 7491 #define FSMC_BWTR2_BUSTURN FSMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */ 7492 #define FSMC_BWTR2_BUSTURN_0 (0x1UL << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */ 7493 #define FSMC_BWTR2_BUSTURN_1 (0x2UL << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */ 7494 #define FSMC_BWTR2_BUSTURN_2 (0x4UL << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */ 7495 #define FSMC_BWTR2_BUSTURN_3 (0x8UL << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */ 7496 7497 #define FSMC_BWTR2_ACCMOD_Pos (28U) 7498 #define FSMC_BWTR2_ACCMOD_Msk (0x3UL << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */ 7499 #define FSMC_BWTR2_ACCMOD FSMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */ 7500 #define FSMC_BWTR2_ACCMOD_0 (0x1UL << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */ 7501 #define FSMC_BWTR2_ACCMOD_1 (0x2UL << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */ 7502 7503 /****************** Bit definition for FSMC_BWTR3 register ******************/ 7504 #define FSMC_BWTR3_ADDSET_Pos (0U) 7505 #define FSMC_BWTR3_ADDSET_Msk (0xFUL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */ 7506 #define FSMC_BWTR3_ADDSET FSMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */ 7507 #define FSMC_BWTR3_ADDSET_0 (0x1UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */ 7508 #define FSMC_BWTR3_ADDSET_1 (0x2UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */ 7509 #define FSMC_BWTR3_ADDSET_2 (0x4UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */ 7510 #define FSMC_BWTR3_ADDSET_3 (0x8UL << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */ 7511 7512 #define FSMC_BWTR3_ADDHLD_Pos (4U) 7513 #define FSMC_BWTR3_ADDHLD_Msk (0xFUL << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */ 7514 #define FSMC_BWTR3_ADDHLD FSMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ 7515 #define FSMC_BWTR3_ADDHLD_0 (0x1UL << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */ 7516 #define FSMC_BWTR3_ADDHLD_1 (0x2UL << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */ 7517 #define FSMC_BWTR3_ADDHLD_2 (0x4UL << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */ 7518 #define FSMC_BWTR3_ADDHLD_3 (0x8UL << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */ 7519 7520 #define FSMC_BWTR3_DATAST_Pos (8U) 7521 #define FSMC_BWTR3_DATAST_Msk (0xFFUL << FSMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */ 7522 #define FSMC_BWTR3_DATAST FSMC_BWTR3_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */ 7523 #define FSMC_BWTR3_DATAST_0 (0x01UL << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */ 7524 #define FSMC_BWTR3_DATAST_1 (0x02UL << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */ 7525 #define FSMC_BWTR3_DATAST_2 (0x04UL << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */ 7526 #define FSMC_BWTR3_DATAST_3 (0x08UL << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */ 7527 #define FSMC_BWTR3_DATAST_4 (0x10UL << FSMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */ 7528 #define FSMC_BWTR3_DATAST_5 (0x20UL << FSMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */ 7529 #define FSMC_BWTR3_DATAST_6 (0x40UL << FSMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */ 7530 #define FSMC_BWTR3_DATAST_7 (0x80UL << FSMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */ 7531 7532 #define FSMC_BWTR3_BUSTURN_Pos (16U) 7533 #define FSMC_BWTR3_BUSTURN_Msk (0xFUL << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */ 7534 #define FSMC_BWTR3_BUSTURN FSMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */ 7535 #define FSMC_BWTR3_BUSTURN_0 (0x1UL << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */ 7536 #define FSMC_BWTR3_BUSTURN_1 (0x2UL << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */ 7537 #define FSMC_BWTR3_BUSTURN_2 (0x4UL << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */ 7538 #define FSMC_BWTR3_BUSTURN_3 (0x8UL << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */ 7539 7540 #define FSMC_BWTR3_ACCMOD_Pos (28U) 7541 #define FSMC_BWTR3_ACCMOD_Msk (0x3UL << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */ 7542 #define FSMC_BWTR3_ACCMOD FSMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */ 7543 #define FSMC_BWTR3_ACCMOD_0 (0x1UL << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */ 7544 #define FSMC_BWTR3_ACCMOD_1 (0x2UL << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */ 7545 7546 /****************** Bit definition for FSMC_BWTR4 register ******************/ 7547 #define FSMC_BWTR4_ADDSET_Pos (0U) 7548 #define FSMC_BWTR4_ADDSET_Msk (0xFUL << FSMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */ 7549 #define FSMC_BWTR4_ADDSET FSMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */ 7550 #define FSMC_BWTR4_ADDSET_0 (0x1UL << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */ 7551 #define FSMC_BWTR4_ADDSET_1 (0x2UL << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */ 7552 #define FSMC_BWTR4_ADDSET_2 (0x4UL << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */ 7553 #define FSMC_BWTR4_ADDSET_3 (0x8UL << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */ 7554 7555 #define FSMC_BWTR4_ADDHLD_Pos (4U) 7556 #define FSMC_BWTR4_ADDHLD_Msk (0xFUL << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */ 7557 #define FSMC_BWTR4_ADDHLD FSMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ 7558 #define FSMC_BWTR4_ADDHLD_0 (0x1UL << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */ 7559 #define FSMC_BWTR4_ADDHLD_1 (0x2UL << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */ 7560 #define FSMC_BWTR4_ADDHLD_2 (0x4UL << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */ 7561 #define FSMC_BWTR4_ADDHLD_3 (0x8UL << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */ 7562 7563 #define FSMC_BWTR4_DATAST_Pos (8U) 7564 #define FSMC_BWTR4_DATAST_Msk (0xFFUL << FSMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */ 7565 #define FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */ 7566 #define FSMC_BWTR4_DATAST_0 (0x01UL << FSMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */ 7567 #define FSMC_BWTR4_DATAST_1 (0x02UL << FSMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */ 7568 #define FSMC_BWTR4_DATAST_2 (0x04UL << FSMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */ 7569 #define FSMC_BWTR4_DATAST_3 (0x08UL << FSMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */ 7570 #define FSMC_BWTR4_DATAST_4 (0x10UL << FSMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */ 7571 #define FSMC_BWTR4_DATAST_5 (0x20UL << FSMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */ 7572 #define FSMC_BWTR4_DATAST_6 (0x40UL << FSMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */ 7573 #define FSMC_BWTR4_DATAST_7 (0x80UL << FSMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */ 7574 7575 #define FSMC_BWTR4_BUSTURN_Pos (16U) 7576 #define FSMC_BWTR4_BUSTURN_Msk (0xFUL << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */ 7577 #define FSMC_BWTR4_BUSTURN FSMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */ 7578 #define FSMC_BWTR4_BUSTURN_0 (0x1UL << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */ 7579 #define FSMC_BWTR4_BUSTURN_1 (0x2UL << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */ 7580 #define FSMC_BWTR4_BUSTURN_2 (0x4UL << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */ 7581 #define FSMC_BWTR4_BUSTURN_3 (0x8UL << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */ 7582 7583 #define FSMC_BWTR4_ACCMOD_Pos (28U) 7584 #define FSMC_BWTR4_ACCMOD_Msk (0x3UL << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */ 7585 #define FSMC_BWTR4_ACCMOD FSMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */ 7586 #define FSMC_BWTR4_ACCMOD_0 (0x1UL << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */ 7587 #define FSMC_BWTR4_ACCMOD_1 (0x2UL << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */ 7588 7589 /****************** Bit definition for FSMC_PCR2 register *******************/ 7590 #define FSMC_PCR2_PWAITEN_Pos (1U) 7591 #define FSMC_PCR2_PWAITEN_Msk (0x1UL << FSMC_PCR2_PWAITEN_Pos) /*!< 0x00000002 */ 7592 #define FSMC_PCR2_PWAITEN FSMC_PCR2_PWAITEN_Msk /*!<Wait feature enable bit */ 7593 #define FSMC_PCR2_PBKEN_Pos (2U) 7594 #define FSMC_PCR2_PBKEN_Msk (0x1UL << FSMC_PCR2_PBKEN_Pos) /*!< 0x00000004 */ 7595 #define FSMC_PCR2_PBKEN FSMC_PCR2_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */ 7596 #define FSMC_PCR2_PTYP_Pos (3U) 7597 #define FSMC_PCR2_PTYP_Msk (0x1UL << FSMC_PCR2_PTYP_Pos) /*!< 0x00000008 */ 7598 #define FSMC_PCR2_PTYP FSMC_PCR2_PTYP_Msk /*!<Memory type */ 7599 7600 #define FSMC_PCR2_PWID_Pos (4U) 7601 #define FSMC_PCR2_PWID_Msk (0x3UL << FSMC_PCR2_PWID_Pos) /*!< 0x00000030 */ 7602 #define FSMC_PCR2_PWID FSMC_PCR2_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */ 7603 #define FSMC_PCR2_PWID_0 (0x1UL << FSMC_PCR2_PWID_Pos) /*!< 0x00000010 */ 7604 #define FSMC_PCR2_PWID_1 (0x2UL << FSMC_PCR2_PWID_Pos) /*!< 0x00000020 */ 7605 7606 #define FSMC_PCR2_ECCEN_Pos (6U) 7607 #define FSMC_PCR2_ECCEN_Msk (0x1UL << FSMC_PCR2_ECCEN_Pos) /*!< 0x00000040 */ 7608 #define FSMC_PCR2_ECCEN FSMC_PCR2_ECCEN_Msk /*!<ECC computation logic enable bit */ 7609 7610 #define FSMC_PCR2_TCLR_Pos (9U) 7611 #define FSMC_PCR2_TCLR_Msk (0xFUL << FSMC_PCR2_TCLR_Pos) /*!< 0x00001E00 */ 7612 #define FSMC_PCR2_TCLR FSMC_PCR2_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */ 7613 #define FSMC_PCR2_TCLR_0 (0x1UL << FSMC_PCR2_TCLR_Pos) /*!< 0x00000200 */ 7614 #define FSMC_PCR2_TCLR_1 (0x2UL << FSMC_PCR2_TCLR_Pos) /*!< 0x00000400 */ 7615 #define FSMC_PCR2_TCLR_2 (0x4UL << FSMC_PCR2_TCLR_Pos) /*!< 0x00000800 */ 7616 #define FSMC_PCR2_TCLR_3 (0x8UL << FSMC_PCR2_TCLR_Pos) /*!< 0x00001000 */ 7617 7618 #define FSMC_PCR2_TAR_Pos (13U) 7619 #define FSMC_PCR2_TAR_Msk (0xFUL << FSMC_PCR2_TAR_Pos) /*!< 0x0001E000 */ 7620 #define FSMC_PCR2_TAR FSMC_PCR2_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */ 7621 #define FSMC_PCR2_TAR_0 (0x1UL << FSMC_PCR2_TAR_Pos) /*!< 0x00002000 */ 7622 #define FSMC_PCR2_TAR_1 (0x2UL << FSMC_PCR2_TAR_Pos) /*!< 0x00004000 */ 7623 #define FSMC_PCR2_TAR_2 (0x4UL << FSMC_PCR2_TAR_Pos) /*!< 0x00008000 */ 7624 #define FSMC_PCR2_TAR_3 (0x8UL << FSMC_PCR2_TAR_Pos) /*!< 0x00010000 */ 7625 7626 #define FSMC_PCR2_ECCPS_Pos (17U) 7627 #define FSMC_PCR2_ECCPS_Msk (0x7UL << FSMC_PCR2_ECCPS_Pos) /*!< 0x000E0000 */ 7628 #define FSMC_PCR2_ECCPS FSMC_PCR2_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */ 7629 #define FSMC_PCR2_ECCPS_0 (0x1UL << FSMC_PCR2_ECCPS_Pos) /*!< 0x00020000 */ 7630 #define FSMC_PCR2_ECCPS_1 (0x2UL << FSMC_PCR2_ECCPS_Pos) /*!< 0x00040000 */ 7631 #define FSMC_PCR2_ECCPS_2 (0x4UL << FSMC_PCR2_ECCPS_Pos) /*!< 0x00080000 */ 7632 7633 /****************** Bit definition for FSMC_PCR3 register *******************/ 7634 #define FSMC_PCR3_PWAITEN_Pos (1U) 7635 #define FSMC_PCR3_PWAITEN_Msk (0x1UL << FSMC_PCR3_PWAITEN_Pos) /*!< 0x00000002 */ 7636 #define FSMC_PCR3_PWAITEN FSMC_PCR3_PWAITEN_Msk /*!<Wait feature enable bit */ 7637 #define FSMC_PCR3_PBKEN_Pos (2U) 7638 #define FSMC_PCR3_PBKEN_Msk (0x1UL << FSMC_PCR3_PBKEN_Pos) /*!< 0x00000004 */ 7639 #define FSMC_PCR3_PBKEN FSMC_PCR3_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */ 7640 #define FSMC_PCR3_PTYP_Pos (3U) 7641 #define FSMC_PCR3_PTYP_Msk (0x1UL << FSMC_PCR3_PTYP_Pos) /*!< 0x00000008 */ 7642 #define FSMC_PCR3_PTYP FSMC_PCR3_PTYP_Msk /*!<Memory type */ 7643 7644 #define FSMC_PCR3_PWID_Pos (4U) 7645 #define FSMC_PCR3_PWID_Msk (0x3UL << FSMC_PCR3_PWID_Pos) /*!< 0x00000030 */ 7646 #define FSMC_PCR3_PWID FSMC_PCR3_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */ 7647 #define FSMC_PCR3_PWID_0 (0x1UL << FSMC_PCR3_PWID_Pos) /*!< 0x00000010 */ 7648 #define FSMC_PCR3_PWID_1 (0x2UL << FSMC_PCR3_PWID_Pos) /*!< 0x00000020 */ 7649 7650 #define FSMC_PCR3_ECCEN_Pos (6U) 7651 #define FSMC_PCR3_ECCEN_Msk (0x1UL << FSMC_PCR3_ECCEN_Pos) /*!< 0x00000040 */ 7652 #define FSMC_PCR3_ECCEN FSMC_PCR3_ECCEN_Msk /*!<ECC computation logic enable bit */ 7653 7654 #define FSMC_PCR3_TCLR_Pos (9U) 7655 #define FSMC_PCR3_TCLR_Msk (0xFUL << FSMC_PCR3_TCLR_Pos) /*!< 0x00001E00 */ 7656 #define FSMC_PCR3_TCLR FSMC_PCR3_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */ 7657 #define FSMC_PCR3_TCLR_0 (0x1UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00000200 */ 7658 #define FSMC_PCR3_TCLR_1 (0x2UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00000400 */ 7659 #define FSMC_PCR3_TCLR_2 (0x4UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00000800 */ 7660 #define FSMC_PCR3_TCLR_3 (0x8UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00001000 */ 7661 7662 #define FSMC_PCR3_TAR_Pos (13U) 7663 #define FSMC_PCR3_TAR_Msk (0xFUL << FSMC_PCR3_TAR_Pos) /*!< 0x0001E000 */ 7664 #define FSMC_PCR3_TAR FSMC_PCR3_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */ 7665 #define FSMC_PCR3_TAR_0 (0x1UL << FSMC_PCR3_TAR_Pos) /*!< 0x00002000 */ 7666 #define FSMC_PCR3_TAR_1 (0x2UL << FSMC_PCR3_TAR_Pos) /*!< 0x00004000 */ 7667 #define FSMC_PCR3_TAR_2 (0x4UL << FSMC_PCR3_TAR_Pos) /*!< 0x00008000 */ 7668 #define FSMC_PCR3_TAR_3 (0x8UL << FSMC_PCR3_TAR_Pos) /*!< 0x00010000 */ 7669 7670 #define FSMC_PCR3_ECCPS_Pos (17U) 7671 #define FSMC_PCR3_ECCPS_Msk (0x7UL << FSMC_PCR3_ECCPS_Pos) /*!< 0x000E0000 */ 7672 #define FSMC_PCR3_ECCPS FSMC_PCR3_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */ 7673 #define FSMC_PCR3_ECCPS_0 (0x1UL << FSMC_PCR3_ECCPS_Pos) /*!< 0x00020000 */ 7674 #define FSMC_PCR3_ECCPS_1 (0x2UL << FSMC_PCR3_ECCPS_Pos) /*!< 0x00040000 */ 7675 #define FSMC_PCR3_ECCPS_2 (0x4UL << FSMC_PCR3_ECCPS_Pos) /*!< 0x00080000 */ 7676 7677 /****************** Bit definition for FSMC_PCR4 register *******************/ 7678 #define FSMC_PCR4_PWAITEN_Pos (1U) 7679 #define FSMC_PCR4_PWAITEN_Msk (0x1UL << FSMC_PCR4_PWAITEN_Pos) /*!< 0x00000002 */ 7680 #define FSMC_PCR4_PWAITEN FSMC_PCR4_PWAITEN_Msk /*!<Wait feature enable bit */ 7681 #define FSMC_PCR4_PBKEN_Pos (2U) 7682 #define FSMC_PCR4_PBKEN_Msk (0x1UL << FSMC_PCR4_PBKEN_Pos) /*!< 0x00000004 */ 7683 #define FSMC_PCR4_PBKEN FSMC_PCR4_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */ 7684 #define FSMC_PCR4_PTYP_Pos (3U) 7685 #define FSMC_PCR4_PTYP_Msk (0x1UL << FSMC_PCR4_PTYP_Pos) /*!< 0x00000008 */ 7686 #define FSMC_PCR4_PTYP FSMC_PCR4_PTYP_Msk /*!<Memory type */ 7687 7688 #define FSMC_PCR4_PWID_Pos (4U) 7689 #define FSMC_PCR4_PWID_Msk (0x3UL << FSMC_PCR4_PWID_Pos) /*!< 0x00000030 */ 7690 #define FSMC_PCR4_PWID FSMC_PCR4_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */ 7691 #define FSMC_PCR4_PWID_0 (0x1UL << FSMC_PCR4_PWID_Pos) /*!< 0x00000010 */ 7692 #define FSMC_PCR4_PWID_1 (0x2UL << FSMC_PCR4_PWID_Pos) /*!< 0x00000020 */ 7693 7694 #define FSMC_PCR4_ECCEN_Pos (6U) 7695 #define FSMC_PCR4_ECCEN_Msk (0x1UL << FSMC_PCR4_ECCEN_Pos) /*!< 0x00000040 */ 7696 #define FSMC_PCR4_ECCEN FSMC_PCR4_ECCEN_Msk /*!<ECC computation logic enable bit */ 7697 7698 #define FSMC_PCR4_TCLR_Pos (9U) 7699 #define FSMC_PCR4_TCLR_Msk (0xFUL << FSMC_PCR4_TCLR_Pos) /*!< 0x00001E00 */ 7700 #define FSMC_PCR4_TCLR FSMC_PCR4_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */ 7701 #define FSMC_PCR4_TCLR_0 (0x1UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00000200 */ 7702 #define FSMC_PCR4_TCLR_1 (0x2UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00000400 */ 7703 #define FSMC_PCR4_TCLR_2 (0x4UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00000800 */ 7704 #define FSMC_PCR4_TCLR_3 (0x8UL << FSMC_PCR4_TCLR_Pos) /*!< 0x00001000 */ 7705 7706 #define FSMC_PCR4_TAR_Pos (13U) 7707 #define FSMC_PCR4_TAR_Msk (0xFUL << FSMC_PCR4_TAR_Pos) /*!< 0x0001E000 */ 7708 #define FSMC_PCR4_TAR FSMC_PCR4_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */ 7709 #define FSMC_PCR4_TAR_0 (0x1UL << FSMC_PCR4_TAR_Pos) /*!< 0x00002000 */ 7710 #define FSMC_PCR4_TAR_1 (0x2UL << FSMC_PCR4_TAR_Pos) /*!< 0x00004000 */ 7711 #define FSMC_PCR4_TAR_2 (0x4UL << FSMC_PCR4_TAR_Pos) /*!< 0x00008000 */ 7712 #define FSMC_PCR4_TAR_3 (0x8UL << FSMC_PCR4_TAR_Pos) /*!< 0x00010000 */ 7713 7714 #define FSMC_PCR4_ECCPS_Pos (17U) 7715 #define FSMC_PCR4_ECCPS_Msk (0x7UL << FSMC_PCR4_ECCPS_Pos) /*!< 0x000E0000 */ 7716 #define FSMC_PCR4_ECCPS FSMC_PCR4_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */ 7717 #define FSMC_PCR4_ECCPS_0 (0x1UL << FSMC_PCR4_ECCPS_Pos) /*!< 0x00020000 */ 7718 #define FSMC_PCR4_ECCPS_1 (0x2UL << FSMC_PCR4_ECCPS_Pos) /*!< 0x00040000 */ 7719 #define FSMC_PCR4_ECCPS_2 (0x4UL << FSMC_PCR4_ECCPS_Pos) /*!< 0x00080000 */ 7720 7721 /******************* Bit definition for FSMC_SR2 register *******************/ 7722 #define FSMC_SR2_IRS_Pos (0U) 7723 #define FSMC_SR2_IRS_Msk (0x1UL << FSMC_SR2_IRS_Pos) /*!< 0x00000001 */ 7724 #define FSMC_SR2_IRS FSMC_SR2_IRS_Msk /*!<Interrupt Rising Edge status */ 7725 #define FSMC_SR2_ILS_Pos (1U) 7726 #define FSMC_SR2_ILS_Msk (0x1UL << FSMC_SR2_ILS_Pos) /*!< 0x00000002 */ 7727 #define FSMC_SR2_ILS FSMC_SR2_ILS_Msk /*!<Interrupt Level status */ 7728 #define FSMC_SR2_IFS_Pos (2U) 7729 #define FSMC_SR2_IFS_Msk (0x1UL << FSMC_SR2_IFS_Pos) /*!< 0x00000004 */ 7730 #define FSMC_SR2_IFS FSMC_SR2_IFS_Msk /*!<Interrupt Falling Edge status */ 7731 #define FSMC_SR2_IREN_Pos (3U) 7732 #define FSMC_SR2_IREN_Msk (0x1UL << FSMC_SR2_IREN_Pos) /*!< 0x00000008 */ 7733 #define FSMC_SR2_IREN FSMC_SR2_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */ 7734 #define FSMC_SR2_ILEN_Pos (4U) 7735 #define FSMC_SR2_ILEN_Msk (0x1UL << FSMC_SR2_ILEN_Pos) /*!< 0x00000010 */ 7736 #define FSMC_SR2_ILEN FSMC_SR2_ILEN_Msk /*!<Interrupt Level detection Enable bit */ 7737 #define FSMC_SR2_IFEN_Pos (5U) 7738 #define FSMC_SR2_IFEN_Msk (0x1UL << FSMC_SR2_IFEN_Pos) /*!< 0x00000020 */ 7739 #define FSMC_SR2_IFEN FSMC_SR2_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */ 7740 #define FSMC_SR2_FEMPT_Pos (6U) 7741 #define FSMC_SR2_FEMPT_Msk (0x1UL << FSMC_SR2_FEMPT_Pos) /*!< 0x00000040 */ 7742 #define FSMC_SR2_FEMPT FSMC_SR2_FEMPT_Msk /*!<FIFO empty */ 7743 7744 /******************* Bit definition for FSMC_SR3 register *******************/ 7745 #define FSMC_SR3_IRS_Pos (0U) 7746 #define FSMC_SR3_IRS_Msk (0x1UL << FSMC_SR3_IRS_Pos) /*!< 0x00000001 */ 7747 #define FSMC_SR3_IRS FSMC_SR3_IRS_Msk /*!<Interrupt Rising Edge status */ 7748 #define FSMC_SR3_ILS_Pos (1U) 7749 #define FSMC_SR3_ILS_Msk (0x1UL << FSMC_SR3_ILS_Pos) /*!< 0x00000002 */ 7750 #define FSMC_SR3_ILS FSMC_SR3_ILS_Msk /*!<Interrupt Level status */ 7751 #define FSMC_SR3_IFS_Pos (2U) 7752 #define FSMC_SR3_IFS_Msk (0x1UL << FSMC_SR3_IFS_Pos) /*!< 0x00000004 */ 7753 #define FSMC_SR3_IFS FSMC_SR3_IFS_Msk /*!<Interrupt Falling Edge status */ 7754 #define FSMC_SR3_IREN_Pos (3U) 7755 #define FSMC_SR3_IREN_Msk (0x1UL << FSMC_SR3_IREN_Pos) /*!< 0x00000008 */ 7756 #define FSMC_SR3_IREN FSMC_SR3_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */ 7757 #define FSMC_SR3_ILEN_Pos (4U) 7758 #define FSMC_SR3_ILEN_Msk (0x1UL << FSMC_SR3_ILEN_Pos) /*!< 0x00000010 */ 7759 #define FSMC_SR3_ILEN FSMC_SR3_ILEN_Msk /*!<Interrupt Level detection Enable bit */ 7760 #define FSMC_SR3_IFEN_Pos (5U) 7761 #define FSMC_SR3_IFEN_Msk (0x1UL << FSMC_SR3_IFEN_Pos) /*!< 0x00000020 */ 7762 #define FSMC_SR3_IFEN FSMC_SR3_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */ 7763 #define FSMC_SR3_FEMPT_Pos (6U) 7764 #define FSMC_SR3_FEMPT_Msk (0x1UL << FSMC_SR3_FEMPT_Pos) /*!< 0x00000040 */ 7765 #define FSMC_SR3_FEMPT FSMC_SR3_FEMPT_Msk /*!<FIFO empty */ 7766 7767 /******************* Bit definition for FSMC_SR4 register *******************/ 7768 #define FSMC_SR4_IRS_Pos (0U) 7769 #define FSMC_SR4_IRS_Msk (0x1UL << FSMC_SR4_IRS_Pos) /*!< 0x00000001 */ 7770 #define FSMC_SR4_IRS FSMC_SR4_IRS_Msk /*!<Interrupt Rising Edge status */ 7771 #define FSMC_SR4_ILS_Pos (1U) 7772 #define FSMC_SR4_ILS_Msk (0x1UL << FSMC_SR4_ILS_Pos) /*!< 0x00000002 */ 7773 #define FSMC_SR4_ILS FSMC_SR4_ILS_Msk /*!<Interrupt Level status */ 7774 #define FSMC_SR4_IFS_Pos (2U) 7775 #define FSMC_SR4_IFS_Msk (0x1UL << FSMC_SR4_IFS_Pos) /*!< 0x00000004 */ 7776 #define FSMC_SR4_IFS FSMC_SR4_IFS_Msk /*!<Interrupt Falling Edge status */ 7777 #define FSMC_SR4_IREN_Pos (3U) 7778 #define FSMC_SR4_IREN_Msk (0x1UL << FSMC_SR4_IREN_Pos) /*!< 0x00000008 */ 7779 #define FSMC_SR4_IREN FSMC_SR4_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */ 7780 #define FSMC_SR4_ILEN_Pos (4U) 7781 #define FSMC_SR4_ILEN_Msk (0x1UL << FSMC_SR4_ILEN_Pos) /*!< 0x00000010 */ 7782 #define FSMC_SR4_ILEN FSMC_SR4_ILEN_Msk /*!<Interrupt Level detection Enable bit */ 7783 #define FSMC_SR4_IFEN_Pos (5U) 7784 #define FSMC_SR4_IFEN_Msk (0x1UL << FSMC_SR4_IFEN_Pos) /*!< 0x00000020 */ 7785 #define FSMC_SR4_IFEN FSMC_SR4_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */ 7786 #define FSMC_SR4_FEMPT_Pos (6U) 7787 #define FSMC_SR4_FEMPT_Msk (0x1UL << FSMC_SR4_FEMPT_Pos) /*!< 0x00000040 */ 7788 #define FSMC_SR4_FEMPT FSMC_SR4_FEMPT_Msk /*!<FIFO empty */ 7789 7790 /****************** Bit definition for FSMC_PMEM2 register ******************/ 7791 #define FSMC_PMEM2_MEMSET2_Pos (0U) 7792 #define FSMC_PMEM2_MEMSET2_Msk (0xFFUL << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x000000FF */ 7793 #define FSMC_PMEM2_MEMSET2 FSMC_PMEM2_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */ 7794 #define FSMC_PMEM2_MEMSET2_0 (0x01UL << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000001 */ 7795 #define FSMC_PMEM2_MEMSET2_1 (0x02UL << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000002 */ 7796 #define FSMC_PMEM2_MEMSET2_2 (0x04UL << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000004 */ 7797 #define FSMC_PMEM2_MEMSET2_3 (0x08UL << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000008 */ 7798 #define FSMC_PMEM2_MEMSET2_4 (0x10UL << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000010 */ 7799 #define FSMC_PMEM2_MEMSET2_5 (0x20UL << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000020 */ 7800 #define FSMC_PMEM2_MEMSET2_6 (0x40UL << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000040 */ 7801 #define FSMC_PMEM2_MEMSET2_7 (0x80UL << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000080 */ 7802 7803 #define FSMC_PMEM2_MEMWAIT2_Pos (8U) 7804 #define FSMC_PMEM2_MEMWAIT2_Msk (0xFFUL << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x0000FF00 */ 7805 #define FSMC_PMEM2_MEMWAIT2 FSMC_PMEM2_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */ 7806 #define FSMC_PMEM2_MEMWAIT2_0 (0x01UL << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000100 */ 7807 #define FSMC_PMEM2_MEMWAIT2_1 (0x02UL << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000200 */ 7808 #define FSMC_PMEM2_MEMWAIT2_2 (0x04UL << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000400 */ 7809 #define FSMC_PMEM2_MEMWAIT2_3 (0x08UL << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000800 */ 7810 #define FSMC_PMEM2_MEMWAIT2_4 (0x10UL << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00001000 */ 7811 #define FSMC_PMEM2_MEMWAIT2_5 (0x20UL << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00002000 */ 7812 #define FSMC_PMEM2_MEMWAIT2_6 (0x40UL << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00004000 */ 7813 #define FSMC_PMEM2_MEMWAIT2_7 (0x80UL << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00008000 */ 7814 7815 #define FSMC_PMEM2_MEMHOLD2_Pos (16U) 7816 #define FSMC_PMEM2_MEMHOLD2_Msk (0xFFUL << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00FF0000 */ 7817 #define FSMC_PMEM2_MEMHOLD2 FSMC_PMEM2_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */ 7818 #define FSMC_PMEM2_MEMHOLD2_0 (0x01UL << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00010000 */ 7819 #define FSMC_PMEM2_MEMHOLD2_1 (0x02UL << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00020000 */ 7820 #define FSMC_PMEM2_MEMHOLD2_2 (0x04UL << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00040000 */ 7821 #define FSMC_PMEM2_MEMHOLD2_3 (0x08UL << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00080000 */ 7822 #define FSMC_PMEM2_MEMHOLD2_4 (0x10UL << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00100000 */ 7823 #define FSMC_PMEM2_MEMHOLD2_5 (0x20UL << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00200000 */ 7824 #define FSMC_PMEM2_MEMHOLD2_6 (0x40UL << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00400000 */ 7825 #define FSMC_PMEM2_MEMHOLD2_7 (0x80UL << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00800000 */ 7826 7827 #define FSMC_PMEM2_MEMHIZ2_Pos (24U) 7828 #define FSMC_PMEM2_MEMHIZ2_Msk (0xFFUL << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0xFF000000 */ 7829 #define FSMC_PMEM2_MEMHIZ2 FSMC_PMEM2_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ 7830 #define FSMC_PMEM2_MEMHIZ2_0 (0x01UL << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x01000000 */ 7831 #define FSMC_PMEM2_MEMHIZ2_1 (0x02UL << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x02000000 */ 7832 #define FSMC_PMEM2_MEMHIZ2_2 (0x04UL << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x04000000 */ 7833 #define FSMC_PMEM2_MEMHIZ2_3 (0x08UL << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x08000000 */ 7834 #define FSMC_PMEM2_MEMHIZ2_4 (0x10UL << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x10000000 */ 7835 #define FSMC_PMEM2_MEMHIZ2_5 (0x20UL << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x20000000 */ 7836 #define FSMC_PMEM2_MEMHIZ2_6 (0x40UL << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x40000000 */ 7837 #define FSMC_PMEM2_MEMHIZ2_7 (0x80UL << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x80000000 */ 7838 7839 /****************** Bit definition for FSMC_PMEM3 register ******************/ 7840 #define FSMC_PMEM3_MEMSET3_Pos (0U) 7841 #define FSMC_PMEM3_MEMSET3_Msk (0xFFUL << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x000000FF */ 7842 #define FSMC_PMEM3_MEMSET3 FSMC_PMEM3_MEMSET3_Msk /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */ 7843 #define FSMC_PMEM3_MEMSET3_0 (0x01UL << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000001 */ 7844 #define FSMC_PMEM3_MEMSET3_1 (0x02UL << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000002 */ 7845 #define FSMC_PMEM3_MEMSET3_2 (0x04UL << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000004 */ 7846 #define FSMC_PMEM3_MEMSET3_3 (0x08UL << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000008 */ 7847 #define FSMC_PMEM3_MEMSET3_4 (0x10UL << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000010 */ 7848 #define FSMC_PMEM3_MEMSET3_5 (0x20UL << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000020 */ 7849 #define FSMC_PMEM3_MEMSET3_6 (0x40UL << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000040 */ 7850 #define FSMC_PMEM3_MEMSET3_7 (0x80UL << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000080 */ 7851 7852 #define FSMC_PMEM3_MEMWAIT3_Pos (8U) 7853 #define FSMC_PMEM3_MEMWAIT3_Msk (0xFFUL << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x0000FF00 */ 7854 #define FSMC_PMEM3_MEMWAIT3 FSMC_PMEM3_MEMWAIT3_Msk /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */ 7855 #define FSMC_PMEM3_MEMWAIT3_0 (0x01UL << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000100 */ 7856 #define FSMC_PMEM3_MEMWAIT3_1 (0x02UL << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000200 */ 7857 #define FSMC_PMEM3_MEMWAIT3_2 (0x04UL << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000400 */ 7858 #define FSMC_PMEM3_MEMWAIT3_3 (0x08UL << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000800 */ 7859 #define FSMC_PMEM3_MEMWAIT3_4 (0x10UL << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00001000 */ 7860 #define FSMC_PMEM3_MEMWAIT3_5 (0x20UL << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00002000 */ 7861 #define FSMC_PMEM3_MEMWAIT3_6 (0x40UL << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00004000 */ 7862 #define FSMC_PMEM3_MEMWAIT3_7 (0x80UL << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00008000 */ 7863 7864 #define FSMC_PMEM3_MEMHOLD3_Pos (16U) 7865 #define FSMC_PMEM3_MEMHOLD3_Msk (0xFFUL << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00FF0000 */ 7866 #define FSMC_PMEM3_MEMHOLD3 FSMC_PMEM3_MEMHOLD3_Msk /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */ 7867 #define FSMC_PMEM3_MEMHOLD3_0 (0x01UL << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00010000 */ 7868 #define FSMC_PMEM3_MEMHOLD3_1 (0x02UL << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00020000 */ 7869 #define FSMC_PMEM3_MEMHOLD3_2 (0x04UL << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00040000 */ 7870 #define FSMC_PMEM3_MEMHOLD3_3 (0x08UL << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00080000 */ 7871 #define FSMC_PMEM3_MEMHOLD3_4 (0x10UL << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00100000 */ 7872 #define FSMC_PMEM3_MEMHOLD3_5 (0x20UL << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00200000 */ 7873 #define FSMC_PMEM3_MEMHOLD3_6 (0x40UL << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00400000 */ 7874 #define FSMC_PMEM3_MEMHOLD3_7 (0x80UL << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00800000 */ 7875 7876 #define FSMC_PMEM3_MEMHIZ3_Pos (24U) 7877 #define FSMC_PMEM3_MEMHIZ3_Msk (0xFFUL << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0xFF000000 */ 7878 #define FSMC_PMEM3_MEMHIZ3 FSMC_PMEM3_MEMHIZ3_Msk /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ 7879 #define FSMC_PMEM3_MEMHIZ3_0 (0x01UL << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x01000000 */ 7880 #define FSMC_PMEM3_MEMHIZ3_1 (0x02UL << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x02000000 */ 7881 #define FSMC_PMEM3_MEMHIZ3_2 (0x04UL << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x04000000 */ 7882 #define FSMC_PMEM3_MEMHIZ3_3 (0x08UL << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x08000000 */ 7883 #define FSMC_PMEM3_MEMHIZ3_4 (0x10UL << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x10000000 */ 7884 #define FSMC_PMEM3_MEMHIZ3_5 (0x20UL << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x20000000 */ 7885 #define FSMC_PMEM3_MEMHIZ3_6 (0x40UL << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x40000000 */ 7886 #define FSMC_PMEM3_MEMHIZ3_7 (0x80UL << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x80000000 */ 7887 7888 /****************** Bit definition for FSMC_PMEM4 register ******************/ 7889 #define FSMC_PMEM4_MEMSET4_Pos (0U) 7890 #define FSMC_PMEM4_MEMSET4_Msk (0xFFUL << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x000000FF */ 7891 #define FSMC_PMEM4_MEMSET4 FSMC_PMEM4_MEMSET4_Msk /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */ 7892 #define FSMC_PMEM4_MEMSET4_0 (0x01UL << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000001 */ 7893 #define FSMC_PMEM4_MEMSET4_1 (0x02UL << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000002 */ 7894 #define FSMC_PMEM4_MEMSET4_2 (0x04UL << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000004 */ 7895 #define FSMC_PMEM4_MEMSET4_3 (0x08UL << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000008 */ 7896 #define FSMC_PMEM4_MEMSET4_4 (0x10UL << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000010 */ 7897 #define FSMC_PMEM4_MEMSET4_5 (0x20UL << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000020 */ 7898 #define FSMC_PMEM4_MEMSET4_6 (0x40UL << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000040 */ 7899 #define FSMC_PMEM4_MEMSET4_7 (0x80UL << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000080 */ 7900 7901 #define FSMC_PMEM4_MEMWAIT4_Pos (8U) 7902 #define FSMC_PMEM4_MEMWAIT4_Msk (0xFFUL << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x0000FF00 */ 7903 #define FSMC_PMEM4_MEMWAIT4 FSMC_PMEM4_MEMWAIT4_Msk /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */ 7904 #define FSMC_PMEM4_MEMWAIT4_0 (0x01UL << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000100 */ 7905 #define FSMC_PMEM4_MEMWAIT4_1 (0x02UL << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000200 */ 7906 #define FSMC_PMEM4_MEMWAIT4_2 (0x04UL << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000400 */ 7907 #define FSMC_PMEM4_MEMWAIT4_3 (0x08UL << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000800 */ 7908 #define FSMC_PMEM4_MEMWAIT4_4 (0x10UL << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00001000 */ 7909 #define FSMC_PMEM4_MEMWAIT4_5 (0x20UL << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00002000 */ 7910 #define FSMC_PMEM4_MEMWAIT4_6 (0x40UL << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00004000 */ 7911 #define FSMC_PMEM4_MEMWAIT4_7 (0x80UL << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00008000 */ 7912 7913 #define FSMC_PMEM4_MEMHOLD4_Pos (16U) 7914 #define FSMC_PMEM4_MEMHOLD4_Msk (0xFFUL << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00FF0000 */ 7915 #define FSMC_PMEM4_MEMHOLD4 FSMC_PMEM4_MEMHOLD4_Msk /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */ 7916 #define FSMC_PMEM4_MEMHOLD4_0 (0x01UL << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00010000 */ 7917 #define FSMC_PMEM4_MEMHOLD4_1 (0x02UL << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00020000 */ 7918 #define FSMC_PMEM4_MEMHOLD4_2 (0x04UL << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00040000 */ 7919 #define FSMC_PMEM4_MEMHOLD4_3 (0x08UL << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00080000 */ 7920 #define FSMC_PMEM4_MEMHOLD4_4 (0x10UL << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00100000 */ 7921 #define FSMC_PMEM4_MEMHOLD4_5 (0x20UL << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00200000 */ 7922 #define FSMC_PMEM4_MEMHOLD4_6 (0x40UL << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00400000 */ 7923 #define FSMC_PMEM4_MEMHOLD4_7 (0x80UL << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00800000 */ 7924 7925 #define FSMC_PMEM4_MEMHIZ4_Pos (24U) 7926 #define FSMC_PMEM4_MEMHIZ4_Msk (0xFFUL << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0xFF000000 */ 7927 #define FSMC_PMEM4_MEMHIZ4 FSMC_PMEM4_MEMHIZ4_Msk /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */ 7928 #define FSMC_PMEM4_MEMHIZ4_0 (0x01UL << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x01000000 */ 7929 #define FSMC_PMEM4_MEMHIZ4_1 (0x02UL << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x02000000 */ 7930 #define FSMC_PMEM4_MEMHIZ4_2 (0x04UL << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x04000000 */ 7931 #define FSMC_PMEM4_MEMHIZ4_3 (0x08UL << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x08000000 */ 7932 #define FSMC_PMEM4_MEMHIZ4_4 (0x10UL << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x10000000 */ 7933 #define FSMC_PMEM4_MEMHIZ4_5 (0x20UL << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x20000000 */ 7934 #define FSMC_PMEM4_MEMHIZ4_6 (0x40UL << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x40000000 */ 7935 #define FSMC_PMEM4_MEMHIZ4_7 (0x80UL << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x80000000 */ 7936 7937 /****************** Bit definition for FSMC_PATT2 register ******************/ 7938 #define FSMC_PATT2_ATTSET2_Pos (0U) 7939 #define FSMC_PATT2_ATTSET2_Msk (0xFFUL << FSMC_PATT2_ATTSET2_Pos) /*!< 0x000000FF */ 7940 #define FSMC_PATT2_ATTSET2 FSMC_PATT2_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */ 7941 #define FSMC_PATT2_ATTSET2_0 (0x01UL << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000001 */ 7942 #define FSMC_PATT2_ATTSET2_1 (0x02UL << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000002 */ 7943 #define FSMC_PATT2_ATTSET2_2 (0x04UL << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000004 */ 7944 #define FSMC_PATT2_ATTSET2_3 (0x08UL << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000008 */ 7945 #define FSMC_PATT2_ATTSET2_4 (0x10UL << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000010 */ 7946 #define FSMC_PATT2_ATTSET2_5 (0x20UL << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000020 */ 7947 #define FSMC_PATT2_ATTSET2_6 (0x40UL << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000040 */ 7948 #define FSMC_PATT2_ATTSET2_7 (0x80UL << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000080 */ 7949 7950 #define FSMC_PATT2_ATTWAIT2_Pos (8U) 7951 #define FSMC_PATT2_ATTWAIT2_Msk (0xFFUL << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x0000FF00 */ 7952 #define FSMC_PATT2_ATTWAIT2 FSMC_PATT2_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ 7953 #define FSMC_PATT2_ATTWAIT2_0 (0x01UL << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000100 */ 7954 #define FSMC_PATT2_ATTWAIT2_1 (0x02UL << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000200 */ 7955 #define FSMC_PATT2_ATTWAIT2_2 (0x04UL << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000400 */ 7956 #define FSMC_PATT2_ATTWAIT2_3 (0x08UL << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000800 */ 7957 #define FSMC_PATT2_ATTWAIT2_4 (0x10UL << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00001000 */ 7958 #define FSMC_PATT2_ATTWAIT2_5 (0x20UL << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00002000 */ 7959 #define FSMC_PATT2_ATTWAIT2_6 (0x40UL << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00004000 */ 7960 #define FSMC_PATT2_ATTWAIT2_7 (0x80UL << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00008000 */ 7961 7962 #define FSMC_PATT2_ATTHOLD2_Pos (16U) 7963 #define FSMC_PATT2_ATTHOLD2_Msk (0xFFUL << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00FF0000 */ 7964 #define FSMC_PATT2_ATTHOLD2 FSMC_PATT2_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ 7965 #define FSMC_PATT2_ATTHOLD2_0 (0x01UL << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00010000 */ 7966 #define FSMC_PATT2_ATTHOLD2_1 (0x02UL << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00020000 */ 7967 #define FSMC_PATT2_ATTHOLD2_2 (0x04UL << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00040000 */ 7968 #define FSMC_PATT2_ATTHOLD2_3 (0x08UL << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00080000 */ 7969 #define FSMC_PATT2_ATTHOLD2_4 (0x10UL << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00100000 */ 7970 #define FSMC_PATT2_ATTHOLD2_5 (0x20UL << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00200000 */ 7971 #define FSMC_PATT2_ATTHOLD2_6 (0x40UL << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00400000 */ 7972 #define FSMC_PATT2_ATTHOLD2_7 (0x80UL << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00800000 */ 7973 7974 #define FSMC_PATT2_ATTHIZ2_Pos (24U) 7975 #define FSMC_PATT2_ATTHIZ2_Msk (0xFFUL << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0xFF000000 */ 7976 #define FSMC_PATT2_ATTHIZ2 FSMC_PATT2_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ 7977 #define FSMC_PATT2_ATTHIZ2_0 (0x01UL << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x01000000 */ 7978 #define FSMC_PATT2_ATTHIZ2_1 (0x02UL << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x02000000 */ 7979 #define FSMC_PATT2_ATTHIZ2_2 (0x04UL << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x04000000 */ 7980 #define FSMC_PATT2_ATTHIZ2_3 (0x08UL << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x08000000 */ 7981 #define FSMC_PATT2_ATTHIZ2_4 (0x10UL << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x10000000 */ 7982 #define FSMC_PATT2_ATTHIZ2_5 (0x20UL << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x20000000 */ 7983 #define FSMC_PATT2_ATTHIZ2_6 (0x40UL << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x40000000 */ 7984 #define FSMC_PATT2_ATTHIZ2_7 (0x80UL << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x80000000 */ 7985 7986 /****************** Bit definition for FSMC_PATT3 register ******************/ 7987 #define FSMC_PATT3_ATTSET3_Pos (0U) 7988 #define FSMC_PATT3_ATTSET3_Msk (0xFFUL << FSMC_PATT3_ATTSET3_Pos) /*!< 0x000000FF */ 7989 #define FSMC_PATT3_ATTSET3 FSMC_PATT3_ATTSET3_Msk /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */ 7990 #define FSMC_PATT3_ATTSET3_0 (0x01UL << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000001 */ 7991 #define FSMC_PATT3_ATTSET3_1 (0x02UL << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000002 */ 7992 #define FSMC_PATT3_ATTSET3_2 (0x04UL << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000004 */ 7993 #define FSMC_PATT3_ATTSET3_3 (0x08UL << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000008 */ 7994 #define FSMC_PATT3_ATTSET3_4 (0x10UL << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000010 */ 7995 #define FSMC_PATT3_ATTSET3_5 (0x20UL << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000020 */ 7996 #define FSMC_PATT3_ATTSET3_6 (0x40UL << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000040 */ 7997 #define FSMC_PATT3_ATTSET3_7 (0x80UL << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000080 */ 7998 7999 #define FSMC_PATT3_ATTWAIT3_Pos (8U) 8000 #define FSMC_PATT3_ATTWAIT3_Msk (0xFFUL << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x0000FF00 */ 8001 #define FSMC_PATT3_ATTWAIT3 FSMC_PATT3_ATTWAIT3_Msk /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ 8002 #define FSMC_PATT3_ATTWAIT3_0 (0x01UL << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000100 */ 8003 #define FSMC_PATT3_ATTWAIT3_1 (0x02UL << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000200 */ 8004 #define FSMC_PATT3_ATTWAIT3_2 (0x04UL << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000400 */ 8005 #define FSMC_PATT3_ATTWAIT3_3 (0x08UL << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000800 */ 8006 #define FSMC_PATT3_ATTWAIT3_4 (0x10UL << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00001000 */ 8007 #define FSMC_PATT3_ATTWAIT3_5 (0x20UL << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00002000 */ 8008 #define FSMC_PATT3_ATTWAIT3_6 (0x40UL << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00004000 */ 8009 #define FSMC_PATT3_ATTWAIT3_7 (0x80UL << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00008000 */ 8010 8011 #define FSMC_PATT3_ATTHOLD3_Pos (16U) 8012 #define FSMC_PATT3_ATTHOLD3_Msk (0xFFUL << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00FF0000 */ 8013 #define FSMC_PATT3_ATTHOLD3 FSMC_PATT3_ATTHOLD3_Msk /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ 8014 #define FSMC_PATT3_ATTHOLD3_0 (0x01UL << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00010000 */ 8015 #define FSMC_PATT3_ATTHOLD3_1 (0x02UL << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00020000 */ 8016 #define FSMC_PATT3_ATTHOLD3_2 (0x04UL << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00040000 */ 8017 #define FSMC_PATT3_ATTHOLD3_3 (0x08UL << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00080000 */ 8018 #define FSMC_PATT3_ATTHOLD3_4 (0x10UL << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00100000 */ 8019 #define FSMC_PATT3_ATTHOLD3_5 (0x20UL << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00200000 */ 8020 #define FSMC_PATT3_ATTHOLD3_6 (0x40UL << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00400000 */ 8021 #define FSMC_PATT3_ATTHOLD3_7 (0x80UL << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00800000 */ 8022 8023 #define FSMC_PATT3_ATTHIZ3_Pos (24U) 8024 #define FSMC_PATT3_ATTHIZ3_Msk (0xFFUL << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0xFF000000 */ 8025 #define FSMC_PATT3_ATTHIZ3 FSMC_PATT3_ATTHIZ3_Msk /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ 8026 #define FSMC_PATT3_ATTHIZ3_0 (0x01UL << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x01000000 */ 8027 #define FSMC_PATT3_ATTHIZ3_1 (0x02UL << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x02000000 */ 8028 #define FSMC_PATT3_ATTHIZ3_2 (0x04UL << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x04000000 */ 8029 #define FSMC_PATT3_ATTHIZ3_3 (0x08UL << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x08000000 */ 8030 #define FSMC_PATT3_ATTHIZ3_4 (0x10UL << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x10000000 */ 8031 #define FSMC_PATT3_ATTHIZ3_5 (0x20UL << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x20000000 */ 8032 #define FSMC_PATT3_ATTHIZ3_6 (0x40UL << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x40000000 */ 8033 #define FSMC_PATT3_ATTHIZ3_7 (0x80UL << FSMC_PATT3_ATTHIZ3_Pos) /*!< 0x80000000 */ 8034 8035 /****************** Bit definition for FSMC_PATT4 register ******************/ 8036 #define FSMC_PATT4_ATTSET4_Pos (0U) 8037 #define FSMC_PATT4_ATTSET4_Msk (0xFFUL << FSMC_PATT4_ATTSET4_Pos) /*!< 0x000000FF */ 8038 #define FSMC_PATT4_ATTSET4 FSMC_PATT4_ATTSET4_Msk /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */ 8039 #define FSMC_PATT4_ATTSET4_0 (0x01UL << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000001 */ 8040 #define FSMC_PATT4_ATTSET4_1 (0x02UL << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000002 */ 8041 #define FSMC_PATT4_ATTSET4_2 (0x04UL << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000004 */ 8042 #define FSMC_PATT4_ATTSET4_3 (0x08UL << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000008 */ 8043 #define FSMC_PATT4_ATTSET4_4 (0x10UL << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000010 */ 8044 #define FSMC_PATT4_ATTSET4_5 (0x20UL << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000020 */ 8045 #define FSMC_PATT4_ATTSET4_6 (0x40UL << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000040 */ 8046 #define FSMC_PATT4_ATTSET4_7 (0x80UL << FSMC_PATT4_ATTSET4_Pos) /*!< 0x00000080 */ 8047 8048 #define FSMC_PATT4_ATTWAIT4_Pos (8U) 8049 #define FSMC_PATT4_ATTWAIT4_Msk (0xFFUL << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x0000FF00 */ 8050 #define FSMC_PATT4_ATTWAIT4 FSMC_PATT4_ATTWAIT4_Msk /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */ 8051 #define FSMC_PATT4_ATTWAIT4_0 (0x01UL << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000100 */ 8052 #define FSMC_PATT4_ATTWAIT4_1 (0x02UL << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000200 */ 8053 #define FSMC_PATT4_ATTWAIT4_2 (0x04UL << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000400 */ 8054 #define FSMC_PATT4_ATTWAIT4_3 (0x08UL << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000800 */ 8055 #define FSMC_PATT4_ATTWAIT4_4 (0x10UL << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00001000 */ 8056 #define FSMC_PATT4_ATTWAIT4_5 (0x20UL << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00002000 */ 8057 #define FSMC_PATT4_ATTWAIT4_6 (0x40UL << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00004000 */ 8058 #define FSMC_PATT4_ATTWAIT4_7 (0x80UL << FSMC_PATT4_ATTWAIT4_Pos) /*!< 0x00008000 */ 8059 8060 #define FSMC_PATT4_ATTHOLD4_Pos (16U) 8061 #define FSMC_PATT4_ATTHOLD4_Msk (0xFFUL << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00FF0000 */ 8062 #define FSMC_PATT4_ATTHOLD4 FSMC_PATT4_ATTHOLD4_Msk /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */ 8063 #define FSMC_PATT4_ATTHOLD4_0 (0x01UL << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00010000 */ 8064 #define FSMC_PATT4_ATTHOLD4_1 (0x02UL << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00020000 */ 8065 #define FSMC_PATT4_ATTHOLD4_2 (0x04UL << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00040000 */ 8066 #define FSMC_PATT4_ATTHOLD4_3 (0x08UL << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00080000 */ 8067 #define FSMC_PATT4_ATTHOLD4_4 (0x10UL << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00100000 */ 8068 #define FSMC_PATT4_ATTHOLD4_5 (0x20UL << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00200000 */ 8069 #define FSMC_PATT4_ATTHOLD4_6 (0x40UL << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00400000 */ 8070 #define FSMC_PATT4_ATTHOLD4_7 (0x80UL << FSMC_PATT4_ATTHOLD4_Pos) /*!< 0x00800000 */ 8071 8072 #define FSMC_PATT4_ATTHIZ4_Pos (24U) 8073 #define FSMC_PATT4_ATTHIZ4_Msk (0xFFUL << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0xFF000000 */ 8074 #define FSMC_PATT4_ATTHIZ4 FSMC_PATT4_ATTHIZ4_Msk /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */ 8075 #define FSMC_PATT4_ATTHIZ4_0 (0x01UL << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x01000000 */ 8076 #define FSMC_PATT4_ATTHIZ4_1 (0x02UL << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x02000000 */ 8077 #define FSMC_PATT4_ATTHIZ4_2 (0x04UL << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x04000000 */ 8078 #define FSMC_PATT4_ATTHIZ4_3 (0x08UL << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x08000000 */ 8079 #define FSMC_PATT4_ATTHIZ4_4 (0x10UL << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x10000000 */ 8080 #define FSMC_PATT4_ATTHIZ4_5 (0x20UL << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x20000000 */ 8081 #define FSMC_PATT4_ATTHIZ4_6 (0x40UL << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x40000000 */ 8082 #define FSMC_PATT4_ATTHIZ4_7 (0x80UL << FSMC_PATT4_ATTHIZ4_Pos) /*!< 0x80000000 */ 8083 8084 /****************** Bit definition for FSMC_PIO4 register *******************/ 8085 #define FSMC_PIO4_IOSET4_Pos (0U) 8086 #define FSMC_PIO4_IOSET4_Msk (0xFFUL << FSMC_PIO4_IOSET4_Pos) /*!< 0x000000FF */ 8087 #define FSMC_PIO4_IOSET4 FSMC_PIO4_IOSET4_Msk /*!<IOSET4[7:0] bits (I/O 4 setup time) */ 8088 #define FSMC_PIO4_IOSET4_0 (0x01UL << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000001 */ 8089 #define FSMC_PIO4_IOSET4_1 (0x02UL << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000002 */ 8090 #define FSMC_PIO4_IOSET4_2 (0x04UL << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000004 */ 8091 #define FSMC_PIO4_IOSET4_3 (0x08UL << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000008 */ 8092 #define FSMC_PIO4_IOSET4_4 (0x10UL << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000010 */ 8093 #define FSMC_PIO4_IOSET4_5 (0x20UL << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000020 */ 8094 #define FSMC_PIO4_IOSET4_6 (0x40UL << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000040 */ 8095 #define FSMC_PIO4_IOSET4_7 (0x80UL << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000080 */ 8096 8097 #define FSMC_PIO4_IOWAIT4_Pos (8U) 8098 #define FSMC_PIO4_IOWAIT4_Msk (0xFFUL << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x0000FF00 */ 8099 #define FSMC_PIO4_IOWAIT4 FSMC_PIO4_IOWAIT4_Msk /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */ 8100 #define FSMC_PIO4_IOWAIT4_0 (0x01UL << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000100 */ 8101 #define FSMC_PIO4_IOWAIT4_1 (0x02UL << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000200 */ 8102 #define FSMC_PIO4_IOWAIT4_2 (0x04UL << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000400 */ 8103 #define FSMC_PIO4_IOWAIT4_3 (0x08UL << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000800 */ 8104 #define FSMC_PIO4_IOWAIT4_4 (0x10UL << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00001000 */ 8105 #define FSMC_PIO4_IOWAIT4_5 (0x20UL << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00002000 */ 8106 #define FSMC_PIO4_IOWAIT4_6 (0x40UL << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00004000 */ 8107 #define FSMC_PIO4_IOWAIT4_7 (0x80UL << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00008000 */ 8108 8109 #define FSMC_PIO4_IOHOLD4_Pos (16U) 8110 #define FSMC_PIO4_IOHOLD4_Msk (0xFFUL << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00FF0000 */ 8111 #define FSMC_PIO4_IOHOLD4 FSMC_PIO4_IOHOLD4_Msk /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */ 8112 #define FSMC_PIO4_IOHOLD4_0 (0x01UL << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00010000 */ 8113 #define FSMC_PIO4_IOHOLD4_1 (0x02UL << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00020000 */ 8114 #define FSMC_PIO4_IOHOLD4_2 (0x04UL << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00040000 */ 8115 #define FSMC_PIO4_IOHOLD4_3 (0x08UL << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00080000 */ 8116 #define FSMC_PIO4_IOHOLD4_4 (0x10UL << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00100000 */ 8117 #define FSMC_PIO4_IOHOLD4_5 (0x20UL << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00200000 */ 8118 #define FSMC_PIO4_IOHOLD4_6 (0x40UL << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00400000 */ 8119 #define FSMC_PIO4_IOHOLD4_7 (0x80UL << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00800000 */ 8120 8121 #define FSMC_PIO4_IOHIZ4_Pos (24U) 8122 #define FSMC_PIO4_IOHIZ4_Msk (0xFFUL << FSMC_PIO4_IOHIZ4_Pos) /*!< 0xFF000000 */ 8123 #define FSMC_PIO4_IOHIZ4 FSMC_PIO4_IOHIZ4_Msk /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */ 8124 #define FSMC_PIO4_IOHIZ4_0 (0x01UL << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x01000000 */ 8125 #define FSMC_PIO4_IOHIZ4_1 (0x02UL << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x02000000 */ 8126 #define FSMC_PIO4_IOHIZ4_2 (0x04UL << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x04000000 */ 8127 #define FSMC_PIO4_IOHIZ4_3 (0x08UL << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x08000000 */ 8128 #define FSMC_PIO4_IOHIZ4_4 (0x10UL << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x10000000 */ 8129 #define FSMC_PIO4_IOHIZ4_5 (0x20UL << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x20000000 */ 8130 #define FSMC_PIO4_IOHIZ4_6 (0x40UL << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x40000000 */ 8131 #define FSMC_PIO4_IOHIZ4_7 (0x80UL << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x80000000 */ 8132 8133 /****************** Bit definition for FSMC_ECCR2 register ******************/ 8134 #define FSMC_ECCR2_ECC2_Pos (0U) 8135 #define FSMC_ECCR2_ECC2_Msk (0xFFFFFFFFUL << FSMC_ECCR2_ECC2_Pos) /*!< 0xFFFFFFFF */ 8136 #define FSMC_ECCR2_ECC2 FSMC_ECCR2_ECC2_Msk /*!<ECC result */ 8137 8138 /****************** Bit definition for FSMC_ECCR3 register ******************/ 8139 #define FSMC_ECCR3_ECC3_Pos (0U) 8140 #define FSMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FSMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */ 8141 #define FSMC_ECCR3_ECC3 FSMC_ECCR3_ECC3_Msk /*!<ECC result */ 8142 8143 /******************************************************************************/ 8144 /* */ 8145 /* General Purpose I/O */ 8146 /* */ 8147 /******************************************************************************/ 8148 /****************** Bits definition for GPIO_MODER register *****************/ 8149 #define GPIO_MODER_MODE0 0x00000003U 8150 #define GPIO_MODER_MODE0_0 0x00000001U 8151 #define GPIO_MODER_MODE0_1 0x00000002U 8152 #define GPIO_MODER_MODE1 0x0000000CU 8153 #define GPIO_MODER_MODE1_0 0x00000004U 8154 #define GPIO_MODER_MODE1_1 0x00000008U 8155 #define GPIO_MODER_MODE2 0x00000030U 8156 #define GPIO_MODER_MODE2_0 0x00000010U 8157 #define GPIO_MODER_MODE2_1 0x00000020U 8158 #define GPIO_MODER_MODE3 0x000000C0U 8159 #define GPIO_MODER_MODE3_0 0x00000040U 8160 #define GPIO_MODER_MODE3_1 0x00000080U 8161 #define GPIO_MODER_MODE4 0x00000300U 8162 #define GPIO_MODER_MODE4_0 0x00000100U 8163 #define GPIO_MODER_MODE4_1 0x00000200U 8164 #define GPIO_MODER_MODE5 0x00000C00U 8165 #define GPIO_MODER_MODE5_0 0x00000400U 8166 #define GPIO_MODER_MODE5_1 0x00000800U 8167 #define GPIO_MODER_MODE6 0x00003000U 8168 #define GPIO_MODER_MODE6_0 0x00001000U 8169 #define GPIO_MODER_MODE6_1 0x00002000U 8170 #define GPIO_MODER_MODE7 0x0000C000U 8171 #define GPIO_MODER_MODE7_0 0x00004000U 8172 #define GPIO_MODER_MODE7_1 0x00008000U 8173 #define GPIO_MODER_MODE8 0x00030000U 8174 #define GPIO_MODER_MODE8_0 0x00010000U 8175 #define GPIO_MODER_MODE8_1 0x00020000U 8176 #define GPIO_MODER_MODE9 0x000C0000U 8177 #define GPIO_MODER_MODE9_0 0x00040000U 8178 #define GPIO_MODER_MODE9_1 0x00080000U 8179 #define GPIO_MODER_MODE10 0x00300000U 8180 #define GPIO_MODER_MODE10_0 0x00100000U 8181 #define GPIO_MODER_MODE10_1 0x00200000U 8182 #define GPIO_MODER_MODE11 0x00C00000U 8183 #define GPIO_MODER_MODE11_0 0x00400000U 8184 #define GPIO_MODER_MODE11_1 0x00800000U 8185 #define GPIO_MODER_MODE12 0x03000000U 8186 #define GPIO_MODER_MODE12_0 0x01000000U 8187 #define GPIO_MODER_MODE12_1 0x02000000U 8188 #define GPIO_MODER_MODE13 0x0C000000U 8189 #define GPIO_MODER_MODE13_0 0x04000000U 8190 #define GPIO_MODER_MODE13_1 0x08000000U 8191 #define GPIO_MODER_MODE14 0x30000000U 8192 #define GPIO_MODER_MODE14_0 0x10000000U 8193 #define GPIO_MODER_MODE14_1 0x20000000U 8194 #define GPIO_MODER_MODE15 0xC0000000U 8195 #define GPIO_MODER_MODE15_0 0x40000000U 8196 #define GPIO_MODER_MODE15_1 0x80000000U 8197 8198 /* Legacy defines */ 8199 #define GPIO_MODER_MODER0_Pos (0U) 8200 #define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ 8201 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk 8202 #define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ 8203 #define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ 8204 #define GPIO_MODER_MODER1_Pos (2U) 8205 #define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ 8206 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk 8207 #define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ 8208 #define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ 8209 #define GPIO_MODER_MODER2_Pos (4U) 8210 #define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ 8211 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk 8212 #define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ 8213 #define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ 8214 #define GPIO_MODER_MODER3_Pos (6U) 8215 #define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ 8216 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk 8217 #define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ 8218 #define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ 8219 #define GPIO_MODER_MODER4_Pos (8U) 8220 #define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ 8221 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk 8222 #define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ 8223 #define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ 8224 #define GPIO_MODER_MODER5_Pos (10U) 8225 #define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ 8226 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk 8227 #define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ 8228 #define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ 8229 #define GPIO_MODER_MODER6_Pos (12U) 8230 #define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ 8231 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk 8232 #define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ 8233 #define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ 8234 #define GPIO_MODER_MODER7_Pos (14U) 8235 #define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ 8236 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk 8237 #define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ 8238 #define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ 8239 #define GPIO_MODER_MODER8_Pos (16U) 8240 #define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ 8241 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk 8242 #define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ 8243 #define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ 8244 #define GPIO_MODER_MODER9_Pos (18U) 8245 #define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ 8246 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk 8247 #define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ 8248 #define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ 8249 #define GPIO_MODER_MODER10_Pos (20U) 8250 #define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ 8251 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk 8252 #define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ 8253 #define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ 8254 #define GPIO_MODER_MODER11_Pos (22U) 8255 #define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ 8256 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk 8257 #define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ 8258 #define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ 8259 #define GPIO_MODER_MODER12_Pos (24U) 8260 #define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ 8261 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk 8262 #define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ 8263 #define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ 8264 #define GPIO_MODER_MODER13_Pos (26U) 8265 #define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ 8266 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk 8267 #define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ 8268 #define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ 8269 #define GPIO_MODER_MODER14_Pos (28U) 8270 #define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ 8271 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk 8272 #define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ 8273 #define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ 8274 #define GPIO_MODER_MODER15_Pos (30U) 8275 #define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ 8276 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk 8277 #define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ 8278 #define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ 8279 8280 /****************** Bits definition for GPIO_OTYPER register ****************/ 8281 #define GPIO_OTYPER_OT0 0x00000001U 8282 #define GPIO_OTYPER_OT1 0x00000002U 8283 #define GPIO_OTYPER_OT2 0x00000004U 8284 #define GPIO_OTYPER_OT3 0x00000008U 8285 #define GPIO_OTYPER_OT4 0x00000010U 8286 #define GPIO_OTYPER_OT5 0x00000020U 8287 #define GPIO_OTYPER_OT6 0x00000040U 8288 #define GPIO_OTYPER_OT7 0x00000080U 8289 #define GPIO_OTYPER_OT8 0x00000100U 8290 #define GPIO_OTYPER_OT9 0x00000200U 8291 #define GPIO_OTYPER_OT10 0x00000400U 8292 #define GPIO_OTYPER_OT11 0x00000800U 8293 #define GPIO_OTYPER_OT12 0x00001000U 8294 #define GPIO_OTYPER_OT13 0x00002000U 8295 #define GPIO_OTYPER_OT14 0x00004000U 8296 #define GPIO_OTYPER_OT15 0x00008000U 8297 8298 /* Legacy defines */ 8299 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0 8300 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1 8301 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2 8302 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3 8303 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4 8304 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5 8305 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6 8306 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7 8307 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8 8308 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9 8309 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10 8310 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11 8311 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12 8312 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13 8313 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14 8314 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15 8315 8316 /****************** Bits definition for GPIO_OSPEEDR register ***************/ 8317 #define GPIO_OSPEEDR_OSPEED0 0x00000003U 8318 #define GPIO_OSPEEDR_OSPEED0_0 0x00000001U 8319 #define GPIO_OSPEEDR_OSPEED0_1 0x00000002U 8320 #define GPIO_OSPEEDR_OSPEED1 0x0000000CU 8321 #define GPIO_OSPEEDR_OSPEED1_0 0x00000004U 8322 #define GPIO_OSPEEDR_OSPEED1_1 0x00000008U 8323 #define GPIO_OSPEEDR_OSPEED2 0x00000030U 8324 #define GPIO_OSPEEDR_OSPEED2_0 0x00000010U 8325 #define GPIO_OSPEEDR_OSPEED2_1 0x00000020U 8326 #define GPIO_OSPEEDR_OSPEED3 0x000000C0U 8327 #define GPIO_OSPEEDR_OSPEED3_0 0x00000040U 8328 #define GPIO_OSPEEDR_OSPEED3_1 0x00000080U 8329 #define GPIO_OSPEEDR_OSPEED4 0x00000300U 8330 #define GPIO_OSPEEDR_OSPEED4_0 0x00000100U 8331 #define GPIO_OSPEEDR_OSPEED4_1 0x00000200U 8332 #define GPIO_OSPEEDR_OSPEED5 0x00000C00U 8333 #define GPIO_OSPEEDR_OSPEED5_0 0x00000400U 8334 #define GPIO_OSPEEDR_OSPEED5_1 0x00000800U 8335 #define GPIO_OSPEEDR_OSPEED6 0x00003000U 8336 #define GPIO_OSPEEDR_OSPEED6_0 0x00001000U 8337 #define GPIO_OSPEEDR_OSPEED6_1 0x00002000U 8338 #define GPIO_OSPEEDR_OSPEED7 0x0000C000U 8339 #define GPIO_OSPEEDR_OSPEED7_0 0x00004000U 8340 #define GPIO_OSPEEDR_OSPEED7_1 0x00008000U 8341 #define GPIO_OSPEEDR_OSPEED8 0x00030000U 8342 #define GPIO_OSPEEDR_OSPEED8_0 0x00010000U 8343 #define GPIO_OSPEEDR_OSPEED8_1 0x00020000U 8344 #define GPIO_OSPEEDR_OSPEED9 0x000C0000U 8345 #define GPIO_OSPEEDR_OSPEED9_0 0x00040000U 8346 #define GPIO_OSPEEDR_OSPEED9_1 0x00080000U 8347 #define GPIO_OSPEEDR_OSPEED10 0x00300000U 8348 #define GPIO_OSPEEDR_OSPEED10_0 0x00100000U 8349 #define GPIO_OSPEEDR_OSPEED10_1 0x00200000U 8350 #define GPIO_OSPEEDR_OSPEED11 0x00C00000U 8351 #define GPIO_OSPEEDR_OSPEED11_0 0x00400000U 8352 #define GPIO_OSPEEDR_OSPEED11_1 0x00800000U 8353 #define GPIO_OSPEEDR_OSPEED12 0x03000000U 8354 #define GPIO_OSPEEDR_OSPEED12_0 0x01000000U 8355 #define GPIO_OSPEEDR_OSPEED12_1 0x02000000U 8356 #define GPIO_OSPEEDR_OSPEED13 0x0C000000U 8357 #define GPIO_OSPEEDR_OSPEED13_0 0x04000000U 8358 #define GPIO_OSPEEDR_OSPEED13_1 0x08000000U 8359 #define GPIO_OSPEEDR_OSPEED14 0x30000000U 8360 #define GPIO_OSPEEDR_OSPEED14_0 0x10000000U 8361 #define GPIO_OSPEEDR_OSPEED14_1 0x20000000U 8362 #define GPIO_OSPEEDR_OSPEED15 0xC0000000U 8363 #define GPIO_OSPEEDR_OSPEED15_0 0x40000000U 8364 #define GPIO_OSPEEDR_OSPEED15_1 0x80000000U 8365 8366 /* Legacy defines */ 8367 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0 8368 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0 8369 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1 8370 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1 8371 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0 8372 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1 8373 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2 8374 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0 8375 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1 8376 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3 8377 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0 8378 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1 8379 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4 8380 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0 8381 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1 8382 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5 8383 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0 8384 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1 8385 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6 8386 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0 8387 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1 8388 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7 8389 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0 8390 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1 8391 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8 8392 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0 8393 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1 8394 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9 8395 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0 8396 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1 8397 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10 8398 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0 8399 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1 8400 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11 8401 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0 8402 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1 8403 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12 8404 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0 8405 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1 8406 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13 8407 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0 8408 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1 8409 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14 8410 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0 8411 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1 8412 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15 8413 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0 8414 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1 8415 8416 /****************** Bits definition for GPIO_PUPDR register *****************/ 8417 #define GPIO_PUPDR_PUPD0 0x00000003U 8418 #define GPIO_PUPDR_PUPD0_0 0x00000001U 8419 #define GPIO_PUPDR_PUPD0_1 0x00000002U 8420 #define GPIO_PUPDR_PUPD1 0x0000000CU 8421 #define GPIO_PUPDR_PUPD1_0 0x00000004U 8422 #define GPIO_PUPDR_PUPD1_1 0x00000008U 8423 #define GPIO_PUPDR_PUPD2 0x00000030U 8424 #define GPIO_PUPDR_PUPD2_0 0x00000010U 8425 #define GPIO_PUPDR_PUPD2_1 0x00000020U 8426 #define GPIO_PUPDR_PUPD3 0x000000C0U 8427 #define GPIO_PUPDR_PUPD3_0 0x00000040U 8428 #define GPIO_PUPDR_PUPD3_1 0x00000080U 8429 #define GPIO_PUPDR_PUPD4 0x00000300U 8430 #define GPIO_PUPDR_PUPD4_0 0x00000100U 8431 #define GPIO_PUPDR_PUPD4_1 0x00000200U 8432 #define GPIO_PUPDR_PUPD5 0x00000C00U 8433 #define GPIO_PUPDR_PUPD5_0 0x00000400U 8434 #define GPIO_PUPDR_PUPD5_1 0x00000800U 8435 #define GPIO_PUPDR_PUPD6 0x00003000U 8436 #define GPIO_PUPDR_PUPD6_0 0x00001000U 8437 #define GPIO_PUPDR_PUPD6_1 0x00002000U 8438 #define GPIO_PUPDR_PUPD7 0x0000C000U 8439 #define GPIO_PUPDR_PUPD7_0 0x00004000U 8440 #define GPIO_PUPDR_PUPD7_1 0x00008000U 8441 #define GPIO_PUPDR_PUPD8 0x00030000U 8442 #define GPIO_PUPDR_PUPD8_0 0x00010000U 8443 #define GPIO_PUPDR_PUPD8_1 0x00020000U 8444 #define GPIO_PUPDR_PUPD9 0x000C0000U 8445 #define GPIO_PUPDR_PUPD9_0 0x00040000U 8446 #define GPIO_PUPDR_PUPD9_1 0x00080000U 8447 #define GPIO_PUPDR_PUPD10 0x00300000U 8448 #define GPIO_PUPDR_PUPD10_0 0x00100000U 8449 #define GPIO_PUPDR_PUPD10_1 0x00200000U 8450 #define GPIO_PUPDR_PUPD11 0x00C00000U 8451 #define GPIO_PUPDR_PUPD11_0 0x00400000U 8452 #define GPIO_PUPDR_PUPD11_1 0x00800000U 8453 #define GPIO_PUPDR_PUPD12 0x03000000U 8454 #define GPIO_PUPDR_PUPD12_0 0x01000000U 8455 #define GPIO_PUPDR_PUPD12_1 0x02000000U 8456 #define GPIO_PUPDR_PUPD13 0x0C000000U 8457 #define GPIO_PUPDR_PUPD13_0 0x04000000U 8458 #define GPIO_PUPDR_PUPD13_1 0x08000000U 8459 #define GPIO_PUPDR_PUPD14 0x30000000U 8460 #define GPIO_PUPDR_PUPD14_0 0x10000000U 8461 #define GPIO_PUPDR_PUPD14_1 0x20000000U 8462 #define GPIO_PUPDR_PUPD15 0xC0000000U 8463 #define GPIO_PUPDR_PUPD15_0 0x40000000U 8464 #define GPIO_PUPDR_PUPD15_1 0x80000000U 8465 8466 /* Legacy defines */ 8467 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0 8468 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0 8469 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1 8470 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1 8471 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0 8472 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1 8473 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2 8474 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0 8475 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1 8476 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3 8477 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0 8478 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1 8479 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4 8480 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0 8481 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1 8482 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5 8483 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0 8484 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1 8485 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6 8486 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0 8487 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1 8488 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7 8489 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0 8490 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1 8491 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8 8492 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0 8493 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1 8494 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9 8495 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0 8496 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1 8497 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10 8498 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0 8499 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1 8500 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11 8501 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0 8502 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1 8503 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12 8504 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0 8505 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1 8506 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13 8507 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0 8508 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1 8509 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14 8510 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0 8511 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1 8512 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15 8513 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0 8514 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1 8515 8516 /****************** Bits definition for GPIO_IDR register *******************/ 8517 #define GPIO_IDR_ID0 0x00000001U 8518 #define GPIO_IDR_ID1 0x00000002U 8519 #define GPIO_IDR_ID2 0x00000004U 8520 #define GPIO_IDR_ID3 0x00000008U 8521 #define GPIO_IDR_ID4 0x00000010U 8522 #define GPIO_IDR_ID5 0x00000020U 8523 #define GPIO_IDR_ID6 0x00000040U 8524 #define GPIO_IDR_ID7 0x00000080U 8525 #define GPIO_IDR_ID8 0x00000100U 8526 #define GPIO_IDR_ID9 0x00000200U 8527 #define GPIO_IDR_ID10 0x00000400U 8528 #define GPIO_IDR_ID11 0x00000800U 8529 #define GPIO_IDR_ID12 0x00001000U 8530 #define GPIO_IDR_ID13 0x00002000U 8531 #define GPIO_IDR_ID14 0x00004000U 8532 #define GPIO_IDR_ID15 0x00008000U 8533 8534 /* Legacy defines */ 8535 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0 8536 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1 8537 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2 8538 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3 8539 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4 8540 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5 8541 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6 8542 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7 8543 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8 8544 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9 8545 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10 8546 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11 8547 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12 8548 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13 8549 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14 8550 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15 8551 8552 /****************** Bits definition for GPIO_ODR register *******************/ 8553 #define GPIO_ODR_OD0 0x00000001U 8554 #define GPIO_ODR_OD1 0x00000002U 8555 #define GPIO_ODR_OD2 0x00000004U 8556 #define GPIO_ODR_OD3 0x00000008U 8557 #define GPIO_ODR_OD4 0x00000010U 8558 #define GPIO_ODR_OD5 0x00000020U 8559 #define GPIO_ODR_OD6 0x00000040U 8560 #define GPIO_ODR_OD7 0x00000080U 8561 #define GPIO_ODR_OD8 0x00000100U 8562 #define GPIO_ODR_OD9 0x00000200U 8563 #define GPIO_ODR_OD10 0x00000400U 8564 #define GPIO_ODR_OD11 0x00000800U 8565 #define GPIO_ODR_OD12 0x00001000U 8566 #define GPIO_ODR_OD13 0x00002000U 8567 #define GPIO_ODR_OD14 0x00004000U 8568 #define GPIO_ODR_OD15 0x00008000U 8569 8570 /* Legacy defines */ 8571 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0 8572 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1 8573 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2 8574 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3 8575 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4 8576 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5 8577 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6 8578 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7 8579 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8 8580 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9 8581 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10 8582 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11 8583 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12 8584 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13 8585 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14 8586 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15 8587 8588 /****************** Bits definition for GPIO_BSRR register ******************/ 8589 #define GPIO_BSRR_BS0 0x00000001U 8590 #define GPIO_BSRR_BS1 0x00000002U 8591 #define GPIO_BSRR_BS2 0x00000004U 8592 #define GPIO_BSRR_BS3 0x00000008U 8593 #define GPIO_BSRR_BS4 0x00000010U 8594 #define GPIO_BSRR_BS5 0x00000020U 8595 #define GPIO_BSRR_BS6 0x00000040U 8596 #define GPIO_BSRR_BS7 0x00000080U 8597 #define GPIO_BSRR_BS8 0x00000100U 8598 #define GPIO_BSRR_BS9 0x00000200U 8599 #define GPIO_BSRR_BS10 0x00000400U 8600 #define GPIO_BSRR_BS11 0x00000800U 8601 #define GPIO_BSRR_BS12 0x00001000U 8602 #define GPIO_BSRR_BS13 0x00002000U 8603 #define GPIO_BSRR_BS14 0x00004000U 8604 #define GPIO_BSRR_BS15 0x00008000U 8605 #define GPIO_BSRR_BR0 0x00010000U 8606 #define GPIO_BSRR_BR1 0x00020000U 8607 #define GPIO_BSRR_BR2 0x00040000U 8608 #define GPIO_BSRR_BR3 0x00080000U 8609 #define GPIO_BSRR_BR4 0x00100000U 8610 #define GPIO_BSRR_BR5 0x00200000U 8611 #define GPIO_BSRR_BR6 0x00400000U 8612 #define GPIO_BSRR_BR7 0x00800000U 8613 #define GPIO_BSRR_BR8 0x01000000U 8614 #define GPIO_BSRR_BR9 0x02000000U 8615 #define GPIO_BSRR_BR10 0x04000000U 8616 #define GPIO_BSRR_BR11 0x08000000U 8617 #define GPIO_BSRR_BR12 0x10000000U 8618 #define GPIO_BSRR_BR13 0x20000000U 8619 #define GPIO_BSRR_BR14 0x40000000U 8620 #define GPIO_BSRR_BR15 0x80000000U 8621 8622 /* Legacy defines */ 8623 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0 8624 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1 8625 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2 8626 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3 8627 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4 8628 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5 8629 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6 8630 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7 8631 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8 8632 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9 8633 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10 8634 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11 8635 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12 8636 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13 8637 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14 8638 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15 8639 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0 8640 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1 8641 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2 8642 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3 8643 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4 8644 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5 8645 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6 8646 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7 8647 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8 8648 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9 8649 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10 8650 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11 8651 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12 8652 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13 8653 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14 8654 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15 8655 8656 /****************** Bit definition for GPIO_LCKR register *********************/ 8657 #define GPIO_LCKR_LCK0_Pos (0U) 8658 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ 8659 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk 8660 #define GPIO_LCKR_LCK1_Pos (1U) 8661 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ 8662 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk 8663 #define GPIO_LCKR_LCK2_Pos (2U) 8664 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ 8665 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk 8666 #define GPIO_LCKR_LCK3_Pos (3U) 8667 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ 8668 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk 8669 #define GPIO_LCKR_LCK4_Pos (4U) 8670 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ 8671 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk 8672 #define GPIO_LCKR_LCK5_Pos (5U) 8673 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ 8674 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk 8675 #define GPIO_LCKR_LCK6_Pos (6U) 8676 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ 8677 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk 8678 #define GPIO_LCKR_LCK7_Pos (7U) 8679 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ 8680 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk 8681 #define GPIO_LCKR_LCK8_Pos (8U) 8682 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ 8683 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk 8684 #define GPIO_LCKR_LCK9_Pos (9U) 8685 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ 8686 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk 8687 #define GPIO_LCKR_LCK10_Pos (10U) 8688 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ 8689 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk 8690 #define GPIO_LCKR_LCK11_Pos (11U) 8691 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ 8692 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk 8693 #define GPIO_LCKR_LCK12_Pos (12U) 8694 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ 8695 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk 8696 #define GPIO_LCKR_LCK13_Pos (13U) 8697 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ 8698 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk 8699 #define GPIO_LCKR_LCK14_Pos (14U) 8700 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ 8701 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk 8702 #define GPIO_LCKR_LCK15_Pos (15U) 8703 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ 8704 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk 8705 #define GPIO_LCKR_LCKK_Pos (16U) 8706 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ 8707 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk 8708 8709 /****************** Bit definition for GPIO_AFRL register *********************/ 8710 #define GPIO_AFRL_AFSEL0 0x0000000FU 8711 #define GPIO_AFRL_AFSEL0_0 0x00000001U 8712 #define GPIO_AFRL_AFSEL0_1 0x00000002U 8713 #define GPIO_AFRL_AFSEL0_2 0x00000004U 8714 #define GPIO_AFRL_AFSEL0_3 0x00000008U 8715 #define GPIO_AFRL_AFSEL1 0x000000F0U 8716 #define GPIO_AFRL_AFSEL1_0 0x00000010U 8717 #define GPIO_AFRL_AFSEL1_1 0x00000020U 8718 #define GPIO_AFRL_AFSEL1_2 0x00000040U 8719 #define GPIO_AFRL_AFSEL1_3 0x00000080U 8720 #define GPIO_AFRL_AFSEL2 0x00000F00U 8721 #define GPIO_AFRL_AFSEL2_0 0x00000100U 8722 #define GPIO_AFRL_AFSEL2_1 0x00000200U 8723 #define GPIO_AFRL_AFSEL2_2 0x00000400U 8724 #define GPIO_AFRL_AFSEL2_3 0x00000800U 8725 #define GPIO_AFRL_AFSEL3 0x0000F000U 8726 #define GPIO_AFRL_AFSEL3_0 0x00001000U 8727 #define GPIO_AFRL_AFSEL3_1 0x00002000U 8728 #define GPIO_AFRL_AFSEL3_2 0x00004000U 8729 #define GPIO_AFRL_AFSEL3_3 0x00008000U 8730 #define GPIO_AFRL_AFSEL4 0x000F0000U 8731 #define GPIO_AFRL_AFSEL4_0 0x00010000U 8732 #define GPIO_AFRL_AFSEL4_1 0x00020000U 8733 #define GPIO_AFRL_AFSEL4_2 0x00040000U 8734 #define GPIO_AFRL_AFSEL4_3 0x00080000U 8735 #define GPIO_AFRL_AFSEL5 0x00F00000U 8736 #define GPIO_AFRL_AFSEL5_0 0x00100000U 8737 #define GPIO_AFRL_AFSEL5_1 0x00200000U 8738 #define GPIO_AFRL_AFSEL5_2 0x00400000U 8739 #define GPIO_AFRL_AFSEL5_3 0x00800000U 8740 #define GPIO_AFRL_AFSEL6 0x0F000000U 8741 #define GPIO_AFRL_AFSEL6_0 0x01000000U 8742 #define GPIO_AFRL_AFSEL6_1 0x02000000U 8743 #define GPIO_AFRL_AFSEL6_2 0x04000000U 8744 #define GPIO_AFRL_AFSEL6_3 0x08000000U 8745 #define GPIO_AFRL_AFSEL7 0xF0000000U 8746 #define GPIO_AFRL_AFSEL7_0 0x10000000U 8747 #define GPIO_AFRL_AFSEL7_1 0x20000000U 8748 #define GPIO_AFRL_AFSEL7_2 0x40000000U 8749 #define GPIO_AFRL_AFSEL7_3 0x80000000U 8750 8751 /* Legacy defines */ 8752 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 8753 #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0 8754 #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1 8755 #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2 8756 #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3 8757 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 8758 #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0 8759 #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1 8760 #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2 8761 #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3 8762 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 8763 #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0 8764 #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1 8765 #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2 8766 #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3 8767 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 8768 #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0 8769 #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1 8770 #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2 8771 #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3 8772 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 8773 #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0 8774 #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1 8775 #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2 8776 #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3 8777 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 8778 #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0 8779 #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1 8780 #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2 8781 #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3 8782 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 8783 #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0 8784 #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1 8785 #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2 8786 #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3 8787 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 8788 #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0 8789 #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1 8790 #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2 8791 #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3 8792 8793 /****************** Bit definition for GPIO_AFRH register *********************/ 8794 #define GPIO_AFRH_AFSEL8 0x0000000FU 8795 #define GPIO_AFRH_AFSEL8_0 0x00000001U 8796 #define GPIO_AFRH_AFSEL8_1 0x00000002U 8797 #define GPIO_AFRH_AFSEL8_2 0x00000004U 8798 #define GPIO_AFRH_AFSEL8_3 0x00000008U 8799 #define GPIO_AFRH_AFSEL9 0x000000F0U 8800 #define GPIO_AFRH_AFSEL9_0 0x00000010U 8801 #define GPIO_AFRH_AFSEL9_1 0x00000020U 8802 #define GPIO_AFRH_AFSEL9_2 0x00000040U 8803 #define GPIO_AFRH_AFSEL9_3 0x00000080U 8804 #define GPIO_AFRH_AFSEL10 0x00000F00U 8805 #define GPIO_AFRH_AFSEL10_0 0x00000100U 8806 #define GPIO_AFRH_AFSEL10_1 0x00000200U 8807 #define GPIO_AFRH_AFSEL10_2 0x00000400U 8808 #define GPIO_AFRH_AFSEL10_3 0x00000800U 8809 #define GPIO_AFRH_AFSEL11 0x0000F000U 8810 #define GPIO_AFRH_AFSEL11_0 0x00001000U 8811 #define GPIO_AFRH_AFSEL11_1 0x00002000U 8812 #define GPIO_AFRH_AFSEL11_2 0x00004000U 8813 #define GPIO_AFRH_AFSEL11_3 0x00008000U 8814 #define GPIO_AFRH_AFSEL12 0x000F0000U 8815 #define GPIO_AFRH_AFSEL12_0 0x00010000U 8816 #define GPIO_AFRH_AFSEL12_1 0x00020000U 8817 #define GPIO_AFRH_AFSEL12_2 0x00040000U 8818 #define GPIO_AFRH_AFSEL12_3 0x00080000U 8819 #define GPIO_AFRH_AFSEL13 0x00F00000U 8820 #define GPIO_AFRH_AFSEL13_0 0x00100000U 8821 #define GPIO_AFRH_AFSEL13_1 0x00200000U 8822 #define GPIO_AFRH_AFSEL13_2 0x00400000U 8823 #define GPIO_AFRH_AFSEL13_3 0x00800000U 8824 #define GPIO_AFRH_AFSEL14 0x0F000000U 8825 #define GPIO_AFRH_AFSEL14_0 0x01000000U 8826 #define GPIO_AFRH_AFSEL14_1 0x02000000U 8827 #define GPIO_AFRH_AFSEL14_2 0x04000000U 8828 #define GPIO_AFRH_AFSEL14_3 0x08000000U 8829 #define GPIO_AFRH_AFSEL15 0xF0000000U 8830 #define GPIO_AFRH_AFSEL15_0 0x10000000U 8831 #define GPIO_AFRH_AFSEL15_1 0x20000000U 8832 #define GPIO_AFRH_AFSEL15_2 0x40000000U 8833 #define GPIO_AFRH_AFSEL15_3 0x80000000U 8834 8835 /* Legacy defines */ 8836 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 8837 #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0 8838 #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1 8839 #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2 8840 #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3 8841 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 8842 #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0 8843 #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1 8844 #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2 8845 #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3 8846 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 8847 #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0 8848 #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1 8849 #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2 8850 #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3 8851 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 8852 #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0 8853 #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1 8854 #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2 8855 #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3 8856 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 8857 #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0 8858 #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1 8859 #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2 8860 #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3 8861 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 8862 #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0 8863 #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1 8864 #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2 8865 #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3 8866 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 8867 #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0 8868 #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1 8869 #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2 8870 #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3 8871 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 8872 #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0 8873 #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1 8874 #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2 8875 #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3 8876 8877 8878 /******************************************************************************/ 8879 /* */ 8880 /* HASH */ 8881 /* */ 8882 /******************************************************************************/ 8883 /****************** Bits definition for HASH_CR register ********************/ 8884 #define HASH_CR_INIT_Pos (2U) 8885 #define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos) /*!< 0x00000004 */ 8886 #define HASH_CR_INIT HASH_CR_INIT_Msk 8887 #define HASH_CR_DMAE_Pos (3U) 8888 #define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos) /*!< 0x00000008 */ 8889 #define HASH_CR_DMAE HASH_CR_DMAE_Msk 8890 #define HASH_CR_DATATYPE_Pos (4U) 8891 #define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */ 8892 #define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk 8893 #define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */ 8894 #define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */ 8895 #define HASH_CR_MODE_Pos (6U) 8896 #define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos) /*!< 0x00000040 */ 8897 #define HASH_CR_MODE HASH_CR_MODE_Msk 8898 #define HASH_CR_ALGO_Pos (7U) 8899 #define HASH_CR_ALGO_Msk (0x1UL << HASH_CR_ALGO_Pos) /*!< 0x00000080 */ 8900 #define HASH_CR_ALGO HASH_CR_ALGO_Msk 8901 #define HASH_CR_ALGO_0 (0x1UL << HASH_CR_ALGO_Pos) /*!< 0x00000080 */ 8902 #define HASH_CR_NBW_Pos (8U) 8903 #define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos) /*!< 0x00000F00 */ 8904 #define HASH_CR_NBW HASH_CR_NBW_Msk 8905 #define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos) /*!< 0x00000100 */ 8906 #define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos) /*!< 0x00000200 */ 8907 #define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos) /*!< 0x00000400 */ 8908 #define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos) /*!< 0x00000800 */ 8909 #define HASH_CR_DINNE_Pos (12U) 8910 #define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos) /*!< 0x00001000 */ 8911 #define HASH_CR_DINNE HASH_CR_DINNE_Msk 8912 #define HASH_CR_LKEY_Pos (16U) 8913 #define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos) /*!< 0x00010000 */ 8914 #define HASH_CR_LKEY HASH_CR_LKEY_Msk 8915 8916 /****************** Bits definition for HASH_STR register *******************/ 8917 #define HASH_STR_NBLW_Pos (0U) 8918 #define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos) /*!< 0x0000001F */ 8919 #define HASH_STR_NBLW HASH_STR_NBLW_Msk 8920 #define HASH_STR_NBLW_0 (0x01UL << HASH_STR_NBLW_Pos) /*!< 0x00000001 */ 8921 #define HASH_STR_NBLW_1 (0x02UL << HASH_STR_NBLW_Pos) /*!< 0x00000002 */ 8922 #define HASH_STR_NBLW_2 (0x04UL << HASH_STR_NBLW_Pos) /*!< 0x00000004 */ 8923 #define HASH_STR_NBLW_3 (0x08UL << HASH_STR_NBLW_Pos) /*!< 0x00000008 */ 8924 #define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos) /*!< 0x00000010 */ 8925 #define HASH_STR_DCAL_Pos (8U) 8926 #define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos) /*!< 0x00000100 */ 8927 #define HASH_STR_DCAL HASH_STR_DCAL_Msk 8928 /* Aliases for HASH_STR register */ 8929 #define HASH_STR_NBW HASH_STR_NBLW 8930 #define HASH_STR_NBW_0 HASH_STR_NBLW_0 8931 #define HASH_STR_NBW_1 HASH_STR_NBLW_1 8932 #define HASH_STR_NBW_2 HASH_STR_NBLW_2 8933 #define HASH_STR_NBW_3 HASH_STR_NBLW_3 8934 #define HASH_STR_NBW_4 HASH_STR_NBLW_4 8935 8936 8937 /****************** Bits definition for HASH_IMR register *******************/ 8938 #define HASH_IMR_DINIE_Pos (0U) 8939 #define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */ 8940 #define HASH_IMR_DINIE HASH_IMR_DINIE_Msk 8941 #define HASH_IMR_DCIE_Pos (1U) 8942 #define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */ 8943 #define HASH_IMR_DCIE HASH_IMR_DCIE_Msk 8944 /* Aliases for HASH_IMR register */ 8945 #define HASH_IMR_DINIM HASH_IMR_DINIE 8946 #define HASH_IMR_DCIM HASH_IMR_DCIE 8947 8948 8949 /****************** Bits definition for HASH_SR register ********************/ 8950 #define HASH_SR_DINIS_Pos (0U) 8951 #define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos) /*!< 0x00000001 */ 8952 #define HASH_SR_DINIS HASH_SR_DINIS_Msk 8953 #define HASH_SR_DCIS_Pos (1U) 8954 #define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos) /*!< 0x00000002 */ 8955 #define HASH_SR_DCIS HASH_SR_DCIS_Msk 8956 #define HASH_SR_DMAS_Pos (2U) 8957 #define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos) /*!< 0x00000004 */ 8958 #define HASH_SR_DMAS HASH_SR_DMAS_Msk 8959 #define HASH_SR_BUSY_Pos (3U) 8960 #define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos) /*!< 0x00000008 */ 8961 #define HASH_SR_BUSY HASH_SR_BUSY_Msk 8962 8963 /******************************************************************************/ 8964 /* */ 8965 /* Inter-integrated Circuit Interface */ 8966 /* */ 8967 /******************************************************************************/ 8968 /******************* Bit definition for I2C_CR1 register ********************/ 8969 #define I2C_CR1_PE_Pos (0U) 8970 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ 8971 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */ 8972 #define I2C_CR1_SMBUS_Pos (1U) 8973 #define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */ 8974 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */ 8975 #define I2C_CR1_SMBTYPE_Pos (3U) 8976 #define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */ 8977 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */ 8978 #define I2C_CR1_ENARP_Pos (4U) 8979 #define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */ 8980 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */ 8981 #define I2C_CR1_ENPEC_Pos (5U) 8982 #define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */ 8983 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */ 8984 #define I2C_CR1_ENGC_Pos (6U) 8985 #define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */ 8986 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */ 8987 #define I2C_CR1_NOSTRETCH_Pos (7U) 8988 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */ 8989 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */ 8990 #define I2C_CR1_START_Pos (8U) 8991 #define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos) /*!< 0x00000100 */ 8992 #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */ 8993 #define I2C_CR1_STOP_Pos (9U) 8994 #define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos) /*!< 0x00000200 */ 8995 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */ 8996 #define I2C_CR1_ACK_Pos (10U) 8997 #define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos) /*!< 0x00000400 */ 8998 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */ 8999 #define I2C_CR1_POS_Pos (11U) 9000 #define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos) /*!< 0x00000800 */ 9001 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */ 9002 #define I2C_CR1_PEC_Pos (12U) 9003 #define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos) /*!< 0x00001000 */ 9004 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */ 9005 #define I2C_CR1_ALERT_Pos (13U) 9006 #define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */ 9007 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */ 9008 #define I2C_CR1_SWRST_Pos (15U) 9009 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */ 9010 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */ 9011 9012 /******************* Bit definition for I2C_CR2 register ********************/ 9013 #define I2C_CR2_FREQ_Pos (0U) 9014 #define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */ 9015 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */ 9016 #define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */ 9017 #define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */ 9018 #define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */ 9019 #define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */ 9020 #define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */ 9021 #define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */ 9022 9023 #define I2C_CR2_ITERREN_Pos (8U) 9024 #define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */ 9025 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */ 9026 #define I2C_CR2_ITEVTEN_Pos (9U) 9027 #define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */ 9028 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */ 9029 #define I2C_CR2_ITBUFEN_Pos (10U) 9030 #define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */ 9031 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */ 9032 #define I2C_CR2_DMAEN_Pos (11U) 9033 #define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */ 9034 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */ 9035 #define I2C_CR2_LAST_Pos (12U) 9036 #define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos) /*!< 0x00001000 */ 9037 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */ 9038 9039 /******************* Bit definition for I2C_OAR1 register *******************/ 9040 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */ 9041 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */ 9042 9043 #define I2C_OAR1_ADD0_Pos (0U) 9044 #define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */ 9045 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */ 9046 #define I2C_OAR1_ADD1_Pos (1U) 9047 #define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */ 9048 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */ 9049 #define I2C_OAR1_ADD2_Pos (2U) 9050 #define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */ 9051 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */ 9052 #define I2C_OAR1_ADD3_Pos (3U) 9053 #define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */ 9054 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */ 9055 #define I2C_OAR1_ADD4_Pos (4U) 9056 #define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */ 9057 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */ 9058 #define I2C_OAR1_ADD5_Pos (5U) 9059 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */ 9060 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */ 9061 #define I2C_OAR1_ADD6_Pos (6U) 9062 #define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */ 9063 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */ 9064 #define I2C_OAR1_ADD7_Pos (7U) 9065 #define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */ 9066 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */ 9067 #define I2C_OAR1_ADD8_Pos (8U) 9068 #define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */ 9069 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */ 9070 #define I2C_OAR1_ADD9_Pos (9U) 9071 #define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */ 9072 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */ 9073 9074 #define I2C_OAR1_ADDMODE_Pos (15U) 9075 #define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */ 9076 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */ 9077 9078 /******************* Bit definition for I2C_OAR2 register *******************/ 9079 #define I2C_OAR2_ENDUAL_Pos (0U) 9080 #define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */ 9081 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */ 9082 #define I2C_OAR2_ADD2_Pos (1U) 9083 #define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */ 9084 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */ 9085 9086 /******************** Bit definition for I2C_DR register ********************/ 9087 #define I2C_DR_DR_Pos (0U) 9088 #define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos) /*!< 0x000000FF */ 9089 #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */ 9090 9091 /******************* Bit definition for I2C_SR1 register ********************/ 9092 #define I2C_SR1_SB_Pos (0U) 9093 #define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos) /*!< 0x00000001 */ 9094 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */ 9095 #define I2C_SR1_ADDR_Pos (1U) 9096 #define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */ 9097 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */ 9098 #define I2C_SR1_BTF_Pos (2U) 9099 #define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos) /*!< 0x00000004 */ 9100 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */ 9101 #define I2C_SR1_ADD10_Pos (3U) 9102 #define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */ 9103 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */ 9104 #define I2C_SR1_STOPF_Pos (4U) 9105 #define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */ 9106 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */ 9107 #define I2C_SR1_RXNE_Pos (6U) 9108 #define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */ 9109 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */ 9110 #define I2C_SR1_TXE_Pos (7U) 9111 #define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos) /*!< 0x00000080 */ 9112 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */ 9113 #define I2C_SR1_BERR_Pos (8U) 9114 #define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos) /*!< 0x00000100 */ 9115 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */ 9116 #define I2C_SR1_ARLO_Pos (9U) 9117 #define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */ 9118 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */ 9119 #define I2C_SR1_AF_Pos (10U) 9120 #define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos) /*!< 0x00000400 */ 9121 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */ 9122 #define I2C_SR1_OVR_Pos (11U) 9123 #define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos) /*!< 0x00000800 */ 9124 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */ 9125 #define I2C_SR1_PECERR_Pos (12U) 9126 #define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */ 9127 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */ 9128 #define I2C_SR1_TIMEOUT_Pos (14U) 9129 #define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */ 9130 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */ 9131 #define I2C_SR1_SMBALERT_Pos (15U) 9132 #define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */ 9133 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */ 9134 9135 /******************* Bit definition for I2C_SR2 register ********************/ 9136 #define I2C_SR2_MSL_Pos (0U) 9137 #define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos) /*!< 0x00000001 */ 9138 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */ 9139 #define I2C_SR2_BUSY_Pos (1U) 9140 #define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */ 9141 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */ 9142 #define I2C_SR2_TRA_Pos (2U) 9143 #define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos) /*!< 0x00000004 */ 9144 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */ 9145 #define I2C_SR2_GENCALL_Pos (4U) 9146 #define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */ 9147 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */ 9148 #define I2C_SR2_SMBDEFAULT_Pos (5U) 9149 #define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */ 9150 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */ 9151 #define I2C_SR2_SMBHOST_Pos (6U) 9152 #define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */ 9153 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */ 9154 #define I2C_SR2_DUALF_Pos (7U) 9155 #define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */ 9156 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */ 9157 #define I2C_SR2_PEC_Pos (8U) 9158 #define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */ 9159 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */ 9160 9161 /******************* Bit definition for I2C_CCR register ********************/ 9162 #define I2C_CCR_CCR_Pos (0U) 9163 #define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */ 9164 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */ 9165 #define I2C_CCR_DUTY_Pos (14U) 9166 #define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */ 9167 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */ 9168 #define I2C_CCR_FS_Pos (15U) 9169 #define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos) /*!< 0x00008000 */ 9170 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */ 9171 9172 /****************** Bit definition for I2C_TRISE register *******************/ 9173 #define I2C_TRISE_TRISE_Pos (0U) 9174 #define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */ 9175 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */ 9176 9177 /******************************************************************************/ 9178 /* */ 9179 /* Independent WATCHDOG */ 9180 /* */ 9181 /******************************************************************************/ 9182 /******************* Bit definition for IWDG_KR register ********************/ 9183 #define IWDG_KR_KEY_Pos (0U) 9184 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ 9185 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */ 9186 9187 /******************* Bit definition for IWDG_PR register ********************/ 9188 #define IWDG_PR_PR_Pos (0U) 9189 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */ 9190 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */ 9191 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */ 9192 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */ 9193 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */ 9194 9195 /******************* Bit definition for IWDG_RLR register *******************/ 9196 #define IWDG_RLR_RL_Pos (0U) 9197 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ 9198 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */ 9199 9200 /******************* Bit definition for IWDG_SR register ********************/ 9201 #define IWDG_SR_PVU_Pos (0U) 9202 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ 9203 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */ 9204 #define IWDG_SR_RVU_Pos (1U) 9205 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ 9206 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */ 9207 9208 /******************************************************************************/ 9209 /* */ 9210 /* Power Control */ 9211 /* */ 9212 /******************************************************************************/ 9213 /******************** Bit definition for PWR_CR register ********************/ 9214 #define PWR_CR_LPDS_Pos (0U) 9215 #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ 9216 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */ 9217 #define PWR_CR_PDDS_Pos (1U) 9218 #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ 9219 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ 9220 #define PWR_CR_CWUF_Pos (2U) 9221 #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ 9222 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ 9223 #define PWR_CR_CSBF_Pos (3U) 9224 #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ 9225 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ 9226 #define PWR_CR_PVDE_Pos (4U) 9227 #define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ 9228 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ 9229 9230 #define PWR_CR_PLS_Pos (5U) 9231 #define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ 9232 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ 9233 #define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */ 9234 #define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */ 9235 #define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */ 9236 9237 /*!< PVD level configuration */ 9238 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */ 9239 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */ 9240 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */ 9241 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */ 9242 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */ 9243 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */ 9244 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */ 9245 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */ 9246 9247 #define PWR_CR_DBP_Pos (8U) 9248 #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */ 9249 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ 9250 #define PWR_CR_FPDS_Pos (9U) 9251 #define PWR_CR_FPDS_Msk (0x1UL << PWR_CR_FPDS_Pos) /*!< 0x00000200 */ 9252 #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */ 9253 9254 /******************* Bit definition for PWR_CSR register ********************/ 9255 #define PWR_CSR_WUF_Pos (0U) 9256 #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ 9257 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ 9258 #define PWR_CSR_SBF_Pos (1U) 9259 #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ 9260 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ 9261 #define PWR_CSR_PVDO_Pos (2U) 9262 #define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ 9263 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ 9264 #define PWR_CSR_BRR_Pos (3U) 9265 #define PWR_CSR_BRR_Msk (0x1UL << PWR_CSR_BRR_Pos) /*!< 0x00000008 */ 9266 #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */ 9267 #define PWR_CSR_EWUP_Pos (8U) 9268 #define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */ 9269 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */ 9270 #define PWR_CSR_BRE_Pos (9U) 9271 #define PWR_CSR_BRE_Msk (0x1UL << PWR_CSR_BRE_Pos) /*!< 0x00000200 */ 9272 #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */ 9273 9274 /******************************************************************************/ 9275 /* */ 9276 /* Reset and Clock Control */ 9277 /* */ 9278 /******************************************************************************/ 9279 /******************** Bit definition for RCC_CR register ********************/ 9280 #define RCC_CR_HSION_Pos (0U) 9281 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ 9282 #define RCC_CR_HSION RCC_CR_HSION_Msk 9283 #define RCC_CR_HSIRDY_Pos (1U) 9284 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ 9285 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk 9286 9287 #define RCC_CR_HSITRIM_Pos (3U) 9288 #define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ 9289 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk 9290 #define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */ 9291 #define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */ 9292 #define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */ 9293 #define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */ 9294 #define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */ 9295 9296 #define RCC_CR_HSICAL_Pos (8U) 9297 #define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ 9298 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk 9299 #define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */ 9300 #define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */ 9301 #define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */ 9302 #define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */ 9303 #define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */ 9304 #define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */ 9305 #define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */ 9306 #define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */ 9307 9308 #define RCC_CR_HSEON_Pos (16U) 9309 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ 9310 #define RCC_CR_HSEON RCC_CR_HSEON_Msk 9311 #define RCC_CR_HSERDY_Pos (17U) 9312 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ 9313 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk 9314 #define RCC_CR_HSEBYP_Pos (18U) 9315 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ 9316 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk 9317 #define RCC_CR_CSSON_Pos (19U) 9318 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ 9319 #define RCC_CR_CSSON RCC_CR_CSSON_Msk 9320 #define RCC_CR_PLLON_Pos (24U) 9321 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ 9322 #define RCC_CR_PLLON RCC_CR_PLLON_Msk 9323 #define RCC_CR_PLLRDY_Pos (25U) 9324 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ 9325 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk 9326 #define RCC_CR_PLLI2SON_Pos (26U) 9327 #define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */ 9328 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk 9329 #define RCC_CR_PLLI2SRDY_Pos (27U) 9330 #define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */ 9331 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk 9332 9333 /******************** Bit definition for RCC_PLLCFGR register ***************/ 9334 #define RCC_PLLCFGR_PLLM_Pos (0U) 9335 #define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */ 9336 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk 9337 #define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */ 9338 #define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */ 9339 #define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */ 9340 #define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */ 9341 #define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */ 9342 #define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */ 9343 9344 #define RCC_PLLCFGR_PLLN_Pos (6U) 9345 #define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */ 9346 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk 9347 #define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */ 9348 #define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */ 9349 #define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */ 9350 #define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */ 9351 #define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */ 9352 #define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */ 9353 #define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */ 9354 #define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */ 9355 #define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */ 9356 9357 #define RCC_PLLCFGR_PLLP_Pos (16U) 9358 #define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */ 9359 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk 9360 #define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */ 9361 #define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */ 9362 9363 #define RCC_PLLCFGR_PLLSRC_Pos (22U) 9364 #define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */ 9365 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk 9366 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U) 9367 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */ 9368 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk 9369 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U 9370 9371 #define RCC_PLLCFGR_PLLQ_Pos (24U) 9372 #define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */ 9373 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk 9374 #define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */ 9375 #define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */ 9376 #define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */ 9377 #define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */ 9378 9379 /******************** Bit definition for RCC_CFGR register ******************/ 9380 /*!< SW configuration */ 9381 #define RCC_CFGR_SW_Pos (0U) 9382 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ 9383 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ 9384 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ 9385 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ 9386 9387 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */ 9388 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */ 9389 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */ 9390 9391 /*!< SWS configuration */ 9392 #define RCC_CFGR_SWS_Pos (2U) 9393 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ 9394 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ 9395 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ 9396 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ 9397 9398 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */ 9399 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */ 9400 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */ 9401 9402 /*!< HPRE configuration */ 9403 #define RCC_CFGR_HPRE_Pos (4U) 9404 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ 9405 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ 9406 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ 9407 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ 9408 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ 9409 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ 9410 9411 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */ 9412 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */ 9413 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */ 9414 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */ 9415 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */ 9416 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */ 9417 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */ 9418 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */ 9419 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */ 9420 9421 /*!< PPRE1 configuration */ 9422 #define RCC_CFGR_PPRE1_Pos (10U) 9423 #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */ 9424 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ 9425 #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ 9426 #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */ 9427 #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */ 9428 9429 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */ 9430 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */ 9431 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */ 9432 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */ 9433 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */ 9434 9435 /*!< PPRE2 configuration */ 9436 #define RCC_CFGR_PPRE2_Pos (13U) 9437 #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */ 9438 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ 9439 #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ 9440 #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */ 9441 #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */ 9442 9443 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */ 9444 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */ 9445 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */ 9446 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */ 9447 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */ 9448 9449 /*!< RTCPRE configuration */ 9450 #define RCC_CFGR_RTCPRE_Pos (16U) 9451 #define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */ 9452 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk 9453 #define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */ 9454 #define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */ 9455 #define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */ 9456 #define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */ 9457 #define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */ 9458 9459 /*!< MCO1 configuration */ 9460 #define RCC_CFGR_MCO1_Pos (21U) 9461 #define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */ 9462 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk 9463 #define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */ 9464 #define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */ 9465 9466 #define RCC_CFGR_I2SSRC_Pos (23U) 9467 #define RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */ 9468 #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk 9469 9470 #define RCC_CFGR_MCO1PRE_Pos (24U) 9471 #define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */ 9472 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk 9473 #define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */ 9474 #define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */ 9475 #define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */ 9476 9477 #define RCC_CFGR_MCO2PRE_Pos (27U) 9478 #define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */ 9479 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk 9480 #define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */ 9481 #define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */ 9482 #define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */ 9483 9484 #define RCC_CFGR_MCO2_Pos (30U) 9485 #define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */ 9486 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk 9487 #define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */ 9488 #define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */ 9489 9490 /******************** Bit definition for RCC_CIR register *******************/ 9491 #define RCC_CIR_LSIRDYF_Pos (0U) 9492 #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ 9493 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk 9494 #define RCC_CIR_LSERDYF_Pos (1U) 9495 #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ 9496 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk 9497 #define RCC_CIR_HSIRDYF_Pos (2U) 9498 #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ 9499 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk 9500 #define RCC_CIR_HSERDYF_Pos (3U) 9501 #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ 9502 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk 9503 #define RCC_CIR_PLLRDYF_Pos (4U) 9504 #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ 9505 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk 9506 #define RCC_CIR_PLLI2SRDYF_Pos (5U) 9507 #define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */ 9508 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk 9509 9510 #define RCC_CIR_CSSF_Pos (7U) 9511 #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ 9512 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk 9513 #define RCC_CIR_LSIRDYIE_Pos (8U) 9514 #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ 9515 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk 9516 #define RCC_CIR_LSERDYIE_Pos (9U) 9517 #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ 9518 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk 9519 #define RCC_CIR_HSIRDYIE_Pos (10U) 9520 #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ 9521 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk 9522 #define RCC_CIR_HSERDYIE_Pos (11U) 9523 #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ 9524 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk 9525 #define RCC_CIR_PLLRDYIE_Pos (12U) 9526 #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ 9527 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk 9528 #define RCC_CIR_PLLI2SRDYIE_Pos (13U) 9529 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */ 9530 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk 9531 9532 #define RCC_CIR_LSIRDYC_Pos (16U) 9533 #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ 9534 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk 9535 #define RCC_CIR_LSERDYC_Pos (17U) 9536 #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ 9537 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk 9538 #define RCC_CIR_HSIRDYC_Pos (18U) 9539 #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ 9540 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk 9541 #define RCC_CIR_HSERDYC_Pos (19U) 9542 #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ 9543 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk 9544 #define RCC_CIR_PLLRDYC_Pos (20U) 9545 #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ 9546 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk 9547 #define RCC_CIR_PLLI2SRDYC_Pos (21U) 9548 #define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */ 9549 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk 9550 9551 #define RCC_CIR_CSSC_Pos (23U) 9552 #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ 9553 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk 9554 9555 /******************** Bit definition for RCC_AHB1RSTR register **************/ 9556 #define RCC_AHB1RSTR_GPIOARST_Pos (0U) 9557 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */ 9558 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk 9559 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U) 9560 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ 9561 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk 9562 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U) 9563 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ 9564 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk 9565 #define RCC_AHB1RSTR_GPIODRST_Pos (3U) 9566 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */ 9567 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk 9568 #define RCC_AHB1RSTR_GPIOERST_Pos (4U) 9569 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */ 9570 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk 9571 #define RCC_AHB1RSTR_GPIOFRST_Pos (5U) 9572 #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */ 9573 #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk 9574 #define RCC_AHB1RSTR_GPIOGRST_Pos (6U) 9575 #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */ 9576 #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk 9577 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U) 9578 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ 9579 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk 9580 #define RCC_AHB1RSTR_GPIOIRST_Pos (8U) 9581 #define RCC_AHB1RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */ 9582 #define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk 9583 #define RCC_AHB1RSTR_CRCRST_Pos (12U) 9584 #define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */ 9585 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk 9586 #define RCC_AHB1RSTR_DMA1RST_Pos (21U) 9587 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */ 9588 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk 9589 #define RCC_AHB1RSTR_DMA2RST_Pos (22U) 9590 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */ 9591 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk 9592 #define RCC_AHB1RSTR_ETHMACRST_Pos (25U) 9593 #define RCC_AHB1RSTR_ETHMACRST_Msk (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */ 9594 #define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk 9595 #define RCC_AHB1RSTR_OTGHRST_Pos (29U) 9596 #define RCC_AHB1RSTR_OTGHRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */ 9597 #define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk 9598 9599 /******************** Bit definition for RCC_AHB2RSTR register **************/ 9600 #define RCC_AHB2RSTR_DCMIRST_Pos (0U) 9601 #define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */ 9602 #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk 9603 #define RCC_AHB2RSTR_CRYPRST_Pos (4U) 9604 #define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */ 9605 #define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk 9606 #define RCC_AHB2RSTR_HASHRST_Pos (5U) 9607 #define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */ 9608 #define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk 9609 /* maintained for legacy purpose */ 9610 #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST 9611 #define RCC_AHB2RSTR_RNGRST_Pos (6U) 9612 #define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */ 9613 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk 9614 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U) 9615 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */ 9616 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk 9617 9618 /******************** Bit definition for RCC_AHB3RSTR register **************/ 9619 9620 #define RCC_AHB3RSTR_FSMCRST_Pos (0U) 9621 #define RCC_AHB3RSTR_FSMCRST_Msk (0x1UL << RCC_AHB3RSTR_FSMCRST_Pos) /*!< 0x00000001 */ 9622 #define RCC_AHB3RSTR_FSMCRST RCC_AHB3RSTR_FSMCRST_Msk 9623 9624 /******************** Bit definition for RCC_APB1RSTR register **************/ 9625 #define RCC_APB1RSTR_TIM2RST_Pos (0U) 9626 #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ 9627 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk 9628 #define RCC_APB1RSTR_TIM3RST_Pos (1U) 9629 #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ 9630 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk 9631 #define RCC_APB1RSTR_TIM4RST_Pos (2U) 9632 #define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ 9633 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk 9634 #define RCC_APB1RSTR_TIM5RST_Pos (3U) 9635 #define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */ 9636 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk 9637 #define RCC_APB1RSTR_TIM6RST_Pos (4U) 9638 #define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ 9639 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk 9640 #define RCC_APB1RSTR_TIM7RST_Pos (5U) 9641 #define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ 9642 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk 9643 #define RCC_APB1RSTR_TIM12RST_Pos (6U) 9644 #define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */ 9645 #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk 9646 #define RCC_APB1RSTR_TIM13RST_Pos (7U) 9647 #define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */ 9648 #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk 9649 #define RCC_APB1RSTR_TIM14RST_Pos (8U) 9650 #define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ 9651 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk 9652 #define RCC_APB1RSTR_WWDGRST_Pos (11U) 9653 #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ 9654 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk 9655 #define RCC_APB1RSTR_SPI2RST_Pos (14U) 9656 #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ 9657 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk 9658 #define RCC_APB1RSTR_SPI3RST_Pos (15U) 9659 #define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */ 9660 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk 9661 #define RCC_APB1RSTR_USART2RST_Pos (17U) 9662 #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ 9663 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk 9664 #define RCC_APB1RSTR_USART3RST_Pos (18U) 9665 #define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ 9666 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk 9667 #define RCC_APB1RSTR_UART4RST_Pos (19U) 9668 #define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */ 9669 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk 9670 #define RCC_APB1RSTR_UART5RST_Pos (20U) 9671 #define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */ 9672 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk 9673 #define RCC_APB1RSTR_I2C1RST_Pos (21U) 9674 #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ 9675 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk 9676 #define RCC_APB1RSTR_I2C2RST_Pos (22U) 9677 #define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ 9678 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk 9679 #define RCC_APB1RSTR_I2C3RST_Pos (23U) 9680 #define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */ 9681 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk 9682 #define RCC_APB1RSTR_CAN1RST_Pos (25U) 9683 #define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */ 9684 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk 9685 #define RCC_APB1RSTR_CAN2RST_Pos (26U) 9686 #define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */ 9687 #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk 9688 #define RCC_APB1RSTR_PWRRST_Pos (28U) 9689 #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ 9690 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk 9691 #define RCC_APB1RSTR_DACRST_Pos (29U) 9692 #define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ 9693 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk 9694 9695 /******************** Bit definition for RCC_APB2RSTR register **************/ 9696 #define RCC_APB2RSTR_TIM1RST_Pos (0U) 9697 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */ 9698 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk 9699 #define RCC_APB2RSTR_TIM8RST_Pos (1U) 9700 #define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */ 9701 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk 9702 #define RCC_APB2RSTR_USART1RST_Pos (4U) 9703 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */ 9704 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk 9705 #define RCC_APB2RSTR_USART6RST_Pos (5U) 9706 #define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */ 9707 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk 9708 #define RCC_APB2RSTR_ADCRST_Pos (8U) 9709 #define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */ 9710 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk 9711 #define RCC_APB2RSTR_SDIORST_Pos (11U) 9712 #define RCC_APB2RSTR_SDIORST_Msk (0x1UL << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */ 9713 #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk 9714 #define RCC_APB2RSTR_SPI1RST_Pos (12U) 9715 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ 9716 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk 9717 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U) 9718 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */ 9719 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk 9720 #define RCC_APB2RSTR_TIM9RST_Pos (16U) 9721 #define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */ 9722 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk 9723 #define RCC_APB2RSTR_TIM10RST_Pos (17U) 9724 #define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */ 9725 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk 9726 #define RCC_APB2RSTR_TIM11RST_Pos (18U) 9727 #define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */ 9728 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk 9729 9730 /* Old SPI1RST bit definition, maintained for legacy purpose */ 9731 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST 9732 9733 /******************** Bit definition for RCC_AHB1ENR register ***************/ 9734 #define RCC_AHB1ENR_GPIOAEN_Pos (0U) 9735 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */ 9736 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk 9737 #define RCC_AHB1ENR_GPIOBEN_Pos (1U) 9738 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */ 9739 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk 9740 #define RCC_AHB1ENR_GPIOCEN_Pos (2U) 9741 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */ 9742 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk 9743 #define RCC_AHB1ENR_GPIODEN_Pos (3U) 9744 #define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */ 9745 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk 9746 #define RCC_AHB1ENR_GPIOEEN_Pos (4U) 9747 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */ 9748 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk 9749 #define RCC_AHB1ENR_GPIOFEN_Pos (5U) 9750 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */ 9751 #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk 9752 #define RCC_AHB1ENR_GPIOGEN_Pos (6U) 9753 #define RCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */ 9754 #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk 9755 #define RCC_AHB1ENR_GPIOHEN_Pos (7U) 9756 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */ 9757 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk 9758 #define RCC_AHB1ENR_GPIOIEN_Pos (8U) 9759 #define RCC_AHB1ENR_GPIOIEN_Msk (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */ 9760 #define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk 9761 #define RCC_AHB1ENR_CRCEN_Pos (12U) 9762 #define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ 9763 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk 9764 #define RCC_AHB1ENR_BKPSRAMEN_Pos (18U) 9765 #define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */ 9766 #define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk 9767 #define RCC_AHB1ENR_DMA1EN_Pos (21U) 9768 #define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */ 9769 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk 9770 #define RCC_AHB1ENR_DMA2EN_Pos (22U) 9771 #define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */ 9772 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk 9773 9774 #define RCC_AHB1ENR_ETHMACEN_Pos (25U) 9775 #define RCC_AHB1ENR_ETHMACEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos) /*!< 0x02000000 */ 9776 #define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk 9777 #define RCC_AHB1ENR_ETHMACTXEN_Pos (26U) 9778 #define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */ 9779 #define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk 9780 #define RCC_AHB1ENR_ETHMACRXEN_Pos (27U) 9781 #define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */ 9782 #define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk 9783 #define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U) 9784 #define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */ 9785 #define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk 9786 #define RCC_AHB1ENR_OTGHSEN_Pos (29U) 9787 #define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */ 9788 #define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk 9789 #define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U) 9790 #define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */ 9791 #define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk 9792 9793 /******************** Bit definition for RCC_AHB2ENR register ***************/ 9794 #define RCC_AHB2ENR_DCMIEN_Pos (0U) 9795 #define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */ 9796 #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk 9797 #define RCC_AHB2ENR_CRYPEN_Pos (4U) 9798 #define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */ 9799 #define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk 9800 #define RCC_AHB2ENR_HASHEN_Pos (5U) 9801 #define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */ 9802 #define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk 9803 #define RCC_AHB2ENR_RNGEN_Pos (6U) 9804 #define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */ 9805 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk 9806 #define RCC_AHB2ENR_OTGFSEN_Pos (7U) 9807 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */ 9808 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk 9809 9810 /******************** Bit definition for RCC_AHB3ENR register ***************/ 9811 9812 #define RCC_AHB3ENR_FSMCEN_Pos (0U) 9813 #define RCC_AHB3ENR_FSMCEN_Msk (0x1UL << RCC_AHB3ENR_FSMCEN_Pos) /*!< 0x00000001 */ 9814 #define RCC_AHB3ENR_FSMCEN RCC_AHB3ENR_FSMCEN_Msk 9815 9816 /******************** Bit definition for RCC_APB1ENR register ***************/ 9817 #define RCC_APB1ENR_TIM2EN_Pos (0U) 9818 #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ 9819 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk 9820 #define RCC_APB1ENR_TIM3EN_Pos (1U) 9821 #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ 9822 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk 9823 #define RCC_APB1ENR_TIM4EN_Pos (2U) 9824 #define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ 9825 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk 9826 #define RCC_APB1ENR_TIM5EN_Pos (3U) 9827 #define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */ 9828 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk 9829 #define RCC_APB1ENR_TIM6EN_Pos (4U) 9830 #define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ 9831 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk 9832 #define RCC_APB1ENR_TIM7EN_Pos (5U) 9833 #define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */ 9834 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk 9835 #define RCC_APB1ENR_TIM12EN_Pos (6U) 9836 #define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */ 9837 #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk 9838 #define RCC_APB1ENR_TIM13EN_Pos (7U) 9839 #define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */ 9840 #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk 9841 #define RCC_APB1ENR_TIM14EN_Pos (8U) 9842 #define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */ 9843 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk 9844 #define RCC_APB1ENR_WWDGEN_Pos (11U) 9845 #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ 9846 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk 9847 #define RCC_APB1ENR_SPI2EN_Pos (14U) 9848 #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ 9849 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk 9850 #define RCC_APB1ENR_SPI3EN_Pos (15U) 9851 #define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */ 9852 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk 9853 #define RCC_APB1ENR_USART2EN_Pos (17U) 9854 #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ 9855 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk 9856 #define RCC_APB1ENR_USART3EN_Pos (18U) 9857 #define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ 9858 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk 9859 #define RCC_APB1ENR_UART4EN_Pos (19U) 9860 #define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */ 9861 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk 9862 #define RCC_APB1ENR_UART5EN_Pos (20U) 9863 #define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */ 9864 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk 9865 #define RCC_APB1ENR_I2C1EN_Pos (21U) 9866 #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ 9867 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk 9868 #define RCC_APB1ENR_I2C2EN_Pos (22U) 9869 #define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ 9870 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk 9871 #define RCC_APB1ENR_I2C3EN_Pos (23U) 9872 #define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */ 9873 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk 9874 #define RCC_APB1ENR_CAN1EN_Pos (25U) 9875 #define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */ 9876 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk 9877 #define RCC_APB1ENR_CAN2EN_Pos (26U) 9878 #define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */ 9879 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk 9880 #define RCC_APB1ENR_PWREN_Pos (28U) 9881 #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ 9882 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk 9883 #define RCC_APB1ENR_DACEN_Pos (29U) 9884 #define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */ 9885 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk 9886 9887 /******************** Bit definition for RCC_APB2ENR register ***************/ 9888 #define RCC_APB2ENR_TIM1EN_Pos (0U) 9889 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */ 9890 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk 9891 #define RCC_APB2ENR_TIM8EN_Pos (1U) 9892 #define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */ 9893 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk 9894 #define RCC_APB2ENR_USART1EN_Pos (4U) 9895 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */ 9896 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk 9897 #define RCC_APB2ENR_USART6EN_Pos (5U) 9898 #define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */ 9899 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk 9900 #define RCC_APB2ENR_ADC1EN_Pos (8U) 9901 #define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */ 9902 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk 9903 #define RCC_APB2ENR_ADC2EN_Pos (9U) 9904 #define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */ 9905 #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk 9906 #define RCC_APB2ENR_ADC3EN_Pos (10U) 9907 #define RCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */ 9908 #define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk 9909 #define RCC_APB2ENR_SDIOEN_Pos (11U) 9910 #define RCC_APB2ENR_SDIOEN_Msk (0x1UL << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */ 9911 #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk 9912 #define RCC_APB2ENR_SPI1EN_Pos (12U) 9913 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ 9914 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk 9915 #define RCC_APB2ENR_SYSCFGEN_Pos (14U) 9916 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */ 9917 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk 9918 #define RCC_APB2ENR_TIM9EN_Pos (16U) 9919 #define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */ 9920 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk 9921 #define RCC_APB2ENR_TIM10EN_Pos (17U) 9922 #define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */ 9923 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk 9924 #define RCC_APB2ENR_TIM11EN_Pos (18U) 9925 #define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */ 9926 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk 9927 9928 /******************** Bit definition for RCC_AHB1LPENR register *************/ 9929 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U) 9930 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */ 9931 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk 9932 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U) 9933 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */ 9934 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk 9935 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U) 9936 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */ 9937 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk 9938 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U) 9939 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */ 9940 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk 9941 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U) 9942 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */ 9943 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk 9944 #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U) 9945 #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */ 9946 #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk 9947 #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U) 9948 #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */ 9949 #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk 9950 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U) 9951 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */ 9952 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk 9953 #define RCC_AHB1LPENR_GPIOILPEN_Pos (8U) 9954 #define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */ 9955 #define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk 9956 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U) 9957 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */ 9958 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk 9959 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U) 9960 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */ 9961 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk 9962 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U) 9963 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */ 9964 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk 9965 #define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U) 9966 #define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */ 9967 #define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk 9968 #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U) 9969 #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */ 9970 #define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk 9971 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U) 9972 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */ 9973 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk 9974 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U) 9975 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */ 9976 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk 9977 #define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U) 9978 #define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */ 9979 #define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk 9980 #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U) 9981 #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */ 9982 #define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk 9983 #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U) 9984 #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */ 9985 #define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk 9986 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U) 9987 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */ 9988 #define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk 9989 #define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U) 9990 #define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */ 9991 #define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk 9992 #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U) 9993 #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */ 9994 #define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk 9995 9996 /******************** Bit definition for RCC_AHB2LPENR register *************/ 9997 #define RCC_AHB2LPENR_DCMILPEN_Pos (0U) 9998 #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */ 9999 #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk 10000 #define RCC_AHB2LPENR_CRYPLPEN_Pos (4U) 10001 #define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */ 10002 #define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk 10003 #define RCC_AHB2LPENR_HASHLPEN_Pos (5U) 10004 #define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */ 10005 #define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk 10006 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U) 10007 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */ 10008 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk 10009 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U) 10010 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */ 10011 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk 10012 10013 /******************** Bit definition for RCC_AHB3LPENR register *************/ 10014 10015 #define RCC_AHB3LPENR_FSMCLPEN_Pos (0U) 10016 #define RCC_AHB3LPENR_FSMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FSMCLPEN_Pos) /*!< 0x00000001 */ 10017 #define RCC_AHB3LPENR_FSMCLPEN RCC_AHB3LPENR_FSMCLPEN_Msk 10018 10019 /******************** Bit definition for RCC_APB1LPENR register *************/ 10020 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U) 10021 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */ 10022 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk 10023 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U) 10024 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */ 10025 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk 10026 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U) 10027 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */ 10028 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk 10029 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U) 10030 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */ 10031 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk 10032 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U) 10033 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */ 10034 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk 10035 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U) 10036 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */ 10037 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk 10038 #define RCC_APB1LPENR_TIM12LPEN_Pos (6U) 10039 #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */ 10040 #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk 10041 #define RCC_APB1LPENR_TIM13LPEN_Pos (7U) 10042 #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */ 10043 #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk 10044 #define RCC_APB1LPENR_TIM14LPEN_Pos (8U) 10045 #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */ 10046 #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk 10047 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U) 10048 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */ 10049 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk 10050 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U) 10051 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */ 10052 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk 10053 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U) 10054 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */ 10055 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk 10056 #define RCC_APB1LPENR_USART2LPEN_Pos (17U) 10057 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */ 10058 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk 10059 #define RCC_APB1LPENR_USART3LPEN_Pos (18U) 10060 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */ 10061 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk 10062 #define RCC_APB1LPENR_UART4LPEN_Pos (19U) 10063 #define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */ 10064 #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk 10065 #define RCC_APB1LPENR_UART5LPEN_Pos (20U) 10066 #define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */ 10067 #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk 10068 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U) 10069 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */ 10070 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk 10071 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U) 10072 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */ 10073 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk 10074 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U) 10075 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */ 10076 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk 10077 #define RCC_APB1LPENR_CAN1LPEN_Pos (25U) 10078 #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */ 10079 #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk 10080 #define RCC_APB1LPENR_CAN2LPEN_Pos (26U) 10081 #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */ 10082 #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk 10083 #define RCC_APB1LPENR_PWRLPEN_Pos (28U) 10084 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */ 10085 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk 10086 #define RCC_APB1LPENR_DACLPEN_Pos (29U) 10087 #define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */ 10088 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk 10089 10090 /******************** Bit definition for RCC_APB2LPENR register *************/ 10091 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U) 10092 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */ 10093 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk 10094 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U) 10095 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */ 10096 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk 10097 #define RCC_APB2LPENR_USART1LPEN_Pos (4U) 10098 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */ 10099 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk 10100 #define RCC_APB2LPENR_USART6LPEN_Pos (5U) 10101 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */ 10102 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk 10103 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U) 10104 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */ 10105 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk 10106 #define RCC_APB2LPENR_ADC2LPEN_Pos (9U) 10107 #define RCC_APB2LPENR_ADC2LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */ 10108 #define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk 10109 #define RCC_APB2LPENR_ADC3LPEN_Pos (10U) 10110 #define RCC_APB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */ 10111 #define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk 10112 #define RCC_APB2LPENR_SDIOLPEN_Pos (11U) 10113 #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */ 10114 #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk 10115 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U) 10116 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ 10117 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk 10118 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U) 10119 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */ 10120 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk 10121 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U) 10122 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */ 10123 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk 10124 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U) 10125 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */ 10126 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk 10127 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U) 10128 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */ 10129 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk 10130 10131 /******************** Bit definition for RCC_BDCR register ******************/ 10132 #define RCC_BDCR_LSEON_Pos (0U) 10133 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ 10134 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk 10135 #define RCC_BDCR_LSERDY_Pos (1U) 10136 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ 10137 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk 10138 #define RCC_BDCR_LSEBYP_Pos (2U) 10139 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ 10140 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk 10141 10142 #define RCC_BDCR_RTCSEL_Pos (8U) 10143 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ 10144 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk 10145 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ 10146 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ 10147 10148 #define RCC_BDCR_RTCEN_Pos (15U) 10149 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ 10150 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk 10151 #define RCC_BDCR_BDRST_Pos (16U) 10152 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ 10153 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk 10154 10155 /******************** Bit definition for RCC_CSR register *******************/ 10156 #define RCC_CSR_LSION_Pos (0U) 10157 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ 10158 #define RCC_CSR_LSION RCC_CSR_LSION_Msk 10159 #define RCC_CSR_LSIRDY_Pos (1U) 10160 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ 10161 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk 10162 #define RCC_CSR_RMVF_Pos (24U) 10163 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ 10164 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk 10165 #define RCC_CSR_BORRSTF_Pos (25U) 10166 #define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */ 10167 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk 10168 #define RCC_CSR_PINRSTF_Pos (26U) 10169 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ 10170 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk 10171 #define RCC_CSR_PORRSTF_Pos (27U) 10172 #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ 10173 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk 10174 #define RCC_CSR_SFTRSTF_Pos (28U) 10175 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ 10176 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk 10177 #define RCC_CSR_IWDGRSTF_Pos (29U) 10178 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ 10179 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk 10180 #define RCC_CSR_WWDGRSTF_Pos (30U) 10181 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ 10182 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk 10183 #define RCC_CSR_LPWRRSTF_Pos (31U) 10184 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ 10185 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk 10186 /* Legacy defines */ 10187 #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF 10188 #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF 10189 10190 /******************** Bit definition for RCC_SSCGR register *****************/ 10191 #define RCC_SSCGR_MODPER_Pos (0U) 10192 #define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */ 10193 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk 10194 #define RCC_SSCGR_INCSTEP_Pos (13U) 10195 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */ 10196 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk 10197 #define RCC_SSCGR_SPREADSEL_Pos (30U) 10198 #define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */ 10199 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk 10200 #define RCC_SSCGR_SSCGEN_Pos (31U) 10201 #define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */ 10202 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk 10203 10204 /******************** Bit definition for RCC_PLLI2SCFGR register ************/ 10205 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U) 10206 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */ 10207 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk 10208 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */ 10209 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */ 10210 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */ 10211 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */ 10212 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */ 10213 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */ 10214 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */ 10215 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */ 10216 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */ 10217 10218 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U) 10219 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */ 10220 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk 10221 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */ 10222 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */ 10223 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */ 10224 10225 /******************************************************************************/ 10226 /* */ 10227 /* RNG */ 10228 /* */ 10229 /******************************************************************************/ 10230 /******************** Bits definition for RNG_CR register *******************/ 10231 #define RNG_CR_RNGEN_Pos (2U) 10232 #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ 10233 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk 10234 #define RNG_CR_IE_Pos (3U) 10235 #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ 10236 #define RNG_CR_IE RNG_CR_IE_Msk 10237 10238 /******************** Bits definition for RNG_SR register *******************/ 10239 #define RNG_SR_DRDY_Pos (0U) 10240 #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ 10241 #define RNG_SR_DRDY RNG_SR_DRDY_Msk 10242 #define RNG_SR_CECS_Pos (1U) 10243 #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ 10244 #define RNG_SR_CECS RNG_SR_CECS_Msk 10245 #define RNG_SR_SECS_Pos (2U) 10246 #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ 10247 #define RNG_SR_SECS RNG_SR_SECS_Msk 10248 #define RNG_SR_CEIS_Pos (5U) 10249 #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ 10250 #define RNG_SR_CEIS RNG_SR_CEIS_Msk 10251 #define RNG_SR_SEIS_Pos (6U) 10252 #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ 10253 #define RNG_SR_SEIS RNG_SR_SEIS_Msk 10254 10255 /******************************************************************************/ 10256 /* */ 10257 /* Real-Time Clock (RTC) */ 10258 /* */ 10259 /******************************************************************************/ 10260 /******************** Bits definition for RTC_TR register *******************/ 10261 #define RTC_TR_PM_Pos (22U) 10262 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ 10263 #define RTC_TR_PM RTC_TR_PM_Msk 10264 #define RTC_TR_HT_Pos (20U) 10265 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ 10266 #define RTC_TR_HT RTC_TR_HT_Msk 10267 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ 10268 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ 10269 #define RTC_TR_HU_Pos (16U) 10270 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ 10271 #define RTC_TR_HU RTC_TR_HU_Msk 10272 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ 10273 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ 10274 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ 10275 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ 10276 #define RTC_TR_MNT_Pos (12U) 10277 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ 10278 #define RTC_TR_MNT RTC_TR_MNT_Msk 10279 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ 10280 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ 10281 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ 10282 #define RTC_TR_MNU_Pos (8U) 10283 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ 10284 #define RTC_TR_MNU RTC_TR_MNU_Msk 10285 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ 10286 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ 10287 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ 10288 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ 10289 #define RTC_TR_ST_Pos (4U) 10290 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ 10291 #define RTC_TR_ST RTC_TR_ST_Msk 10292 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ 10293 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ 10294 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ 10295 #define RTC_TR_SU_Pos (0U) 10296 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ 10297 #define RTC_TR_SU RTC_TR_SU_Msk 10298 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ 10299 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ 10300 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ 10301 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ 10302 10303 /******************** Bits definition for RTC_DR register *******************/ 10304 #define RTC_DR_YT_Pos (20U) 10305 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ 10306 #define RTC_DR_YT RTC_DR_YT_Msk 10307 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ 10308 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ 10309 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ 10310 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ 10311 #define RTC_DR_YU_Pos (16U) 10312 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ 10313 #define RTC_DR_YU RTC_DR_YU_Msk 10314 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ 10315 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ 10316 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ 10317 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ 10318 #define RTC_DR_WDU_Pos (13U) 10319 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ 10320 #define RTC_DR_WDU RTC_DR_WDU_Msk 10321 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ 10322 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ 10323 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ 10324 #define RTC_DR_MT_Pos (12U) 10325 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ 10326 #define RTC_DR_MT RTC_DR_MT_Msk 10327 #define RTC_DR_MU_Pos (8U) 10328 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ 10329 #define RTC_DR_MU RTC_DR_MU_Msk 10330 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ 10331 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ 10332 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ 10333 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ 10334 #define RTC_DR_DT_Pos (4U) 10335 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ 10336 #define RTC_DR_DT RTC_DR_DT_Msk 10337 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ 10338 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ 10339 #define RTC_DR_DU_Pos (0U) 10340 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ 10341 #define RTC_DR_DU RTC_DR_DU_Msk 10342 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ 10343 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ 10344 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ 10345 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ 10346 10347 /******************** Bits definition for RTC_CR register *******************/ 10348 #define RTC_CR_COE_Pos (23U) 10349 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ 10350 #define RTC_CR_COE RTC_CR_COE_Msk 10351 #define RTC_CR_OSEL_Pos (21U) 10352 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ 10353 #define RTC_CR_OSEL RTC_CR_OSEL_Msk 10354 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ 10355 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ 10356 #define RTC_CR_POL_Pos (20U) 10357 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ 10358 #define RTC_CR_POL RTC_CR_POL_Msk 10359 #define RTC_CR_BKP_Pos (18U) 10360 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ 10361 #define RTC_CR_BKP RTC_CR_BKP_Msk 10362 #define RTC_CR_SUB1H_Pos (17U) 10363 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ 10364 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk 10365 #define RTC_CR_ADD1H_Pos (16U) 10366 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ 10367 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk 10368 #define RTC_CR_TSIE_Pos (15U) 10369 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ 10370 #define RTC_CR_TSIE RTC_CR_TSIE_Msk 10371 #define RTC_CR_WUTIE_Pos (14U) 10372 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ 10373 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk 10374 #define RTC_CR_ALRBIE_Pos (13U) 10375 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ 10376 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk 10377 #define RTC_CR_ALRAIE_Pos (12U) 10378 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ 10379 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk 10380 #define RTC_CR_TSE_Pos (11U) 10381 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ 10382 #define RTC_CR_TSE RTC_CR_TSE_Msk 10383 #define RTC_CR_WUTE_Pos (10U) 10384 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ 10385 #define RTC_CR_WUTE RTC_CR_WUTE_Msk 10386 #define RTC_CR_ALRBE_Pos (9U) 10387 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ 10388 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk 10389 #define RTC_CR_ALRAE_Pos (8U) 10390 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ 10391 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk 10392 #define RTC_CR_DCE_Pos (7U) 10393 #define RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos) /*!< 0x00000080 */ 10394 #define RTC_CR_DCE RTC_CR_DCE_Msk 10395 #define RTC_CR_FMT_Pos (6U) 10396 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ 10397 #define RTC_CR_FMT RTC_CR_FMT_Msk 10398 #define RTC_CR_REFCKON_Pos (4U) 10399 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ 10400 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk 10401 #define RTC_CR_TSEDGE_Pos (3U) 10402 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ 10403 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk 10404 #define RTC_CR_WUCKSEL_Pos (0U) 10405 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ 10406 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk 10407 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ 10408 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ 10409 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ 10410 10411 /* Legacy defines */ 10412 #define RTC_CR_BCK RTC_CR_BKP 10413 10414 /******************** Bits definition for RTC_ISR register ******************/ 10415 #define RTC_ISR_TAMP1F_Pos (13U) 10416 #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */ 10417 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk 10418 #define RTC_ISR_TSOVF_Pos (12U) 10419 #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ 10420 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk 10421 #define RTC_ISR_TSF_Pos (11U) 10422 #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ 10423 #define RTC_ISR_TSF RTC_ISR_TSF_Msk 10424 #define RTC_ISR_WUTF_Pos (10U) 10425 #define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */ 10426 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk 10427 #define RTC_ISR_ALRBF_Pos (9U) 10428 #define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */ 10429 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk 10430 #define RTC_ISR_ALRAF_Pos (8U) 10431 #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ 10432 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk 10433 #define RTC_ISR_INIT_Pos (7U) 10434 #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ 10435 #define RTC_ISR_INIT RTC_ISR_INIT_Msk 10436 #define RTC_ISR_INITF_Pos (6U) 10437 #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ 10438 #define RTC_ISR_INITF RTC_ISR_INITF_Msk 10439 #define RTC_ISR_RSF_Pos (5U) 10440 #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ 10441 #define RTC_ISR_RSF RTC_ISR_RSF_Msk 10442 #define RTC_ISR_INITS_Pos (4U) 10443 #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ 10444 #define RTC_ISR_INITS RTC_ISR_INITS_Msk 10445 #define RTC_ISR_WUTWF_Pos (2U) 10446 #define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ 10447 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk 10448 #define RTC_ISR_ALRBWF_Pos (1U) 10449 #define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ 10450 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk 10451 #define RTC_ISR_ALRAWF_Pos (0U) 10452 #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ 10453 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk 10454 10455 /******************** Bits definition for RTC_PRER register *****************/ 10456 #define RTC_PRER_PREDIV_A_Pos (16U) 10457 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ 10458 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk 10459 #define RTC_PRER_PREDIV_S_Pos (0U) 10460 #define RTC_PRER_PREDIV_S_Msk (0x1FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00001FFF */ 10461 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk 10462 10463 /******************** Bits definition for RTC_WUTR register *****************/ 10464 #define RTC_WUTR_WUT_Pos (0U) 10465 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ 10466 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk 10467 10468 /******************** Bits definition for RTC_CALIBR register ***************/ 10469 #define RTC_CALIBR_DCS_Pos (7U) 10470 #define RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */ 10471 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk 10472 #define RTC_CALIBR_DC_Pos (0U) 10473 #define RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */ 10474 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk 10475 10476 /******************** Bits definition for RTC_ALRMAR register ***************/ 10477 #define RTC_ALRMAR_MSK4_Pos (31U) 10478 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ 10479 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk 10480 #define RTC_ALRMAR_WDSEL_Pos (30U) 10481 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ 10482 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk 10483 #define RTC_ALRMAR_DT_Pos (28U) 10484 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ 10485 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk 10486 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ 10487 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ 10488 #define RTC_ALRMAR_DU_Pos (24U) 10489 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ 10490 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk 10491 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ 10492 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ 10493 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ 10494 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ 10495 #define RTC_ALRMAR_MSK3_Pos (23U) 10496 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ 10497 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk 10498 #define RTC_ALRMAR_PM_Pos (22U) 10499 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ 10500 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk 10501 #define RTC_ALRMAR_HT_Pos (20U) 10502 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ 10503 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk 10504 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ 10505 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ 10506 #define RTC_ALRMAR_HU_Pos (16U) 10507 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ 10508 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk 10509 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ 10510 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ 10511 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ 10512 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ 10513 #define RTC_ALRMAR_MSK2_Pos (15U) 10514 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ 10515 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk 10516 #define RTC_ALRMAR_MNT_Pos (12U) 10517 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ 10518 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk 10519 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ 10520 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ 10521 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ 10522 #define RTC_ALRMAR_MNU_Pos (8U) 10523 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ 10524 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk 10525 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ 10526 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ 10527 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ 10528 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ 10529 #define RTC_ALRMAR_MSK1_Pos (7U) 10530 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ 10531 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk 10532 #define RTC_ALRMAR_ST_Pos (4U) 10533 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ 10534 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk 10535 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ 10536 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ 10537 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ 10538 #define RTC_ALRMAR_SU_Pos (0U) 10539 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ 10540 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk 10541 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ 10542 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ 10543 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ 10544 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ 10545 10546 /******************** Bits definition for RTC_ALRMBR register ***************/ 10547 #define RTC_ALRMBR_MSK4_Pos (31U) 10548 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ 10549 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk 10550 #define RTC_ALRMBR_WDSEL_Pos (30U) 10551 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ 10552 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk 10553 #define RTC_ALRMBR_DT_Pos (28U) 10554 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ 10555 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk 10556 #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ 10557 #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ 10558 #define RTC_ALRMBR_DU_Pos (24U) 10559 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ 10560 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk 10561 #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ 10562 #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ 10563 #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ 10564 #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ 10565 #define RTC_ALRMBR_MSK3_Pos (23U) 10566 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ 10567 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk 10568 #define RTC_ALRMBR_PM_Pos (22U) 10569 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ 10570 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk 10571 #define RTC_ALRMBR_HT_Pos (20U) 10572 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ 10573 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk 10574 #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ 10575 #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ 10576 #define RTC_ALRMBR_HU_Pos (16U) 10577 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ 10578 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk 10579 #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ 10580 #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ 10581 #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ 10582 #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ 10583 #define RTC_ALRMBR_MSK2_Pos (15U) 10584 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ 10585 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk 10586 #define RTC_ALRMBR_MNT_Pos (12U) 10587 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ 10588 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk 10589 #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ 10590 #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ 10591 #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ 10592 #define RTC_ALRMBR_MNU_Pos (8U) 10593 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ 10594 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk 10595 #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ 10596 #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ 10597 #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ 10598 #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ 10599 #define RTC_ALRMBR_MSK1_Pos (7U) 10600 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ 10601 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk 10602 #define RTC_ALRMBR_ST_Pos (4U) 10603 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ 10604 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk 10605 #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ 10606 #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ 10607 #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ 10608 #define RTC_ALRMBR_SU_Pos (0U) 10609 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ 10610 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk 10611 #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ 10612 #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ 10613 #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ 10614 #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ 10615 10616 /******************** Bits definition for RTC_WPR register ******************/ 10617 #define RTC_WPR_KEY_Pos (0U) 10618 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ 10619 #define RTC_WPR_KEY RTC_WPR_KEY_Msk 10620 10621 /******************** Bits definition for RTC_TSTR register *****************/ 10622 #define RTC_TSTR_PM_Pos (22U) 10623 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ 10624 #define RTC_TSTR_PM RTC_TSTR_PM_Msk 10625 #define RTC_TSTR_HT_Pos (20U) 10626 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ 10627 #define RTC_TSTR_HT RTC_TSTR_HT_Msk 10628 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ 10629 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ 10630 #define RTC_TSTR_HU_Pos (16U) 10631 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ 10632 #define RTC_TSTR_HU RTC_TSTR_HU_Msk 10633 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ 10634 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ 10635 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ 10636 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ 10637 #define RTC_TSTR_MNT_Pos (12U) 10638 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ 10639 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk 10640 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ 10641 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ 10642 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ 10643 #define RTC_TSTR_MNU_Pos (8U) 10644 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ 10645 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk 10646 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ 10647 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ 10648 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ 10649 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ 10650 #define RTC_TSTR_ST_Pos (4U) 10651 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ 10652 #define RTC_TSTR_ST RTC_TSTR_ST_Msk 10653 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ 10654 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ 10655 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ 10656 #define RTC_TSTR_SU_Pos (0U) 10657 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ 10658 #define RTC_TSTR_SU RTC_TSTR_SU_Msk 10659 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ 10660 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ 10661 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ 10662 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ 10663 10664 /******************** Bits definition for RTC_TSDR register *****************/ 10665 #define RTC_TSDR_WDU_Pos (13U) 10666 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ 10667 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk 10668 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ 10669 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ 10670 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ 10671 #define RTC_TSDR_MT_Pos (12U) 10672 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ 10673 #define RTC_TSDR_MT RTC_TSDR_MT_Msk 10674 #define RTC_TSDR_MU_Pos (8U) 10675 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ 10676 #define RTC_TSDR_MU RTC_TSDR_MU_Msk 10677 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ 10678 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ 10679 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ 10680 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ 10681 #define RTC_TSDR_DT_Pos (4U) 10682 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ 10683 #define RTC_TSDR_DT RTC_TSDR_DT_Msk 10684 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ 10685 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ 10686 #define RTC_TSDR_DU_Pos (0U) 10687 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ 10688 #define RTC_TSDR_DU RTC_TSDR_DU_Msk 10689 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ 10690 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ 10691 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ 10692 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ 10693 10694 /******************** Bits definition for RTC_TAFCR register ****************/ 10695 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U) 10696 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */ 10697 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk 10698 #define RTC_TAFCR_TSINSEL_Pos (17U) 10699 #define RTC_TAFCR_TSINSEL_Msk (0x1UL << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */ 10700 #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk 10701 #define RTC_TAFCR_TAMP1INSEL_Pos (16U) 10702 #define RTC_TAFCR_TAMP1INSEL_Msk (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */ 10703 #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk 10704 #define RTC_TAFCR_TAMPIE_Pos (2U) 10705 #define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ 10706 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk 10707 #define RTC_TAFCR_TAMP1TRG_Pos (1U) 10708 #define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ 10709 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk 10710 #define RTC_TAFCR_TAMP1E_Pos (0U) 10711 #define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ 10712 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk 10713 10714 /* Legacy defines */ 10715 #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL 10716 10717 /******************** Bits definition for RTC_BKP0R register ****************/ 10718 #define RTC_BKP0R_Pos (0U) 10719 #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */ 10720 #define RTC_BKP0R RTC_BKP0R_Msk 10721 10722 /******************** Bits definition for RTC_BKP1R register ****************/ 10723 #define RTC_BKP1R_Pos (0U) 10724 #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */ 10725 #define RTC_BKP1R RTC_BKP1R_Msk 10726 10727 /******************** Bits definition for RTC_BKP2R register ****************/ 10728 #define RTC_BKP2R_Pos (0U) 10729 #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */ 10730 #define RTC_BKP2R RTC_BKP2R_Msk 10731 10732 /******************** Bits definition for RTC_BKP3R register ****************/ 10733 #define RTC_BKP3R_Pos (0U) 10734 #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */ 10735 #define RTC_BKP3R RTC_BKP3R_Msk 10736 10737 /******************** Bits definition for RTC_BKP4R register ****************/ 10738 #define RTC_BKP4R_Pos (0U) 10739 #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */ 10740 #define RTC_BKP4R RTC_BKP4R_Msk 10741 10742 /******************** Bits definition for RTC_BKP5R register ****************/ 10743 #define RTC_BKP5R_Pos (0U) 10744 #define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */ 10745 #define RTC_BKP5R RTC_BKP5R_Msk 10746 10747 /******************** Bits definition for RTC_BKP6R register ****************/ 10748 #define RTC_BKP6R_Pos (0U) 10749 #define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */ 10750 #define RTC_BKP6R RTC_BKP6R_Msk 10751 10752 /******************** Bits definition for RTC_BKP7R register ****************/ 10753 #define RTC_BKP7R_Pos (0U) 10754 #define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */ 10755 #define RTC_BKP7R RTC_BKP7R_Msk 10756 10757 /******************** Bits definition for RTC_BKP8R register ****************/ 10758 #define RTC_BKP8R_Pos (0U) 10759 #define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */ 10760 #define RTC_BKP8R RTC_BKP8R_Msk 10761 10762 /******************** Bits definition for RTC_BKP9R register ****************/ 10763 #define RTC_BKP9R_Pos (0U) 10764 #define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */ 10765 #define RTC_BKP9R RTC_BKP9R_Msk 10766 10767 /******************** Bits definition for RTC_BKP10R register ***************/ 10768 #define RTC_BKP10R_Pos (0U) 10769 #define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */ 10770 #define RTC_BKP10R RTC_BKP10R_Msk 10771 10772 /******************** Bits definition for RTC_BKP11R register ***************/ 10773 #define RTC_BKP11R_Pos (0U) 10774 #define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */ 10775 #define RTC_BKP11R RTC_BKP11R_Msk 10776 10777 /******************** Bits definition for RTC_BKP12R register ***************/ 10778 #define RTC_BKP12R_Pos (0U) 10779 #define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */ 10780 #define RTC_BKP12R RTC_BKP12R_Msk 10781 10782 /******************** Bits definition for RTC_BKP13R register ***************/ 10783 #define RTC_BKP13R_Pos (0U) 10784 #define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */ 10785 #define RTC_BKP13R RTC_BKP13R_Msk 10786 10787 /******************** Bits definition for RTC_BKP14R register ***************/ 10788 #define RTC_BKP14R_Pos (0U) 10789 #define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */ 10790 #define RTC_BKP14R RTC_BKP14R_Msk 10791 10792 /******************** Bits definition for RTC_BKP15R register ***************/ 10793 #define RTC_BKP15R_Pos (0U) 10794 #define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */ 10795 #define RTC_BKP15R RTC_BKP15R_Msk 10796 10797 /******************** Bits definition for RTC_BKP16R register ***************/ 10798 #define RTC_BKP16R_Pos (0U) 10799 #define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */ 10800 #define RTC_BKP16R RTC_BKP16R_Msk 10801 10802 /******************** Bits definition for RTC_BKP17R register ***************/ 10803 #define RTC_BKP17R_Pos (0U) 10804 #define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */ 10805 #define RTC_BKP17R RTC_BKP17R_Msk 10806 10807 /******************** Bits definition for RTC_BKP18R register ***************/ 10808 #define RTC_BKP18R_Pos (0U) 10809 #define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */ 10810 #define RTC_BKP18R RTC_BKP18R_Msk 10811 10812 /******************** Bits definition for RTC_BKP19R register ***************/ 10813 #define RTC_BKP19R_Pos (0U) 10814 #define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */ 10815 #define RTC_BKP19R RTC_BKP19R_Msk 10816 10817 /******************** Number of backup registers ******************************/ 10818 #define RTC_BKP_NUMBER 0x000000014U 10819 10820 /******************************************************************************/ 10821 /* */ 10822 /* SD host Interface */ 10823 /* */ 10824 /******************************************************************************/ 10825 /****************** Bit definition for SDIO_POWER register ******************/ 10826 #define SDIO_POWER_PWRCTRL_Pos (0U) 10827 #define SDIO_POWER_PWRCTRL_Msk (0x3UL << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */ 10828 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */ 10829 #define SDIO_POWER_PWRCTRL_0 (0x1UL << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000001 */ 10830 #define SDIO_POWER_PWRCTRL_1 (0x2UL << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000002 */ 10831 10832 /****************** Bit definition for SDIO_CLKCR register ******************/ 10833 #define SDIO_CLKCR_CLKDIV_Pos (0U) 10834 #define SDIO_CLKCR_CLKDIV_Msk (0xFFUL << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */ 10835 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */ 10836 #define SDIO_CLKCR_CLKEN_Pos (8U) 10837 #define SDIO_CLKCR_CLKEN_Msk (0x1UL << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */ 10838 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */ 10839 #define SDIO_CLKCR_PWRSAV_Pos (9U) 10840 #define SDIO_CLKCR_PWRSAV_Msk (0x1UL << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */ 10841 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */ 10842 #define SDIO_CLKCR_BYPASS_Pos (10U) 10843 #define SDIO_CLKCR_BYPASS_Msk (0x1UL << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */ 10844 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */ 10845 10846 #define SDIO_CLKCR_WIDBUS_Pos (11U) 10847 #define SDIO_CLKCR_WIDBUS_Msk (0x3UL << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */ 10848 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */ 10849 #define SDIO_CLKCR_WIDBUS_0 (0x1UL << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00000800 */ 10850 #define SDIO_CLKCR_WIDBUS_1 (0x2UL << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001000 */ 10851 10852 #define SDIO_CLKCR_NEGEDGE_Pos (13U) 10853 #define SDIO_CLKCR_NEGEDGE_Msk (0x1UL << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */ 10854 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */ 10855 #define SDIO_CLKCR_HWFC_EN_Pos (14U) 10856 #define SDIO_CLKCR_HWFC_EN_Msk (0x1UL << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */ 10857 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */ 10858 10859 /******************* Bit definition for SDIO_ARG register *******************/ 10860 #define SDIO_ARG_CMDARG_Pos (0U) 10861 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */ 10862 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */ 10863 10864 /******************* Bit definition for SDIO_CMD register *******************/ 10865 #define SDIO_CMD_CMDINDEX_Pos (0U) 10866 #define SDIO_CMD_CMDINDEX_Msk (0x3FUL << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */ 10867 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */ 10868 10869 #define SDIO_CMD_WAITRESP_Pos (6U) 10870 #define SDIO_CMD_WAITRESP_Msk (0x3UL << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */ 10871 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */ 10872 #define SDIO_CMD_WAITRESP_0 (0x1UL << SDIO_CMD_WAITRESP_Pos) /*!< 0x00000040 */ 10873 #define SDIO_CMD_WAITRESP_1 (0x2UL << SDIO_CMD_WAITRESP_Pos) /*!< 0x00000080 */ 10874 10875 #define SDIO_CMD_WAITINT_Pos (8U) 10876 #define SDIO_CMD_WAITINT_Msk (0x1UL << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */ 10877 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */ 10878 #define SDIO_CMD_WAITPEND_Pos (9U) 10879 #define SDIO_CMD_WAITPEND_Msk (0x1UL << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */ 10880 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */ 10881 #define SDIO_CMD_CPSMEN_Pos (10U) 10882 #define SDIO_CMD_CPSMEN_Msk (0x1UL << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */ 10883 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */ 10884 #define SDIO_CMD_SDIOSUSPEND_Pos (11U) 10885 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */ 10886 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */ 10887 #define SDIO_CMD_ENCMDCOMPL_Pos (12U) 10888 #define SDIO_CMD_ENCMDCOMPL_Msk (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */ 10889 #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */ 10890 #define SDIO_CMD_NIEN_Pos (13U) 10891 #define SDIO_CMD_NIEN_Msk (0x1UL << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */ 10892 #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */ 10893 #define SDIO_CMD_CEATACMD_Pos (14U) 10894 #define SDIO_CMD_CEATACMD_Msk (0x1UL << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */ 10895 #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */ 10896 10897 /***************** Bit definition for SDIO_RESPCMD register *****************/ 10898 #define SDIO_RESPCMD_RESPCMD_Pos (0U) 10899 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */ 10900 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */ 10901 10902 /****************** Bit definition for SDIO_RESP0 register ******************/ 10903 #define SDIO_RESP0_CARDSTATUS0_Pos (0U) 10904 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */ 10905 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */ 10906 10907 /****************** Bit definition for SDIO_RESP1 register ******************/ 10908 #define SDIO_RESP1_CARDSTATUS1_Pos (0U) 10909 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */ 10910 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */ 10911 10912 /****************** Bit definition for SDIO_RESP2 register ******************/ 10913 #define SDIO_RESP2_CARDSTATUS2_Pos (0U) 10914 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */ 10915 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */ 10916 10917 /****************** Bit definition for SDIO_RESP3 register ******************/ 10918 #define SDIO_RESP3_CARDSTATUS3_Pos (0U) 10919 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */ 10920 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */ 10921 10922 /****************** Bit definition for SDIO_RESP4 register ******************/ 10923 #define SDIO_RESP4_CARDSTATUS4_Pos (0U) 10924 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */ 10925 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */ 10926 10927 /****************** Bit definition for SDIO_DTIMER register *****************/ 10928 #define SDIO_DTIMER_DATATIME_Pos (0U) 10929 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */ 10930 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */ 10931 10932 /****************** Bit definition for SDIO_DLEN register *******************/ 10933 #define SDIO_DLEN_DATALENGTH_Pos (0U) 10934 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */ 10935 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */ 10936 10937 /****************** Bit definition for SDIO_DCTRL register ******************/ 10938 #define SDIO_DCTRL_DTEN_Pos (0U) 10939 #define SDIO_DCTRL_DTEN_Msk (0x1UL << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */ 10940 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */ 10941 #define SDIO_DCTRL_DTDIR_Pos (1U) 10942 #define SDIO_DCTRL_DTDIR_Msk (0x1UL << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */ 10943 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */ 10944 #define SDIO_DCTRL_DTMODE_Pos (2U) 10945 #define SDIO_DCTRL_DTMODE_Msk (0x1UL << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */ 10946 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */ 10947 #define SDIO_DCTRL_DMAEN_Pos (3U) 10948 #define SDIO_DCTRL_DMAEN_Msk (0x1UL << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */ 10949 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */ 10950 10951 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U) 10952 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */ 10953 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */ 10954 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */ 10955 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */ 10956 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */ 10957 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */ 10958 10959 #define SDIO_DCTRL_RWSTART_Pos (8U) 10960 #define SDIO_DCTRL_RWSTART_Msk (0x1UL << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */ 10961 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */ 10962 #define SDIO_DCTRL_RWSTOP_Pos (9U) 10963 #define SDIO_DCTRL_RWSTOP_Msk (0x1UL << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */ 10964 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */ 10965 #define SDIO_DCTRL_RWMOD_Pos (10U) 10966 #define SDIO_DCTRL_RWMOD_Msk (0x1UL << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */ 10967 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */ 10968 #define SDIO_DCTRL_SDIOEN_Pos (11U) 10969 #define SDIO_DCTRL_SDIOEN_Msk (0x1UL << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */ 10970 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */ 10971 10972 /****************** Bit definition for SDIO_DCOUNT register *****************/ 10973 #define SDIO_DCOUNT_DATACOUNT_Pos (0U) 10974 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */ 10975 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */ 10976 10977 /****************** Bit definition for SDIO_STA register ********************/ 10978 #define SDIO_STA_CCRCFAIL_Pos (0U) 10979 #define SDIO_STA_CCRCFAIL_Msk (0x1UL << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */ 10980 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */ 10981 #define SDIO_STA_DCRCFAIL_Pos (1U) 10982 #define SDIO_STA_DCRCFAIL_Msk (0x1UL << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */ 10983 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */ 10984 #define SDIO_STA_CTIMEOUT_Pos (2U) 10985 #define SDIO_STA_CTIMEOUT_Msk (0x1UL << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */ 10986 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */ 10987 #define SDIO_STA_DTIMEOUT_Pos (3U) 10988 #define SDIO_STA_DTIMEOUT_Msk (0x1UL << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */ 10989 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */ 10990 #define SDIO_STA_TXUNDERR_Pos (4U) 10991 #define SDIO_STA_TXUNDERR_Msk (0x1UL << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */ 10992 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */ 10993 #define SDIO_STA_RXOVERR_Pos (5U) 10994 #define SDIO_STA_RXOVERR_Msk (0x1UL << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */ 10995 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */ 10996 #define SDIO_STA_CMDREND_Pos (6U) 10997 #define SDIO_STA_CMDREND_Msk (0x1UL << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */ 10998 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */ 10999 #define SDIO_STA_CMDSENT_Pos (7U) 11000 #define SDIO_STA_CMDSENT_Msk (0x1UL << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */ 11001 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */ 11002 #define SDIO_STA_DATAEND_Pos (8U) 11003 #define SDIO_STA_DATAEND_Msk (0x1UL << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */ 11004 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */ 11005 #define SDIO_STA_STBITERR_Pos (9U) 11006 #define SDIO_STA_STBITERR_Msk (0x1UL << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */ 11007 #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */ 11008 #define SDIO_STA_DBCKEND_Pos (10U) 11009 #define SDIO_STA_DBCKEND_Msk (0x1UL << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */ 11010 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */ 11011 #define SDIO_STA_CMDACT_Pos (11U) 11012 #define SDIO_STA_CMDACT_Msk (0x1UL << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */ 11013 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */ 11014 #define SDIO_STA_TXACT_Pos (12U) 11015 #define SDIO_STA_TXACT_Msk (0x1UL << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */ 11016 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */ 11017 #define SDIO_STA_RXACT_Pos (13U) 11018 #define SDIO_STA_RXACT_Msk (0x1UL << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */ 11019 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */ 11020 #define SDIO_STA_TXFIFOHE_Pos (14U) 11021 #define SDIO_STA_TXFIFOHE_Msk (0x1UL << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */ 11022 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ 11023 #define SDIO_STA_RXFIFOHF_Pos (15U) 11024 #define SDIO_STA_RXFIFOHF_Msk (0x1UL << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */ 11025 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */ 11026 #define SDIO_STA_TXFIFOF_Pos (16U) 11027 #define SDIO_STA_TXFIFOF_Msk (0x1UL << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */ 11028 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */ 11029 #define SDIO_STA_RXFIFOF_Pos (17U) 11030 #define SDIO_STA_RXFIFOF_Msk (0x1UL << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */ 11031 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */ 11032 #define SDIO_STA_TXFIFOE_Pos (18U) 11033 #define SDIO_STA_TXFIFOE_Msk (0x1UL << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */ 11034 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */ 11035 #define SDIO_STA_RXFIFOE_Pos (19U) 11036 #define SDIO_STA_RXFIFOE_Msk (0x1UL << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */ 11037 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */ 11038 #define SDIO_STA_TXDAVL_Pos (20U) 11039 #define SDIO_STA_TXDAVL_Msk (0x1UL << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */ 11040 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */ 11041 #define SDIO_STA_RXDAVL_Pos (21U) 11042 #define SDIO_STA_RXDAVL_Msk (0x1UL << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */ 11043 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */ 11044 #define SDIO_STA_SDIOIT_Pos (22U) 11045 #define SDIO_STA_SDIOIT_Msk (0x1UL << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */ 11046 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */ 11047 #define SDIO_STA_CEATAEND_Pos (23U) 11048 #define SDIO_STA_CEATAEND_Msk (0x1UL << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */ 11049 #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion signal received for CMD61 */ 11050 11051 /******************* Bit definition for SDIO_ICR register *******************/ 11052 #define SDIO_ICR_CCRCFAILC_Pos (0U) 11053 #define SDIO_ICR_CCRCFAILC_Msk (0x1UL << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */ 11054 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */ 11055 #define SDIO_ICR_DCRCFAILC_Pos (1U) 11056 #define SDIO_ICR_DCRCFAILC_Msk (0x1UL << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */ 11057 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */ 11058 #define SDIO_ICR_CTIMEOUTC_Pos (2U) 11059 #define SDIO_ICR_CTIMEOUTC_Msk (0x1UL << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */ 11060 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */ 11061 #define SDIO_ICR_DTIMEOUTC_Pos (3U) 11062 #define SDIO_ICR_DTIMEOUTC_Msk (0x1UL << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */ 11063 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */ 11064 #define SDIO_ICR_TXUNDERRC_Pos (4U) 11065 #define SDIO_ICR_TXUNDERRC_Msk (0x1UL << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */ 11066 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */ 11067 #define SDIO_ICR_RXOVERRC_Pos (5U) 11068 #define SDIO_ICR_RXOVERRC_Msk (0x1UL << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */ 11069 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */ 11070 #define SDIO_ICR_CMDRENDC_Pos (6U) 11071 #define SDIO_ICR_CMDRENDC_Msk (0x1UL << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */ 11072 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */ 11073 #define SDIO_ICR_CMDSENTC_Pos (7U) 11074 #define SDIO_ICR_CMDSENTC_Msk (0x1UL << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */ 11075 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */ 11076 #define SDIO_ICR_DATAENDC_Pos (8U) 11077 #define SDIO_ICR_DATAENDC_Msk (0x1UL << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */ 11078 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */ 11079 #define SDIO_ICR_STBITERRC_Pos (9U) 11080 #define SDIO_ICR_STBITERRC_Msk (0x1UL << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */ 11081 #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */ 11082 #define SDIO_ICR_DBCKENDC_Pos (10U) 11083 #define SDIO_ICR_DBCKENDC_Msk (0x1UL << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */ 11084 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */ 11085 #define SDIO_ICR_SDIOITC_Pos (22U) 11086 #define SDIO_ICR_SDIOITC_Msk (0x1UL << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */ 11087 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */ 11088 #define SDIO_ICR_CEATAENDC_Pos (23U) 11089 #define SDIO_ICR_CEATAENDC_Msk (0x1UL << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */ 11090 #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!<CEATAEND flag clear bit */ 11091 11092 /****************** Bit definition for SDIO_MASK register *******************/ 11093 #define SDIO_MASK_CCRCFAILIE_Pos (0U) 11094 #define SDIO_MASK_CCRCFAILIE_Msk (0x1UL << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */ 11095 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */ 11096 #define SDIO_MASK_DCRCFAILIE_Pos (1U) 11097 #define SDIO_MASK_DCRCFAILIE_Msk (0x1UL << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */ 11098 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */ 11099 #define SDIO_MASK_CTIMEOUTIE_Pos (2U) 11100 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */ 11101 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */ 11102 #define SDIO_MASK_DTIMEOUTIE_Pos (3U) 11103 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */ 11104 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */ 11105 #define SDIO_MASK_TXUNDERRIE_Pos (4U) 11106 #define SDIO_MASK_TXUNDERRIE_Msk (0x1UL << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */ 11107 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */ 11108 #define SDIO_MASK_RXOVERRIE_Pos (5U) 11109 #define SDIO_MASK_RXOVERRIE_Msk (0x1UL << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */ 11110 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */ 11111 #define SDIO_MASK_CMDRENDIE_Pos (6U) 11112 #define SDIO_MASK_CMDRENDIE_Msk (0x1UL << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */ 11113 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */ 11114 #define SDIO_MASK_CMDSENTIE_Pos (7U) 11115 #define SDIO_MASK_CMDSENTIE_Msk (0x1UL << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */ 11116 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */ 11117 #define SDIO_MASK_DATAENDIE_Pos (8U) 11118 #define SDIO_MASK_DATAENDIE_Msk (0x1UL << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */ 11119 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */ 11120 #define SDIO_MASK_STBITERRIE_Pos (9U) 11121 #define SDIO_MASK_STBITERRIE_Msk (0x1UL << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */ 11122 #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt Enable */ 11123 #define SDIO_MASK_DBCKENDIE_Pos (10U) 11124 #define SDIO_MASK_DBCKENDIE_Msk (0x1UL << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */ 11125 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */ 11126 #define SDIO_MASK_CMDACTIE_Pos (11U) 11127 #define SDIO_MASK_CMDACTIE_Msk (0x1UL << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */ 11128 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */ 11129 #define SDIO_MASK_TXACTIE_Pos (12U) 11130 #define SDIO_MASK_TXACTIE_Msk (0x1UL << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */ 11131 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */ 11132 #define SDIO_MASK_RXACTIE_Pos (13U) 11133 #define SDIO_MASK_RXACTIE_Msk (0x1UL << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */ 11134 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */ 11135 #define SDIO_MASK_TXFIFOHEIE_Pos (14U) 11136 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */ 11137 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */ 11138 #define SDIO_MASK_RXFIFOHFIE_Pos (15U) 11139 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */ 11140 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */ 11141 #define SDIO_MASK_TXFIFOFIE_Pos (16U) 11142 #define SDIO_MASK_TXFIFOFIE_Msk (0x1UL << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */ 11143 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */ 11144 #define SDIO_MASK_RXFIFOFIE_Pos (17U) 11145 #define SDIO_MASK_RXFIFOFIE_Msk (0x1UL << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */ 11146 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */ 11147 #define SDIO_MASK_TXFIFOEIE_Pos (18U) 11148 #define SDIO_MASK_TXFIFOEIE_Msk (0x1UL << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */ 11149 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */ 11150 #define SDIO_MASK_RXFIFOEIE_Pos (19U) 11151 #define SDIO_MASK_RXFIFOEIE_Msk (0x1UL << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */ 11152 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */ 11153 #define SDIO_MASK_TXDAVLIE_Pos (20U) 11154 #define SDIO_MASK_TXDAVLIE_Msk (0x1UL << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */ 11155 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */ 11156 #define SDIO_MASK_RXDAVLIE_Pos (21U) 11157 #define SDIO_MASK_RXDAVLIE_Msk (0x1UL << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */ 11158 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */ 11159 #define SDIO_MASK_SDIOITIE_Pos (22U) 11160 #define SDIO_MASK_SDIOITIE_Msk (0x1UL << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */ 11161 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */ 11162 #define SDIO_MASK_CEATAENDIE_Pos (23U) 11163 #define SDIO_MASK_CEATAENDIE_Msk (0x1UL << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */ 11164 #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion signal received Interrupt Enable */ 11165 11166 /***************** Bit definition for SDIO_FIFOCNT register *****************/ 11167 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U) 11168 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */ 11169 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */ 11170 11171 /****************** Bit definition for SDIO_FIFO register *******************/ 11172 #define SDIO_FIFO_FIFODATA_Pos (0U) 11173 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */ 11174 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */ 11175 11176 /******************************************************************************/ 11177 /* */ 11178 /* Serial Peripheral Interface */ 11179 /* */ 11180 /******************************************************************************/ 11181 /******************* Bit definition for SPI_CR1 register ********************/ 11182 #define SPI_CR1_CPHA_Pos (0U) 11183 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ 11184 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */ 11185 #define SPI_CR1_CPOL_Pos (1U) 11186 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ 11187 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */ 11188 #define SPI_CR1_MSTR_Pos (2U) 11189 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ 11190 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */ 11191 11192 #define SPI_CR1_BR_Pos (3U) 11193 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */ 11194 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */ 11195 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */ 11196 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */ 11197 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */ 11198 11199 #define SPI_CR1_SPE_Pos (6U) 11200 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ 11201 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */ 11202 #define SPI_CR1_LSBFIRST_Pos (7U) 11203 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ 11204 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */ 11205 #define SPI_CR1_SSI_Pos (8U) 11206 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ 11207 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */ 11208 #define SPI_CR1_SSM_Pos (9U) 11209 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ 11210 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */ 11211 #define SPI_CR1_RXONLY_Pos (10U) 11212 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ 11213 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */ 11214 #define SPI_CR1_DFF_Pos (11U) 11215 #define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */ 11216 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */ 11217 #define SPI_CR1_CRCNEXT_Pos (12U) 11218 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ 11219 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */ 11220 #define SPI_CR1_CRCEN_Pos (13U) 11221 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ 11222 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */ 11223 #define SPI_CR1_BIDIOE_Pos (14U) 11224 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ 11225 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */ 11226 #define SPI_CR1_BIDIMODE_Pos (15U) 11227 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ 11228 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */ 11229 11230 /******************* Bit definition for SPI_CR2 register ********************/ 11231 #define SPI_CR2_RXDMAEN_Pos (0U) 11232 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ 11233 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */ 11234 #define SPI_CR2_TXDMAEN_Pos (1U) 11235 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ 11236 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */ 11237 #define SPI_CR2_SSOE_Pos (2U) 11238 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ 11239 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */ 11240 #define SPI_CR2_FRF_Pos (4U) 11241 #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ 11242 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */ 11243 #define SPI_CR2_ERRIE_Pos (5U) 11244 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ 11245 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */ 11246 #define SPI_CR2_RXNEIE_Pos (6U) 11247 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ 11248 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */ 11249 #define SPI_CR2_TXEIE_Pos (7U) 11250 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ 11251 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */ 11252 11253 /******************** Bit definition for SPI_SR register ********************/ 11254 #define SPI_SR_RXNE_Pos (0U) 11255 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ 11256 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */ 11257 #define SPI_SR_TXE_Pos (1U) 11258 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */ 11259 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */ 11260 #define SPI_SR_CHSIDE_Pos (2U) 11261 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ 11262 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */ 11263 #define SPI_SR_UDR_Pos (3U) 11264 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ 11265 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */ 11266 #define SPI_SR_CRCERR_Pos (4U) 11267 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ 11268 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */ 11269 #define SPI_SR_MODF_Pos (5U) 11270 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */ 11271 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */ 11272 #define SPI_SR_OVR_Pos (6U) 11273 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */ 11274 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */ 11275 #define SPI_SR_BSY_Pos (7U) 11276 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */ 11277 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */ 11278 #define SPI_SR_FRE_Pos (8U) 11279 #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */ 11280 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */ 11281 11282 /******************** Bit definition for SPI_DR register ********************/ 11283 #define SPI_DR_DR_Pos (0U) 11284 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ 11285 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */ 11286 11287 /******************* Bit definition for SPI_CRCPR register ******************/ 11288 #define SPI_CRCPR_CRCPOLY_Pos (0U) 11289 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ 11290 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */ 11291 11292 /****************** Bit definition for SPI_RXCRCR register ******************/ 11293 #define SPI_RXCRCR_RXCRC_Pos (0U) 11294 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ 11295 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */ 11296 11297 /****************** Bit definition for SPI_TXCRCR register ******************/ 11298 #define SPI_TXCRCR_TXCRC_Pos (0U) 11299 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ 11300 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */ 11301 11302 /****************** Bit definition for SPI_I2SCFGR register *****************/ 11303 #define SPI_I2SCFGR_CHLEN_Pos (0U) 11304 #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */ 11305 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */ 11306 11307 #define SPI_I2SCFGR_DATLEN_Pos (1U) 11308 #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */ 11309 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */ 11310 #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */ 11311 #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */ 11312 11313 #define SPI_I2SCFGR_CKPOL_Pos (3U) 11314 #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */ 11315 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */ 11316 11317 #define SPI_I2SCFGR_I2SSTD_Pos (4U) 11318 #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */ 11319 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */ 11320 #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */ 11321 #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */ 11322 11323 #define SPI_I2SCFGR_PCMSYNC_Pos (7U) 11324 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */ 11325 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */ 11326 11327 #define SPI_I2SCFGR_I2SCFG_Pos (8U) 11328 #define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */ 11329 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */ 11330 #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */ 11331 #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */ 11332 11333 #define SPI_I2SCFGR_I2SE_Pos (10U) 11334 #define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */ 11335 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */ 11336 #define SPI_I2SCFGR_I2SMOD_Pos (11U) 11337 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ 11338 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */ 11339 11340 /****************** Bit definition for SPI_I2SPR register *******************/ 11341 #define SPI_I2SPR_I2SDIV_Pos (0U) 11342 #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */ 11343 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */ 11344 #define SPI_I2SPR_ODD_Pos (8U) 11345 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */ 11346 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */ 11347 #define SPI_I2SPR_MCKOE_Pos (9U) 11348 #define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */ 11349 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */ 11350 11351 /******************************************************************************/ 11352 /* */ 11353 /* SYSCFG */ 11354 /* */ 11355 /******************************************************************************/ 11356 /****************** Bit definition for SYSCFG_MEMRMP register ***************/ 11357 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U) 11358 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */ 11359 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!<SYSCFG_Memory Remap Config */ 11360 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */ 11361 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */ 11362 /****************** Bit definition for SYSCFG_PMC register ******************/ 11363 #define SYSCFG_PMC_MII_RMII_SEL_Pos (23U) 11364 #define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */ 11365 #define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */ 11366 11367 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ 11368 #define SYSCFG_EXTICR1_EXTI0_Pos (0U) 11369 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ 11370 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */ 11371 #define SYSCFG_EXTICR1_EXTI1_Pos (4U) 11372 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ 11373 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */ 11374 #define SYSCFG_EXTICR1_EXTI2_Pos (8U) 11375 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ 11376 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */ 11377 #define SYSCFG_EXTICR1_EXTI3_Pos (12U) 11378 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ 11379 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */ 11380 /** 11381 * @brief EXTI0 configuration 11382 */ 11383 #define SYSCFG_EXTICR1_EXTI0_PA 0x00000000U /*!<PA[0] pin */ 11384 #define SYSCFG_EXTICR1_EXTI0_PB 0x00000001U /*!<PB[0] pin */ 11385 #define SYSCFG_EXTICR1_EXTI0_PC 0x00000002U /*!<PC[0] pin */ 11386 #define SYSCFG_EXTICR1_EXTI0_PD 0x00000003U /*!<PD[0] pin */ 11387 #define SYSCFG_EXTICR1_EXTI0_PE 0x00000004U /*!<PE[0] pin */ 11388 #define SYSCFG_EXTICR1_EXTI0_PF 0x00000005U /*!<PF[0] pin */ 11389 #define SYSCFG_EXTICR1_EXTI0_PG 0x00000006U /*!<PG[0] pin */ 11390 #define SYSCFG_EXTICR1_EXTI0_PH 0x00000007U /*!<PH[0] pin */ 11391 #define SYSCFG_EXTICR1_EXTI0_PI 0x00000008U /*!<PI[0] pin */ 11392 /** 11393 * @brief EXTI1 configuration 11394 */ 11395 #define SYSCFG_EXTICR1_EXTI1_PA 0x00000000U /*!<PA[1] pin */ 11396 #define SYSCFG_EXTICR1_EXTI1_PB 0x00000010U /*!<PB[1] pin */ 11397 #define SYSCFG_EXTICR1_EXTI1_PC 0x00000020U /*!<PC[1] pin */ 11398 #define SYSCFG_EXTICR1_EXTI1_PD 0x00000030U /*!<PD[1] pin */ 11399 #define SYSCFG_EXTICR1_EXTI1_PE 0x00000040U /*!<PE[1] pin */ 11400 #define SYSCFG_EXTICR1_EXTI1_PF 0x00000050U /*!<PF[1] pin */ 11401 #define SYSCFG_EXTICR1_EXTI1_PG 0x00000060U /*!<PG[1] pin */ 11402 #define SYSCFG_EXTICR1_EXTI1_PH 0x00000070U /*!<PH[1] pin */ 11403 #define SYSCFG_EXTICR1_EXTI1_PI 0x00000080U /*!<PI[1] pin */ 11404 /** 11405 * @brief EXTI2 configuration 11406 */ 11407 #define SYSCFG_EXTICR1_EXTI2_PA 0x00000000U /*!<PA[2] pin */ 11408 #define SYSCFG_EXTICR1_EXTI2_PB 0x00000100U /*!<PB[2] pin */ 11409 #define SYSCFG_EXTICR1_EXTI2_PC 0x00000200U /*!<PC[2] pin */ 11410 #define SYSCFG_EXTICR1_EXTI2_PD 0x00000300U /*!<PD[2] pin */ 11411 #define SYSCFG_EXTICR1_EXTI2_PE 0x00000400U /*!<PE[2] pin */ 11412 #define SYSCFG_EXTICR1_EXTI2_PF 0x00000500U /*!<PF[2] pin */ 11413 #define SYSCFG_EXTICR1_EXTI2_PG 0x00000600U /*!<PG[2] pin */ 11414 #define SYSCFG_EXTICR1_EXTI2_PH 0x00000700U /*!<PH[2] pin */ 11415 #define SYSCFG_EXTICR1_EXTI2_PI 0x00000800U /*!<PI[2] pin */ 11416 /** 11417 * @brief EXTI3 configuration 11418 */ 11419 #define SYSCFG_EXTICR1_EXTI3_PA 0x00000000U /*!<PA[3] pin */ 11420 #define SYSCFG_EXTICR1_EXTI3_PB 0x00001000U /*!<PB[3] pin */ 11421 #define SYSCFG_EXTICR1_EXTI3_PC 0x00002000U /*!<PC[3] pin */ 11422 #define SYSCFG_EXTICR1_EXTI3_PD 0x00003000U /*!<PD[3] pin */ 11423 #define SYSCFG_EXTICR1_EXTI3_PE 0x00004000U /*!<PE[3] pin */ 11424 #define SYSCFG_EXTICR1_EXTI3_PF 0x00005000U /*!<PF[3] pin */ 11425 #define SYSCFG_EXTICR1_EXTI3_PG 0x00006000U /*!<PG[3] pin */ 11426 #define SYSCFG_EXTICR1_EXTI3_PH 0x00007000U /*!<PH[3] pin */ 11427 #define SYSCFG_EXTICR1_EXTI3_PI 0x00008000U /*!<PI[3] pin */ 11428 11429 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ 11430 #define SYSCFG_EXTICR2_EXTI4_Pos (0U) 11431 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ 11432 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */ 11433 #define SYSCFG_EXTICR2_EXTI5_Pos (4U) 11434 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ 11435 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */ 11436 #define SYSCFG_EXTICR2_EXTI6_Pos (8U) 11437 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ 11438 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */ 11439 #define SYSCFG_EXTICR2_EXTI7_Pos (12U) 11440 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ 11441 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */ 11442 /** 11443 * @brief EXTI4 configuration 11444 */ 11445 #define SYSCFG_EXTICR2_EXTI4_PA 0x00000000U /*!<PA[4] pin */ 11446 #define SYSCFG_EXTICR2_EXTI4_PB 0x00000001U /*!<PB[4] pin */ 11447 #define SYSCFG_EXTICR2_EXTI4_PC 0x00000002U /*!<PC[4] pin */ 11448 #define SYSCFG_EXTICR2_EXTI4_PD 0x00000003U /*!<PD[4] pin */ 11449 #define SYSCFG_EXTICR2_EXTI4_PE 0x00000004U /*!<PE[4] pin */ 11450 #define SYSCFG_EXTICR2_EXTI4_PF 0x00000005U /*!<PF[4] pin */ 11451 #define SYSCFG_EXTICR2_EXTI4_PG 0x00000006U /*!<PG[4] pin */ 11452 #define SYSCFG_EXTICR2_EXTI4_PH 0x00000007U /*!<PH[4] pin */ 11453 #define SYSCFG_EXTICR2_EXTI4_PI 0x00000008U /*!<PI[4] pin */ 11454 /** 11455 * @brief EXTI5 configuration 11456 */ 11457 #define SYSCFG_EXTICR2_EXTI5_PA 0x00000000U /*!<PA[5] pin */ 11458 #define SYSCFG_EXTICR2_EXTI5_PB 0x00000010U /*!<PB[5] pin */ 11459 #define SYSCFG_EXTICR2_EXTI5_PC 0x00000020U /*!<PC[5] pin */ 11460 #define SYSCFG_EXTICR2_EXTI5_PD 0x00000030U /*!<PD[5] pin */ 11461 #define SYSCFG_EXTICR2_EXTI5_PE 0x00000040U /*!<PE[5] pin */ 11462 #define SYSCFG_EXTICR2_EXTI5_PF 0x00000050U /*!<PF[5] pin */ 11463 #define SYSCFG_EXTICR2_EXTI5_PG 0x00000060U /*!<PG[5] pin */ 11464 #define SYSCFG_EXTICR2_EXTI5_PH 0x00000070U /*!<PH[5] pin */ 11465 #define SYSCFG_EXTICR2_EXTI5_PI 0x00000080U /*!<PI[5] pin */ 11466 /** 11467 * @brief EXTI6 configuration 11468 */ 11469 #define SYSCFG_EXTICR2_EXTI6_PA 0x00000000U /*!<PA[6] pin */ 11470 #define SYSCFG_EXTICR2_EXTI6_PB 0x00000100U /*!<PB[6] pin */ 11471 #define SYSCFG_EXTICR2_EXTI6_PC 0x00000200U /*!<PC[6] pin */ 11472 #define SYSCFG_EXTICR2_EXTI6_PD 0x00000300U /*!<PD[6] pin */ 11473 #define SYSCFG_EXTICR2_EXTI6_PE 0x00000400U /*!<PE[6] pin */ 11474 #define SYSCFG_EXTICR2_EXTI6_PF 0x00000500U /*!<PF[6] pin */ 11475 #define SYSCFG_EXTICR2_EXTI6_PG 0x00000600U /*!<PG[6] pin */ 11476 #define SYSCFG_EXTICR2_EXTI6_PH 0x00000700U /*!<PH[6] pin */ 11477 #define SYSCFG_EXTICR2_EXTI6_PI 0x00000800U /*!<PI[6] pin */ 11478 /** 11479 * @brief EXTI7 configuration 11480 */ 11481 #define SYSCFG_EXTICR2_EXTI7_PA 0x00000000U /*!<PA[7] pin */ 11482 #define SYSCFG_EXTICR2_EXTI7_PB 0x00001000U /*!<PB[7] pin */ 11483 #define SYSCFG_EXTICR2_EXTI7_PC 0x00002000U /*!<PC[7] pin */ 11484 #define SYSCFG_EXTICR2_EXTI7_PD 0x00003000U /*!<PD[7] pin */ 11485 #define SYSCFG_EXTICR2_EXTI7_PE 0x00004000U /*!<PE[7] pin */ 11486 #define SYSCFG_EXTICR2_EXTI7_PF 0x00005000U /*!<PF[7] pin */ 11487 #define SYSCFG_EXTICR2_EXTI7_PG 0x00006000U /*!<PG[7] pin */ 11488 #define SYSCFG_EXTICR2_EXTI7_PH 0x00007000U /*!<PH[7] pin */ 11489 #define SYSCFG_EXTICR2_EXTI7_PI 0x00008000U /*!<PI[7] pin */ 11490 11491 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ 11492 #define SYSCFG_EXTICR3_EXTI8_Pos (0U) 11493 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ 11494 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */ 11495 #define SYSCFG_EXTICR3_EXTI9_Pos (4U) 11496 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ 11497 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */ 11498 #define SYSCFG_EXTICR3_EXTI10_Pos (8U) 11499 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ 11500 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */ 11501 #define SYSCFG_EXTICR3_EXTI11_Pos (12U) 11502 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ 11503 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */ 11504 11505 /** 11506 * @brief EXTI8 configuration 11507 */ 11508 #define SYSCFG_EXTICR3_EXTI8_PA 0x00000000U /*!<PA[8] pin */ 11509 #define SYSCFG_EXTICR3_EXTI8_PB 0x00000001U /*!<PB[8] pin */ 11510 #define SYSCFG_EXTICR3_EXTI8_PC 0x00000002U /*!<PC[8] pin */ 11511 #define SYSCFG_EXTICR3_EXTI8_PD 0x00000003U /*!<PD[8] pin */ 11512 #define SYSCFG_EXTICR3_EXTI8_PE 0x00000004U /*!<PE[8] pin */ 11513 #define SYSCFG_EXTICR3_EXTI8_PF 0x00000005U /*!<PF[8] pin */ 11514 #define SYSCFG_EXTICR3_EXTI8_PG 0x00000006U /*!<PG[8] pin */ 11515 #define SYSCFG_EXTICR3_EXTI8_PH 0x00000007U /*!<PH[8] pin */ 11516 #define SYSCFG_EXTICR3_EXTI8_PI 0x00000008U /*!<PI[8] pin */ 11517 /** 11518 * @brief EXTI9 configuration 11519 */ 11520 #define SYSCFG_EXTICR3_EXTI9_PA 0x00000000U /*!<PA[9] pin */ 11521 #define SYSCFG_EXTICR3_EXTI9_PB 0x00000010U /*!<PB[9] pin */ 11522 #define SYSCFG_EXTICR3_EXTI9_PC 0x00000020U /*!<PC[9] pin */ 11523 #define SYSCFG_EXTICR3_EXTI9_PD 0x00000030U /*!<PD[9] pin */ 11524 #define SYSCFG_EXTICR3_EXTI9_PE 0x00000040U /*!<PE[9] pin */ 11525 #define SYSCFG_EXTICR3_EXTI9_PF 0x00000050U /*!<PF[9] pin */ 11526 #define SYSCFG_EXTICR3_EXTI9_PG 0x00000060U /*!<PG[9] pin */ 11527 #define SYSCFG_EXTICR3_EXTI9_PH 0x00000070U /*!<PH[9] pin */ 11528 #define SYSCFG_EXTICR3_EXTI9_PI 0x00000080U /*!<PI[9] pin */ 11529 /** 11530 * @brief EXTI10 configuration 11531 */ 11532 #define SYSCFG_EXTICR3_EXTI10_PA 0x00000000U /*!<PA[10] pin */ 11533 #define SYSCFG_EXTICR3_EXTI10_PB 0x00000100U /*!<PB[10] pin */ 11534 #define SYSCFG_EXTICR3_EXTI10_PC 0x00000200U /*!<PC[10] pin */ 11535 #define SYSCFG_EXTICR3_EXTI10_PD 0x00000300U /*!<PD[10] pin */ 11536 #define SYSCFG_EXTICR3_EXTI10_PE 0x00000400U /*!<PE[10] pin */ 11537 #define SYSCFG_EXTICR3_EXTI10_PF 0x00000500U /*!<PF[10] pin */ 11538 #define SYSCFG_EXTICR3_EXTI10_PG 0x00000600U /*!<PG[10] pin */ 11539 #define SYSCFG_EXTICR3_EXTI10_PH 0x00000700U /*!<PH[10] pin */ 11540 #define SYSCFG_EXTICR3_EXTI10_PI 0x00000800U /*!<PI[10] pin */ 11541 /** 11542 * @brief EXTI11 configuration 11543 */ 11544 #define SYSCFG_EXTICR3_EXTI11_PA 0x00000000U /*!<PA[11] pin */ 11545 #define SYSCFG_EXTICR3_EXTI11_PB 0x00001000U /*!<PB[11] pin */ 11546 #define SYSCFG_EXTICR3_EXTI11_PC 0x00002000U /*!<PC[11] pin */ 11547 #define SYSCFG_EXTICR3_EXTI11_PD 0x00003000U /*!<PD[11] pin */ 11548 #define SYSCFG_EXTICR3_EXTI11_PE 0x00004000U /*!<PE[11] pin */ 11549 #define SYSCFG_EXTICR3_EXTI11_PF 0x00005000U /*!<PF[11] pin */ 11550 #define SYSCFG_EXTICR3_EXTI11_PG 0x00006000U /*!<PG[11] pin */ 11551 #define SYSCFG_EXTICR3_EXTI11_PH 0x00007000U /*!<PH[11] pin */ 11552 #define SYSCFG_EXTICR3_EXTI11_PI 0x00008000U /*!<PI[11] pin */ 11553 11554 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ 11555 #define SYSCFG_EXTICR4_EXTI12_Pos (0U) 11556 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ 11557 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */ 11558 #define SYSCFG_EXTICR4_EXTI13_Pos (4U) 11559 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ 11560 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */ 11561 #define SYSCFG_EXTICR4_EXTI14_Pos (8U) 11562 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ 11563 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */ 11564 #define SYSCFG_EXTICR4_EXTI15_Pos (12U) 11565 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ 11566 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */ 11567 /** 11568 * @brief EXTI12 configuration 11569 */ 11570 #define SYSCFG_EXTICR4_EXTI12_PA 0x00000000U /*!<PA[12] pin */ 11571 #define SYSCFG_EXTICR4_EXTI12_PB 0x00000001U /*!<PB[12] pin */ 11572 #define SYSCFG_EXTICR4_EXTI12_PC 0x00000002U /*!<PC[12] pin */ 11573 #define SYSCFG_EXTICR4_EXTI12_PD 0x00000003U /*!<PD[12] pin */ 11574 #define SYSCFG_EXTICR4_EXTI12_PE 0x00000004U /*!<PE[12] pin */ 11575 #define SYSCFG_EXTICR4_EXTI12_PF 0x00000005U /*!<PF[12] pin */ 11576 #define SYSCFG_EXTICR4_EXTI12_PG 0x00000006U /*!<PG[12] pin */ 11577 #define SYSCFG_EXTICR3_EXTI12_PH 0x00000007U /*!<PH[12] pin */ 11578 /** 11579 * @brief EXTI13 configuration 11580 */ 11581 #define SYSCFG_EXTICR4_EXTI13_PA 0x00000000U /*!<PA[13] pin */ 11582 #define SYSCFG_EXTICR4_EXTI13_PB 0x00000010U /*!<PB[13] pin */ 11583 #define SYSCFG_EXTICR4_EXTI13_PC 0x00000020U /*!<PC[13] pin */ 11584 #define SYSCFG_EXTICR4_EXTI13_PD 0x00000030U /*!<PD[13] pin */ 11585 #define SYSCFG_EXTICR4_EXTI13_PE 0x00000040U /*!<PE[13] pin */ 11586 #define SYSCFG_EXTICR4_EXTI13_PF 0x00000050U /*!<PF[13] pin */ 11587 #define SYSCFG_EXTICR4_EXTI13_PG 0x00000060U /*!<PG[13] pin */ 11588 #define SYSCFG_EXTICR3_EXTI13_PH 0x00000070U /*!<PH[13] pin */ 11589 /** 11590 * @brief EXTI14 configuration 11591 */ 11592 #define SYSCFG_EXTICR4_EXTI14_PA 0x00000000U /*!<PA[14] pin */ 11593 #define SYSCFG_EXTICR4_EXTI14_PB 0x00000100U /*!<PB[14] pin */ 11594 #define SYSCFG_EXTICR4_EXTI14_PC 0x00000200U /*!<PC[14] pin */ 11595 #define SYSCFG_EXTICR4_EXTI14_PD 0x00000300U /*!<PD[14] pin */ 11596 #define SYSCFG_EXTICR4_EXTI14_PE 0x00000400U /*!<PE[14] pin */ 11597 #define SYSCFG_EXTICR4_EXTI14_PF 0x00000500U /*!<PF[14] pin */ 11598 #define SYSCFG_EXTICR4_EXTI14_PG 0x00000600U /*!<PG[14] pin */ 11599 #define SYSCFG_EXTICR3_EXTI14_PH 0x00000700U /*!<PH[14] pin */ 11600 /** 11601 * @brief EXTI15 configuration 11602 */ 11603 #define SYSCFG_EXTICR4_EXTI15_PA 0x00000000U /*!<PA[15] pin */ 11604 #define SYSCFG_EXTICR4_EXTI15_PB 0x00001000U /*!<PB[15] pin */ 11605 #define SYSCFG_EXTICR4_EXTI15_PC 0x00002000U /*!<PC[15] pin */ 11606 #define SYSCFG_EXTICR4_EXTI15_PD 0x00003000U /*!<PD[15] pin */ 11607 #define SYSCFG_EXTICR4_EXTI15_PE 0x00004000U /*!<PE[15] pin */ 11608 #define SYSCFG_EXTICR4_EXTI15_PF 0x00005000U /*!<PF[15] pin */ 11609 #define SYSCFG_EXTICR4_EXTI15_PG 0x00006000U /*!<PG[15] pin */ 11610 #define SYSCFG_EXTICR3_EXTI15_PH 0x00007000U /*!<PH[15] pin */ 11611 11612 /****************** Bit definition for SYSCFG_CMPCR register ****************/ 11613 #define SYSCFG_CMPCR_CMP_PD_Pos (0U) 11614 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */ 11615 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */ 11616 #define SYSCFG_CMPCR_READY_Pos (8U) 11617 #define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */ 11618 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */ 11619 11620 /******************************************************************************/ 11621 /* */ 11622 /* TIM */ 11623 /* */ 11624 /******************************************************************************/ 11625 /******************* Bit definition for TIM_CR1 register ********************/ 11626 #define TIM_CR1_CEN_Pos (0U) 11627 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ 11628 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ 11629 #define TIM_CR1_UDIS_Pos (1U) 11630 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ 11631 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ 11632 #define TIM_CR1_URS_Pos (2U) 11633 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */ 11634 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ 11635 #define TIM_CR1_OPM_Pos (3U) 11636 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ 11637 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ 11638 #define TIM_CR1_DIR_Pos (4U) 11639 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ 11640 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ 11641 11642 #define TIM_CR1_CMS_Pos (5U) 11643 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ 11644 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ 11645 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ 11646 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ 11647 11648 #define TIM_CR1_ARPE_Pos (7U) 11649 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ 11650 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ 11651 11652 #define TIM_CR1_CKD_Pos (8U) 11653 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ 11654 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ 11655 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ 11656 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ 11657 11658 /******************* Bit definition for TIM_CR2 register ********************/ 11659 #define TIM_CR2_CCPC_Pos (0U) 11660 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ 11661 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ 11662 #define TIM_CR2_CCUS_Pos (2U) 11663 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ 11664 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ 11665 #define TIM_CR2_CCDS_Pos (3U) 11666 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ 11667 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ 11668 11669 #define TIM_CR2_MMS_Pos (4U) 11670 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ 11671 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 11672 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ 11673 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ 11674 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ 11675 11676 #define TIM_CR2_TI1S_Pos (7U) 11677 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ 11678 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ 11679 #define TIM_CR2_OIS1_Pos (8U) 11680 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ 11681 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ 11682 #define TIM_CR2_OIS1N_Pos (9U) 11683 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ 11684 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ 11685 #define TIM_CR2_OIS2_Pos (10U) 11686 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ 11687 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ 11688 #define TIM_CR2_OIS2N_Pos (11U) 11689 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ 11690 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ 11691 #define TIM_CR2_OIS3_Pos (12U) 11692 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ 11693 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ 11694 #define TIM_CR2_OIS3N_Pos (13U) 11695 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ 11696 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ 11697 #define TIM_CR2_OIS4_Pos (14U) 11698 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ 11699 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ 11700 11701 /******************* Bit definition for TIM_SMCR register *******************/ 11702 #define TIM_SMCR_SMS_Pos (0U) 11703 #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */ 11704 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ 11705 #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ 11706 #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ 11707 #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ 11708 11709 #define TIM_SMCR_TS_Pos (4U) 11710 #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ 11711 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ 11712 #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ 11713 #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ 11714 #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ 11715 11716 #define TIM_SMCR_MSM_Pos (7U) 11717 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ 11718 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ 11719 11720 #define TIM_SMCR_ETF_Pos (8U) 11721 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ 11722 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ 11723 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ 11724 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ 11725 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ 11726 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ 11727 11728 #define TIM_SMCR_ETPS_Pos (12U) 11729 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ 11730 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ 11731 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ 11732 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ 11733 11734 #define TIM_SMCR_ECE_Pos (14U) 11735 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ 11736 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ 11737 #define TIM_SMCR_ETP_Pos (15U) 11738 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ 11739 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ 11740 11741 /******************* Bit definition for TIM_DIER register *******************/ 11742 #define TIM_DIER_UIE_Pos (0U) 11743 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ 11744 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ 11745 #define TIM_DIER_CC1IE_Pos (1U) 11746 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ 11747 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ 11748 #define TIM_DIER_CC2IE_Pos (2U) 11749 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ 11750 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ 11751 #define TIM_DIER_CC3IE_Pos (3U) 11752 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ 11753 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ 11754 #define TIM_DIER_CC4IE_Pos (4U) 11755 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ 11756 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ 11757 #define TIM_DIER_COMIE_Pos (5U) 11758 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ 11759 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ 11760 #define TIM_DIER_TIE_Pos (6U) 11761 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ 11762 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ 11763 #define TIM_DIER_BIE_Pos (7U) 11764 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ 11765 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ 11766 #define TIM_DIER_UDE_Pos (8U) 11767 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ 11768 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ 11769 #define TIM_DIER_CC1DE_Pos (9U) 11770 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ 11771 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ 11772 #define TIM_DIER_CC2DE_Pos (10U) 11773 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ 11774 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ 11775 #define TIM_DIER_CC3DE_Pos (11U) 11776 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ 11777 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ 11778 #define TIM_DIER_CC4DE_Pos (12U) 11779 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ 11780 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ 11781 #define TIM_DIER_COMDE_Pos (13U) 11782 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ 11783 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ 11784 #define TIM_DIER_TDE_Pos (14U) 11785 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ 11786 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ 11787 11788 /******************** Bit definition for TIM_SR register ********************/ 11789 #define TIM_SR_UIF_Pos (0U) 11790 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */ 11791 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ 11792 #define TIM_SR_CC1IF_Pos (1U) 11793 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ 11794 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ 11795 #define TIM_SR_CC2IF_Pos (2U) 11796 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ 11797 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ 11798 #define TIM_SR_CC3IF_Pos (3U) 11799 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ 11800 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ 11801 #define TIM_SR_CC4IF_Pos (4U) 11802 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ 11803 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ 11804 #define TIM_SR_COMIF_Pos (5U) 11805 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ 11806 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ 11807 #define TIM_SR_TIF_Pos (6U) 11808 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */ 11809 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ 11810 #define TIM_SR_BIF_Pos (7U) 11811 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */ 11812 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ 11813 #define TIM_SR_CC1OF_Pos (9U) 11814 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ 11815 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ 11816 #define TIM_SR_CC2OF_Pos (10U) 11817 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ 11818 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ 11819 #define TIM_SR_CC3OF_Pos (11U) 11820 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ 11821 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ 11822 #define TIM_SR_CC4OF_Pos (12U) 11823 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ 11824 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ 11825 11826 /******************* Bit definition for TIM_EGR register ********************/ 11827 #define TIM_EGR_UG_Pos (0U) 11828 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */ 11829 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ 11830 #define TIM_EGR_CC1G_Pos (1U) 11831 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ 11832 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ 11833 #define TIM_EGR_CC2G_Pos (2U) 11834 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ 11835 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ 11836 #define TIM_EGR_CC3G_Pos (3U) 11837 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ 11838 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ 11839 #define TIM_EGR_CC4G_Pos (4U) 11840 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ 11841 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ 11842 #define TIM_EGR_COMG_Pos (5U) 11843 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ 11844 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ 11845 #define TIM_EGR_TG_Pos (6U) 11846 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */ 11847 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ 11848 #define TIM_EGR_BG_Pos (7U) 11849 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */ 11850 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ 11851 11852 /****************** Bit definition for TIM_CCMR1 register *******************/ 11853 #define TIM_CCMR1_CC1S_Pos (0U) 11854 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ 11855 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ 11856 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ 11857 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ 11858 11859 #define TIM_CCMR1_OC1FE_Pos (2U) 11860 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ 11861 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ 11862 #define TIM_CCMR1_OC1PE_Pos (3U) 11863 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ 11864 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ 11865 11866 #define TIM_CCMR1_OC1M_Pos (4U) 11867 #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */ 11868 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ 11869 #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ 11870 #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ 11871 #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ 11872 11873 #define TIM_CCMR1_OC1CE_Pos (7U) 11874 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ 11875 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ 11876 11877 #define TIM_CCMR1_CC2S_Pos (8U) 11878 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ 11879 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ 11880 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ 11881 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ 11882 11883 #define TIM_CCMR1_OC2FE_Pos (10U) 11884 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ 11885 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ 11886 #define TIM_CCMR1_OC2PE_Pos (11U) 11887 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ 11888 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ 11889 11890 #define TIM_CCMR1_OC2M_Pos (12U) 11891 #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */ 11892 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ 11893 #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ 11894 #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ 11895 #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ 11896 11897 #define TIM_CCMR1_OC2CE_Pos (15U) 11898 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ 11899 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ 11900 11901 /*----------------------------------------------------------------------------*/ 11902 11903 #define TIM_CCMR1_IC1PSC_Pos (2U) 11904 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ 11905 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ 11906 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ 11907 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ 11908 11909 #define TIM_CCMR1_IC1F_Pos (4U) 11910 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ 11911 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ 11912 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ 11913 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ 11914 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ 11915 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ 11916 11917 #define TIM_CCMR1_IC2PSC_Pos (10U) 11918 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ 11919 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ 11920 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ 11921 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ 11922 11923 #define TIM_CCMR1_IC2F_Pos (12U) 11924 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ 11925 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ 11926 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ 11927 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ 11928 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ 11929 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ 11930 11931 /****************** Bit definition for TIM_CCMR2 register *******************/ 11932 #define TIM_CCMR2_CC3S_Pos (0U) 11933 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ 11934 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ 11935 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ 11936 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ 11937 11938 #define TIM_CCMR2_OC3FE_Pos (2U) 11939 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ 11940 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ 11941 #define TIM_CCMR2_OC3PE_Pos (3U) 11942 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ 11943 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ 11944 11945 #define TIM_CCMR2_OC3M_Pos (4U) 11946 #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */ 11947 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ 11948 #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ 11949 #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ 11950 #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ 11951 11952 #define TIM_CCMR2_OC3CE_Pos (7U) 11953 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ 11954 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ 11955 11956 #define TIM_CCMR2_CC4S_Pos (8U) 11957 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ 11958 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ 11959 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ 11960 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ 11961 11962 #define TIM_CCMR2_OC4FE_Pos (10U) 11963 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ 11964 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ 11965 #define TIM_CCMR2_OC4PE_Pos (11U) 11966 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ 11967 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ 11968 11969 #define TIM_CCMR2_OC4M_Pos (12U) 11970 #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */ 11971 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 11972 #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ 11973 #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ 11974 #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ 11975 11976 #define TIM_CCMR2_OC4CE_Pos (15U) 11977 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ 11978 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ 11979 11980 /*----------------------------------------------------------------------------*/ 11981 11982 #define TIM_CCMR2_IC3PSC_Pos (2U) 11983 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ 11984 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ 11985 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ 11986 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ 11987 11988 #define TIM_CCMR2_IC3F_Pos (4U) 11989 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ 11990 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ 11991 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ 11992 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ 11993 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ 11994 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ 11995 11996 #define TIM_CCMR2_IC4PSC_Pos (10U) 11997 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ 11998 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ 11999 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ 12000 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ 12001 12002 #define TIM_CCMR2_IC4F_Pos (12U) 12003 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ 12004 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ 12005 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ 12006 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ 12007 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ 12008 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ 12009 12010 /******************* Bit definition for TIM_CCER register *******************/ 12011 #define TIM_CCER_CC1E_Pos (0U) 12012 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ 12013 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ 12014 #define TIM_CCER_CC1P_Pos (1U) 12015 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ 12016 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ 12017 #define TIM_CCER_CC1NE_Pos (2U) 12018 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ 12019 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ 12020 #define TIM_CCER_CC1NP_Pos (3U) 12021 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ 12022 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ 12023 #define TIM_CCER_CC2E_Pos (4U) 12024 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ 12025 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ 12026 #define TIM_CCER_CC2P_Pos (5U) 12027 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ 12028 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ 12029 #define TIM_CCER_CC2NE_Pos (6U) 12030 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ 12031 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ 12032 #define TIM_CCER_CC2NP_Pos (7U) 12033 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ 12034 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ 12035 #define TIM_CCER_CC3E_Pos (8U) 12036 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ 12037 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ 12038 #define TIM_CCER_CC3P_Pos (9U) 12039 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ 12040 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ 12041 #define TIM_CCER_CC3NE_Pos (10U) 12042 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ 12043 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ 12044 #define TIM_CCER_CC3NP_Pos (11U) 12045 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ 12046 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ 12047 #define TIM_CCER_CC4E_Pos (12U) 12048 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ 12049 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ 12050 #define TIM_CCER_CC4P_Pos (13U) 12051 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ 12052 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ 12053 #define TIM_CCER_CC4NP_Pos (15U) 12054 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ 12055 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ 12056 12057 /******************* Bit definition for TIM_CNT register ********************/ 12058 #define TIM_CNT_CNT_Pos (0U) 12059 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ 12060 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ 12061 12062 /******************* Bit definition for TIM_PSC register ********************/ 12063 #define TIM_PSC_PSC_Pos (0U) 12064 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ 12065 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ 12066 12067 /******************* Bit definition for TIM_ARR register ********************/ 12068 #define TIM_ARR_ARR_Pos (0U) 12069 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ 12070 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ 12071 12072 /******************* Bit definition for TIM_RCR register ********************/ 12073 #define TIM_RCR_REP_Pos (0U) 12074 #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /*!< 0x000000FF */ 12075 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ 12076 12077 /******************* Bit definition for TIM_CCR1 register *******************/ 12078 #define TIM_CCR1_CCR1_Pos (0U) 12079 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ 12080 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ 12081 12082 /******************* Bit definition for TIM_CCR2 register *******************/ 12083 #define TIM_CCR2_CCR2_Pos (0U) 12084 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ 12085 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ 12086 12087 /******************* Bit definition for TIM_CCR3 register *******************/ 12088 #define TIM_CCR3_CCR3_Pos (0U) 12089 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ 12090 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ 12091 12092 /******************* Bit definition for TIM_CCR4 register *******************/ 12093 #define TIM_CCR4_CCR4_Pos (0U) 12094 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ 12095 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ 12096 12097 /******************* Bit definition for TIM_BDTR register *******************/ 12098 #define TIM_BDTR_DTG_Pos (0U) 12099 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ 12100 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ 12101 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ 12102 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */ 12103 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */ 12104 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */ 12105 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */ 12106 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */ 12107 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ 12108 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */ 12109 12110 #define TIM_BDTR_LOCK_Pos (8U) 12111 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ 12112 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ 12113 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ 12114 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */ 12115 12116 #define TIM_BDTR_OSSI_Pos (10U) 12117 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ 12118 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ 12119 #define TIM_BDTR_OSSR_Pos (11U) 12120 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ 12121 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ 12122 #define TIM_BDTR_BKE_Pos (12U) 12123 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ 12124 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */ 12125 #define TIM_BDTR_BKP_Pos (13U) 12126 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ 12127 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */ 12128 #define TIM_BDTR_AOE_Pos (14U) 12129 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ 12130 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ 12131 #define TIM_BDTR_MOE_Pos (15U) 12132 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ 12133 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ 12134 12135 /******************* Bit definition for TIM_DCR register ********************/ 12136 #define TIM_DCR_DBA_Pos (0U) 12137 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ 12138 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ 12139 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ 12140 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ 12141 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ 12142 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ 12143 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ 12144 12145 #define TIM_DCR_DBL_Pos (8U) 12146 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ 12147 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ 12148 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ 12149 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ 12150 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ 12151 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ 12152 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ 12153 12154 /******************* Bit definition for TIM_DMAR register *******************/ 12155 #define TIM_DMAR_DMAB_Pos (0U) 12156 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ 12157 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ 12158 12159 /******************* Bit definition for TIM_OR register *********************/ 12160 #define TIM_OR_TI1_RMP_Pos (0U) 12161 #define TIM_OR_TI1_RMP_Msk (0x3UL << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */ 12162 #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */ 12163 #define TIM_OR_TI1_RMP_0 (0x1UL << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */ 12164 #define TIM_OR_TI1_RMP_1 (0x2UL << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */ 12165 #define TIM_OR_TI4_RMP_Pos (6U) 12166 #define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */ 12167 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */ 12168 #define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos) /*!< 0x00000040 */ 12169 #define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos) /*!< 0x00000080 */ 12170 #define TIM_OR_ITR1_RMP_Pos (10U) 12171 #define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */ 12172 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */ 12173 #define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000400 */ 12174 #define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000800 */ 12175 12176 /******************************************************************************/ 12177 /* */ 12178 /* Universal Synchronous Asynchronous Receiver Transmitter */ 12179 /* */ 12180 /******************************************************************************/ 12181 /******************* Bit definition for USART_SR register *******************/ 12182 #define USART_SR_PE_Pos (0U) 12183 #define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos) /*!< 0x00000001 */ 12184 #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */ 12185 #define USART_SR_FE_Pos (1U) 12186 #define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos) /*!< 0x00000002 */ 12187 #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */ 12188 #define USART_SR_NE_Pos (2U) 12189 #define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos) /*!< 0x00000004 */ 12190 #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */ 12191 #define USART_SR_ORE_Pos (3U) 12192 #define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos) /*!< 0x00000008 */ 12193 #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */ 12194 #define USART_SR_IDLE_Pos (4U) 12195 #define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos) /*!< 0x00000010 */ 12196 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */ 12197 #define USART_SR_RXNE_Pos (5U) 12198 #define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos) /*!< 0x00000020 */ 12199 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */ 12200 #define USART_SR_TC_Pos (6U) 12201 #define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos) /*!< 0x00000040 */ 12202 #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */ 12203 #define USART_SR_TXE_Pos (7U) 12204 #define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos) /*!< 0x00000080 */ 12205 #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */ 12206 #define USART_SR_LBD_Pos (8U) 12207 #define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos) /*!< 0x00000100 */ 12208 #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */ 12209 #define USART_SR_CTS_Pos (9U) 12210 #define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos) /*!< 0x00000200 */ 12211 #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */ 12212 12213 /******************* Bit definition for USART_DR register *******************/ 12214 #define USART_DR_DR_Pos (0U) 12215 #define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos) /*!< 0x000001FF */ 12216 #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */ 12217 12218 /****************** Bit definition for USART_BRR register *******************/ 12219 #define USART_BRR_DIV_Fraction_Pos (0U) 12220 #define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */ 12221 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */ 12222 #define USART_BRR_DIV_Mantissa_Pos (4U) 12223 #define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */ 12224 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */ 12225 12226 /****************** Bit definition for USART_CR1 register *******************/ 12227 #define USART_CR1_SBK_Pos (0U) 12228 #define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos) /*!< 0x00000001 */ 12229 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */ 12230 #define USART_CR1_RWU_Pos (1U) 12231 #define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos) /*!< 0x00000002 */ 12232 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */ 12233 #define USART_CR1_RE_Pos (2U) 12234 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */ 12235 #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */ 12236 #define USART_CR1_TE_Pos (3U) 12237 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */ 12238 #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */ 12239 #define USART_CR1_IDLEIE_Pos (4U) 12240 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ 12241 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */ 12242 #define USART_CR1_RXNEIE_Pos (5U) 12243 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ 12244 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */ 12245 #define USART_CR1_TCIE_Pos (6U) 12246 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ 12247 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */ 12248 #define USART_CR1_TXEIE_Pos (7U) 12249 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ 12250 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<PE Interrupt Enable */ 12251 #define USART_CR1_PEIE_Pos (8U) 12252 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ 12253 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */ 12254 #define USART_CR1_PS_Pos (9U) 12255 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */ 12256 #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */ 12257 #define USART_CR1_PCE_Pos (10U) 12258 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */ 12259 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */ 12260 #define USART_CR1_WAKE_Pos (11U) 12261 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ 12262 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */ 12263 #define USART_CR1_M_Pos (12U) 12264 #define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos) /*!< 0x00001000 */ 12265 #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */ 12266 #define USART_CR1_UE_Pos (13U) 12267 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00002000 */ 12268 #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */ 12269 #define USART_CR1_OVER8_Pos (15U) 12270 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ 12271 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */ 12272 12273 /****************** Bit definition for USART_CR2 register *******************/ 12274 #define USART_CR2_ADD_Pos (0U) 12275 #define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos) /*!< 0x0000000F */ 12276 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */ 12277 #define USART_CR2_LBDL_Pos (5U) 12278 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ 12279 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */ 12280 #define USART_CR2_LBDIE_Pos (6U) 12281 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ 12282 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */ 12283 #define USART_CR2_LBCL_Pos (8U) 12284 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ 12285 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */ 12286 #define USART_CR2_CPHA_Pos (9U) 12287 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ 12288 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */ 12289 #define USART_CR2_CPOL_Pos (10U) 12290 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ 12291 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */ 12292 #define USART_CR2_CLKEN_Pos (11U) 12293 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ 12294 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */ 12295 12296 #define USART_CR2_STOP_Pos (12U) 12297 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */ 12298 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */ 12299 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */ 12300 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */ 12301 12302 #define USART_CR2_LINEN_Pos (14U) 12303 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ 12304 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */ 12305 12306 /****************** Bit definition for USART_CR3 register *******************/ 12307 #define USART_CR3_EIE_Pos (0U) 12308 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */ 12309 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */ 12310 #define USART_CR3_IREN_Pos (1U) 12311 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */ 12312 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */ 12313 #define USART_CR3_IRLP_Pos (2U) 12314 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ 12315 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */ 12316 #define USART_CR3_HDSEL_Pos (3U) 12317 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ 12318 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */ 12319 #define USART_CR3_NACK_Pos (4U) 12320 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */ 12321 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */ 12322 #define USART_CR3_SCEN_Pos (5U) 12323 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ 12324 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */ 12325 #define USART_CR3_DMAR_Pos (6U) 12326 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ 12327 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */ 12328 #define USART_CR3_DMAT_Pos (7U) 12329 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ 12330 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */ 12331 #define USART_CR3_RTSE_Pos (8U) 12332 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ 12333 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */ 12334 #define USART_CR3_CTSE_Pos (9U) 12335 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ 12336 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */ 12337 #define USART_CR3_CTSIE_Pos (10U) 12338 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ 12339 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */ 12340 #define USART_CR3_ONEBIT_Pos (11U) 12341 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ 12342 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */ 12343 12344 /****************** Bit definition for USART_GTPR register ******************/ 12345 #define USART_GTPR_PSC_Pos (0U) 12346 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ 12347 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */ 12348 #define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos) /*!< 0x00000001 */ 12349 #define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos) /*!< 0x00000002 */ 12350 #define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos) /*!< 0x00000004 */ 12351 #define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos) /*!< 0x00000008 */ 12352 #define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos) /*!< 0x00000010 */ 12353 #define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos) /*!< 0x00000020 */ 12354 #define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos) /*!< 0x00000040 */ 12355 #define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos) /*!< 0x00000080 */ 12356 12357 #define USART_GTPR_GT_Pos (8U) 12358 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ 12359 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */ 12360 12361 /******************************************************************************/ 12362 /* */ 12363 /* Window WATCHDOG */ 12364 /* */ 12365 /******************************************************************************/ 12366 /******************* Bit definition for WWDG_CR register ********************/ 12367 #define WWDG_CR_T_Pos (0U) 12368 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */ 12369 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */ 12370 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */ 12371 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */ 12372 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */ 12373 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */ 12374 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */ 12375 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */ 12376 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */ 12377 12378 /* Legacy defines */ 12379 #define WWDG_CR_T0 WWDG_CR_T_0 12380 #define WWDG_CR_T1 WWDG_CR_T_1 12381 #define WWDG_CR_T2 WWDG_CR_T_2 12382 #define WWDG_CR_T3 WWDG_CR_T_3 12383 #define WWDG_CR_T4 WWDG_CR_T_4 12384 #define WWDG_CR_T5 WWDG_CR_T_5 12385 #define WWDG_CR_T6 WWDG_CR_T_6 12386 #define WWDG_CR_WDGA_Pos (7U) 12387 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ 12388 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */ 12389 12390 /******************* Bit definition for WWDG_CFR register *******************/ 12391 #define WWDG_CFR_W_Pos (0U) 12392 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */ 12393 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */ 12394 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */ 12395 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */ 12396 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */ 12397 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */ 12398 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */ 12399 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */ 12400 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */ 12401 12402 /* Legacy defines */ 12403 #define WWDG_CFR_W0 WWDG_CFR_W_0 12404 #define WWDG_CFR_W1 WWDG_CFR_W_1 12405 #define WWDG_CFR_W2 WWDG_CFR_W_2 12406 #define WWDG_CFR_W3 WWDG_CFR_W_3 12407 #define WWDG_CFR_W4 WWDG_CFR_W_4 12408 #define WWDG_CFR_W5 WWDG_CFR_W_5 12409 #define WWDG_CFR_W6 WWDG_CFR_W_6 12410 12411 #define WWDG_CFR_WDGTB_Pos (7U) 12412 #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ 12413 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */ 12414 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ 12415 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ 12416 12417 /* Legacy defines */ 12418 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 12419 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 12420 12421 #define WWDG_CFR_EWI_Pos (9U) 12422 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ 12423 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */ 12424 12425 /******************* Bit definition for WWDG_SR register ********************/ 12426 #define WWDG_SR_EWIF_Pos (0U) 12427 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ 12428 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */ 12429 12430 /******************************************************************************/ 12431 /* */ 12432 /* DBG */ 12433 /* */ 12434 /******************************************************************************/ 12435 /******************** Bit definition for DBGMCU_IDCODE register *************/ 12436 #define DBGMCU_IDCODE_DEV_ID_Pos (0U) 12437 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ 12438 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk 12439 #define DBGMCU_IDCODE_REV_ID_Pos (16U) 12440 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ 12441 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk 12442 12443 /******************** Bit definition for DBGMCU_CR register *****************/ 12444 #define DBGMCU_CR_DBG_SLEEP_Pos (0U) 12445 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ 12446 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk 12447 #define DBGMCU_CR_DBG_STOP_Pos (1U) 12448 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ 12449 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk 12450 #define DBGMCU_CR_DBG_STANDBY_Pos (2U) 12451 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ 12452 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk 12453 #define DBGMCU_CR_TRACE_IOEN_Pos (5U) 12454 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */ 12455 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk 12456 12457 #define DBGMCU_CR_TRACE_MODE_Pos (6U) 12458 #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ 12459 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk 12460 #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ 12461 #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ 12462 12463 /******************** Bit definition for DBGMCU_APB1_FZ register ************/ 12464 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) 12465 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ 12466 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk 12467 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U) 12468 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ 12469 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk 12470 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U) 12471 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */ 12472 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk 12473 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U) 12474 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */ 12475 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk 12476 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U) 12477 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ 12478 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk 12479 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U) 12480 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ 12481 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk 12482 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U) 12483 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */ 12484 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk 12485 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U) 12486 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */ 12487 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk 12488 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U) 12489 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */ 12490 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk 12491 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) 12492 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ 12493 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk 12494 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) 12495 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ 12496 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk 12497 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) 12498 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ 12499 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk 12500 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U) 12501 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */ 12502 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk 12503 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U) 12504 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */ 12505 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk 12506 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U) 12507 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */ 12508 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk 12509 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U) 12510 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */ 12511 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk 12512 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U) 12513 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */ 12514 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk 12515 /* Old IWDGSTOP bit definition, maintained for legacy purpose */ 12516 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP 12517 12518 /******************** Bit definition for DBGMCU_APB2_FZ register ************/ 12519 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U) 12520 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */ 12521 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk 12522 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U) 12523 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */ 12524 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk 12525 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U) 12526 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */ 12527 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk 12528 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U) 12529 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */ 12530 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk 12531 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U) 12532 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */ 12533 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk 12534 12535 /******************************************************************************/ 12536 /* */ 12537 /* Ethernet MAC Registers bits definitions */ 12538 /* */ 12539 /******************************************************************************/ 12540 /* Bit definition for Ethernet MAC Control Register register */ 12541 #define ETH_MACCR_WD_Pos (23U) 12542 #define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00800000 */ 12543 #define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */ 12544 #define ETH_MACCR_JD_Pos (22U) 12545 #define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00400000 */ 12546 #define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */ 12547 #define ETH_MACCR_IFG_Pos (17U) 12548 #define ETH_MACCR_IFG_Msk (0x7UL << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */ 12549 #define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */ 12550 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */ 12551 #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */ 12552 #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */ 12553 #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */ 12554 #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */ 12555 #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */ 12556 #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */ 12557 #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */ 12558 #define ETH_MACCR_CSD_Pos (16U) 12559 #define ETH_MACCR_CSD_Msk (0x1UL << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */ 12560 #define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */ 12561 #define ETH_MACCR_FES_Pos (14U) 12562 #define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */ 12563 #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */ 12564 #define ETH_MACCR_ROD_Pos (13U) 12565 #define ETH_MACCR_ROD_Msk (0x1UL << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */ 12566 #define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */ 12567 #define ETH_MACCR_LM_Pos (12U) 12568 #define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */ 12569 #define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */ 12570 #define ETH_MACCR_DM_Pos (11U) 12571 #define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00000800 */ 12572 #define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */ 12573 #define ETH_MACCR_IPCO_Pos (10U) 12574 #define ETH_MACCR_IPCO_Msk (0x1UL << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */ 12575 #define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */ 12576 #define ETH_MACCR_RD_Pos (9U) 12577 #define ETH_MACCR_RD_Msk (0x1UL << ETH_MACCR_RD_Pos) /*!< 0x00000200 */ 12578 #define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */ 12579 #define ETH_MACCR_APCS_Pos (7U) 12580 #define ETH_MACCR_APCS_Msk (0x1UL << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */ 12581 #define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */ 12582 #define ETH_MACCR_BL_Pos (5U) 12583 #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ 12584 #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling 12585 a transmission attempt during retries after a collision: 0 =< r <2^k */ 12586 #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */ 12587 #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */ 12588 #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */ 12589 #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */ 12590 #define ETH_MACCR_DC_Pos (4U) 12591 #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ 12592 #define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */ 12593 #define ETH_MACCR_TE_Pos (3U) 12594 #define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000008 */ 12595 #define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */ 12596 #define ETH_MACCR_RE_Pos (2U) 12597 #define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000004 */ 12598 #define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */ 12599 12600 /* Bit definition for Ethernet MAC Frame Filter Register */ 12601 #define ETH_MACFFR_RA_Pos (31U) 12602 #define ETH_MACFFR_RA_Msk (0x1UL << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */ 12603 #define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */ 12604 #define ETH_MACFFR_HPF_Pos (10U) 12605 #define ETH_MACFFR_HPF_Msk (0x1UL << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */ 12606 #define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */ 12607 #define ETH_MACFFR_SAF_Pos (9U) 12608 #define ETH_MACFFR_SAF_Msk (0x1UL << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */ 12609 #define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */ 12610 #define ETH_MACFFR_SAIF_Pos (8U) 12611 #define ETH_MACFFR_SAIF_Msk (0x1UL << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */ 12612 #define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */ 12613 #define ETH_MACFFR_PCF_Pos (6U) 12614 #define ETH_MACFFR_PCF_Msk (0x3UL << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */ 12615 #define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */ 12616 #define ETH_MACFFR_PCF_BlockAll_Pos (6U) 12617 #define ETH_MACFFR_PCF_BlockAll_Msk (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */ 12618 #define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */ 12619 #define ETH_MACFFR_PCF_ForwardAll_Pos (7U) 12620 #define ETH_MACFFR_PCF_ForwardAll_Msk (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */ 12621 #define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */ 12622 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U) 12623 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */ 12624 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */ 12625 #define ETH_MACFFR_BFD_Pos (5U) 12626 #define ETH_MACFFR_BFD_Msk (0x1UL << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */ 12627 #define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */ 12628 #define ETH_MACFFR_PAM_Pos (4U) 12629 #define ETH_MACFFR_PAM_Msk (0x1UL << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */ 12630 #define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */ 12631 #define ETH_MACFFR_DAIF_Pos (3U) 12632 #define ETH_MACFFR_DAIF_Msk (0x1UL << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */ 12633 #define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */ 12634 #define ETH_MACFFR_HM_Pos (2U) 12635 #define ETH_MACFFR_HM_Msk (0x1UL << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */ 12636 #define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */ 12637 #define ETH_MACFFR_HU_Pos (1U) 12638 #define ETH_MACFFR_HU_Msk (0x1UL << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */ 12639 #define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */ 12640 #define ETH_MACFFR_PM_Pos (0U) 12641 #define ETH_MACFFR_PM_Msk (0x1UL << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */ 12642 #define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */ 12643 12644 /* Bit definition for Ethernet MAC Hash Table High Register */ 12645 #define ETH_MACHTHR_HTH_Pos (0U) 12646 #define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */ 12647 #define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */ 12648 12649 /* Bit definition for Ethernet MAC Hash Table Low Register */ 12650 #define ETH_MACHTLR_HTL_Pos (0U) 12651 #define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */ 12652 #define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */ 12653 12654 /* Bit definition for Ethernet MAC MII Address Register */ 12655 #define ETH_MACMIIAR_PA_Pos (11U) 12656 #define ETH_MACMIIAR_PA_Msk (0x1FUL << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */ 12657 #define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */ 12658 #define ETH_MACMIIAR_MR_Pos (6U) 12659 #define ETH_MACMIIAR_MR_Msk (0x1FUL << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */ 12660 #define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */ 12661 #define ETH_MACMIIAR_CR_Pos (2U) 12662 #define ETH_MACMIIAR_CR_Msk (0x7UL << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */ 12663 #define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */ 12664 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ 12665 #define ETH_MACMIIAR_CR_Div62_Pos (2U) 12666 #define ETH_MACMIIAR_CR_Div62_Msk (0x1UL << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */ 12667 #define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-120 MHz; MDC clock= HCLK/62 */ 12668 #define ETH_MACMIIAR_CR_Div16_Pos (3U) 12669 #define ETH_MACMIIAR_CR_Div16_Msk (0x1UL << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */ 12670 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ 12671 #define ETH_MACMIIAR_CR_Div26_Pos (2U) 12672 #define ETH_MACMIIAR_CR_Div26_Msk (0x3UL << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */ 12673 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/42 */ 12674 #define ETH_MACMIIAR_MW_Pos (1U) 12675 #define ETH_MACMIIAR_MW_Msk (0x1UL << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */ 12676 #define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */ 12677 #define ETH_MACMIIAR_MB_Pos (0U) 12678 #define ETH_MACMIIAR_MB_Msk (0x1UL << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */ 12679 #define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */ 12680 12681 /* Bit definition for Ethernet MAC MII Data Register */ 12682 #define ETH_MACMIIDR_MD_Pos (0U) 12683 #define ETH_MACMIIDR_MD_Msk (0xFFFFUL << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */ 12684 #define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */ 12685 12686 /* Bit definition for Ethernet MAC Flow Control Register */ 12687 #define ETH_MACFCR_PT_Pos (16U) 12688 #define ETH_MACFCR_PT_Msk (0xFFFFUL << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */ 12689 #define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */ 12690 #define ETH_MACFCR_ZQPD_Pos (7U) 12691 #define ETH_MACFCR_ZQPD_Msk (0x1UL << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */ 12692 #define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */ 12693 #define ETH_MACFCR_PLT_Pos (4U) 12694 #define ETH_MACFCR_PLT_Msk (0x3UL << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */ 12695 #define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */ 12696 #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */ 12697 #define ETH_MACFCR_PLT_Minus28_Pos (4U) 12698 #define ETH_MACFCR_PLT_Minus28_Msk (0x1UL << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */ 12699 #define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */ 12700 #define ETH_MACFCR_PLT_Minus144_Pos (5U) 12701 #define ETH_MACFCR_PLT_Minus144_Msk (0x1UL << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */ 12702 #define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */ 12703 #define ETH_MACFCR_PLT_Minus256_Pos (4U) 12704 #define ETH_MACFCR_PLT_Minus256_Msk (0x3UL << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */ 12705 #define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */ 12706 #define ETH_MACFCR_UPFD_Pos (3U) 12707 #define ETH_MACFCR_UPFD_Msk (0x1UL << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */ 12708 #define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */ 12709 #define ETH_MACFCR_RFCE_Pos (2U) 12710 #define ETH_MACFCR_RFCE_Msk (0x1UL << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */ 12711 #define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */ 12712 #define ETH_MACFCR_TFCE_Pos (1U) 12713 #define ETH_MACFCR_TFCE_Msk (0x1UL << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */ 12714 #define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */ 12715 #define ETH_MACFCR_FCBBPA_Pos (0U) 12716 #define ETH_MACFCR_FCBBPA_Msk (0x1UL << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */ 12717 #define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */ 12718 12719 /* Bit definition for Ethernet MAC VLAN Tag Register */ 12720 #define ETH_MACVLANTR_VLANTC_Pos (16U) 12721 #define ETH_MACVLANTR_VLANTC_Msk (0x1UL << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */ 12722 #define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */ 12723 #define ETH_MACVLANTR_VLANTI_Pos (0U) 12724 #define ETH_MACVLANTR_VLANTI_Msk (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */ 12725 #define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */ 12726 12727 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 12728 #define ETH_MACRWUFFR_D_Pos (0U) 12729 #define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */ 12730 #define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */ 12731 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. 12732 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ 12733 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask 12734 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask 12735 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask 12736 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask 12737 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 12738 RSVD - Filter1 Command - RSVD - Filter0 Command 12739 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset 12740 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 12741 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ 12742 12743 /* Bit definition for Ethernet MAC PMT Control and Status Register */ 12744 #define ETH_MACPMTCSR_WFFRPR_Pos (31U) 12745 #define ETH_MACPMTCSR_WFFRPR_Msk (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */ 12746 #define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */ 12747 #define ETH_MACPMTCSR_GU_Pos (9U) 12748 #define ETH_MACPMTCSR_GU_Msk (0x1UL << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */ 12749 #define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */ 12750 #define ETH_MACPMTCSR_WFR_Pos (6U) 12751 #define ETH_MACPMTCSR_WFR_Msk (0x1UL << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */ 12752 #define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */ 12753 #define ETH_MACPMTCSR_MPR_Pos (5U) 12754 #define ETH_MACPMTCSR_MPR_Msk (0x1UL << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */ 12755 #define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */ 12756 #define ETH_MACPMTCSR_WFE_Pos (2U) 12757 #define ETH_MACPMTCSR_WFE_Msk (0x1UL << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */ 12758 #define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */ 12759 #define ETH_MACPMTCSR_MPE_Pos (1U) 12760 #define ETH_MACPMTCSR_MPE_Msk (0x1UL << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */ 12761 #define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */ 12762 #define ETH_MACPMTCSR_PD_Pos (0U) 12763 #define ETH_MACPMTCSR_PD_Msk (0x1UL << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */ 12764 #define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */ 12765 12766 /* Bit definition for Ethernet MAC debug Register */ 12767 #define ETH_MACDBGR_TFF_Pos (25U) 12768 #define ETH_MACDBGR_TFF_Msk (0x1UL << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */ 12769 #define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */ 12770 #define ETH_MACDBGR_TFNE_Pos (24U) 12771 #define ETH_MACDBGR_TFNE_Msk (0x1UL << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */ 12772 #define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */ 12773 #define ETH_MACDBGR_TFWA_Pos (22U) 12774 #define ETH_MACDBGR_TFWA_Msk (0x1UL << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */ 12775 #define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */ 12776 #define ETH_MACDBGR_TFRS_Pos (20U) 12777 #define ETH_MACDBGR_TFRS_Msk (0x3UL << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */ 12778 #define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */ 12779 #define ETH_MACDBGR_TFRS_WRITING_Pos (20U) 12780 #define ETH_MACDBGR_TFRS_WRITING_Msk (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */ 12781 #define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */ 12782 #define ETH_MACDBGR_TFRS_WAITING_Pos (21U) 12783 #define ETH_MACDBGR_TFRS_WAITING_Msk (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */ 12784 #define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */ 12785 #define ETH_MACDBGR_TFRS_READ_Pos (20U) 12786 #define ETH_MACDBGR_TFRS_READ_Msk (0x1UL << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */ 12787 #define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */ 12788 #define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */ 12789 #define ETH_MACDBGR_MTP_Pos (19U) 12790 #define ETH_MACDBGR_MTP_Msk (0x1UL << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */ 12791 #define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */ 12792 #define ETH_MACDBGR_MTFCS_Pos (17U) 12793 #define ETH_MACDBGR_MTFCS_Msk (0x3UL << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */ 12794 #define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */ 12795 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U) 12796 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */ 12797 #define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */ 12798 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U) 12799 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */ 12800 #define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */ 12801 #define ETH_MACDBGR_MTFCS_WAITING_Pos (17U) 12802 #define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */ 12803 #define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */ 12804 #define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */ 12805 #define ETH_MACDBGR_MMTEA_Pos (16U) 12806 #define ETH_MACDBGR_MMTEA_Msk (0x1UL << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */ 12807 #define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */ 12808 #define ETH_MACDBGR_RFFL_Pos (8U) 12809 #define ETH_MACDBGR_RFFL_Msk (0x3UL << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */ 12810 #define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */ 12811 #define ETH_MACDBGR_RFFL_FULL_Pos (8U) 12812 #define ETH_MACDBGR_RFFL_FULL_Msk (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */ 12813 #define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */ 12814 #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U) 12815 #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */ 12816 #define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */ 12817 #define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U) 12818 #define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */ 12819 #define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */ 12820 #define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */ 12821 #define ETH_MACDBGR_RFRCS_Pos (5U) 12822 #define ETH_MACDBGR_RFRCS_Msk (0x3UL << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */ 12823 #define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */ 12824 #define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U) 12825 #define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */ 12826 #define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */ 12827 #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U) 12828 #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */ 12829 #define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */ 12830 #define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U) 12831 #define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */ 12832 #define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */ 12833 #define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */ 12834 #define ETH_MACDBGR_RFWRA_Pos (4U) 12835 #define ETH_MACDBGR_RFWRA_Msk (0x1UL << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */ 12836 #define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */ 12837 #define ETH_MACDBGR_MSFRWCS_Pos (1U) 12838 #define ETH_MACDBGR_MSFRWCS_Msk (0x3UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */ 12839 #define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */ 12840 #define ETH_MACDBGR_MSFRWCS_1 (0x2UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */ 12841 #define ETH_MACDBGR_MSFRWCS_0 (0x1UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */ 12842 #define ETH_MACDBGR_MMRPEA_Pos (0U) 12843 #define ETH_MACDBGR_MMRPEA_Msk (0x1UL << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */ 12844 #define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */ 12845 12846 /* Bit definition for Ethernet MAC Status Register */ 12847 #define ETH_MACSR_TSTS_Pos (9U) 12848 #define ETH_MACSR_TSTS_Msk (0x1UL << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */ 12849 #define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */ 12850 #define ETH_MACSR_MMCTS_Pos (6U) 12851 #define ETH_MACSR_MMCTS_Msk (0x1UL << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */ 12852 #define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */ 12853 #define ETH_MACSR_MMMCRS_Pos (5U) 12854 #define ETH_MACSR_MMMCRS_Msk (0x1UL << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */ 12855 #define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */ 12856 #define ETH_MACSR_MMCS_Pos (4U) 12857 #define ETH_MACSR_MMCS_Msk (0x1UL << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */ 12858 #define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */ 12859 #define ETH_MACSR_PMTS_Pos (3U) 12860 #define ETH_MACSR_PMTS_Msk (0x1UL << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */ 12861 #define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */ 12862 12863 /* Bit definition for Ethernet MAC Interrupt Mask Register */ 12864 #define ETH_MACIMR_TSTIM_Pos (9U) 12865 #define ETH_MACIMR_TSTIM_Msk (0x1UL << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */ 12866 #define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */ 12867 #define ETH_MACIMR_PMTIM_Pos (3U) 12868 #define ETH_MACIMR_PMTIM_Msk (0x1UL << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */ 12869 #define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */ 12870 12871 /* Bit definition for Ethernet MAC Address0 High Register */ 12872 #define ETH_MACA0HR_MACA0H_Pos (0U) 12873 #define ETH_MACA0HR_MACA0H_Msk (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */ 12874 #define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */ 12875 12876 /* Bit definition for Ethernet MAC Address0 Low Register */ 12877 #define ETH_MACA0LR_MACA0L_Pos (0U) 12878 #define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */ 12879 #define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */ 12880 12881 /* Bit definition for Ethernet MAC Address1 High Register */ 12882 #define ETH_MACA1HR_AE_Pos (31U) 12883 #define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */ 12884 #define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */ 12885 #define ETH_MACA1HR_SA_Pos (30U) 12886 #define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */ 12887 #define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */ 12888 #define ETH_MACA1HR_MBC_Pos (24U) 12889 #define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */ 12890 #define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ 12891 #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */ 12892 #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */ 12893 #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */ 12894 #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */ 12895 #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */ 12896 #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */ 12897 #define ETH_MACA1HR_MACA1H_Pos (0U) 12898 #define ETH_MACA1HR_MACA1H_Msk (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */ 12899 #define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */ 12900 12901 /* Bit definition for Ethernet MAC Address1 Low Register */ 12902 #define ETH_MACA1LR_MACA1L_Pos (0U) 12903 #define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */ 12904 #define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */ 12905 12906 /* Bit definition for Ethernet MAC Address2 High Register */ 12907 #define ETH_MACA2HR_AE_Pos (31U) 12908 #define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */ 12909 #define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */ 12910 #define ETH_MACA2HR_SA_Pos (30U) 12911 #define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */ 12912 #define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */ 12913 #define ETH_MACA2HR_MBC_Pos (24U) 12914 #define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */ 12915 #define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */ 12916 #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */ 12917 #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */ 12918 #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */ 12919 #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */ 12920 #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */ 12921 #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */ 12922 #define ETH_MACA2HR_MACA2H_Pos (0U) 12923 #define ETH_MACA2HR_MACA2H_Msk (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */ 12924 #define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */ 12925 12926 /* Bit definition for Ethernet MAC Address2 Low Register */ 12927 #define ETH_MACA2LR_MACA2L_Pos (0U) 12928 #define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */ 12929 #define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */ 12930 12931 /* Bit definition for Ethernet MAC Address3 High Register */ 12932 #define ETH_MACA3HR_AE_Pos (31U) 12933 #define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */ 12934 #define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */ 12935 #define ETH_MACA3HR_SA_Pos (30U) 12936 #define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */ 12937 #define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */ 12938 #define ETH_MACA3HR_MBC_Pos (24U) 12939 #define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */ 12940 #define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */ 12941 #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */ 12942 #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */ 12943 #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */ 12944 #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */ 12945 #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */ 12946 #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */ 12947 #define ETH_MACA3HR_MACA3H_Pos (0U) 12948 #define ETH_MACA3HR_MACA3H_Msk (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */ 12949 #define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */ 12950 12951 /* Bit definition for Ethernet MAC Address3 Low Register */ 12952 #define ETH_MACA3LR_MACA3L_Pos (0U) 12953 #define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */ 12954 #define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */ 12955 12956 /******************************************************************************/ 12957 /* Ethernet MMC Registers bits definition */ 12958 /******************************************************************************/ 12959 12960 /* Bit definition for Ethernet MMC Control Register */ 12961 #define ETH_MMCCR_MCFHP_Pos (5U) 12962 #define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */ 12963 #define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */ 12964 #define ETH_MMCCR_MCP_Pos (4U) 12965 #define ETH_MMCCR_MCP_Msk (0x1UL << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */ 12966 #define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */ 12967 #define ETH_MMCCR_MCF_Pos (3U) 12968 #define ETH_MMCCR_MCF_Msk (0x1UL << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */ 12969 #define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */ 12970 #define ETH_MMCCR_ROR_Pos (2U) 12971 #define ETH_MMCCR_ROR_Msk (0x1UL << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */ 12972 #define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */ 12973 #define ETH_MMCCR_CSR_Pos (1U) 12974 #define ETH_MMCCR_CSR_Msk (0x1UL << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */ 12975 #define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */ 12976 #define ETH_MMCCR_CR_Pos (0U) 12977 #define ETH_MMCCR_CR_Msk (0x1UL << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */ 12978 #define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */ 12979 12980 /* Bit definition for Ethernet MMC Receive Interrupt Register */ 12981 #define ETH_MMCRIR_RGUFS_Pos (17U) 12982 #define ETH_MMCRIR_RGUFS_Msk (0x1UL << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */ 12983 #define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */ 12984 #define ETH_MMCRIR_RFAES_Pos (6U) 12985 #define ETH_MMCRIR_RFAES_Msk (0x1UL << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */ 12986 #define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */ 12987 #define ETH_MMCRIR_RFCES_Pos (5U) 12988 #define ETH_MMCRIR_RFCES_Msk (0x1UL << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */ 12989 #define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */ 12990 12991 /* Bit definition for Ethernet MMC Transmit Interrupt Register */ 12992 #define ETH_MMCTIR_TGFS_Pos (21U) 12993 #define ETH_MMCTIR_TGFS_Msk (0x1UL << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */ 12994 #define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */ 12995 #define ETH_MMCTIR_TGFMSCS_Pos (15U) 12996 #define ETH_MMCTIR_TGFMSCS_Msk (0x1UL << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */ 12997 #define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */ 12998 #define ETH_MMCTIR_TGFSCS_Pos (14U) 12999 #define ETH_MMCTIR_TGFSCS_Msk (0x1UL << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */ 13000 #define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */ 13001 13002 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ 13003 #define ETH_MMCRIMR_RGUFM_Pos (17U) 13004 #define ETH_MMCRIMR_RGUFM_Msk (0x1UL << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */ 13005 #define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ 13006 #define ETH_MMCRIMR_RFAEM_Pos (6U) 13007 #define ETH_MMCRIMR_RFAEM_Msk (0x1UL << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */ 13008 #define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when Rx alignment error counter reaches half the maximum value */ 13009 #define ETH_MMCRIMR_RFCEM_Pos (5U) 13010 #define ETH_MMCRIMR_RFCEM_Msk (0x1UL << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */ 13011 #define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ 13012 13013 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ 13014 #define ETH_MMCTIMR_TGFM_Pos (21U) 13015 #define ETH_MMCTIMR_TGFM_Msk (0x1UL << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */ 13016 #define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ 13017 #define ETH_MMCTIMR_TGFMSCM_Pos (15U) 13018 #define ETH_MMCTIMR_TGFMSCM_Msk (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */ 13019 #define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ 13020 #define ETH_MMCTIMR_TGFSCM_Pos (14U) 13021 #define ETH_MMCTIMR_TGFSCM_Msk (0x1UL << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */ 13022 #define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ 13023 13024 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ 13025 #define ETH_MMCTGFSCCR_TGFSCC_Pos (0U) 13026 #define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */ 13027 #define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ 13028 13029 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ 13030 #define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U) 13031 #define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */ 13032 #define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ 13033 13034 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ 13035 #define ETH_MMCTGFCR_TGFC_Pos (0U) 13036 #define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */ 13037 #define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */ 13038 13039 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ 13040 #define ETH_MMCRFCECR_RFCEC_Pos (0U) 13041 #define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */ 13042 #define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */ 13043 13044 /* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */ 13045 #define ETH_MMCRFAECR_RFAEC_Pos (0U) 13046 #define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */ 13047 #define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */ 13048 13049 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ 13050 #define ETH_MMCRGUFCR_RGUFC_Pos (0U) 13051 #define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */ 13052 #define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */ 13053 13054 /******************************************************************************/ 13055 /* Ethernet PTP Registers bits definition */ 13056 /******************************************************************************/ 13057 13058 /* Bit definition for Ethernet PTP Time Stamp Control Register */ 13059 #define ETH_PTPTSCR_TSCNT_Pos (16U) 13060 #define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */ 13061 #define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */ 13062 #define ETH_PTPTSSR_TSSMRME_Pos (15U) 13063 #define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */ 13064 #define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */ 13065 #define ETH_PTPTSSR_TSSEME_Pos (14U) 13066 #define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */ 13067 #define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */ 13068 #define ETH_PTPTSSR_TSSIPV4FE_Pos (13U) 13069 #define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */ 13070 #define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */ 13071 #define ETH_PTPTSSR_TSSIPV6FE_Pos (12U) 13072 #define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */ 13073 #define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */ 13074 #define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U) 13075 #define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */ 13076 #define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */ 13077 #define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U) 13078 #define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */ 13079 #define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */ 13080 #define ETH_PTPTSSR_TSSSR_Pos (9U) 13081 #define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */ 13082 #define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */ 13083 #define ETH_PTPTSSR_TSSARFE_Pos (8U) 13084 #define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */ 13085 #define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */ 13086 13087 #define ETH_PTPTSCR_TSARU_Pos (5U) 13088 #define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */ 13089 #define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */ 13090 #define ETH_PTPTSCR_TSITE_Pos (4U) 13091 #define ETH_PTPTSCR_TSITE_Msk (0x1UL << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */ 13092 #define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */ 13093 #define ETH_PTPTSCR_TSSTU_Pos (3U) 13094 #define ETH_PTPTSCR_TSSTU_Msk (0x1UL << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */ 13095 #define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */ 13096 #define ETH_PTPTSCR_TSSTI_Pos (2U) 13097 #define ETH_PTPTSCR_TSSTI_Msk (0x1UL << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */ 13098 #define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */ 13099 #define ETH_PTPTSCR_TSFCU_Pos (1U) 13100 #define ETH_PTPTSCR_TSFCU_Msk (0x1UL << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */ 13101 #define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */ 13102 #define ETH_PTPTSCR_TSE_Pos (0U) 13103 #define ETH_PTPTSCR_TSE_Msk (0x1UL << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */ 13104 #define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */ 13105 13106 /* Bit definition for Ethernet PTP Sub-Second Increment Register */ 13107 #define ETH_PTPSSIR_STSSI_Pos (0U) 13108 #define ETH_PTPSSIR_STSSI_Msk (0xFFUL << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */ 13109 #define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */ 13110 13111 /* Bit definition for Ethernet PTP Time Stamp High Register */ 13112 #define ETH_PTPTSHR_STS_Pos (0U) 13113 #define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */ 13114 #define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */ 13115 13116 /* Bit definition for Ethernet PTP Time Stamp Low Register */ 13117 #define ETH_PTPTSLR_STPNS_Pos (31U) 13118 #define ETH_PTPTSLR_STPNS_Msk (0x1UL << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */ 13119 #define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */ 13120 #define ETH_PTPTSLR_STSS_Pos (0U) 13121 #define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */ 13122 #define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */ 13123 13124 /* Bit definition for Ethernet PTP Time Stamp High Update Register */ 13125 #define ETH_PTPTSHUR_TSUS_Pos (0U) 13126 #define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */ 13127 #define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */ 13128 13129 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */ 13130 #define ETH_PTPTSLUR_TSUPNS_Pos (31U) 13131 #define ETH_PTPTSLUR_TSUPNS_Msk (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */ 13132 #define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */ 13133 #define ETH_PTPTSLUR_TSUSS_Pos (0U) 13134 #define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */ 13135 #define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */ 13136 13137 /* Bit definition for Ethernet PTP Time Stamp Addend Register */ 13138 #define ETH_PTPTSAR_TSA_Pos (0U) 13139 #define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */ 13140 #define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */ 13141 13142 /* Bit definition for Ethernet PTP Target Time High Register */ 13143 #define ETH_PTPTTHR_TTSH_Pos (0U) 13144 #define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */ 13145 #define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */ 13146 13147 /* Bit definition for Ethernet PTP Target Time Low Register */ 13148 #define ETH_PTPTTLR_TTSL_Pos (0U) 13149 #define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */ 13150 #define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */ 13151 13152 /* Bit definition for Ethernet PTP Time Stamp Status Register */ 13153 #define ETH_PTPTSSR_TSTTR_Pos (5U) 13154 #define ETH_PTPTSSR_TSTTR_Msk (0x1UL << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */ 13155 #define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */ 13156 #define ETH_PTPTSSR_TSSO_Pos (4U) 13157 #define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */ 13158 #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */ 13159 13160 /******************************************************************************/ 13161 /* Ethernet DMA Registers bits definition */ 13162 /******************************************************************************/ 13163 13164 /* Bit definition for Ethernet DMA Bus Mode Register */ 13165 #define ETH_DMABMR_AAB_Pos (25U) 13166 #define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */ 13167 #define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */ 13168 #define ETH_DMABMR_FPM_Pos (24U) 13169 #define ETH_DMABMR_FPM_Msk (0x1UL << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */ 13170 #define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */ 13171 #define ETH_DMABMR_USP_Pos (23U) 13172 #define ETH_DMABMR_USP_Msk (0x1UL << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */ 13173 #define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */ 13174 #define ETH_DMABMR_RDP_Pos (17U) 13175 #define ETH_DMABMR_RDP_Msk (0x3FUL << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */ 13176 #define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */ 13177 #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ 13178 #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ 13179 #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ 13180 #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ 13181 #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ 13182 #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ 13183 #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ 13184 #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ 13185 #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ 13186 #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ 13187 #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ 13188 #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ 13189 #define ETH_DMABMR_FB_Pos (16U) 13190 #define ETH_DMABMR_FB_Msk (0x1UL << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */ 13191 #define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */ 13192 #define ETH_DMABMR_RTPR_Pos (14U) 13193 #define ETH_DMABMR_RTPR_Msk (0x3UL << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */ 13194 #define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */ 13195 #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */ 13196 #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */ 13197 #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */ 13198 #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */ 13199 #define ETH_DMABMR_PBL_Pos (8U) 13200 #define ETH_DMABMR_PBL_Msk (0x3FUL << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */ 13201 #define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */ 13202 #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ 13203 #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ 13204 #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 13205 #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 13206 #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 13207 #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 13208 #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 13209 #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 13210 #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 13211 #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 13212 #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ 13213 #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ 13214 #define ETH_DMABMR_EDE_Pos (7U) 13215 #define ETH_DMABMR_EDE_Msk (0x1UL << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */ 13216 #define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */ 13217 #define ETH_DMABMR_DSL_Pos (2U) 13218 #define ETH_DMABMR_DSL_Msk (0x1FUL << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */ 13219 #define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */ 13220 #define ETH_DMABMR_DA_Pos (1U) 13221 #define ETH_DMABMR_DA_Msk (0x1UL << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */ 13222 #define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */ 13223 #define ETH_DMABMR_SR_Pos (0U) 13224 #define ETH_DMABMR_SR_Msk (0x1UL << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */ 13225 #define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */ 13226 13227 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */ 13228 #define ETH_DMATPDR_TPD_Pos (0U) 13229 #define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */ 13230 #define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */ 13231 13232 /* Bit definition for Ethernet DMA Receive Poll Demand Register */ 13233 #define ETH_DMARPDR_RPD_Pos (0U) 13234 #define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */ 13235 #define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */ 13236 13237 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ 13238 #define ETH_DMARDLAR_SRL_Pos (0U) 13239 #define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */ 13240 #define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */ 13241 13242 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ 13243 #define ETH_DMATDLAR_STL_Pos (0U) 13244 #define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */ 13245 #define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */ 13246 13247 /* Bit definition for Ethernet DMA Status Register */ 13248 #define ETH_DMASR_TSTS_Pos (29U) 13249 #define ETH_DMASR_TSTS_Msk (0x1UL << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */ 13250 #define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */ 13251 #define ETH_DMASR_PMTS_Pos (28U) 13252 #define ETH_DMASR_PMTS_Msk (0x1UL << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */ 13253 #define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */ 13254 #define ETH_DMASR_MMCS_Pos (27U) 13255 #define ETH_DMASR_MMCS_Msk (0x1UL << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */ 13256 #define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */ 13257 #define ETH_DMASR_EBS_Pos (23U) 13258 #define ETH_DMASR_EBS_Msk (0x7UL << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */ 13259 #define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */ 13260 /* combination with EBS[2:0] for GetFlagStatus function */ 13261 #define ETH_DMASR_EBS_DescAccess_Pos (25U) 13262 #define ETH_DMASR_EBS_DescAccess_Msk (0x1UL << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */ 13263 #define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */ 13264 #define ETH_DMASR_EBS_ReadTransf_Pos (24U) 13265 #define ETH_DMASR_EBS_ReadTransf_Msk (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */ 13266 #define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */ 13267 #define ETH_DMASR_EBS_DataTransfTx_Pos (23U) 13268 #define ETH_DMASR_EBS_DataTransfTx_Msk (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */ 13269 #define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */ 13270 #define ETH_DMASR_TPS_Pos (20U) 13271 #define ETH_DMASR_TPS_Msk (0x7UL << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */ 13272 #define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */ 13273 #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */ 13274 #define ETH_DMASR_TPS_Fetching_Pos (20U) 13275 #define ETH_DMASR_TPS_Fetching_Msk (0x1UL << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */ 13276 #define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */ 13277 #define ETH_DMASR_TPS_Waiting_Pos (21U) 13278 #define ETH_DMASR_TPS_Waiting_Msk (0x1UL << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */ 13279 #define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */ 13280 #define ETH_DMASR_TPS_Reading_Pos (20U) 13281 #define ETH_DMASR_TPS_Reading_Msk (0x3UL << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */ 13282 #define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */ 13283 #define ETH_DMASR_TPS_Suspended_Pos (21U) 13284 #define ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */ 13285 #define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailable */ 13286 #define ETH_DMASR_TPS_Closing_Pos (20U) 13287 #define ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */ 13288 #define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */ 13289 #define ETH_DMASR_RPS_Pos (17U) 13290 #define ETH_DMASR_RPS_Msk (0x7UL << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */ 13291 #define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */ 13292 #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */ 13293 #define ETH_DMASR_RPS_Fetching_Pos (17U) 13294 #define ETH_DMASR_RPS_Fetching_Msk (0x1UL << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */ 13295 #define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */ 13296 #define ETH_DMASR_RPS_Waiting_Pos (17U) 13297 #define ETH_DMASR_RPS_Waiting_Msk (0x3UL << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */ 13298 #define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */ 13299 #define ETH_DMASR_RPS_Suspended_Pos (19U) 13300 #define ETH_DMASR_RPS_Suspended_Msk (0x1UL << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */ 13301 #define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */ 13302 #define ETH_DMASR_RPS_Closing_Pos (17U) 13303 #define ETH_DMASR_RPS_Closing_Msk (0x5UL << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */ 13304 #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */ 13305 #define ETH_DMASR_RPS_Queuing_Pos (17U) 13306 #define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */ 13307 #define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */ 13308 #define ETH_DMASR_NIS_Pos (16U) 13309 #define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */ 13310 #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */ 13311 #define ETH_DMASR_AIS_Pos (15U) 13312 #define ETH_DMASR_AIS_Msk (0x1UL << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */ 13313 #define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */ 13314 #define ETH_DMASR_ERS_Pos (14U) 13315 #define ETH_DMASR_ERS_Msk (0x1UL << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */ 13316 #define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */ 13317 #define ETH_DMASR_FBES_Pos (13U) 13318 #define ETH_DMASR_FBES_Msk (0x1UL << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */ 13319 #define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */ 13320 #define ETH_DMASR_ETS_Pos (10U) 13321 #define ETH_DMASR_ETS_Msk (0x1UL << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */ 13322 #define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */ 13323 #define ETH_DMASR_RWTS_Pos (9U) 13324 #define ETH_DMASR_RWTS_Msk (0x1UL << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */ 13325 #define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */ 13326 #define ETH_DMASR_RPSS_Pos (8U) 13327 #define ETH_DMASR_RPSS_Msk (0x1UL << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */ 13328 #define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */ 13329 #define ETH_DMASR_RBUS_Pos (7U) 13330 #define ETH_DMASR_RBUS_Msk (0x1UL << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */ 13331 #define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */ 13332 #define ETH_DMASR_RS_Pos (6U) 13333 #define ETH_DMASR_RS_Msk (0x1UL << ETH_DMASR_RS_Pos) /*!< 0x00000040 */ 13334 #define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */ 13335 #define ETH_DMASR_TUS_Pos (5U) 13336 #define ETH_DMASR_TUS_Msk (0x1UL << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */ 13337 #define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */ 13338 #define ETH_DMASR_ROS_Pos (4U) 13339 #define ETH_DMASR_ROS_Msk (0x1UL << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */ 13340 #define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */ 13341 #define ETH_DMASR_TJTS_Pos (3U) 13342 #define ETH_DMASR_TJTS_Msk (0x1UL << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */ 13343 #define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */ 13344 #define ETH_DMASR_TBUS_Pos (2U) 13345 #define ETH_DMASR_TBUS_Msk (0x1UL << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */ 13346 #define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */ 13347 #define ETH_DMASR_TPSS_Pos (1U) 13348 #define ETH_DMASR_TPSS_Msk (0x1UL << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */ 13349 #define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */ 13350 #define ETH_DMASR_TS_Pos (0U) 13351 #define ETH_DMASR_TS_Msk (0x1UL << ETH_DMASR_TS_Pos) /*!< 0x00000001 */ 13352 #define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */ 13353 13354 /* Bit definition for Ethernet DMA Operation Mode Register */ 13355 #define ETH_DMAOMR_DTCEFD_Pos (26U) 13356 #define ETH_DMAOMR_DTCEFD_Msk (0x1UL << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */ 13357 #define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */ 13358 #define ETH_DMAOMR_RSF_Pos (25U) 13359 #define ETH_DMAOMR_RSF_Msk (0x1UL << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */ 13360 #define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */ 13361 #define ETH_DMAOMR_DFRF_Pos (24U) 13362 #define ETH_DMAOMR_DFRF_Msk (0x1UL << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */ 13363 #define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */ 13364 #define ETH_DMAOMR_TSF_Pos (21U) 13365 #define ETH_DMAOMR_TSF_Msk (0x1UL << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */ 13366 #define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */ 13367 #define ETH_DMAOMR_FTF_Pos (20U) 13368 #define ETH_DMAOMR_FTF_Msk (0x1UL << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */ 13369 #define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */ 13370 #define ETH_DMAOMR_TTC_Pos (14U) 13371 #define ETH_DMAOMR_TTC_Msk (0x7UL << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */ 13372 #define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */ 13373 #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */ 13374 #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */ 13375 #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */ 13376 #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */ 13377 #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */ 13378 #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */ 13379 #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */ 13380 #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */ 13381 #define ETH_DMAOMR_ST_Pos (13U) 13382 #define ETH_DMAOMR_ST_Msk (0x1UL << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */ 13383 #define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */ 13384 #define ETH_DMAOMR_FEF_Pos (7U) 13385 #define ETH_DMAOMR_FEF_Msk (0x1UL << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */ 13386 #define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */ 13387 #define ETH_DMAOMR_FUGF_Pos (6U) 13388 #define ETH_DMAOMR_FUGF_Msk (0x1UL << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */ 13389 #define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */ 13390 #define ETH_DMAOMR_RTC_Pos (3U) 13391 #define ETH_DMAOMR_RTC_Msk (0x3UL << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */ 13392 #define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */ 13393 #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */ 13394 #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */ 13395 #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */ 13396 #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */ 13397 #define ETH_DMAOMR_OSF_Pos (2U) 13398 #define ETH_DMAOMR_OSF_Msk (0x1UL << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */ 13399 #define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */ 13400 #define ETH_DMAOMR_SR_Pos (1U) 13401 #define ETH_DMAOMR_SR_Msk (0x1UL << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */ 13402 #define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */ 13403 13404 /* Bit definition for Ethernet DMA Interrupt Enable Register */ 13405 #define ETH_DMAIER_NISE_Pos (16U) 13406 #define ETH_DMAIER_NISE_Msk (0x1UL << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */ 13407 #define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */ 13408 #define ETH_DMAIER_AISE_Pos (15U) 13409 #define ETH_DMAIER_AISE_Msk (0x1UL << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */ 13410 #define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */ 13411 #define ETH_DMAIER_ERIE_Pos (14U) 13412 #define ETH_DMAIER_ERIE_Msk (0x1UL << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */ 13413 #define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */ 13414 #define ETH_DMAIER_FBEIE_Pos (13U) 13415 #define ETH_DMAIER_FBEIE_Msk (0x1UL << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */ 13416 #define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */ 13417 #define ETH_DMAIER_ETIE_Pos (10U) 13418 #define ETH_DMAIER_ETIE_Msk (0x1UL << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */ 13419 #define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */ 13420 #define ETH_DMAIER_RWTIE_Pos (9U) 13421 #define ETH_DMAIER_RWTIE_Msk (0x1UL << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */ 13422 #define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */ 13423 #define ETH_DMAIER_RPSIE_Pos (8U) 13424 #define ETH_DMAIER_RPSIE_Msk (0x1UL << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */ 13425 #define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */ 13426 #define ETH_DMAIER_RBUIE_Pos (7U) 13427 #define ETH_DMAIER_RBUIE_Msk (0x1UL << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */ 13428 #define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */ 13429 #define ETH_DMAIER_RIE_Pos (6U) 13430 #define ETH_DMAIER_RIE_Msk (0x1UL << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */ 13431 #define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */ 13432 #define ETH_DMAIER_TUIE_Pos (5U) 13433 #define ETH_DMAIER_TUIE_Msk (0x1UL << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */ 13434 #define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */ 13435 #define ETH_DMAIER_ROIE_Pos (4U) 13436 #define ETH_DMAIER_ROIE_Msk (0x1UL << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */ 13437 #define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */ 13438 #define ETH_DMAIER_TJTIE_Pos (3U) 13439 #define ETH_DMAIER_TJTIE_Msk (0x1UL << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */ 13440 #define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */ 13441 #define ETH_DMAIER_TBUIE_Pos (2U) 13442 #define ETH_DMAIER_TBUIE_Msk (0x1UL << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */ 13443 #define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */ 13444 #define ETH_DMAIER_TPSIE_Pos (1U) 13445 #define ETH_DMAIER_TPSIE_Msk (0x1UL << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */ 13446 #define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */ 13447 #define ETH_DMAIER_TIE_Pos (0U) 13448 #define ETH_DMAIER_TIE_Msk (0x1UL << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */ 13449 #define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */ 13450 13451 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ 13452 #define ETH_DMAMFBOCR_OFOC_Pos (28U) 13453 #define ETH_DMAMFBOCR_OFOC_Msk (0x1UL << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */ 13454 #define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */ 13455 #define ETH_DMAMFBOCR_MFA_Pos (17U) 13456 #define ETH_DMAMFBOCR_MFA_Msk (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */ 13457 #define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */ 13458 #define ETH_DMAMFBOCR_OMFC_Pos (16U) 13459 #define ETH_DMAMFBOCR_OMFC_Msk (0x1UL << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */ 13460 #define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */ 13461 #define ETH_DMAMFBOCR_MFC_Pos (0U) 13462 #define ETH_DMAMFBOCR_MFC_Msk (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */ 13463 #define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */ 13464 13465 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ 13466 #define ETH_DMACHTDR_HTDAP_Pos (0U) 13467 #define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */ 13468 #define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */ 13469 13470 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ 13471 #define ETH_DMACHRDR_HRDAP_Pos (0U) 13472 #define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */ 13473 #define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */ 13474 13475 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ 13476 #define ETH_DMACHTBAR_HTBAP_Pos (0U) 13477 #define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */ 13478 #define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */ 13479 13480 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ 13481 #define ETH_DMACHRBAR_HRBAP_Pos (0U) 13482 #define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */ 13483 #define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */ 13484 13485 /******************************************************************************/ 13486 /* */ 13487 /* USB_OTG */ 13488 /* */ 13489 /******************************************************************************/ 13490 /******************** Bit definition for USB_OTG_GOTGCTL register ***********/ 13491 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U) 13492 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */ 13493 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */ 13494 #define USB_OTG_GOTGCTL_SRQ_Pos (1U) 13495 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */ 13496 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */ 13497 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U) 13498 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */ 13499 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */ 13500 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U) 13501 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */ 13502 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */ 13503 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U) 13504 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */ 13505 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */ 13506 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U) 13507 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */ 13508 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */ 13509 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) 13510 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ 13511 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ 13512 #define USB_OTG_GOTGCTL_DBCT_Pos (17U) 13513 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ 13514 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ 13515 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U) 13516 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ 13517 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ 13518 #define USB_OTG_GOTGCTL_BSVLD_Pos (19U) 13519 #define USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ 13520 #define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ 13521 13522 /******************** Bit definition for USB_OTG_HCFG register ********************/ 13523 13524 #define USB_OTG_HCFG_FSLSPCS_Pos (0U) 13525 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */ 13526 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */ 13527 #define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */ 13528 #define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */ 13529 #define USB_OTG_HCFG_FSLSS_Pos (2U) 13530 #define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */ 13531 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */ 13532 13533 /******************** Bit definition for USB_OTG_DCFG register ********************/ 13534 13535 #define USB_OTG_DCFG_DSPD_Pos (0U) 13536 #define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */ 13537 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */ 13538 #define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */ 13539 #define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */ 13540 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U) 13541 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */ 13542 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */ 13543 13544 #define USB_OTG_DCFG_DAD_Pos (4U) 13545 #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ 13546 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ 13547 #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ 13548 #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ 13549 #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ 13550 #define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */ 13551 #define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */ 13552 #define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */ 13553 #define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */ 13554 13555 #define USB_OTG_DCFG_PFIVL_Pos (11U) 13556 #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ 13557 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ 13558 #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ 13559 #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ 13560 13561 #define USB_OTG_DCFG_XCVRDLY_Pos (14U) 13562 #define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ 13563 #define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */ 13564 13565 #define USB_OTG_DCFG_ERRATIM_Pos (15U) 13566 #define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ 13567 #define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ 13568 13569 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) 13570 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ 13571 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ 13572 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ 13573 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ 13574 13575 /******************** Bit definition for USB_OTG_PCGCR register ********************/ 13576 #define USB_OTG_PCGCR_STPPCLK_Pos (0U) 13577 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */ 13578 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */ 13579 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U) 13580 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */ 13581 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */ 13582 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U) 13583 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */ 13584 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */ 13585 13586 /******************** Bit definition for USB_OTG_GOTGINT register ********************/ 13587 #define USB_OTG_GOTGINT_SEDET_Pos (2U) 13588 #define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */ 13589 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */ 13590 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U) 13591 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */ 13592 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */ 13593 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U) 13594 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */ 13595 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */ 13596 #define USB_OTG_GOTGINT_HNGDET_Pos (17U) 13597 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */ 13598 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */ 13599 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U) 13600 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */ 13601 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */ 13602 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U) 13603 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */ 13604 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */ 13605 13606 /******************** Bit definition for USB_OTG_DCTL register ********************/ 13607 #define USB_OTG_DCTL_RWUSIG_Pos (0U) 13608 #define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */ 13609 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */ 13610 #define USB_OTG_DCTL_SDIS_Pos (1U) 13611 #define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */ 13612 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */ 13613 #define USB_OTG_DCTL_GINSTS_Pos (2U) 13614 #define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */ 13615 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */ 13616 #define USB_OTG_DCTL_GONSTS_Pos (3U) 13617 #define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */ 13618 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */ 13619 13620 #define USB_OTG_DCTL_TCTL_Pos (4U) 13621 #define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */ 13622 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */ 13623 #define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */ 13624 #define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */ 13625 #define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */ 13626 #define USB_OTG_DCTL_SGINAK_Pos (7U) 13627 #define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */ 13628 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */ 13629 #define USB_OTG_DCTL_CGINAK_Pos (8U) 13630 #define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */ 13631 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */ 13632 #define USB_OTG_DCTL_SGONAK_Pos (9U) 13633 #define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */ 13634 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */ 13635 #define USB_OTG_DCTL_CGONAK_Pos (10U) 13636 #define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */ 13637 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */ 13638 #define USB_OTG_DCTL_POPRGDNE_Pos (11U) 13639 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ 13640 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ 13641 13642 /******************** Bit definition for USB_OTG_HFIR register ********************/ 13643 #define USB_OTG_HFIR_FRIVL_Pos (0U) 13644 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ 13645 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ 13646 13647 /******************** Bit definition for USB_OTG_HFNUM register ********************/ 13648 #define USB_OTG_HFNUM_FRNUM_Pos (0U) 13649 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */ 13650 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */ 13651 #define USB_OTG_HFNUM_FTREM_Pos (16U) 13652 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */ 13653 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */ 13654 13655 /******************** Bit definition for USB_OTG_DSTS register ********************/ 13656 #define USB_OTG_DSTS_SUSPSTS_Pos (0U) 13657 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */ 13658 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */ 13659 13660 #define USB_OTG_DSTS_ENUMSPD_Pos (1U) 13661 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */ 13662 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */ 13663 #define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */ 13664 #define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */ 13665 #define USB_OTG_DSTS_EERR_Pos (3U) 13666 #define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */ 13667 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */ 13668 #define USB_OTG_DSTS_FNSOF_Pos (8U) 13669 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ 13670 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ 13671 13672 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ 13673 #define USB_OTG_GAHBCFG_GINT_Pos (0U) 13674 #define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ 13675 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ 13676 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) 13677 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ 13678 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ 13679 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */ 13680 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */ 13681 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */ 13682 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */ 13683 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */ 13684 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U) 13685 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */ 13686 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */ 13687 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U) 13688 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */ 13689 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */ 13690 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U) 13691 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */ 13692 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */ 13693 13694 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/ 13695 13696 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U) 13697 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */ 13698 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */ 13699 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */ 13700 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */ 13701 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */ 13702 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U) 13703 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */ 13704 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ 13705 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U) 13706 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */ 13707 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */ 13708 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U) 13709 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */ 13710 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */ 13711 #define USB_OTG_GUSBCFG_TRDT_Pos (10U) 13712 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */ 13713 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */ 13714 #define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */ 13715 #define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ 13716 #define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ 13717 #define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ 13718 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) 13719 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ 13720 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ 13721 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) 13722 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ 13723 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ 13724 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U) 13725 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */ 13726 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */ 13727 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U) 13728 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */ 13729 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */ 13730 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U) 13731 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */ 13732 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */ 13733 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U) 13734 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */ 13735 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */ 13736 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U) 13737 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */ 13738 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */ 13739 #define USB_OTG_GUSBCFG_PCCI_Pos (23U) 13740 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */ 13741 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */ 13742 #define USB_OTG_GUSBCFG_PTCI_Pos (24U) 13743 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */ 13744 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */ 13745 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U) 13746 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */ 13747 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */ 13748 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U) 13749 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */ 13750 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */ 13751 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U) 13752 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */ 13753 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ 13754 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) 13755 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ 13756 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ 13757 13758 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/ 13759 #define USB_OTG_GRSTCTL_CSRST_Pos (0U) 13760 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ 13761 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ 13762 #define USB_OTG_GRSTCTL_HSRST_Pos (1U) 13763 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ 13764 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ 13765 #define USB_OTG_GRSTCTL_FCRST_Pos (2U) 13766 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ 13767 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ 13768 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U) 13769 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */ 13770 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */ 13771 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U) 13772 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */ 13773 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */ 13774 13775 13776 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U) 13777 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */ 13778 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */ 13779 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */ 13780 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */ 13781 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */ 13782 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */ 13783 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */ 13784 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U) 13785 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */ 13786 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */ 13787 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U) 13788 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */ 13789 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */ 13790 13791 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/ 13792 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U) 13793 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */ 13794 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ 13795 #define USB_OTG_DIEPMSK_EPDM_Pos (1U) 13796 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ 13797 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ 13798 #define USB_OTG_DIEPMSK_TOM_Pos (3U) 13799 #define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ 13800 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ 13801 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U) 13802 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */ 13803 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ 13804 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U) 13805 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */ 13806 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ 13807 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U) 13808 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */ 13809 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ 13810 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U) 13811 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */ 13812 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */ 13813 #define USB_OTG_DIEPMSK_BIM_Pos (9U) 13814 #define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ 13815 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ 13816 13817 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ 13818 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) 13819 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */ 13820 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */ 13821 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U) 13822 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */ 13823 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */ 13824 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */ 13825 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */ 13826 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */ 13827 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */ 13828 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */ 13829 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */ 13830 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */ 13831 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */ 13832 13833 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U) 13834 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */ 13835 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */ 13836 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */ 13837 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */ 13838 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */ 13839 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */ 13840 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */ 13841 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */ 13842 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */ 13843 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */ 13844 13845 /******************** Bit definition for USB_OTG_HAINT register ********************/ 13846 #define USB_OTG_HAINT_HAINT_Pos (0U) 13847 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */ 13848 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */ 13849 13850 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/ 13851 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U) 13852 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */ 13853 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ 13854 #define USB_OTG_DOEPMSK_EPDM_Pos (1U) 13855 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ 13856 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ 13857 #define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) 13858 #define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ 13859 #define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */ 13860 #define USB_OTG_DOEPMSK_STUPM_Pos (3U) 13861 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ 13862 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ 13863 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) 13864 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ 13865 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ 13866 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U) 13867 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */ 13868 #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */ 13869 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) 13870 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ 13871 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ 13872 #define USB_OTG_DOEPMSK_OPEM_Pos (8U) 13873 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ 13874 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ 13875 #define USB_OTG_DOEPMSK_BOIM_Pos (9U) 13876 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ 13877 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ 13878 #define USB_OTG_DOEPMSK_BERRM_Pos (12U) 13879 #define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ 13880 #define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ 13881 #define USB_OTG_DOEPMSK_NAKM_Pos (13U) 13882 #define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */ 13883 #define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */ 13884 #define USB_OTG_DOEPMSK_NYETM_Pos (14U) 13885 #define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */ 13886 #define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */ 13887 /******************** Bit definition for USB_OTG_GINTSTS register ********************/ 13888 #define USB_OTG_GINTSTS_CMOD_Pos (0U) 13889 #define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */ 13890 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */ 13891 #define USB_OTG_GINTSTS_MMIS_Pos (1U) 13892 #define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */ 13893 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */ 13894 #define USB_OTG_GINTSTS_OTGINT_Pos (2U) 13895 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */ 13896 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */ 13897 #define USB_OTG_GINTSTS_SOF_Pos (3U) 13898 #define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */ 13899 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */ 13900 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U) 13901 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */ 13902 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */ 13903 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U) 13904 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */ 13905 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */ 13906 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) 13907 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ 13908 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ 13909 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) 13910 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ 13911 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ 13912 #define USB_OTG_GINTSTS_ESUSP_Pos (10U) 13913 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ 13914 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ 13915 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U) 13916 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */ 13917 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */ 13918 #define USB_OTG_GINTSTS_USBRST_Pos (12U) 13919 #define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */ 13920 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */ 13921 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U) 13922 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */ 13923 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */ 13924 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U) 13925 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */ 13926 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */ 13927 #define USB_OTG_GINTSTS_EOPF_Pos (15U) 13928 #define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */ 13929 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */ 13930 #define USB_OTG_GINTSTS_IEPINT_Pos (18U) 13931 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */ 13932 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */ 13933 #define USB_OTG_GINTSTS_OEPINT_Pos (19U) 13934 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */ 13935 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */ 13936 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U) 13937 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */ 13938 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */ 13939 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) 13940 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */ 13941 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */ 13942 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) 13943 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ 13944 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ 13945 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) 13946 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ 13947 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ 13948 #define USB_OTG_GINTSTS_HCINT_Pos (25U) 13949 #define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */ 13950 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */ 13951 #define USB_OTG_GINTSTS_PTXFE_Pos (26U) 13952 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */ 13953 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */ 13954 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U) 13955 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */ 13956 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */ 13957 #define USB_OTG_GINTSTS_DISCINT_Pos (29U) 13958 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */ 13959 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */ 13960 #define USB_OTG_GINTSTS_SRQINT_Pos (30U) 13961 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ 13962 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ 13963 #define USB_OTG_GINTSTS_WKUINT_Pos (31U) 13964 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ 13965 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ 13966 13967 /******************** Bit definition for USB_OTG_GINTMSK register ********************/ 13968 #define USB_OTG_GINTMSK_MMISM_Pos (1U) 13969 #define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */ 13970 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */ 13971 #define USB_OTG_GINTMSK_OTGINT_Pos (2U) 13972 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */ 13973 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */ 13974 #define USB_OTG_GINTMSK_SOFM_Pos (3U) 13975 #define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */ 13976 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */ 13977 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U) 13978 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */ 13979 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */ 13980 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U) 13981 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */ 13982 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */ 13983 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U) 13984 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */ 13985 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */ 13986 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U) 13987 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */ 13988 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */ 13989 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U) 13990 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */ 13991 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */ 13992 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U) 13993 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */ 13994 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */ 13995 #define USB_OTG_GINTMSK_USBRST_Pos (12U) 13996 #define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */ 13997 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */ 13998 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U) 13999 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */ 14000 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */ 14001 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U) 14002 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */ 14003 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */ 14004 #define USB_OTG_GINTMSK_EOPFM_Pos (15U) 14005 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */ 14006 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */ 14007 #define USB_OTG_GINTMSK_EPMISM_Pos (17U) 14008 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */ 14009 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */ 14010 #define USB_OTG_GINTMSK_IEPINT_Pos (18U) 14011 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */ 14012 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */ 14013 #define USB_OTG_GINTMSK_OEPINT_Pos (19U) 14014 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */ 14015 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */ 14016 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) 14017 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ 14018 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ 14019 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) 14020 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ 14021 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ 14022 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) 14023 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ 14024 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ 14025 #define USB_OTG_GINTMSK_PRTIM_Pos (24U) 14026 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ 14027 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ 14028 #define USB_OTG_GINTMSK_HCIM_Pos (25U) 14029 #define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */ 14030 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */ 14031 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U) 14032 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */ 14033 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */ 14034 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U) 14035 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */ 14036 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */ 14037 #define USB_OTG_GINTMSK_DISCINT_Pos (29U) 14038 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */ 14039 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */ 14040 #define USB_OTG_GINTMSK_SRQIM_Pos (30U) 14041 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */ 14042 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */ 14043 #define USB_OTG_GINTMSK_WUIM_Pos (31U) 14044 #define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */ 14045 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */ 14046 14047 /******************** Bit definition for USB_OTG_DAINT register ********************/ 14048 #define USB_OTG_DAINT_IEPINT_Pos (0U) 14049 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */ 14050 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */ 14051 #define USB_OTG_DAINT_OEPINT_Pos (16U) 14052 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */ 14053 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */ 14054 14055 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/ 14056 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U) 14057 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ 14058 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ 14059 14060 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ 14061 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U) 14062 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ 14063 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ 14064 #define USB_OTG_GRXSTSP_BCNT_Pos (4U) 14065 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ 14066 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ 14067 #define USB_OTG_GRXSTSP_DPID_Pos (15U) 14068 #define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ 14069 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ 14070 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) 14071 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ 14072 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ 14073 14074 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ 14075 #define USB_OTG_DAINTMSK_IEPM_Pos (0U) 14076 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */ 14077 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */ 14078 #define USB_OTG_DAINTMSK_OEPM_Pos (16U) 14079 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ 14080 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ 14081 14082 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ 14083 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U) 14084 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ 14085 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */ 14086 14087 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/ 14088 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U) 14089 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */ 14090 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */ 14091 14092 /******************** Bit definition for OTG register ********************/ 14093 #define USB_OTG_NPTXFSA_Pos (0U) 14094 #define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */ 14095 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */ 14096 #define USB_OTG_NPTXFD_Pos (16U) 14097 #define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */ 14098 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */ 14099 #define USB_OTG_TX0FSA_Pos (0U) 14100 #define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */ 14101 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */ 14102 #define USB_OTG_TX0FD_Pos (16U) 14103 #define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */ 14104 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */ 14105 14106 /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/ 14107 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U) 14108 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */ 14109 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */ 14110 14111 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/ 14112 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U) 14113 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */ 14114 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */ 14115 14116 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U) 14117 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */ 14118 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */ 14119 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */ 14120 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */ 14121 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */ 14122 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */ 14123 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */ 14124 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */ 14125 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */ 14126 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */ 14127 14128 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U) 14129 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */ 14130 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */ 14131 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */ 14132 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */ 14133 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */ 14134 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */ 14135 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */ 14136 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */ 14137 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */ 14138 14139 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/ 14140 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U) 14141 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */ 14142 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */ 14143 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U) 14144 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */ 14145 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */ 14146 14147 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U) 14148 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */ 14149 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */ 14150 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */ 14151 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */ 14152 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */ 14153 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */ 14154 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */ 14155 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */ 14156 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */ 14157 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */ 14158 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */ 14159 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U) 14160 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */ 14161 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */ 14162 14163 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U) 14164 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */ 14165 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */ 14166 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */ 14167 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */ 14168 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */ 14169 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */ 14170 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */ 14171 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */ 14172 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */ 14173 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */ 14174 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */ 14175 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U) 14176 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */ 14177 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */ 14178 14179 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/ 14180 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U) 14181 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */ 14182 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */ 14183 14184 /******************** Bit definition for USB_OTG_DEACHINT register ********************/ 14185 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U) 14186 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */ 14187 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */ 14188 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U) 14189 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */ 14190 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */ 14191 14192 /******************** Bit definition for USB_OTG_GCCFG register ********************/ 14193 #define USB_OTG_GCCFG_PWRDWN_Pos (16U) 14194 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */ 14195 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */ 14196 #define USB_OTG_GCCFG_I2CPADEN_Pos (17U) 14197 #define USB_OTG_GCCFG_I2CPADEN_Msk (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */ 14198 #define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface */ 14199 #define USB_OTG_GCCFG_VBUSASEN_Pos (18U) 14200 #define USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */ 14201 #define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */ 14202 #define USB_OTG_GCCFG_VBUSBSEN_Pos (19U) 14203 #define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */ 14204 #define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */ 14205 #define USB_OTG_GCCFG_SOFOUTEN_Pos (20U) 14206 #define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */ 14207 #define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */ 14208 #define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U) 14209 #define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */ 14210 #define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option */ 14211 14212 /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/ 14213 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U) 14214 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */ 14215 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */ 14216 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U) 14217 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */ 14218 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */ 14219 14220 /******************** Bit definition for USB_OTG_CID register ********************/ 14221 #define USB_OTG_CID_PRODUCT_ID_Pos (0U) 14222 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */ 14223 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */ 14224 14225 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ 14226 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) 14227 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ 14228 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ 14229 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U) 14230 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ 14231 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ 14232 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U) 14233 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ 14234 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ 14235 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U) 14236 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ 14237 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ 14238 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U) 14239 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ 14240 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ 14241 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U) 14242 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ 14243 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ 14244 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U) 14245 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ 14246 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */ 14247 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U) 14248 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ 14249 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ 14250 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U) 14251 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ 14252 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ 14253 14254 /******************** Bit definition for USB_OTG_HPRT register ********************/ 14255 #define USB_OTG_HPRT_PCSTS_Pos (0U) 14256 #define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */ 14257 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */ 14258 #define USB_OTG_HPRT_PCDET_Pos (1U) 14259 #define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */ 14260 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */ 14261 #define USB_OTG_HPRT_PENA_Pos (2U) 14262 #define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */ 14263 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */ 14264 #define USB_OTG_HPRT_PENCHNG_Pos (3U) 14265 #define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */ 14266 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */ 14267 #define USB_OTG_HPRT_POCA_Pos (4U) 14268 #define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */ 14269 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */ 14270 #define USB_OTG_HPRT_POCCHNG_Pos (5U) 14271 #define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */ 14272 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */ 14273 #define USB_OTG_HPRT_PRES_Pos (6U) 14274 #define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */ 14275 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */ 14276 #define USB_OTG_HPRT_PSUSP_Pos (7U) 14277 #define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */ 14278 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */ 14279 #define USB_OTG_HPRT_PRST_Pos (8U) 14280 #define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ 14281 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ 14282 14283 #define USB_OTG_HPRT_PLSTS_Pos (10U) 14284 #define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ 14285 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ 14286 #define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */ 14287 #define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */ 14288 #define USB_OTG_HPRT_PPWR_Pos (12U) 14289 #define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ 14290 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ 14291 14292 #define USB_OTG_HPRT_PTCTL_Pos (13U) 14293 #define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ 14294 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ 14295 #define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */ 14296 #define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ 14297 #define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ 14298 #define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ 14299 14300 #define USB_OTG_HPRT_PSPD_Pos (17U) 14301 #define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ 14302 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ 14303 #define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */ 14304 #define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */ 14305 14306 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/ 14307 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U) 14308 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ 14309 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ 14310 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U) 14311 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ 14312 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ 14313 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U) 14314 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ 14315 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */ 14316 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U) 14317 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ 14318 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ 14319 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U) 14320 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ 14321 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ 14322 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U) 14323 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ 14324 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ 14325 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U) 14326 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ 14327 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */ 14328 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U) 14329 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ 14330 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ 14331 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U) 14332 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */ 14333 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */ 14334 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U) 14335 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ 14336 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ 14337 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U) 14338 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */ 14339 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */ 14340 14341 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/ 14342 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) 14343 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ 14344 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ 14345 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) 14346 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ 14347 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ 14348 14349 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ 14350 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) 14351 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ 14352 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */ 14353 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U) 14354 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */ 14355 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */ 14356 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U) 14357 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */ 14358 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */ 14359 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U) 14360 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ 14361 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */ 14362 14363 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U) 14364 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ 14365 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */ 14366 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */ 14367 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */ 14368 #define USB_OTG_DIEPCTL_STALL_Pos (21U) 14369 #define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */ 14370 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */ 14371 14372 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U) 14373 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */ 14374 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */ 14375 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */ 14376 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */ 14377 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */ 14378 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */ 14379 #define USB_OTG_DIEPCTL_CNAK_Pos (26U) 14380 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */ 14381 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */ 14382 #define USB_OTG_DIEPCTL_SNAK_Pos (27U) 14383 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */ 14384 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ 14385 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) 14386 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ 14387 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ 14388 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) 14389 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ 14390 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ 14391 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) 14392 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ 14393 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ 14394 #define USB_OTG_DIEPCTL_EPENA_Pos (31U) 14395 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */ 14396 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */ 14397 14398 /******************** Bit definition for USB_OTG_HCCHAR register ********************/ 14399 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) 14400 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ 14401 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ 14402 14403 #define USB_OTG_HCCHAR_EPNUM_Pos (11U) 14404 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ 14405 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ 14406 #define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */ 14407 #define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */ 14408 #define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */ 14409 #define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */ 14410 #define USB_OTG_HCCHAR_EPDIR_Pos (15U) 14411 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */ 14412 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */ 14413 #define USB_OTG_HCCHAR_LSDEV_Pos (17U) 14414 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ 14415 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ 14416 14417 #define USB_OTG_HCCHAR_EPTYP_Pos (18U) 14418 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ 14419 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ 14420 #define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ 14421 #define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ 14422 14423 #define USB_OTG_HCCHAR_MC_Pos (20U) 14424 #define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ 14425 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ 14426 #define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ 14427 #define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ 14428 14429 #define USB_OTG_HCCHAR_DAD_Pos (22U) 14430 #define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ 14431 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ 14432 #define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */ 14433 #define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */ 14434 #define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */ 14435 #define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */ 14436 #define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */ 14437 #define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */ 14438 #define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */ 14439 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U) 14440 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */ 14441 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */ 14442 #define USB_OTG_HCCHAR_CHDIS_Pos (30U) 14443 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */ 14444 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */ 14445 #define USB_OTG_HCCHAR_CHENA_Pos (31U) 14446 #define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */ 14447 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */ 14448 14449 /******************** Bit definition for USB_OTG_HCSPLT register ********************/ 14450 14451 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U) 14452 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */ 14453 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */ 14454 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */ 14455 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */ 14456 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */ 14457 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */ 14458 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */ 14459 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */ 14460 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */ 14461 14462 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U) 14463 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */ 14464 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */ 14465 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */ 14466 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */ 14467 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */ 14468 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */ 14469 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */ 14470 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */ 14471 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */ 14472 14473 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U) 14474 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */ 14475 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */ 14476 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */ 14477 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */ 14478 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U) 14479 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */ 14480 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */ 14481 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U) 14482 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */ 14483 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */ 14484 14485 /******************** Bit definition for USB_OTG_HCINT register ********************/ 14486 #define USB_OTG_HCINT_XFRC_Pos (0U) 14487 #define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */ 14488 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */ 14489 #define USB_OTG_HCINT_CHH_Pos (1U) 14490 #define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */ 14491 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */ 14492 #define USB_OTG_HCINT_AHBERR_Pos (2U) 14493 #define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */ 14494 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */ 14495 #define USB_OTG_HCINT_STALL_Pos (3U) 14496 #define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */ 14497 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */ 14498 #define USB_OTG_HCINT_NAK_Pos (4U) 14499 #define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */ 14500 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */ 14501 #define USB_OTG_HCINT_ACK_Pos (5U) 14502 #define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */ 14503 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */ 14504 #define USB_OTG_HCINT_NYET_Pos (6U) 14505 #define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */ 14506 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */ 14507 #define USB_OTG_HCINT_TXERR_Pos (7U) 14508 #define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */ 14509 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */ 14510 #define USB_OTG_HCINT_BBERR_Pos (8U) 14511 #define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */ 14512 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */ 14513 #define USB_OTG_HCINT_FRMOR_Pos (9U) 14514 #define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */ 14515 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */ 14516 #define USB_OTG_HCINT_DTERR_Pos (10U) 14517 #define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */ 14518 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */ 14519 14520 /******************** Bit definition for USB_OTG_DIEPINT register ********************/ 14521 #define USB_OTG_DIEPINT_XFRC_Pos (0U) 14522 #define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */ 14523 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */ 14524 #define USB_OTG_DIEPINT_EPDISD_Pos (1U) 14525 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */ 14526 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ 14527 #define USB_OTG_DIEPINT_AHBERR_Pos (2U) 14528 #define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */ 14529 #define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */ 14530 #define USB_OTG_DIEPINT_TOC_Pos (3U) 14531 #define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */ 14532 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */ 14533 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) 14534 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ 14535 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ 14536 #define USB_OTG_DIEPINT_INEPNM_Pos (5U) 14537 #define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */ 14538 #define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ 14539 #define USB_OTG_DIEPINT_INEPNE_Pos (6U) 14540 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ 14541 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ 14542 #define USB_OTG_DIEPINT_TXFE_Pos (7U) 14543 #define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */ 14544 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */ 14545 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U) 14546 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */ 14547 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */ 14548 #define USB_OTG_DIEPINT_BNA_Pos (9U) 14549 #define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */ 14550 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */ 14551 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U) 14552 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */ 14553 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */ 14554 #define USB_OTG_DIEPINT_BERR_Pos (12U) 14555 #define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */ 14556 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */ 14557 #define USB_OTG_DIEPINT_NAK_Pos (13U) 14558 #define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */ 14559 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */ 14560 14561 /******************** Bit definition for USB_OTG_HCINTMSK register ********************/ 14562 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U) 14563 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */ 14564 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */ 14565 #define USB_OTG_HCINTMSK_CHHM_Pos (1U) 14566 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ 14567 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ 14568 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U) 14569 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ 14570 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ 14571 #define USB_OTG_HCINTMSK_STALLM_Pos (3U) 14572 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ 14573 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ 14574 #define USB_OTG_HCINTMSK_NAKM_Pos (4U) 14575 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */ 14576 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */ 14577 #define USB_OTG_HCINTMSK_ACKM_Pos (5U) 14578 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */ 14579 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */ 14580 #define USB_OTG_HCINTMSK_NYET_Pos (6U) 14581 #define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */ 14582 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */ 14583 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U) 14584 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */ 14585 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */ 14586 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U) 14587 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */ 14588 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */ 14589 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U) 14590 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */ 14591 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */ 14592 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U) 14593 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */ 14594 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */ 14595 14596 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/ 14597 14598 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U) 14599 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ 14600 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ 14601 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) 14602 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ 14603 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ 14604 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) 14605 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ 14606 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ 14607 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ 14608 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) 14609 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ 14610 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */ 14611 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) 14612 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ 14613 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ 14614 #define USB_OTG_HCTSIZ_DOPING_Pos (31U) 14615 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ 14616 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ 14617 #define USB_OTG_HCTSIZ_DPID_Pos (29U) 14618 #define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ 14619 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ 14620 #define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ 14621 #define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ 14622 14623 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ 14624 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) 14625 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ 14626 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */ 14627 14628 /******************** Bit definition for USB_OTG_HCDMA register ********************/ 14629 #define USB_OTG_HCDMA_DMAADDR_Pos (0U) 14630 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ 14631 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */ 14632 14633 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/ 14634 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U) 14635 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */ 14636 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */ 14637 14638 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/ 14639 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U) 14640 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */ 14641 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */ 14642 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U) 14643 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */ 14644 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */ 14645 14646 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/ 14647 14648 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U) 14649 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ 14650 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */ 14651 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) 14652 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ 14653 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ 14654 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) 14655 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ 14656 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ 14657 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) 14658 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ 14659 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ 14660 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) 14661 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ 14662 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ 14663 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) 14664 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ 14665 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ 14666 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */ 14667 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */ 14668 #define USB_OTG_DOEPCTL_SNPM_Pos (20U) 14669 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */ 14670 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */ 14671 #define USB_OTG_DOEPCTL_STALL_Pos (21U) 14672 #define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */ 14673 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */ 14674 #define USB_OTG_DOEPCTL_CNAK_Pos (26U) 14675 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */ 14676 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */ 14677 #define USB_OTG_DOEPCTL_SNAK_Pos (27U) 14678 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ 14679 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ 14680 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) 14681 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ 14682 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ 14683 #define USB_OTG_DOEPCTL_EPENA_Pos (31U) 14684 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */ 14685 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */ 14686 14687 /******************** Bit definition for USB_OTG_DOEPINT register ********************/ 14688 #define USB_OTG_DOEPINT_XFRC_Pos (0U) 14689 #define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */ 14690 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */ 14691 #define USB_OTG_DOEPINT_EPDISD_Pos (1U) 14692 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ 14693 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ 14694 #define USB_OTG_DOEPINT_AHBERR_Pos (2U) 14695 #define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ 14696 #define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an OUT transaction */ 14697 #define USB_OTG_DOEPINT_STUP_Pos (3U) 14698 #define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ 14699 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ 14700 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) 14701 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ 14702 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ 14703 #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U) 14704 #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */ 14705 #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */ 14706 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) 14707 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ 14708 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ 14709 #define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) 14710 #define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ 14711 #define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ 14712 #define USB_OTG_DOEPINT_NAK_Pos (13U) 14713 #define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ 14714 #define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK Packet is transmitted by the device */ 14715 #define USB_OTG_DOEPINT_NYET_Pos (14U) 14716 #define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ 14717 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ 14718 #define USB_OTG_DOEPINT_STPKTRX_Pos (15U) 14719 #define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ 14720 #define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup Packet Received */ 14721 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ 14722 14723 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) 14724 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ 14725 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ 14726 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U) 14727 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ 14728 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ 14729 14730 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) 14731 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ 14732 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ 14733 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ 14734 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ 14735 14736 /******************** Bit definition for PCGCCTL register ********************/ 14737 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) 14738 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ 14739 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ 14740 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U) 14741 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ 14742 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */ 14743 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U) 14744 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */ 14745 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */ 14746 14747 /* Legacy define */ 14748 /******************** Bit definition for OTG register ********************/ 14749 #define USB_OTG_CHNUM_Pos (0U) 14750 #define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ 14751 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ 14752 #define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ 14753 #define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ 14754 #define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ 14755 #define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ 14756 #define USB_OTG_BCNT_Pos (4U) 14757 #define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ 14758 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ 14759 14760 #define USB_OTG_DPID_Pos (15U) 14761 #define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */ 14762 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ 14763 #define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */ 14764 #define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */ 14765 14766 #define USB_OTG_PKTSTS_Pos (17U) 14767 #define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ 14768 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ 14769 #define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ 14770 #define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ 14771 #define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ 14772 #define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ 14773 14774 #define USB_OTG_EPNUM_Pos (0U) 14775 #define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ 14776 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ 14777 #define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ 14778 #define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ 14779 #define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ 14780 #define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ 14781 14782 #define USB_OTG_FRMNUM_Pos (21U) 14783 #define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ 14784 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ 14785 #define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ 14786 #define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ 14787 #define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ 14788 #define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ 14789 /** 14790 * @} 14791 */ 14792 14793 /** 14794 * @} 14795 */ 14796 14797 /** @addtogroup Exported_macros 14798 * @{ 14799 */ 14800 14801 /******************************* ADC Instances ********************************/ 14802 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \ 14803 ((INSTANCE) == ADC2) || \ 14804 ((INSTANCE) == ADC3)) 14805 14806 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) 14807 14808 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON) 14809 14810 /******************************* CAN Instances ********************************/ 14811 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \ 14812 ((INSTANCE) == CAN2)) 14813 14814 /******************************* CRC Instances ********************************/ 14815 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) 14816 14817 /******************************* DAC Instances ********************************/ 14818 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) 14819 14820 /******************************* DCMI Instances *******************************/ 14821 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI) 14822 14823 /******************************** DMA Instances *******************************/ 14824 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \ 14825 ((INSTANCE) == DMA1_Stream1) || \ 14826 ((INSTANCE) == DMA1_Stream2) || \ 14827 ((INSTANCE) == DMA1_Stream3) || \ 14828 ((INSTANCE) == DMA1_Stream4) || \ 14829 ((INSTANCE) == DMA1_Stream5) || \ 14830 ((INSTANCE) == DMA1_Stream6) || \ 14831 ((INSTANCE) == DMA1_Stream7) || \ 14832 ((INSTANCE) == DMA2_Stream0) || \ 14833 ((INSTANCE) == DMA2_Stream1) || \ 14834 ((INSTANCE) == DMA2_Stream2) || \ 14835 ((INSTANCE) == DMA2_Stream3) || \ 14836 ((INSTANCE) == DMA2_Stream4) || \ 14837 ((INSTANCE) == DMA2_Stream5) || \ 14838 ((INSTANCE) == DMA2_Stream6) || \ 14839 ((INSTANCE) == DMA2_Stream7)) 14840 14841 /******************************* GPIO Instances *******************************/ 14842 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 14843 ((INSTANCE) == GPIOB) || \ 14844 ((INSTANCE) == GPIOC) || \ 14845 ((INSTANCE) == GPIOD) || \ 14846 ((INSTANCE) == GPIOE) || \ 14847 ((INSTANCE) == GPIOF) || \ 14848 ((INSTANCE) == GPIOG) || \ 14849 ((INSTANCE) == GPIOH) || \ 14850 ((INSTANCE) == GPIOI)) 14851 14852 /**************************** GPIO Alternate Function Instances ***************/ 14853 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) 14854 14855 /******************************** I2C Instances *******************************/ 14856 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ 14857 ((INSTANCE) == I2C2) || \ 14858 ((INSTANCE) == I2C3)) 14859 14860 /******************************* SMBUS Instances ******************************/ 14861 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE 14862 14863 /******************************** I2S Instances *******************************/ 14864 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \ 14865 ((INSTANCE) == SPI3)) 14866 14867 /******************************* RNG Instances ********************************/ 14868 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) 14869 14870 /****************************** RTC Instances *********************************/ 14871 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) 14872 14873 /******************************** SPI Instances *******************************/ 14874 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ 14875 ((INSTANCE) == SPI2) || \ 14876 ((INSTANCE) == SPI3)) 14877 14878 /****************** TIM Instances : All supported instances *******************/ 14879 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14880 ((INSTANCE) == TIM2) || \ 14881 ((INSTANCE) == TIM3) || \ 14882 ((INSTANCE) == TIM4) || \ 14883 ((INSTANCE) == TIM5) || \ 14884 ((INSTANCE) == TIM6) || \ 14885 ((INSTANCE) == TIM7) || \ 14886 ((INSTANCE) == TIM8) || \ 14887 ((INSTANCE) == TIM9) || \ 14888 ((INSTANCE) == TIM10) || \ 14889 ((INSTANCE) == TIM11) || \ 14890 ((INSTANCE) == TIM12) || \ 14891 ((INSTANCE) == TIM13) || \ 14892 ((INSTANCE) == TIM14)) 14893 14894 /************* TIM Instances : at least 1 capture/compare channel *************/ 14895 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14896 ((INSTANCE) == TIM2) || \ 14897 ((INSTANCE) == TIM3) || \ 14898 ((INSTANCE) == TIM4) || \ 14899 ((INSTANCE) == TIM5) || \ 14900 ((INSTANCE) == TIM8) || \ 14901 ((INSTANCE) == TIM9) || \ 14902 ((INSTANCE) == TIM10) || \ 14903 ((INSTANCE) == TIM11) || \ 14904 ((INSTANCE) == TIM12) || \ 14905 ((INSTANCE) == TIM13) || \ 14906 ((INSTANCE) == TIM14)) 14907 14908 /************ TIM Instances : at least 2 capture/compare channels *************/ 14909 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14910 ((INSTANCE) == TIM2) || \ 14911 ((INSTANCE) == TIM3) || \ 14912 ((INSTANCE) == TIM4) || \ 14913 ((INSTANCE) == TIM5) || \ 14914 ((INSTANCE) == TIM8) || \ 14915 ((INSTANCE) == TIM9) || \ 14916 ((INSTANCE) == TIM12)) 14917 14918 /************ TIM Instances : at least 3 capture/compare channels *************/ 14919 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14920 ((INSTANCE) == TIM2) || \ 14921 ((INSTANCE) == TIM3) || \ 14922 ((INSTANCE) == TIM4) || \ 14923 ((INSTANCE) == TIM5) || \ 14924 ((INSTANCE) == TIM8)) 14925 14926 /************ TIM Instances : at least 4 capture/compare channels *************/ 14927 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14928 ((INSTANCE) == TIM2) || \ 14929 ((INSTANCE) == TIM3) || \ 14930 ((INSTANCE) == TIM4) || \ 14931 ((INSTANCE) == TIM5) || \ 14932 ((INSTANCE) == TIM8)) 14933 14934 /******************** TIM Instances : Advanced-control timers *****************/ 14935 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14936 ((INSTANCE) == TIM8)) 14937 14938 /******************* TIM Instances : Timer input XOR function *****************/ 14939 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14940 ((INSTANCE) == TIM2) || \ 14941 ((INSTANCE) == TIM3) || \ 14942 ((INSTANCE) == TIM4) || \ 14943 ((INSTANCE) == TIM5) || \ 14944 ((INSTANCE) == TIM8)) 14945 14946 /****************** TIM Instances : DMA requests generation (UDE) *************/ 14947 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14948 ((INSTANCE) == TIM2) || \ 14949 ((INSTANCE) == TIM3) || \ 14950 ((INSTANCE) == TIM4) || \ 14951 ((INSTANCE) == TIM5) || \ 14952 ((INSTANCE) == TIM6) || \ 14953 ((INSTANCE) == TIM7) || \ 14954 ((INSTANCE) == TIM8)) 14955 14956 /************ TIM Instances : DMA requests generation (CCxDE) *****************/ 14957 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14958 ((INSTANCE) == TIM2) || \ 14959 ((INSTANCE) == TIM3) || \ 14960 ((INSTANCE) == TIM4) || \ 14961 ((INSTANCE) == TIM5) || \ 14962 ((INSTANCE) == TIM8)) 14963 14964 /************ TIM Instances : DMA requests generation (COMDE) *****************/ 14965 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14966 ((INSTANCE) == TIM2) || \ 14967 ((INSTANCE) == TIM3) || \ 14968 ((INSTANCE) == TIM4) || \ 14969 ((INSTANCE) == TIM5) || \ 14970 ((INSTANCE) == TIM8)) 14971 14972 /******************** TIM Instances : DMA burst feature ***********************/ 14973 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14974 ((INSTANCE) == TIM2) || \ 14975 ((INSTANCE) == TIM3) || \ 14976 ((INSTANCE) == TIM4) || \ 14977 ((INSTANCE) == TIM5) || \ 14978 ((INSTANCE) == TIM8)) 14979 14980 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/ 14981 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14982 ((INSTANCE) == TIM2) || \ 14983 ((INSTANCE) == TIM3) || \ 14984 ((INSTANCE) == TIM4) || \ 14985 ((INSTANCE) == TIM5) || \ 14986 ((INSTANCE) == TIM6) || \ 14987 ((INSTANCE) == TIM7) || \ 14988 ((INSTANCE) == TIM8) || \ 14989 ((INSTANCE) == TIM9) || \ 14990 ((INSTANCE) == TIM12)) 14991 14992 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ 14993 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14994 ((INSTANCE) == TIM2) || \ 14995 ((INSTANCE) == TIM3) || \ 14996 ((INSTANCE) == TIM4) || \ 14997 ((INSTANCE) == TIM5) || \ 14998 ((INSTANCE) == TIM8) || \ 14999 ((INSTANCE) == TIM9) || \ 15000 ((INSTANCE) == TIM12)) 15001 15002 /********************** TIM Instances : 32 bit Counter ************************/ 15003 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \ 15004 ((INSTANCE) == TIM5)) 15005 15006 /***************** TIM Instances : external trigger input available ***********/ 15007 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 15008 ((INSTANCE) == TIM2) || \ 15009 ((INSTANCE) == TIM3) || \ 15010 ((INSTANCE) == TIM4) || \ 15011 ((INSTANCE) == TIM5) || \ 15012 ((INSTANCE) == TIM8)) 15013 15014 /****************** TIM Instances : remapping capability **********************/ 15015 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 15016 ((INSTANCE) == TIM5) || \ 15017 ((INSTANCE) == TIM11)) 15018 15019 /******************* TIM Instances : output(s) available **********************/ 15020 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ 15021 ((((INSTANCE) == TIM1) && \ 15022 (((CHANNEL) == TIM_CHANNEL_1) || \ 15023 ((CHANNEL) == TIM_CHANNEL_2) || \ 15024 ((CHANNEL) == TIM_CHANNEL_3) || \ 15025 ((CHANNEL) == TIM_CHANNEL_4))) \ 15026 || \ 15027 (((INSTANCE) == TIM2) && \ 15028 (((CHANNEL) == TIM_CHANNEL_1) || \ 15029 ((CHANNEL) == TIM_CHANNEL_2) || \ 15030 ((CHANNEL) == TIM_CHANNEL_3) || \ 15031 ((CHANNEL) == TIM_CHANNEL_4))) \ 15032 || \ 15033 (((INSTANCE) == TIM3) && \ 15034 (((CHANNEL) == TIM_CHANNEL_1) || \ 15035 ((CHANNEL) == TIM_CHANNEL_2) || \ 15036 ((CHANNEL) == TIM_CHANNEL_3) || \ 15037 ((CHANNEL) == TIM_CHANNEL_4))) \ 15038 || \ 15039 (((INSTANCE) == TIM4) && \ 15040 (((CHANNEL) == TIM_CHANNEL_1) || \ 15041 ((CHANNEL) == TIM_CHANNEL_2) || \ 15042 ((CHANNEL) == TIM_CHANNEL_3) || \ 15043 ((CHANNEL) == TIM_CHANNEL_4))) \ 15044 || \ 15045 (((INSTANCE) == TIM5) && \ 15046 (((CHANNEL) == TIM_CHANNEL_1) || \ 15047 ((CHANNEL) == TIM_CHANNEL_2) || \ 15048 ((CHANNEL) == TIM_CHANNEL_3) || \ 15049 ((CHANNEL) == TIM_CHANNEL_4))) \ 15050 || \ 15051 (((INSTANCE) == TIM8) && \ 15052 (((CHANNEL) == TIM_CHANNEL_1) || \ 15053 ((CHANNEL) == TIM_CHANNEL_2) || \ 15054 ((CHANNEL) == TIM_CHANNEL_3) || \ 15055 ((CHANNEL) == TIM_CHANNEL_4))) \ 15056 || \ 15057 (((INSTANCE) == TIM9) && \ 15058 (((CHANNEL) == TIM_CHANNEL_1) || \ 15059 ((CHANNEL) == TIM_CHANNEL_2))) \ 15060 || \ 15061 (((INSTANCE) == TIM10) && \ 15062 (((CHANNEL) == TIM_CHANNEL_1))) \ 15063 || \ 15064 (((INSTANCE) == TIM11) && \ 15065 (((CHANNEL) == TIM_CHANNEL_1))) \ 15066 || \ 15067 (((INSTANCE) == TIM12) && \ 15068 (((CHANNEL) == TIM_CHANNEL_1) || \ 15069 ((CHANNEL) == TIM_CHANNEL_2))) \ 15070 || \ 15071 (((INSTANCE) == TIM13) && \ 15072 (((CHANNEL) == TIM_CHANNEL_1))) \ 15073 || \ 15074 (((INSTANCE) == TIM14) && \ 15075 (((CHANNEL) == TIM_CHANNEL_1)))) 15076 15077 /************ TIM Instances : complementary output(s) available ***************/ 15078 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ 15079 ((((INSTANCE) == TIM1) && \ 15080 (((CHANNEL) == TIM_CHANNEL_1) || \ 15081 ((CHANNEL) == TIM_CHANNEL_2) || \ 15082 ((CHANNEL) == TIM_CHANNEL_3))) \ 15083 || \ 15084 (((INSTANCE) == TIM8) && \ 15085 (((CHANNEL) == TIM_CHANNEL_1) || \ 15086 ((CHANNEL) == TIM_CHANNEL_2) || \ 15087 ((CHANNEL) == TIM_CHANNEL_3)))) 15088 15089 /****************** TIM Instances : supporting counting mode selection ********/ 15090 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 15091 ((INSTANCE) == TIM2) || \ 15092 ((INSTANCE) == TIM3) || \ 15093 ((INSTANCE) == TIM4) || \ 15094 ((INSTANCE) == TIM5) || \ 15095 ((INSTANCE) == TIM8)) 15096 15097 /****************** TIM Instances : supporting clock division *****************/ 15098 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 15099 ((INSTANCE) == TIM2) || \ 15100 ((INSTANCE) == TIM3) || \ 15101 ((INSTANCE) == TIM4) || \ 15102 ((INSTANCE) == TIM5) || \ 15103 ((INSTANCE) == TIM8) || \ 15104 ((INSTANCE) == TIM9) || \ 15105 ((INSTANCE) == TIM10)|| \ 15106 ((INSTANCE) == TIM11)|| \ 15107 ((INSTANCE) == TIM12)|| \ 15108 ((INSTANCE) == TIM13)|| \ 15109 ((INSTANCE) == TIM14)) 15110 15111 /****************** TIM Instances : supporting commutation event generation ***/ 15112 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 15113 ((INSTANCE) == TIM8)) 15114 15115 /****************** TIM Instances : supporting OCxREF clear *******************/ 15116 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 15117 ((INSTANCE) == TIM2) || \ 15118 ((INSTANCE) == TIM3) || \ 15119 ((INSTANCE) == TIM4) || \ 15120 ((INSTANCE) == TIM5) || \ 15121 ((INSTANCE) == TIM8)) 15122 15123 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ 15124 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 15125 ((INSTANCE) == TIM2) || \ 15126 ((INSTANCE) == TIM3) || \ 15127 ((INSTANCE) == TIM4) || \ 15128 ((INSTANCE) == TIM5) || \ 15129 ((INSTANCE) == TIM8) || \ 15130 ((INSTANCE) == TIM9) || \ 15131 ((INSTANCE) == TIM12)) 15132 15133 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ 15134 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 15135 ((INSTANCE) == TIM2) || \ 15136 ((INSTANCE) == TIM3) || \ 15137 ((INSTANCE) == TIM4) || \ 15138 ((INSTANCE) == TIM5) || \ 15139 ((INSTANCE) == TIM8)) 15140 15141 /****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/ 15142 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 15143 ((INSTANCE) == TIM2) || \ 15144 ((INSTANCE) == TIM3) || \ 15145 ((INSTANCE) == TIM4) || \ 15146 ((INSTANCE) == TIM5) || \ 15147 ((INSTANCE) == TIM8) || \ 15148 ((INSTANCE) == TIM9) || \ 15149 ((INSTANCE) == TIM12)) 15150 15151 /********** TIM Instances : supporting internal trigger inputs(ITRX) *********/ 15152 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 15153 ((INSTANCE) == TIM2) || \ 15154 ((INSTANCE) == TIM3) || \ 15155 ((INSTANCE) == TIM4) || \ 15156 ((INSTANCE) == TIM5) || \ 15157 ((INSTANCE) == TIM8) || \ 15158 ((INSTANCE) == TIM9) || \ 15159 ((INSTANCE) == TIM12)) 15160 15161 15162 /****************** TIM Instances : supporting repetition counter *************/ 15163 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 15164 ((INSTANCE) == TIM8)) 15165 15166 /****************** TIM Instances : supporting encoder interface **************/ 15167 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 15168 ((INSTANCE) == TIM2) || \ 15169 ((INSTANCE) == TIM3) || \ 15170 ((INSTANCE) == TIM4) || \ 15171 ((INSTANCE) == TIM5) || \ 15172 ((INSTANCE) == TIM8)) 15173 15174 /****************** TIM Instances : supporting the break function *************/ 15175 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 15176 ((INSTANCE) == TIM8)) 15177 15178 /****************** TIM Instances : supporting Hall sensor interface **********/ 15179 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 15180 ((INSTANCE) == TIM8)) 15181 15182 /******************** USART Instances : Synchronous mode **********************/ 15183 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 15184 ((INSTANCE) == USART2) || \ 15185 ((INSTANCE) == USART3) || \ 15186 ((INSTANCE) == USART6)) 15187 15188 /******************** UART Instances : Asynchronous mode **********************/ 15189 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 15190 ((INSTANCE) == USART2) || \ 15191 ((INSTANCE) == USART3) || \ 15192 ((INSTANCE) == UART4) || \ 15193 ((INSTANCE) == UART5) || \ 15194 ((INSTANCE) == USART6)) 15195 15196 /****************** UART Instances : Hardware Flow control ********************/ 15197 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 15198 ((INSTANCE) == USART2) || \ 15199 ((INSTANCE) == USART3) || \ 15200 ((INSTANCE) == USART6)) 15201 15202 /********************* UART Instances : Smart card mode ***********************/ 15203 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 15204 ((INSTANCE) == USART2) || \ 15205 ((INSTANCE) == USART3) || \ 15206 ((INSTANCE) == USART6)) 15207 15208 /*********************** UART Instances : IRDA mode ***************************/ 15209 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 15210 ((INSTANCE) == USART2) || \ 15211 ((INSTANCE) == USART3) || \ 15212 ((INSTANCE) == UART4) || \ 15213 ((INSTANCE) == UART5) || \ 15214 ((INSTANCE) == USART6)) 15215 15216 /* Legacy defines */ 15217 #define IS_UART_HALFDUPLEX_INSTANCE IS_UART_INSTANCE 15218 #define IS_UART_LIN_INSTANCE IS_UART_INSTANCE 15219 15220 /*********************** PCD Instances ****************************************/ 15221 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \ 15222 ((INSTANCE) == USB_OTG_HS)) 15223 15224 /*********************** HCD Instances ****************************************/ 15225 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \ 15226 ((INSTANCE) == USB_OTG_HS)) 15227 15228 /****************************** IWDG Instances ********************************/ 15229 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) 15230 15231 /****************************** WWDG Instances ********************************/ 15232 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) 15233 15234 /****************************** SDIO Instances ********************************/ 15235 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO) 15236 15237 /****************************** USB Exported Constants ************************/ 15238 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U 15239 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */ 15240 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */ 15241 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */ 15242 15243 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U 15244 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */ 15245 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */ 15246 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */ 15247 15248 /** 15249 * @} 15250 */ 15251 15252 /** 15253 * @} 15254 */ 15255 15256 /** 15257 * @} 15258 */ 15259 15260 #ifdef __cplusplus 15261 } 15262 #endif /* __cplusplus */ 15263 15264 #endif /* __STM32F217xx_H */ 15265 15266