1 /**
2 ******************************************************************************
3 * @file stm32f1xx_ll_spi.h
4 * @author MCD Application Team
5 * @brief Header file of SPI LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32F1xx_LL_SPI_H
21 #define STM32F1xx_LL_SPI_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f1xx.h"
29
30 /** @addtogroup STM32F1xx_LL_Driver
31 * @{
32 */
33
34 #if defined (SPI1) || defined (SPI2) || defined (SPI3)
35
36 /** @defgroup SPI_LL SPI
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private macros ------------------------------------------------------------*/
43
44 /* Exported types ------------------------------------------------------------*/
45 #if defined(USE_FULL_LL_DRIVER)
46 /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
47 * @{
48 */
49
50 /**
51 * @brief SPI Init structures definition
52 */
53 typedef struct
54 {
55 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
56 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
57
58 This feature can be modified afterwards using unitary
59 function @ref LL_SPI_SetTransferDirection().*/
60
61 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
62 This parameter can be a value of @ref SPI_LL_EC_MODE.
63
64 This feature can be modified afterwards using unitary
65 function @ref LL_SPI_SetMode().*/
66
67 uint32_t DataWidth; /*!< Specifies the SPI data width.
68 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
69
70 This feature can be modified afterwards using unitary
71 function @ref LL_SPI_SetDataWidth().*/
72
73 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
74 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
75
76 This feature can be modified afterwards using unitary
77 function @ref LL_SPI_SetClockPolarity().*/
78
79 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
80 This parameter can be a value of @ref SPI_LL_EC_PHASE.
81
82 This feature can be modified afterwards using unitary
83 function @ref LL_SPI_SetClockPhase().*/
84
85 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin)
86 or by software using the SSI bit.
87 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
88
89 This feature can be modified afterwards using unitary
90 function @ref LL_SPI_SetNSSMode().*/
91
92 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used
93 to configure the transmit and receive SCK clock.
94 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
95 @note The communication clock is derived from the master clock.
96 The slave clock does not need to be set.
97
98 This feature can be modified afterwards using unitary
99 function @ref LL_SPI_SetBaudRatePrescaler().*/
100
101 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
102 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
103
104 This feature can be modified afterwards using unitary
105 function @ref LL_SPI_SetTransferBitOrder().*/
106
107 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
108 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
109
110 This feature can be modified afterwards using unitary
111 functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
112
113 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
114 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
115
116 This feature can be modified afterwards using unitary
117 function @ref LL_SPI_SetCRCPolynomial().*/
118
119 } LL_SPI_InitTypeDef;
120
121 /**
122 * @}
123 */
124 #endif /* USE_FULL_LL_DRIVER */
125
126 /* Exported constants --------------------------------------------------------*/
127 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
128 * @{
129 */
130
131 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
132 * @brief Flags defines which can be used with LL_SPI_ReadReg function
133 * @{
134 */
135 #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
136 #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
137 #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
138 #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
139 #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
140 #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
141 #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
142 /**
143 * @}
144 */
145
146 /** @defgroup SPI_LL_EC_IT IT Defines
147 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
148 * @{
149 */
150 #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
151 #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
152 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
153 /**
154 * @}
155 */
156
157 /** @defgroup SPI_LL_EC_MODE Operation Mode
158 * @{
159 */
160 #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
161 #define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
162 /**
163 * @}
164 */
165
166
167 /** @defgroup SPI_LL_EC_PHASE Clock Phase
168 * @{
169 */
170 #define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
171 #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
172 /**
173 * @}
174 */
175
176 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
177 * @{
178 */
179 #define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
180 #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
181 /**
182 * @}
183 */
184
185 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
186 * @{
187 */
188 #define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
189 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
190 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
191 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
192 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
193 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
194 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
195 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
196 /**
197 * @}
198 */
199
200 /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
201 * @{
202 */
203 #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
204 #define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
205 /**
206 * @}
207 */
208
209 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
210 * @{
211 */
212 #define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
213 #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
214 #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
215 #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
216 /**
217 * @}
218 */
219
220 /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
221 * @{
222 */
223 #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
224 #define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
225 #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
226 /**
227 * @}
228 */
229
230 /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
231 * @{
232 */
233 #define LL_SPI_DATAWIDTH_8BIT 0x00000000U /*!< Data length for SPI transfer: 8 bits */
234 #define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /*!< Data length for SPI transfer: 16 bits */
235 /**
236 * @}
237 */
238 #if defined(USE_FULL_LL_DRIVER)
239
240 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
241 * @{
242 */
243 #define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
244 #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
245 /**
246 * @}
247 */
248 #endif /* USE_FULL_LL_DRIVER */
249
250 /**
251 * @}
252 */
253
254 /* Exported macro ------------------------------------------------------------*/
255 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
256 * @{
257 */
258
259 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
260 * @{
261 */
262
263 /**
264 * @brief Write a value in SPI register
265 * @param __INSTANCE__ SPI Instance
266 * @param __REG__ Register to be written
267 * @param __VALUE__ Value to be written in the register
268 * @retval None
269 */
270 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
271
272 /**
273 * @brief Read a value in SPI register
274 * @param __INSTANCE__ SPI Instance
275 * @param __REG__ Register to be read
276 * @retval Register value
277 */
278 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
279 /**
280 * @}
281 */
282
283 /**
284 * @}
285 */
286
287 /* Exported functions --------------------------------------------------------*/
288 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
289 * @{
290 */
291
292 /** @defgroup SPI_LL_EF_Configuration Configuration
293 * @{
294 */
295
296 /**
297 * @brief Enable SPI peripheral
298 * @rmtoll CR1 SPE LL_SPI_Enable
299 * @param SPIx SPI Instance
300 * @retval None
301 */
LL_SPI_Enable(SPI_TypeDef * SPIx)302 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
303 {
304 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
305 }
306
307 /**
308 * @brief Disable SPI peripheral
309 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
310 * @rmtoll CR1 SPE LL_SPI_Disable
311 * @param SPIx SPI Instance
312 * @retval None
313 */
LL_SPI_Disable(SPI_TypeDef * SPIx)314 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
315 {
316 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
317 }
318
319 /**
320 * @brief Check if SPI peripheral is enabled
321 * @rmtoll CR1 SPE LL_SPI_IsEnabled
322 * @param SPIx SPI Instance
323 * @retval State of bit (1 or 0).
324 */
LL_SPI_IsEnabled(const SPI_TypeDef * SPIx)325 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx)
326 {
327 return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
328 }
329
330 /**
331 * @brief Set SPI operation mode to Master or Slave
332 * @note This bit should not be changed when communication is ongoing.
333 * @rmtoll CR1 MSTR LL_SPI_SetMode\n
334 * CR1 SSI LL_SPI_SetMode
335 * @param SPIx SPI Instance
336 * @param Mode This parameter can be one of the following values:
337 * @arg @ref LL_SPI_MODE_MASTER
338 * @arg @ref LL_SPI_MODE_SLAVE
339 * @retval None
340 */
LL_SPI_SetMode(SPI_TypeDef * SPIx,uint32_t Mode)341 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
342 {
343 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
344 }
345
346 /**
347 * @brief Get SPI operation mode (Master or Slave)
348 * @rmtoll CR1 MSTR LL_SPI_GetMode\n
349 * CR1 SSI LL_SPI_GetMode
350 * @param SPIx SPI Instance
351 * @retval Returned value can be one of the following values:
352 * @arg @ref LL_SPI_MODE_MASTER
353 * @arg @ref LL_SPI_MODE_SLAVE
354 */
LL_SPI_GetMode(const SPI_TypeDef * SPIx)355 __STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx)
356 {
357 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
358 }
359
360
361 /**
362 * @brief Set clock phase
363 * @note This bit should not be changed when communication is ongoing.
364 * This bit is not used in SPI TI mode.
365 * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
366 * @param SPIx SPI Instance
367 * @param ClockPhase This parameter can be one of the following values:
368 * @arg @ref LL_SPI_PHASE_1EDGE
369 * @arg @ref LL_SPI_PHASE_2EDGE
370 * @retval None
371 */
LL_SPI_SetClockPhase(SPI_TypeDef * SPIx,uint32_t ClockPhase)372 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
373 {
374 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
375 }
376
377 /**
378 * @brief Get clock phase
379 * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
380 * @param SPIx SPI Instance
381 * @retval Returned value can be one of the following values:
382 * @arg @ref LL_SPI_PHASE_1EDGE
383 * @arg @ref LL_SPI_PHASE_2EDGE
384 */
LL_SPI_GetClockPhase(const SPI_TypeDef * SPIx)385 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx)
386 {
387 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
388 }
389
390 /**
391 * @brief Set clock polarity
392 * @note This bit should not be changed when communication is ongoing.
393 * This bit is not used in SPI TI mode.
394 * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
395 * @param SPIx SPI Instance
396 * @param ClockPolarity This parameter can be one of the following values:
397 * @arg @ref LL_SPI_POLARITY_LOW
398 * @arg @ref LL_SPI_POLARITY_HIGH
399 * @retval None
400 */
LL_SPI_SetClockPolarity(SPI_TypeDef * SPIx,uint32_t ClockPolarity)401 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
402 {
403 MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
404 }
405
406 /**
407 * @brief Get clock polarity
408 * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
409 * @param SPIx SPI Instance
410 * @retval Returned value can be one of the following values:
411 * @arg @ref LL_SPI_POLARITY_LOW
412 * @arg @ref LL_SPI_POLARITY_HIGH
413 */
LL_SPI_GetClockPolarity(const SPI_TypeDef * SPIx)414 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx)
415 {
416 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
417 }
418
419 /**
420 * @brief Set baud rate prescaler
421 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
422 * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
423 * @param SPIx SPI Instance
424 * @param BaudRate This parameter can be one of the following values:
425 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
426 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
427 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
428 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
429 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
430 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
431 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
432 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
433 * @retval None
434 */
LL_SPI_SetBaudRatePrescaler(SPI_TypeDef * SPIx,uint32_t BaudRate)435 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
436 {
437 MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
438 }
439
440 /**
441 * @brief Get baud rate prescaler
442 * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
443 * @param SPIx SPI Instance
444 * @retval Returned value can be one of the following values:
445 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
446 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
447 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
448 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
449 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
450 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
451 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
452 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
453 */
LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef * SPIx)454 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx)
455 {
456 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
457 }
458
459 /**
460 * @brief Set transfer bit order
461 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
462 * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
463 * @param SPIx SPI Instance
464 * @param BitOrder This parameter can be one of the following values:
465 * @arg @ref LL_SPI_LSB_FIRST
466 * @arg @ref LL_SPI_MSB_FIRST
467 * @retval None
468 */
LL_SPI_SetTransferBitOrder(SPI_TypeDef * SPIx,uint32_t BitOrder)469 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
470 {
471 MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
472 }
473
474 /**
475 * @brief Get transfer bit order
476 * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
477 * @param SPIx SPI Instance
478 * @retval Returned value can be one of the following values:
479 * @arg @ref LL_SPI_LSB_FIRST
480 * @arg @ref LL_SPI_MSB_FIRST
481 */
LL_SPI_GetTransferBitOrder(const SPI_TypeDef * SPIx)482 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx)
483 {
484 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
485 }
486
487 /**
488 * @brief Set transfer direction mode
489 * @note For Half-Duplex mode, Rx Direction is set by default.
490 * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
491 * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
492 * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
493 * CR1 BIDIOE LL_SPI_SetTransferDirection
494 * @param SPIx SPI Instance
495 * @param TransferDirection This parameter can be one of the following values:
496 * @arg @ref LL_SPI_FULL_DUPLEX
497 * @arg @ref LL_SPI_SIMPLEX_RX
498 * @arg @ref LL_SPI_HALF_DUPLEX_RX
499 * @arg @ref LL_SPI_HALF_DUPLEX_TX
500 * @retval None
501 */
LL_SPI_SetTransferDirection(SPI_TypeDef * SPIx,uint32_t TransferDirection)502 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
503 {
504 MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
505 }
506
507 /**
508 * @brief Get transfer direction mode
509 * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
510 * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
511 * CR1 BIDIOE LL_SPI_GetTransferDirection
512 * @param SPIx SPI Instance
513 * @retval Returned value can be one of the following values:
514 * @arg @ref LL_SPI_FULL_DUPLEX
515 * @arg @ref LL_SPI_SIMPLEX_RX
516 * @arg @ref LL_SPI_HALF_DUPLEX_RX
517 * @arg @ref LL_SPI_HALF_DUPLEX_TX
518 */
LL_SPI_GetTransferDirection(const SPI_TypeDef * SPIx)519 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx)
520 {
521 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
522 }
523
524 /**
525 * @brief Set frame data width
526 * @rmtoll CR1 DFF LL_SPI_SetDataWidth
527 * @param SPIx SPI Instance
528 * @param DataWidth This parameter can be one of the following values:
529 * @arg @ref LL_SPI_DATAWIDTH_8BIT
530 * @arg @ref LL_SPI_DATAWIDTH_16BIT
531 * @retval None
532 */
LL_SPI_SetDataWidth(SPI_TypeDef * SPIx,uint32_t DataWidth)533 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
534 {
535 MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
536 }
537
538 /**
539 * @brief Get frame data width
540 * @rmtoll CR1 DFF LL_SPI_GetDataWidth
541 * @param SPIx SPI Instance
542 * @retval Returned value can be one of the following values:
543 * @arg @ref LL_SPI_DATAWIDTH_8BIT
544 * @arg @ref LL_SPI_DATAWIDTH_16BIT
545 */
LL_SPI_GetDataWidth(const SPI_TypeDef * SPIx)546 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx)
547 {
548 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
549 }
550
551 /**
552 * @}
553 */
554
555 /** @defgroup SPI_LL_EF_CRC_Management CRC Management
556 * @{
557 */
558
559 /**
560 * @brief Enable CRC
561 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
562 * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
563 * @param SPIx SPI Instance
564 * @retval None
565 */
LL_SPI_EnableCRC(SPI_TypeDef * SPIx)566 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
567 {
568 SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
569 }
570
571 /**
572 * @brief Disable CRC
573 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
574 * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
575 * @param SPIx SPI Instance
576 * @retval None
577 */
LL_SPI_DisableCRC(SPI_TypeDef * SPIx)578 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
579 {
580 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
581 }
582
583 /**
584 * @brief Check if CRC is enabled
585 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
586 * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
587 * @param SPIx SPI Instance
588 * @retval State of bit (1 or 0).
589 */
LL_SPI_IsEnabledCRC(const SPI_TypeDef * SPIx)590 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx)
591 {
592 return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
593 }
594
595 /**
596 * @brief Set CRCNext to transfer CRC on the line
597 * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
598 * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
599 * @param SPIx SPI Instance
600 * @retval None
601 */
LL_SPI_SetCRCNext(SPI_TypeDef * SPIx)602 __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
603 {
604 SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
605 }
606
607 /**
608 * @brief Set polynomial for CRC calculation
609 * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
610 * @param SPIx SPI Instance
611 * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
612 * @retval None
613 */
LL_SPI_SetCRCPolynomial(SPI_TypeDef * SPIx,uint32_t CRCPoly)614 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
615 {
616 WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
617 }
618
619 /**
620 * @brief Get polynomial for CRC calculation
621 * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
622 * @param SPIx SPI Instance
623 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
624 */
LL_SPI_GetCRCPolynomial(const SPI_TypeDef * SPIx)625 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx)
626 {
627 return (uint32_t)(READ_REG(SPIx->CRCPR));
628 }
629
630 /**
631 * @brief Get Rx CRC
632 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
633 * @param SPIx SPI Instance
634 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
635 */
LL_SPI_GetRxCRC(const SPI_TypeDef * SPIx)636 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx)
637 {
638 return (uint32_t)(READ_REG(SPIx->RXCRCR));
639 }
640
641 /**
642 * @brief Get Tx CRC
643 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
644 * @param SPIx SPI Instance
645 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
646 */
LL_SPI_GetTxCRC(const SPI_TypeDef * SPIx)647 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx)
648 {
649 return (uint32_t)(READ_REG(SPIx->TXCRCR));
650 }
651
652 /**
653 * @}
654 */
655
656 /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
657 * @{
658 */
659
660 /**
661 * @brief Set NSS mode
662 * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
663 * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
664 * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
665 * @param SPIx SPI Instance
666 * @param NSS This parameter can be one of the following values:
667 * @arg @ref LL_SPI_NSS_SOFT
668 * @arg @ref LL_SPI_NSS_HARD_INPUT
669 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
670 * @retval None
671 */
LL_SPI_SetNSSMode(SPI_TypeDef * SPIx,uint32_t NSS)672 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
673 {
674 MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
675 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
676 }
677
678 /**
679 * @brief Get NSS mode
680 * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
681 * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
682 * @param SPIx SPI Instance
683 * @retval Returned value can be one of the following values:
684 * @arg @ref LL_SPI_NSS_SOFT
685 * @arg @ref LL_SPI_NSS_HARD_INPUT
686 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
687 */
LL_SPI_GetNSSMode(const SPI_TypeDef * SPIx)688 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx)
689 {
690 uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
691 uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
692 return (Ssm | Ssoe);
693 }
694
695 /**
696 * @}
697 */
698
699 /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
700 * @{
701 */
702
703 /**
704 * @brief Check if Rx buffer is not empty
705 * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
706 * @param SPIx SPI Instance
707 * @retval State of bit (1 or 0).
708 */
LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef * SPIx)709 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx)
710 {
711 return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
712 }
713
714 /**
715 * @brief Check if Tx buffer is empty
716 * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
717 * @param SPIx SPI Instance
718 * @retval State of bit (1 or 0).
719 */
LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef * SPIx)720 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef *SPIx)
721 {
722 return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
723 }
724
725 /**
726 * @brief Get CRC error flag
727 * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
728 * @param SPIx SPI Instance
729 * @retval State of bit (1 or 0).
730 */
LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef * SPIx)731 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx)
732 {
733 return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
734 }
735
736 /**
737 * @brief Get mode fault error flag
738 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
739 * @param SPIx SPI Instance
740 * @retval State of bit (1 or 0).
741 */
LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef * SPIx)742 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx)
743 {
744 return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
745 }
746
747 /**
748 * @brief Get overrun error flag
749 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
750 * @param SPIx SPI Instance
751 * @retval State of bit (1 or 0).
752 */
LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef * SPIx)753 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
754 {
755 return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
756 }
757
758 /**
759 * @brief Get busy flag
760 * @note The BSY flag is cleared under any one of the following conditions:
761 * -When the SPI is correctly disabled
762 * -When a fault is detected in Master mode (MODF bit set to 1)
763 * -In Master mode, when it finishes a data transmission and no new data is ready to be
764 * sent
765 * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
766 * each data transfer.
767 * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
768 * @param SPIx SPI Instance
769 * @retval State of bit (1 or 0).
770 */
LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef * SPIx)771 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef *SPIx)
772 {
773 return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
774 }
775
776
777 /**
778 * @brief Clear CRC error flag
779 * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
780 * @param SPIx SPI Instance
781 * @retval None
782 */
LL_SPI_ClearFlag_CRCERR(SPI_TypeDef * SPIx)783 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
784 {
785 CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
786 }
787
788 /**
789 * @brief Clear mode fault error flag
790 * @note Clearing this flag is done by a read access to the SPIx_SR
791 * register followed by a write access to the SPIx_CR1 register
792 * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
793 * @param SPIx SPI Instance
794 * @retval None
795 */
LL_SPI_ClearFlag_MODF(SPI_TypeDef * SPIx)796 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
797 {
798 __IO uint32_t tmpreg_sr;
799 tmpreg_sr = SPIx->SR;
800 (void) tmpreg_sr;
801 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
802 }
803
804 /**
805 * @brief Clear overrun error flag
806 * @note Clearing this flag is done by a read access to the SPIx_DR
807 * register followed by a read access to the SPIx_SR register
808 * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
809 * @param SPIx SPI Instance
810 * @retval None
811 */
LL_SPI_ClearFlag_OVR(SPI_TypeDef * SPIx)812 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
813 {
814 __IO uint32_t tmpreg;
815 tmpreg = SPIx->DR;
816 (void) tmpreg;
817 tmpreg = SPIx->SR;
818 (void) tmpreg;
819 }
820
821 /**
822 * @brief Clear frame format error flag
823 * @note Clearing this flag is done by reading SPIx_SR register
824 * @rmtoll SR FRE LL_SPI_ClearFlag_FRE
825 * @param SPIx SPI Instance
826 * @retval None
827 */
LL_SPI_ClearFlag_FRE(SPI_TypeDef * SPIx)828 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
829 {
830 __IO uint32_t tmpreg;
831 tmpreg = SPIx->SR;
832 (void) tmpreg;
833 }
834
835 /**
836 * @}
837 */
838
839 /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
840 * @{
841 */
842
843 /**
844 * @brief Enable error interrupt
845 * @note This bit controls the generation of an interrupt when an error condition
846 * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
847 * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
848 * @param SPIx SPI Instance
849 * @retval None
850 */
LL_SPI_EnableIT_ERR(SPI_TypeDef * SPIx)851 __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
852 {
853 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
854 }
855
856 /**
857 * @brief Enable Rx buffer not empty interrupt
858 * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
859 * @param SPIx SPI Instance
860 * @retval None
861 */
LL_SPI_EnableIT_RXNE(SPI_TypeDef * SPIx)862 __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
863 {
864 SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
865 }
866
867 /**
868 * @brief Enable Tx buffer empty interrupt
869 * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
870 * @param SPIx SPI Instance
871 * @retval None
872 */
LL_SPI_EnableIT_TXE(SPI_TypeDef * SPIx)873 __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
874 {
875 SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
876 }
877
878 /**
879 * @brief Disable error interrupt
880 * @note This bit controls the generation of an interrupt when an error condition
881 * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
882 * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
883 * @param SPIx SPI Instance
884 * @retval None
885 */
LL_SPI_DisableIT_ERR(SPI_TypeDef * SPIx)886 __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
887 {
888 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
889 }
890
891 /**
892 * @brief Disable Rx buffer not empty interrupt
893 * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
894 * @param SPIx SPI Instance
895 * @retval None
896 */
LL_SPI_DisableIT_RXNE(SPI_TypeDef * SPIx)897 __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
898 {
899 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
900 }
901
902 /**
903 * @brief Disable Tx buffer empty interrupt
904 * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
905 * @param SPIx SPI Instance
906 * @retval None
907 */
LL_SPI_DisableIT_TXE(SPI_TypeDef * SPIx)908 __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
909 {
910 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
911 }
912
913 /**
914 * @brief Check if error interrupt is enabled
915 * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
916 * @param SPIx SPI Instance
917 * @retval State of bit (1 or 0).
918 */
LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef * SPIx)919 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef *SPIx)
920 {
921 return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
922 }
923
924 /**
925 * @brief Check if Rx buffer not empty interrupt is enabled
926 * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
927 * @param SPIx SPI Instance
928 * @retval State of bit (1 or 0).
929 */
LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef * SPIx)930 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx)
931 {
932 return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
933 }
934
935 /**
936 * @brief Check if Tx buffer empty interrupt
937 * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
938 * @param SPIx SPI Instance
939 * @retval State of bit (1 or 0).
940 */
LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef * SPIx)941 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef *SPIx)
942 {
943 return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
944 }
945
946 /**
947 * @}
948 */
949
950 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
951 * @{
952 */
953
954 /**
955 * @brief Enable DMA Rx
956 * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
957 * @param SPIx SPI Instance
958 * @retval None
959 */
LL_SPI_EnableDMAReq_RX(SPI_TypeDef * SPIx)960 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
961 {
962 SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
963 }
964
965 /**
966 * @brief Disable DMA Rx
967 * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
968 * @param SPIx SPI Instance
969 * @retval None
970 */
LL_SPI_DisableDMAReq_RX(SPI_TypeDef * SPIx)971 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
972 {
973 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
974 }
975
976 /**
977 * @brief Check if DMA Rx is enabled
978 * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
979 * @param SPIx SPI Instance
980 * @retval State of bit (1 or 0).
981 */
LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef * SPIx)982 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
983 {
984 return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
985 }
986
987 /**
988 * @brief Enable DMA Tx
989 * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
990 * @param SPIx SPI Instance
991 * @retval None
992 */
LL_SPI_EnableDMAReq_TX(SPI_TypeDef * SPIx)993 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
994 {
995 SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
996 }
997
998 /**
999 * @brief Disable DMA Tx
1000 * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
1001 * @param SPIx SPI Instance
1002 * @retval None
1003 */
LL_SPI_DisableDMAReq_TX(SPI_TypeDef * SPIx)1004 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
1005 {
1006 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
1007 }
1008
1009 /**
1010 * @brief Check if DMA Tx is enabled
1011 * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
1012 * @param SPIx SPI Instance
1013 * @retval State of bit (1 or 0).
1014 */
LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef * SPIx)1015 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
1016 {
1017 return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
1018 }
1019
1020 /**
1021 * @brief Get the data register address used for DMA transfer
1022 * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
1023 * @param SPIx SPI Instance
1024 * @retval Address of data register
1025 */
LL_SPI_DMA_GetRegAddr(const SPI_TypeDef * SPIx)1026 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(const SPI_TypeDef *SPIx)
1027 {
1028 return (uint32_t) &(SPIx->DR);
1029 }
1030
1031 /**
1032 * @}
1033 */
1034
1035 /** @defgroup SPI_LL_EF_DATA_Management DATA Management
1036 * @{
1037 */
1038
1039 /**
1040 * @brief Read 8-Bits in the data register
1041 * @rmtoll DR DR LL_SPI_ReceiveData8
1042 * @param SPIx SPI Instance
1043 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
1044 */
LL_SPI_ReceiveData8(SPI_TypeDef * SPIx)1045 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
1046 {
1047 return (*((__IO uint8_t *)&SPIx->DR));
1048 }
1049
1050 /**
1051 * @brief Read 16-Bits in the data register
1052 * @rmtoll DR DR LL_SPI_ReceiveData16
1053 * @param SPIx SPI Instance
1054 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
1055 */
LL_SPI_ReceiveData16(SPI_TypeDef * SPIx)1056 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
1057 {
1058 return (uint16_t)(READ_REG(SPIx->DR));
1059 }
1060
1061 /**
1062 * @brief Write 8-Bits in the data register
1063 * @rmtoll DR DR LL_SPI_TransmitData8
1064 * @param SPIx SPI Instance
1065 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
1066 * @retval None
1067 */
LL_SPI_TransmitData8(SPI_TypeDef * SPIx,uint8_t TxData)1068 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
1069 {
1070 #if defined (__GNUC__)
1071 __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
1072 *spidr = TxData;
1073 #else
1074 *((__IO uint8_t *)&SPIx->DR) = TxData;
1075 #endif /* __GNUC__ */
1076 }
1077
1078 /**
1079 * @brief Write 16-Bits in the data register
1080 * @rmtoll DR DR LL_SPI_TransmitData16
1081 * @param SPIx SPI Instance
1082 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
1083 * @retval None
1084 */
LL_SPI_TransmitData16(SPI_TypeDef * SPIx,uint16_t TxData)1085 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
1086 {
1087 #if defined (__GNUC__)
1088 __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
1089 *spidr = TxData;
1090 #else
1091 SPIx->DR = TxData;
1092 #endif /* __GNUC__ */
1093 }
1094
1095 /**
1096 * @}
1097 */
1098 #if defined(USE_FULL_LL_DRIVER)
1099 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
1100 * @{
1101 */
1102
1103 ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx);
1104 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
1105 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
1106
1107 /**
1108 * @}
1109 */
1110 #endif /* USE_FULL_LL_DRIVER */
1111 /**
1112 * @}
1113 */
1114
1115 /**
1116 * @}
1117 */
1118
1119 #if defined(SPI_I2S_SUPPORT)
1120 /** @defgroup I2S_LL I2S
1121 * @{
1122 */
1123
1124 /* Private variables ---------------------------------------------------------*/
1125 /* Private constants ---------------------------------------------------------*/
1126 /* Private macros ------------------------------------------------------------*/
1127
1128 /* Exported types ------------------------------------------------------------*/
1129 #if defined(USE_FULL_LL_DRIVER)
1130 /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
1131 * @{
1132 */
1133
1134 /**
1135 * @brief I2S Init structure definition
1136 */
1137
1138 typedef struct
1139 {
1140 uint32_t Mode; /*!< Specifies the I2S operating mode.
1141 This parameter can be a value of @ref I2S_LL_EC_MODE
1142
1143 This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
1144
1145 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
1146 This parameter can be a value of @ref I2S_LL_EC_STANDARD
1147
1148 This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
1149
1150
1151 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
1152 This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
1153
1154 This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
1155
1156
1157 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
1158 This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
1159
1160 This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
1161
1162
1163 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
1164 This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
1165
1166 Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
1167 and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
1168
1169
1170 uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
1171 This parameter can be a value of @ref I2S_LL_EC_POLARITY
1172
1173 This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
1174
1175 } LL_I2S_InitTypeDef;
1176
1177 /**
1178 * @}
1179 */
1180 #endif /*USE_FULL_LL_DRIVER*/
1181
1182 /* Exported constants --------------------------------------------------------*/
1183 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
1184 * @{
1185 */
1186
1187 /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
1188 * @brief Flags defines which can be used with LL_I2S_ReadReg function
1189 * @{
1190 */
1191 #define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
1192 #define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
1193 #define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
1194 #define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
1195 #define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
1196 #define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
1197 /**
1198 * @}
1199 */
1200
1201 /** @defgroup SPI_LL_EC_IT IT Defines
1202 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
1203 * @{
1204 */
1205 #define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
1206 #define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
1207 #define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
1208 /**
1209 * @}
1210 */
1211
1212 /** @defgroup I2S_LL_EC_DATA_FORMAT Data format
1213 * @{
1214 */
1215 #define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel length 16bit */
1216 #define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel length 32bit */
1217 #define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel length 32bit */
1218 #define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel length 32bit */
1219 /**
1220 * @}
1221 */
1222
1223 /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
1224 * @{
1225 */
1226 #define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */
1227 #define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
1228 /**
1229 * @}
1230 */
1231
1232 /** @defgroup I2S_LL_EC_STANDARD I2s Standard
1233 * @{
1234 */
1235 #define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */
1236 #define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
1237 #define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
1238 #define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
1239 #define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
1240 /**
1241 * @}
1242 */
1243
1244 /** @defgroup I2S_LL_EC_MODE Operation Mode
1245 * @{
1246 */
1247 #define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
1248 #define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
1249 #define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
1250 #define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
1251 /**
1252 * @}
1253 */
1254
1255 /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
1256 * @{
1257 */
1258 #define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
1259 #define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
1260 /**
1261 * @}
1262 */
1263
1264 #if defined(USE_FULL_LL_DRIVER)
1265
1266 /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
1267 * @{
1268 */
1269 #define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */
1270 #define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
1271 /**
1272 * @}
1273 */
1274
1275 /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
1276 * @{
1277 */
1278
1279 #define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
1280 #define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
1281 #define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
1282 #define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
1283 #define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
1284 #define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
1285 #define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
1286 #define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
1287 #define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
1288 #define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
1289 /**
1290 * @}
1291 */
1292 #endif /* USE_FULL_LL_DRIVER */
1293
1294 /**
1295 * @}
1296 */
1297
1298 /* Exported macro ------------------------------------------------------------*/
1299 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
1300 * @{
1301 */
1302
1303 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
1304 * @{
1305 */
1306
1307 /**
1308 * @brief Write a value in I2S register
1309 * @param __INSTANCE__ I2S Instance
1310 * @param __REG__ Register to be written
1311 * @param __VALUE__ Value to be written in the register
1312 * @retval None
1313 */
1314 #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1315
1316 /**
1317 * @brief Read a value in I2S register
1318 * @param __INSTANCE__ I2S Instance
1319 * @param __REG__ Register to be read
1320 * @retval Register value
1321 */
1322 #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1323 /**
1324 * @}
1325 */
1326
1327 /**
1328 * @}
1329 */
1330
1331
1332 /* Exported functions --------------------------------------------------------*/
1333
1334 /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
1335 * @{
1336 */
1337
1338 /** @defgroup I2S_LL_EF_Configuration Configuration
1339 * @{
1340 */
1341
1342 /**
1343 * @brief Select I2S mode and Enable I2S peripheral
1344 * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
1345 * I2SCFGR I2SE LL_I2S_Enable
1346 * @param SPIx SPI Instance
1347 * @retval None
1348 */
LL_I2S_Enable(SPI_TypeDef * SPIx)1349 __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
1350 {
1351 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
1352 }
1353
1354 /**
1355 * @brief Disable I2S peripheral
1356 * @rmtoll I2SCFGR I2SE LL_I2S_Disable
1357 * @param SPIx SPI Instance
1358 * @retval None
1359 */
LL_I2S_Disable(SPI_TypeDef * SPIx)1360 __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
1361 {
1362 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
1363 }
1364
1365 /**
1366 * @brief Check if I2S peripheral is enabled
1367 * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
1368 * @param SPIx SPI Instance
1369 * @retval State of bit (1 or 0).
1370 */
LL_I2S_IsEnabled(const SPI_TypeDef * SPIx)1371 __STATIC_INLINE uint32_t LL_I2S_IsEnabled(const SPI_TypeDef *SPIx)
1372 {
1373 return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
1374 }
1375
1376 /**
1377 * @brief Set I2S data frame length
1378 * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
1379 * I2SCFGR CHLEN LL_I2S_SetDataFormat
1380 * @param SPIx SPI Instance
1381 * @param DataFormat This parameter can be one of the following values:
1382 * @arg @ref LL_I2S_DATAFORMAT_16B
1383 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
1384 * @arg @ref LL_I2S_DATAFORMAT_24B
1385 * @arg @ref LL_I2S_DATAFORMAT_32B
1386 * @retval None
1387 */
LL_I2S_SetDataFormat(SPI_TypeDef * SPIx,uint32_t DataFormat)1388 __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
1389 {
1390 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
1391 }
1392
1393 /**
1394 * @brief Get I2S data frame length
1395 * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
1396 * I2SCFGR CHLEN LL_I2S_GetDataFormat
1397 * @param SPIx SPI Instance
1398 * @retval Returned value can be one of the following values:
1399 * @arg @ref LL_I2S_DATAFORMAT_16B
1400 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
1401 * @arg @ref LL_I2S_DATAFORMAT_24B
1402 * @arg @ref LL_I2S_DATAFORMAT_32B
1403 */
LL_I2S_GetDataFormat(const SPI_TypeDef * SPIx)1404 __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(const SPI_TypeDef *SPIx)
1405 {
1406 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
1407 }
1408
1409 /**
1410 * @brief Set I2S clock polarity
1411 * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
1412 * @param SPIx SPI Instance
1413 * @param ClockPolarity This parameter can be one of the following values:
1414 * @arg @ref LL_I2S_POLARITY_LOW
1415 * @arg @ref LL_I2S_POLARITY_HIGH
1416 * @retval None
1417 */
LL_I2S_SetClockPolarity(SPI_TypeDef * SPIx,uint32_t ClockPolarity)1418 __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
1419 {
1420 SET_BIT(SPIx->I2SCFGR, ClockPolarity);
1421 }
1422
1423 /**
1424 * @brief Get I2S clock polarity
1425 * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
1426 * @param SPIx SPI Instance
1427 * @retval Returned value can be one of the following values:
1428 * @arg @ref LL_I2S_POLARITY_LOW
1429 * @arg @ref LL_I2S_POLARITY_HIGH
1430 */
LL_I2S_GetClockPolarity(const SPI_TypeDef * SPIx)1431 __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(const SPI_TypeDef *SPIx)
1432 {
1433 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
1434 }
1435
1436 /**
1437 * @brief Set I2S standard protocol
1438 * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
1439 * I2SCFGR PCMSYNC LL_I2S_SetStandard
1440 * @param SPIx SPI Instance
1441 * @param Standard This parameter can be one of the following values:
1442 * @arg @ref LL_I2S_STANDARD_PHILIPS
1443 * @arg @ref LL_I2S_STANDARD_MSB
1444 * @arg @ref LL_I2S_STANDARD_LSB
1445 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
1446 * @arg @ref LL_I2S_STANDARD_PCM_LONG
1447 * @retval None
1448 */
LL_I2S_SetStandard(SPI_TypeDef * SPIx,uint32_t Standard)1449 __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
1450 {
1451 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
1452 }
1453
1454 /**
1455 * @brief Get I2S standard protocol
1456 * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
1457 * I2SCFGR PCMSYNC LL_I2S_GetStandard
1458 * @param SPIx SPI Instance
1459 * @retval Returned value can be one of the following values:
1460 * @arg @ref LL_I2S_STANDARD_PHILIPS
1461 * @arg @ref LL_I2S_STANDARD_MSB
1462 * @arg @ref LL_I2S_STANDARD_LSB
1463 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
1464 * @arg @ref LL_I2S_STANDARD_PCM_LONG
1465 */
LL_I2S_GetStandard(const SPI_TypeDef * SPIx)1466 __STATIC_INLINE uint32_t LL_I2S_GetStandard(const SPI_TypeDef *SPIx)
1467 {
1468 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
1469 }
1470
1471 /**
1472 * @brief Set I2S transfer mode
1473 * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
1474 * @param SPIx SPI Instance
1475 * @param Mode This parameter can be one of the following values:
1476 * @arg @ref LL_I2S_MODE_SLAVE_TX
1477 * @arg @ref LL_I2S_MODE_SLAVE_RX
1478 * @arg @ref LL_I2S_MODE_MASTER_TX
1479 * @arg @ref LL_I2S_MODE_MASTER_RX
1480 * @retval None
1481 */
LL_I2S_SetTransferMode(SPI_TypeDef * SPIx,uint32_t Mode)1482 __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
1483 {
1484 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
1485 }
1486
1487 /**
1488 * @brief Get I2S transfer mode
1489 * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
1490 * @param SPIx SPI Instance
1491 * @retval Returned value can be one of the following values:
1492 * @arg @ref LL_I2S_MODE_SLAVE_TX
1493 * @arg @ref LL_I2S_MODE_SLAVE_RX
1494 * @arg @ref LL_I2S_MODE_MASTER_TX
1495 * @arg @ref LL_I2S_MODE_MASTER_RX
1496 */
LL_I2S_GetTransferMode(const SPI_TypeDef * SPIx)1497 __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(const SPI_TypeDef *SPIx)
1498 {
1499 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
1500 }
1501
1502 /**
1503 * @brief Set I2S linear prescaler
1504 * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
1505 * @param SPIx SPI Instance
1506 * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
1507 * @retval None
1508 */
LL_I2S_SetPrescalerLinear(SPI_TypeDef * SPIx,uint8_t PrescalerLinear)1509 __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
1510 {
1511 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
1512 }
1513
1514 /**
1515 * @brief Get I2S linear prescaler
1516 * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
1517 * @param SPIx SPI Instance
1518 * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
1519 */
LL_I2S_GetPrescalerLinear(const SPI_TypeDef * SPIx)1520 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(const SPI_TypeDef *SPIx)
1521 {
1522 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
1523 }
1524
1525 /**
1526 * @brief Set I2S parity prescaler
1527 * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
1528 * @param SPIx SPI Instance
1529 * @param PrescalerParity This parameter can be one of the following values:
1530 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
1531 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
1532 * @retval None
1533 */
LL_I2S_SetPrescalerParity(SPI_TypeDef * SPIx,uint32_t PrescalerParity)1534 __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
1535 {
1536 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
1537 }
1538
1539 /**
1540 * @brief Get I2S parity prescaler
1541 * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
1542 * @param SPIx SPI Instance
1543 * @retval Returned value can be one of the following values:
1544 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
1545 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
1546 */
LL_I2S_GetPrescalerParity(const SPI_TypeDef * SPIx)1547 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(const SPI_TypeDef *SPIx)
1548 {
1549 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
1550 }
1551
1552 /**
1553 * @brief Enable the master clock output (Pin MCK)
1554 * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
1555 * @param SPIx SPI Instance
1556 * @retval None
1557 */
LL_I2S_EnableMasterClock(SPI_TypeDef * SPIx)1558 __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
1559 {
1560 SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
1561 }
1562
1563 /**
1564 * @brief Disable the master clock output (Pin MCK)
1565 * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
1566 * @param SPIx SPI Instance
1567 * @retval None
1568 */
LL_I2S_DisableMasterClock(SPI_TypeDef * SPIx)1569 __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
1570 {
1571 CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
1572 }
1573
1574 /**
1575 * @brief Check if the master clock output (Pin MCK) is enabled
1576 * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
1577 * @param SPIx SPI Instance
1578 * @retval State of bit (1 or 0).
1579 */
LL_I2S_IsEnabledMasterClock(const SPI_TypeDef * SPIx)1580 __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(const SPI_TypeDef *SPIx)
1581 {
1582 return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
1583 }
1584
1585 /**
1586 * @}
1587 */
1588
1589 /** @defgroup I2S_LL_EF_FLAG FLAG Management
1590 * @{
1591 */
1592
1593 /**
1594 * @brief Check if Rx buffer is not empty
1595 * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
1596 * @param SPIx SPI Instance
1597 * @retval State of bit (1 or 0).
1598 */
LL_I2S_IsActiveFlag_RXNE(const SPI_TypeDef * SPIx)1599 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx)
1600 {
1601 return LL_SPI_IsActiveFlag_RXNE(SPIx);
1602 }
1603
1604 /**
1605 * @brief Check if Tx buffer is empty
1606 * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
1607 * @param SPIx SPI Instance
1608 * @retval State of bit (1 or 0).
1609 */
LL_I2S_IsActiveFlag_TXE(const SPI_TypeDef * SPIx)1610 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(const SPI_TypeDef *SPIx)
1611 {
1612 return LL_SPI_IsActiveFlag_TXE(SPIx);
1613 }
1614
1615 /**
1616 * @brief Get busy flag
1617 * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
1618 * @param SPIx SPI Instance
1619 * @retval State of bit (1 or 0).
1620 */
LL_I2S_IsActiveFlag_BSY(const SPI_TypeDef * SPIx)1621 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(const SPI_TypeDef *SPIx)
1622 {
1623 return LL_SPI_IsActiveFlag_BSY(SPIx);
1624 }
1625
1626 /**
1627 * @brief Get overrun error flag
1628 * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
1629 * @param SPIx SPI Instance
1630 * @retval State of bit (1 or 0).
1631 */
LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef * SPIx)1632 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
1633 {
1634 return LL_SPI_IsActiveFlag_OVR(SPIx);
1635 }
1636
1637 /**
1638 * @brief Get underrun error flag
1639 * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
1640 * @param SPIx SPI Instance
1641 * @retval State of bit (1 or 0).
1642 */
LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef * SPIx)1643 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef *SPIx)
1644 {
1645 return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
1646 }
1647
1648
1649 /**
1650 * @brief Get channel side flag.
1651 * @note 0: Channel Left has to be transmitted or has been received\n
1652 * 1: Channel Right has to be transmitted or has been received\n
1653 * It has no significance in PCM mode.
1654 * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
1655 * @param SPIx SPI Instance
1656 * @retval State of bit (1 or 0).
1657 */
LL_I2S_IsActiveFlag_CHSIDE(const SPI_TypeDef * SPIx)1658 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(const SPI_TypeDef *SPIx)
1659 {
1660 return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
1661 }
1662
1663 /**
1664 * @brief Clear overrun error flag
1665 * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
1666 * @param SPIx SPI Instance
1667 * @retval None
1668 */
LL_I2S_ClearFlag_OVR(SPI_TypeDef * SPIx)1669 __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
1670 {
1671 LL_SPI_ClearFlag_OVR(SPIx);
1672 }
1673
1674 /**
1675 * @brief Clear underrun error flag
1676 * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
1677 * @param SPIx SPI Instance
1678 * @retval None
1679 */
LL_I2S_ClearFlag_UDR(SPI_TypeDef * SPIx)1680 __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
1681 {
1682 __IO uint32_t tmpreg;
1683 tmpreg = SPIx->SR;
1684 (void)tmpreg;
1685 }
1686
1687 /**
1688 * @brief Clear frame format error flag
1689 * @rmtoll SR FRE LL_I2S_ClearFlag_FRE
1690 * @param SPIx SPI Instance
1691 * @retval None
1692 */
LL_I2S_ClearFlag_FRE(SPI_TypeDef * SPIx)1693 __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
1694 {
1695 LL_SPI_ClearFlag_FRE(SPIx);
1696 }
1697
1698 /**
1699 * @}
1700 */
1701
1702 /** @defgroup I2S_LL_EF_IT Interrupt Management
1703 * @{
1704 */
1705
1706 /**
1707 * @brief Enable error IT
1708 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
1709 * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
1710 * @param SPIx SPI Instance
1711 * @retval None
1712 */
LL_I2S_EnableIT_ERR(SPI_TypeDef * SPIx)1713 __STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
1714 {
1715 LL_SPI_EnableIT_ERR(SPIx);
1716 }
1717
1718 /**
1719 * @brief Enable Rx buffer not empty IT
1720 * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
1721 * @param SPIx SPI Instance
1722 * @retval None
1723 */
LL_I2S_EnableIT_RXNE(SPI_TypeDef * SPIx)1724 __STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
1725 {
1726 LL_SPI_EnableIT_RXNE(SPIx);
1727 }
1728
1729 /**
1730 * @brief Enable Tx buffer empty IT
1731 * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
1732 * @param SPIx SPI Instance
1733 * @retval None
1734 */
LL_I2S_EnableIT_TXE(SPI_TypeDef * SPIx)1735 __STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
1736 {
1737 LL_SPI_EnableIT_TXE(SPIx);
1738 }
1739
1740 /**
1741 * @brief Disable error IT
1742 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
1743 * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
1744 * @param SPIx SPI Instance
1745 * @retval None
1746 */
LL_I2S_DisableIT_ERR(SPI_TypeDef * SPIx)1747 __STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
1748 {
1749 LL_SPI_DisableIT_ERR(SPIx);
1750 }
1751
1752 /**
1753 * @brief Disable Rx buffer not empty IT
1754 * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
1755 * @param SPIx SPI Instance
1756 * @retval None
1757 */
LL_I2S_DisableIT_RXNE(SPI_TypeDef * SPIx)1758 __STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
1759 {
1760 LL_SPI_DisableIT_RXNE(SPIx);
1761 }
1762
1763 /**
1764 * @brief Disable Tx buffer empty IT
1765 * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
1766 * @param SPIx SPI Instance
1767 * @retval None
1768 */
LL_I2S_DisableIT_TXE(SPI_TypeDef * SPIx)1769 __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
1770 {
1771 LL_SPI_DisableIT_TXE(SPIx);
1772 }
1773
1774 /**
1775 * @brief Check if ERR IT is enabled
1776 * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
1777 * @param SPIx SPI Instance
1778 * @retval State of bit (1 or 0).
1779 */
LL_I2S_IsEnabledIT_ERR(const SPI_TypeDef * SPIx)1780 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(const SPI_TypeDef *SPIx)
1781 {
1782 return LL_SPI_IsEnabledIT_ERR(SPIx);
1783 }
1784
1785 /**
1786 * @brief Check if RXNE IT is enabled
1787 * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
1788 * @param SPIx SPI Instance
1789 * @retval State of bit (1 or 0).
1790 */
LL_I2S_IsEnabledIT_RXNE(const SPI_TypeDef * SPIx)1791 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx)
1792 {
1793 return LL_SPI_IsEnabledIT_RXNE(SPIx);
1794 }
1795
1796 /**
1797 * @brief Check if TXE IT is enabled
1798 * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
1799 * @param SPIx SPI Instance
1800 * @retval State of bit (1 or 0).
1801 */
LL_I2S_IsEnabledIT_TXE(const SPI_TypeDef * SPIx)1802 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(const SPI_TypeDef *SPIx)
1803 {
1804 return LL_SPI_IsEnabledIT_TXE(SPIx);
1805 }
1806
1807 /**
1808 * @}
1809 */
1810
1811 /** @defgroup I2S_LL_EF_DMA DMA Management
1812 * @{
1813 */
1814
1815 /**
1816 * @brief Enable DMA Rx
1817 * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
1818 * @param SPIx SPI Instance
1819 * @retval None
1820 */
LL_I2S_EnableDMAReq_RX(SPI_TypeDef * SPIx)1821 __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
1822 {
1823 LL_SPI_EnableDMAReq_RX(SPIx);
1824 }
1825
1826 /**
1827 * @brief Disable DMA Rx
1828 * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
1829 * @param SPIx SPI Instance
1830 * @retval None
1831 */
LL_I2S_DisableDMAReq_RX(SPI_TypeDef * SPIx)1832 __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
1833 {
1834 LL_SPI_DisableDMAReq_RX(SPIx);
1835 }
1836
1837 /**
1838 * @brief Check if DMA Rx is enabled
1839 * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
1840 * @param SPIx SPI Instance
1841 * @retval State of bit (1 or 0).
1842 */
LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef * SPIx)1843 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
1844 {
1845 return LL_SPI_IsEnabledDMAReq_RX(SPIx);
1846 }
1847
1848 /**
1849 * @brief Enable DMA Tx
1850 * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
1851 * @param SPIx SPI Instance
1852 * @retval None
1853 */
LL_I2S_EnableDMAReq_TX(SPI_TypeDef * SPIx)1854 __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
1855 {
1856 LL_SPI_EnableDMAReq_TX(SPIx);
1857 }
1858
1859 /**
1860 * @brief Disable DMA Tx
1861 * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
1862 * @param SPIx SPI Instance
1863 * @retval None
1864 */
LL_I2S_DisableDMAReq_TX(SPI_TypeDef * SPIx)1865 __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
1866 {
1867 LL_SPI_DisableDMAReq_TX(SPIx);
1868 }
1869
1870 /**
1871 * @brief Check if DMA Tx is enabled
1872 * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
1873 * @param SPIx SPI Instance
1874 * @retval State of bit (1 or 0).
1875 */
LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef * SPIx)1876 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
1877 {
1878 return LL_SPI_IsEnabledDMAReq_TX(SPIx);
1879 }
1880
1881 /**
1882 * @}
1883 */
1884
1885 /** @defgroup I2S_LL_EF_DATA DATA Management
1886 * @{
1887 */
1888
1889 /**
1890 * @brief Read 16-Bits in data register
1891 * @rmtoll DR DR LL_I2S_ReceiveData16
1892 * @param SPIx SPI Instance
1893 * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
1894 */
LL_I2S_ReceiveData16(SPI_TypeDef * SPIx)1895 __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
1896 {
1897 return LL_SPI_ReceiveData16(SPIx);
1898 }
1899
1900 /**
1901 * @brief Write 16-Bits in data register
1902 * @rmtoll DR DR LL_I2S_TransmitData16
1903 * @param SPIx SPI Instance
1904 * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
1905 * @retval None
1906 */
LL_I2S_TransmitData16(SPI_TypeDef * SPIx,uint16_t TxData)1907 __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
1908 {
1909 LL_SPI_TransmitData16(SPIx, TxData);
1910 }
1911
1912 /**
1913 * @}
1914 */
1915
1916 #if defined(USE_FULL_LL_DRIVER)
1917 /** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
1918 * @{
1919 */
1920
1921 ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx);
1922 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
1923 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
1924 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
1925
1926 /**
1927 * @}
1928 */
1929 #endif /* USE_FULL_LL_DRIVER */
1930
1931 /**
1932 * @}
1933 */
1934
1935 /**
1936 * @}
1937 */
1938 #endif /* SPI_I2S_SUPPORT */
1939
1940 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
1941
1942 /**
1943 * @}
1944 */
1945
1946 #ifdef __cplusplus
1947 }
1948 #endif
1949
1950 #endif /* STM32F1xx_LL_SPI_H */
1951
1952
