1 /** 2 ****************************************************************************** 3 * @file stm32f1xx_hal_adc.h 4 * @author MCD Application Team 5 * @brief Header file containing functions prototypes of ADC HAL library. 6 ****************************************************************************** 7 * @attention 8 * 9 * 10 * Copyright (c) 2016 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32F1xx_HAL_ADC_H 22 #define __STM32F1xx_HAL_ADC_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32f1xx_hal_def.h" 30 /** @addtogroup STM32F1xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup ADC 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup ADC_Exported_Types ADC Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief Structure definition of ADC and regular group initialization 45 * @note Parameters of this structure are shared within 2 scopes: 46 * - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode. 47 * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. 48 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. 49 * ADC can be either disabled or enabled without conversion on going on regular group. 50 */ 51 typedef struct 52 { 53 uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) 54 or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). 55 This parameter can be a value of @ref ADC_Data_align */ 56 uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. 57 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. 58 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). 59 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). 60 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). 61 Scan direction is upward: from rank1 to rank 'n'. 62 This parameter can be a value of @ref ADC_Scan_mode 63 Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1) 64 or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the 65 the last conversion of the sequence. All previous conversions would be overwritten by the last one. 66 Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */ 67 FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, 68 after the selected trigger occurred (software start or external trigger). 69 This parameter can be set to ENABLE or DISABLE. */ 70 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. 71 To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 72 This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ 73 FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). 74 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 75 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 76 This parameter can be set to ENABLE or DISABLE. */ 77 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. 78 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 79 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 80 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. 81 If set to ADC_SOFTWARE_START, external triggers are disabled. 82 If set to external trigger source, triggering is on event rising edge. 83 This parameter can be a value of @ref ADC_External_trigger_source_Regular */ 84 }ADC_InitTypeDef; 85 86 /** 87 * @brief Structure definition of ADC channel for regular group 88 * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. 89 * ADC can be either disabled or enabled without conversion on going on regular group. 90 */ 91 typedef struct 92 { 93 uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. 94 This parameter can be a value of @ref ADC_channels 95 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. 96 Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor) 97 Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger. 98 It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. 99 Refer to errata sheet of these devices for more details. */ 100 uint32_t Rank; /*!< Specifies the rank in the regular group sequencer 101 This parameter can be a value of @ref ADC_regular_rank 102 Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ 103 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 104 Unit: ADC clock cycles 105 Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). 106 This parameter can be a value of @ref ADC_sampling_times 107 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. 108 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. 109 Note: In case of usage of internal measurement channels (VrefInt/TempSensor), 110 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 111 Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */ 112 }ADC_ChannelConfTypeDef; 113 114 /** 115 * @brief ADC Configuration analog watchdog definition 116 * @note The setting of these parameters with function is conditioned to ADC state. 117 * ADC state can be either disabled or enabled without conversion on going on regular and injected groups. 118 */ 119 typedef struct 120 { 121 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group. 122 This parameter can be a value of @ref ADC_analog_watchdog_mode. */ 123 uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. 124 This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode) 125 This parameter can be a value of @ref ADC_channels. */ 126 FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. 127 This parameter can be set to ENABLE or DISABLE */ 128 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. 129 This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ 130 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. 131 This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ 132 uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ 133 }ADC_AnalogWDGConfTypeDef; 134 135 /** 136 * @brief HAL ADC state machine: ADC states definition (bitfields) 137 */ 138 /* States of ADC global scope */ 139 #define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */ 140 #define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */ 141 #define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */ 142 #define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */ 143 144 /* States of ADC errors */ 145 #define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */ 146 #define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */ 147 #define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */ 148 149 /* States of ADC group regular */ 150 #define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, 151 external trigger, low power auto power-on, multimode ADC master control) */ 152 #define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */ 153 #define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Not available on STM32F1 device: Overrun occurrence */ 154 #define HAL_ADC_STATE_REG_EOSMP 0x00000800U /*!< Not available on STM32F1 device: End Of Sampling flag raised */ 155 156 /* States of ADC group injected */ 157 #define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, 158 external trigger, low power auto power-on, multimode ADC master control) */ 159 #define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */ 160 #define HAL_ADC_STATE_INJ_JQOVF 0x00004000U /*!< Not available on STM32F1 device: Injected queue overflow occurrence */ 161 162 /* States of ADC analog watchdogs */ 163 #define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */ 164 #define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 */ 165 #define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 */ 166 167 /* States of ADC multi-mode */ 168 #define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< ADC in multimode slave state, controlled by another ADC master ( */ 169 170 171 /** 172 * @brief ADC handle Structure definition 173 */ 174 typedef struct __ADC_HandleTypeDef 175 { 176 ADC_TypeDef *Instance; /*!< Register base address */ 177 178 ADC_InitTypeDef Init; /*!< ADC required parameters */ 179 180 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 181 182 HAL_LockTypeDef Lock; /*!< ADC locking object */ 183 184 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 185 186 __IO uint32_t ErrorCode; /*!< ADC Error code */ 187 188 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 189 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ 190 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ 191 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ 192 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ 193 void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ /*!< ADC end of sampling callback */ 194 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ 195 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ 196 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 197 }ADC_HandleTypeDef; 198 199 200 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 201 /** 202 * @brief HAL ADC Callback ID enumeration definition 203 */ 204 typedef enum 205 { 206 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ 207 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ 208 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ 209 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ 210 HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ 211 HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ 212 HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ 213 } HAL_ADC_CallbackIDTypeDef; 214 215 /** 216 * @brief HAL ADC Callback pointer definition 217 */ 218 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ 219 220 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 221 222 /** 223 * @} 224 */ 225 226 227 228 /* Exported constants --------------------------------------------------------*/ 229 230 /** @defgroup ADC_Exported_Constants ADC Exported Constants 231 * @{ 232 */ 233 234 /** @defgroup ADC_Error_Code ADC Error Code 235 * @{ 236 */ 237 #define HAL_ADC_ERROR_NONE 0x00U /*!< No error */ 238 #define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking, 239 enable/disable, erroneous state */ 240 #define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */ 241 #define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */ 242 243 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 244 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 245 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 246 /** 247 * @} 248 */ 249 250 251 /** @defgroup ADC_Data_align ADC data alignment 252 * @{ 253 */ 254 #define ADC_DATAALIGN_RIGHT 0x00000000U 255 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) 256 /** 257 * @} 258 */ 259 260 /** @defgroup ADC_Scan_mode ADC scan mode 261 * @{ 262 */ 263 /* Note: Scan mode values are not among binary choices ENABLE/DISABLE for */ 264 /* compatibility with other STM32 devices having a sequencer with */ 265 /* additional options. */ 266 #define ADC_SCAN_DISABLE 0x00000000U 267 #define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN) 268 /** 269 * @} 270 */ 271 272 /** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group 273 * @{ 274 */ 275 #define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U 276 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG) 277 /** 278 * @} 279 */ 280 281 /** @defgroup ADC_channels ADC channels 282 * @{ 283 */ 284 /* Note: Depending on devices, some channels may not be available on package */ 285 /* pins. Refer to device datasheet for channels availability. */ 286 #define ADC_CHANNEL_0 0x00000000U 287 #define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR3_SQ1_0)) 288 #define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR3_SQ1_1 )) 289 #define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) 290 #define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR3_SQ1_2 )) 291 #define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0)) 292 #define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 )) 293 #define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) 294 #define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR3_SQ1_3 )) 295 #define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0)) 296 #define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 )) 297 #define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) 298 #define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 )) 299 #define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0)) 300 #define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 )) 301 #define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) 302 #define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4 )) 303 #define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0)) 304 305 #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */ 306 #define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin) */ 307 /** 308 * @} 309 */ 310 311 /** @defgroup ADC_sampling_times ADC sampling times 312 * @{ 313 */ 314 #define ADC_SAMPLETIME_1CYCLE_5 0x00000000U /*!< Sampling time 1.5 ADC clock cycle */ 315 #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_0)) /*!< Sampling time 7.5 ADC clock cycles */ 316 #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 )) /*!< Sampling time 13.5 ADC clock cycles */ 317 #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */ 318 #define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 )) /*!< Sampling time 41.5 ADC clock cycles */ 319 #define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 55.5 ADC clock cycles */ 320 #define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 )) /*!< Sampling time 71.5 ADC clock cycles */ 321 #define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 239.5 ADC clock cycles */ 322 /** 323 * @} 324 */ 325 326 /** @defgroup ADC_regular_rank ADC rank into regular group 327 * @{ 328 */ 329 #define ADC_REGULAR_RANK_1 0x00000001U 330 #define ADC_REGULAR_RANK_2 0x00000002U 331 #define ADC_REGULAR_RANK_3 0x00000003U 332 #define ADC_REGULAR_RANK_4 0x00000004U 333 #define ADC_REGULAR_RANK_5 0x00000005U 334 #define ADC_REGULAR_RANK_6 0x00000006U 335 #define ADC_REGULAR_RANK_7 0x00000007U 336 #define ADC_REGULAR_RANK_8 0x00000008U 337 #define ADC_REGULAR_RANK_9 0x00000009U 338 #define ADC_REGULAR_RANK_10 0x0000000AU 339 #define ADC_REGULAR_RANK_11 0x0000000BU 340 #define ADC_REGULAR_RANK_12 0x0000000CU 341 #define ADC_REGULAR_RANK_13 0x0000000DU 342 #define ADC_REGULAR_RANK_14 0x0000000EU 343 #define ADC_REGULAR_RANK_15 0x0000000FU 344 #define ADC_REGULAR_RANK_16 0x00000010U 345 /** 346 * @} 347 */ 348 349 /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode 350 * @{ 351 */ 352 #define ADC_ANALOGWATCHDOG_NONE 0x00000000U 353 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) 354 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) 355 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) 356 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN) 357 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN) 358 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) 359 /** 360 * @} 361 */ 362 363 /** @defgroup ADC_conversion_group ADC conversion group 364 * @{ 365 */ 366 #define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC)) 367 #define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC)) 368 #define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC)) 369 /** 370 * @} 371 */ 372 373 /** @defgroup ADC_Event_type ADC Event type 374 * @{ 375 */ 376 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */ 377 378 #define ADC_AWD1_EVENT ADC_AWD_EVENT /*!< ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having several analog watchdogs */ 379 /** 380 * @} 381 */ 382 383 /** @defgroup ADC_interrupts_definition ADC interrupts definition 384 * @{ 385 */ 386 #define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */ 387 #define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */ 388 #define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */ 389 /** 390 * @} 391 */ 392 393 /** @defgroup ADC_flags_definition ADC flags definition 394 * @{ 395 */ 396 #define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */ 397 #define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */ 398 #define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */ 399 #define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */ 400 #define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */ 401 /** 402 * @} 403 */ 404 405 406 /** 407 * @} 408 */ 409 410 /* Private constants ---------------------------------------------------------*/ 411 412 /** @addtogroup ADC_Private_Constants ADC Private Constants 413 * @{ 414 */ 415 416 /** @defgroup ADC_conversion_cycles ADC conversion cycles 417 * @{ 418 */ 419 /* ADC conversion cycles (unit: ADC clock cycles) */ 420 /* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */ 421 /* resolution 12 bits) */ 422 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 14U 423 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 20U 424 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 26U 425 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 41U 426 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 54U 427 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 68U 428 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 84U 429 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 252U 430 /** 431 * @} 432 */ 433 434 /** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels 435 * @{ 436 */ 437 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \ 438 (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | \ 439 ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | \ 440 ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2) 441 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \ 442 (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \ 443 ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 ) 444 445 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \ 446 (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | \ 447 ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | \ 448 ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1) 449 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \ 450 (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \ 451 ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 ) 452 453 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \ 454 (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | \ 455 ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | \ 456 ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0) 457 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \ 458 (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \ 459 ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 ) 460 461 #define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS 0x00000000U 462 #define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) 463 #define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) 464 #define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) 465 #define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) 466 #define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) 467 #define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) 468 #define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) 469 470 #define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS 0x00000000U 471 #define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) 472 #define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) 473 #define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) 474 #define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) 475 #define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) 476 #define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) 477 #define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) 478 /** 479 * @} 480 */ 481 482 /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */ 483 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD ) 484 485 /** 486 * @} 487 */ 488 489 490 /* Exported macro ------------------------------------------------------------*/ 491 492 /** @defgroup ADC_Exported_Macros ADC Exported Macros 493 * @{ 494 */ 495 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 496 /* final user. */ 497 498 /** 499 * @brief Enable the ADC peripheral 500 * @note ADC enable requires a delay for ADC stabilization time 501 * (refer to device datasheet, parameter tSTAB) 502 * @note On STM32F1, if ADC is already enabled this macro trigs a conversion 503 * SW start on regular group. 504 * @param __HANDLE__: ADC handle 505 * @retval None 506 */ 507 #define __HAL_ADC_ENABLE(__HANDLE__) \ 508 (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON))) 509 510 /** 511 * @brief Disable the ADC peripheral 512 * @param __HANDLE__: ADC handle 513 * @retval None 514 */ 515 #define __HAL_ADC_DISABLE(__HANDLE__) \ 516 (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON))) 517 518 /** @brief Enable the ADC end of conversion interrupt. 519 * @param __HANDLE__: ADC handle 520 * @param __INTERRUPT__: ADC Interrupt 521 * This parameter can be any combination of the following values: 522 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source 523 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source 524 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source 525 * @retval None 526 */ 527 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 528 (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) 529 530 /** @brief Disable the ADC end of conversion interrupt. 531 * @param __HANDLE__: ADC handle 532 * @param __INTERRUPT__: ADC Interrupt 533 * This parameter can be any combination of the following values: 534 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source 535 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source 536 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source 537 * @retval None 538 */ 539 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 540 (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) 541 542 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 543 * @param __HANDLE__: ADC handle 544 * @param __INTERRUPT__: ADC interrupt source to check 545 * This parameter can be any combination of the following values: 546 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source 547 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source 548 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source 549 * @retval None 550 */ 551 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 552 (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) 553 554 /** @brief Get the selected ADC's flag status. 555 * @param __HANDLE__: ADC handle 556 * @param __FLAG__: ADC flag 557 * This parameter can be any combination of the following values: 558 * @arg ADC_FLAG_STRT: ADC Regular group start flag 559 * @arg ADC_FLAG_JSTRT: ADC Injected group start flag 560 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag 561 * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag 562 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag 563 * @retval None 564 */ 565 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 566 ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 567 568 /** @brief Clear the ADC's pending flags 569 * @param __HANDLE__: ADC handle 570 * @param __FLAG__: ADC flag 571 * This parameter can be any combination of the following values: 572 * @arg ADC_FLAG_STRT: ADC Regular group start flag 573 * @arg ADC_FLAG_JSTRT: ADC Injected group start flag 574 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag 575 * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag 576 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag 577 * @retval None 578 */ 579 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 580 (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__))) 581 582 /** @brief Reset ADC handle state 583 * @param __HANDLE__: ADC handle 584 * @retval None 585 */ 586 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 587 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 588 do{ \ 589 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ 590 (__HANDLE__)->MspInitCallback = NULL; \ 591 (__HANDLE__)->MspDeInitCallback = NULL; \ 592 } while(0) 593 #else 594 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 595 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 596 #endif 597 598 /** 599 * @} 600 */ 601 602 /* Private macro ------------------------------------------------------------*/ 603 604 /** @defgroup ADC_Private_Macros ADC Private Macros 605 * @{ 606 */ 607 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 608 /* code of final user. */ 609 610 /** 611 * @brief Verification of ADC state: enabled or disabled 612 * @param __HANDLE__: ADC handle 613 * @retval SET (ADC enabled) or RESET (ADC disabled) 614 */ 615 #define ADC_IS_ENABLE(__HANDLE__) \ 616 ((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \ 617 ) ? SET : RESET) 618 619 /** 620 * @brief Test if conversion trigger of regular group is software start 621 * or external trigger. 622 * @param __HANDLE__: ADC handle 623 * @retval SET (software start) or RESET (external trigger) 624 */ 625 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ 626 (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START) 627 628 /** 629 * @brief Test if conversion trigger of injected group is software start 630 * or external trigger. 631 * @param __HANDLE__: ADC handle 632 * @retval SET (software start) or RESET (external trigger) 633 */ 634 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 635 (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START) 636 637 /** 638 * @brief Simultaneously clears and sets specific bits of the handle State 639 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 640 * the first parameter is the ADC handle State, the second parameter is the 641 * bit field to clear, the third and last parameter is the bit field to set. 642 * @retval None 643 */ 644 #define ADC_STATE_CLR_SET MODIFY_REG 645 646 /** 647 * @brief Clear ADC error code (set it to error code: "no error") 648 * @param __HANDLE__: ADC handle 649 * @retval None 650 */ 651 #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ 652 ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 653 654 /** 655 * @brief Set ADC number of conversions into regular channel sequence length. 656 * @param _NbrOfConversion_: Regular channel sequence length 657 * @retval None 658 */ 659 #define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \ 660 (((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos) 661 662 /** 663 * @brief Set the ADC's sample time for channel numbers between 10 and 18. 664 * @param _SAMPLETIME_: Sample time parameter. 665 * @param _CHANNELNB_: Channel number. 666 * @retval None 667 */ 668 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \ 669 ((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_) - 10))) 670 671 /** 672 * @brief Set the ADC's sample time for channel numbers between 0 and 9. 673 * @param _SAMPLETIME_: Sample time parameter. 674 * @param _CHANNELNB_: Channel number. 675 * @retval None 676 */ 677 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \ 678 ((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_))) 679 680 /** 681 * @brief Set the selected regular channel rank for rank between 1 and 6. 682 * @param _CHANNELNB_: Channel number. 683 * @param _RANKNB_: Rank number. 684 * @retval None 685 */ 686 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \ 687 ((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_) - 1))) 688 689 /** 690 * @brief Set the selected regular channel rank for rank between 7 and 12. 691 * @param _CHANNELNB_: Channel number. 692 * @param _RANKNB_: Rank number. 693 * @retval None 694 */ 695 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \ 696 ((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_) - 7))) 697 698 /** 699 * @brief Set the selected regular channel rank for rank between 13 and 16. 700 * @param _CHANNELNB_: Channel number. 701 * @param _RANKNB_: Rank number. 702 * @retval None 703 */ 704 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \ 705 ((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_) - 13))) 706 707 /** 708 * @brief Set the injected sequence length. 709 * @param _JSQR_JL_: Sequence length. 710 * @retval None 711 */ 712 #define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \ 713 (((_JSQR_JL_) -1) << ADC_JSQR_JL_Pos) 714 715 /** 716 * @brief Set the selected injected channel rank 717 * Note: on STM32F1 devices, channel rank position in JSQR register 718 * is depending on total number of ranks selected into 719 * injected sequencer (ranks sequence starting from 4-JL) 720 * @param _CHANNELNB_: Channel number. 721 * @param _RANKNB_: Rank number. 722 * @param _JSQR_JL_: Sequence length. 723 * @retval None 724 */ 725 #define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \ 726 ((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1))) 727 728 /** 729 * @brief Enable ADC continuous conversion mode. 730 * @param _CONTINUOUS_MODE_: Continuous mode. 731 * @retval None 732 */ 733 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \ 734 ((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos) 735 736 /** 737 * @brief Configures the number of discontinuous conversions for the regular group channels. 738 * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions. 739 * @retval None 740 */ 741 #define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \ 742 (((_NBR_DISCONTINUOUS_CONV_) - 1) << ADC_CR1_DISCNUM_Pos) 743 744 /** 745 * @brief Enable ADC scan mode to convert multiple ranks with sequencer. 746 * @param _SCAN_MODE_: Scan conversion mode. 747 * @retval None 748 */ 749 /* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */ 750 /* is equivalent to ADC_SCAN_ENABLE. */ 751 #define ADC_CR1_SCAN_SET(_SCAN_MODE_) \ 752 (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \ 753 )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \ 754 ) 755 756 /** 757 * @brief Get the maximum ADC conversion cycles on all channels. 758 * Returns the selected sampling time + conversion time (12.5 ADC clock cycles) 759 * Approximation of sampling time within 4 ranges, returns the highest value: 760 * below 7.5 cycles {1.5 cycle; 7.5 cycles}, 761 * between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles} 762 * between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles} 763 * equal to 239.5 cycles 764 * Unit: ADC clock cycles 765 * @param __HANDLE__: ADC handle 766 * @retval ADC conversion cycles on all channels 767 */ 768 #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ 769 (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ 770 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \ 771 \ 772 (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \ 773 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \ 774 ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \ 775 : \ 776 ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \ 777 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) || \ 778 ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \ 779 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \ 780 ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \ 781 ) 782 783 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ 784 ((ALIGN) == ADC_DATAALIGN_LEFT) ) 785 786 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ 787 ((SCAN_MODE) == ADC_SCAN_ENABLE) ) 788 789 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 790 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) ) 791 792 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ 793 ((CHANNEL) == ADC_CHANNEL_1) || \ 794 ((CHANNEL) == ADC_CHANNEL_2) || \ 795 ((CHANNEL) == ADC_CHANNEL_3) || \ 796 ((CHANNEL) == ADC_CHANNEL_4) || \ 797 ((CHANNEL) == ADC_CHANNEL_5) || \ 798 ((CHANNEL) == ADC_CHANNEL_6) || \ 799 ((CHANNEL) == ADC_CHANNEL_7) || \ 800 ((CHANNEL) == ADC_CHANNEL_8) || \ 801 ((CHANNEL) == ADC_CHANNEL_9) || \ 802 ((CHANNEL) == ADC_CHANNEL_10) || \ 803 ((CHANNEL) == ADC_CHANNEL_11) || \ 804 ((CHANNEL) == ADC_CHANNEL_12) || \ 805 ((CHANNEL) == ADC_CHANNEL_13) || \ 806 ((CHANNEL) == ADC_CHANNEL_14) || \ 807 ((CHANNEL) == ADC_CHANNEL_15) || \ 808 ((CHANNEL) == ADC_CHANNEL_16) || \ 809 ((CHANNEL) == ADC_CHANNEL_17) ) 810 811 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ 812 ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ 813 ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \ 814 ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \ 815 ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \ 816 ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \ 817 ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \ 818 ((TIME) == ADC_SAMPLETIME_239CYCLES_5) ) 819 820 #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ 821 ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ 822 ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ 823 ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ 824 ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ 825 ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \ 826 ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \ 827 ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \ 828 ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \ 829 ((CHANNEL) == ADC_REGULAR_RANK_10) || \ 830 ((CHANNEL) == ADC_REGULAR_RANK_11) || \ 831 ((CHANNEL) == ADC_REGULAR_RANK_12) || \ 832 ((CHANNEL) == ADC_REGULAR_RANK_13) || \ 833 ((CHANNEL) == ADC_REGULAR_RANK_14) || \ 834 ((CHANNEL) == ADC_REGULAR_RANK_15) || \ 835 ((CHANNEL) == ADC_REGULAR_RANK_16) ) 836 837 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ 838 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 839 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 840 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ 841 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 842 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 843 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) 844 845 #define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \ 846 ((CONVERSION) == ADC_INJECTED_GROUP) || \ 847 ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) ) 848 849 #define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT) 850 851 852 /** @defgroup ADC_range_verification ADC range verification 853 * For a unique ADC resolution: 12 bits 854 * @{ 855 */ 856 #define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= 0x0FFFU) 857 /** 858 * @} 859 */ 860 861 /** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification 862 * @{ 863 */ 864 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U)) 865 /** 866 * @} 867 */ 868 869 /** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification 870 * @{ 871 */ 872 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U)) 873 /** 874 * @} 875 */ 876 877 /** 878 * @} 879 */ 880 881 /* Include ADC HAL Extension module */ 882 #include "stm32f1xx_hal_adc_ex.h" 883 884 /* Exported functions --------------------------------------------------------*/ 885 /** @addtogroup ADC_Exported_Functions 886 * @{ 887 */ 888 889 /** @addtogroup ADC_Exported_Functions_Group1 890 * @{ 891 */ 892 893 894 /* Initialization and de-initialization functions **********************************/ 895 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); 896 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 897 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); 898 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); 899 900 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 901 /* Callbacks Register/UnRegister functions ***********************************/ 902 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); 903 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); 904 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 905 906 /** 907 * @} 908 */ 909 910 /* IO operation functions *****************************************************/ 911 912 /** @addtogroup ADC_Exported_Functions_Group2 913 * @{ 914 */ 915 916 917 /* Blocking mode: Polling */ 918 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); 919 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); 920 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); 921 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); 922 923 /* Non-blocking mode: Interruption */ 924 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); 925 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); 926 927 /* Non-blocking mode: DMA */ 928 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); 929 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); 930 931 /* ADC retrieve conversion value intended to be used with polling or interruption */ 932 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); 933 934 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 935 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); 936 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); 937 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); 938 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); 939 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 940 /** 941 * @} 942 */ 943 944 945 /* Peripheral Control functions ***********************************************/ 946 /** @addtogroup ADC_Exported_Functions_Group3 947 * @{ 948 */ 949 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); 950 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); 951 /** 952 * @} 953 */ 954 955 956 /* Peripheral State functions *************************************************/ 957 /** @addtogroup ADC_Exported_Functions_Group4 958 * @{ 959 */ 960 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); 961 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); 962 /** 963 * @} 964 */ 965 966 967 /** 968 * @} 969 */ 970 971 972 /* Internal HAL driver functions **********************************************/ 973 /** @addtogroup ADC_Private_Functions 974 * @{ 975 */ 976 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); 977 HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc); 978 void ADC_StabilizationTime(uint32_t DelayUs); 979 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); 980 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); 981 void ADC_DMAError(DMA_HandleTypeDef *hdma); 982 /** 983 * @} 984 */ 985 986 987 /** 988 * @} 989 */ 990 991 /** 992 * @} 993 */ 994 995 #ifdef __cplusplus 996 } 997 #endif 998 999 1000 #endif /* __STM32F1xx_HAL_ADC_H */ 1001
