1 /**
2 ******************************************************************************
3 * @file stm32f0xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL SYSTEM driver contains a set of generic APIs that can be
12 used by user:
13 (+) Some of the FLASH features need to be handled in the SYSTEM file.
14 (+) Access to DBGCMU registers
15 (+) Access to SYSCFG registers
16
17 @endverbatim
18 ******************************************************************************
19 * @attention
20 *
21 * Copyright (c) 2016 STMicroelectronics.
22 * All rights reserved.
23 *
24 * This software is licensed under terms that can be found in the LICENSE file
25 * in the root directory of this software component.
26 * If no LICENSE file comes with this software, it is provided AS-IS.
27 *
28 ******************************************************************************
29 */
30
31 /* Define to prevent recursive inclusion -------------------------------------*/
32 #ifndef __STM32F0xx_LL_SYSTEM_H
33 #define __STM32F0xx_LL_SYSTEM_H
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /* Includes ------------------------------------------------------------------*/
40 #include "stm32f0xx.h"
41
42 /** @addtogroup STM32F0xx_LL_Driver
43 * @{
44 */
45
46 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
47
48 /** @defgroup SYSTEM_LL SYSTEM
49 * @{
50 */
51
52 /* Private types -------------------------------------------------------------*/
53 /* Private variables ---------------------------------------------------------*/
54
55 /* Private constants ---------------------------------------------------------*/
56 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
57 * @{
58 */
59
60 /**
61 * @}
62 */
63
64 /* Private macros ------------------------------------------------------------*/
65
66 /* Exported types ------------------------------------------------------------*/
67 /* Exported constants --------------------------------------------------------*/
68 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
69 * @{
70 */
71
72 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG Remap
73 * @{
74 */
75 #define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000U /*!< Main Flash memory mapped at 0x00000000 */
76 #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */
77 #define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /*!< Embedded SRAM mapped at 0x00000000 */
78 /**
79 * @}
80 */
81
82 #if defined(SYSCFG_CFGR1_IR_MOD)
83 /** @defgroup SYSTEM_LL_EC_IR_MOD SYSCFG IR Modulation
84 * @{
85 */
86 #define LL_SYSCFG_IR_MOD_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /*!< Timer16 is selected as IR Modulation envelope source */
87 #define LL_SYSCFG_IR_MOD_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< USART1 is selected as IR Modulation envelope source */
88 #define LL_SYSCFG_IR_MOD_USART4 (SYSCFG_CFGR1_IR_MOD_1) /*!< USART4 is selected as IR Modulation envelope source */
89 /**
90 * @}
91 */
92
93 #endif /* SYSCFG_CFGR1_IR_MOD */
94
95 #if defined(SYSCFG_CFGR1_USART1TX_DMA_RMP) || defined(SYSCFG_CFGR1_USART1RX_DMA_RMP) || defined(SYSCFG_CFGR1_USART2_DMA_RMP) || defined(SYSCFG_CFGR1_USART3_DMA_RMP)
96 /** @defgroup SYSTEM_LL_EC_USART1TX_RMP SYSCFG USART DMA Remap
97 * @{
98 */
99 #if defined (SYSCFG_CFGR1_USART1TX_DMA_RMP)
100 #define LL_SYSCFG_USART1TX_RMP_DMA1CH2 ((SYSCFG_CFGR1_USART1TX_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< USART1_TX DMA request mapped on DMA channel 2U */
101 #define LL_SYSCFG_USART1TX_RMP_DMA1CH4 ((SYSCFG_CFGR1_USART1TX_DMA_RMP >> 8U) | SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1_TX DMA request mapped on DMA channel 4U */
102 #endif /*SYSCFG_CFGR1_USART1TX_DMA_RMP*/
103 #if defined (SYSCFG_CFGR1_USART1RX_DMA_RMP)
104 #define LL_SYSCFG_USART1RX_RMP_DMA1CH3 ((SYSCFG_CFGR1_USART1RX_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< USART1_RX DMA request mapped on DMA channel 3U */
105 #define LL_SYSCFG_USART1RX_RMP_DMA1CH5 ((SYSCFG_CFGR1_USART1RX_DMA_RMP >> 8U) | SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1_RX DMA request mapped on DMA channel 5 */
106 #endif /*SYSCFG_CFGR1_USART1RX_DMA_RMP*/
107 #if defined (SYSCFG_CFGR1_USART2_DMA_RMP)
108 #define LL_SYSCFG_USART2_RMP_DMA1CH54 ((SYSCFG_CFGR1_USART2_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4U respectively */
109 #define LL_SYSCFG_USART2_RMP_DMA1CH67 ((SYSCFG_CFGR1_USART2_DMA_RMP >> 8U) | SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively */
110 #endif /*SYSCFG_CFGR1_USART2_DMA_RMP*/
111 #if defined (SYSCFG_CFGR1_USART3_DMA_RMP)
112 #define LL_SYSCFG_USART3_RMP_DMA1CH67 ((SYSCFG_CFGR1_USART3_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively */
113 #define LL_SYSCFG_USART3_RMP_DMA1CH32 ((SYSCFG_CFGR1_USART3_DMA_RMP >> 8U) | SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3_RX and USART3_TX DMA requests mapped on DMA channel 3U and 2U respectively */
114 #endif /* SYSCFG_CFGR1_USART3_DMA_RMP */
115 /**
116 * @}
117 */
118 #endif /* SYSCFG_CFGR1_USART1TX_DMA_RMP || SYSCFG_CFGR1_USART1RX_DMA_RMP || SYSCFG_CFGR1_USART2_DMA_RMP || SYSCFG_CFGR1_USART3_DMA_RMP */
119
120 #if defined (SYSCFG_CFGR1_SPI2_DMA_RMP)
121 /** @defgroup SYSTEM_LL_EC_SPI2_RMP_DMA1 SYSCFG SPI2 DMA Remap
122 * @{
123 */
124 #define LL_SYSCFG_SPI2_RMP_DMA1_CH45 (uint32_t)0x00000000U /*!< SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4U and 5 respectively */
125 #define LL_SYSCFG_SPI2_RMP_DMA1_CH67 SYSCFG_CFGR1_SPI2_DMA_RMP /*!< SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively */
126 /**
127 * @}
128 */
129
130 #endif /*SYSCFG_CFGR1_SPI2_DMA_RMP*/
131
132 #if defined (SYSCFG_CFGR1_I2C1_DMA_RMP)
133 /** @defgroup SYSTEM_LL_EC_I2C1_RMP_DMA1 SYSCFG I2C1 DMA Remap
134 * @{
135 */
136 #define LL_SYSCFG_I2C1_RMP_DMA1_CH32 (uint32_t)0x00000000U /*!< I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3U and 2U respectively */
137 #define LL_SYSCFG_I2C1_RMP_DMA1_CH76 SYSCFG_CFGR1_I2C1_DMA_RMP /*!< I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively */
138 /**
139 * @}
140 */
141
142 #endif /*SYSCFG_CFGR1_I2C1_DMA_RMP*/
143
144 #if defined(SYSCFG_CFGR1_ADC_DMA_RMP)
145 /** @defgroup SYSTEM_LL_EC_ADC1_RMP_DMA1 SYSCFG ADC1 DMA Remap
146 * @{
147 */
148 #define LL_SYSCFG_ADC1_RMP_DMA1_CH1 (uint32_t)0x00000000U /*!< ADC DMA request mapped on DMA channel 1U */
149 #define LL_SYSCFG_ADC1_RMP_DMA1_CH2 SYSCFG_CFGR1_ADC_DMA_RMP /*!< ADC DMA request mapped on DMA channel 2U */
150 /**
151 * @}
152 */
153
154 #endif /* SYSCFG_CFGR1_ADC_DMA_RMP */
155
156 #if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) || defined(SYSCFG_CFGR1_TIM17_DMA_RMP) || defined(SYSCFG_CFGR1_TIM1_DMA_RMP) || defined(SYSCFG_CFGR1_TIM2_DMA_RMP) || defined(SYSCFG_CFGR1_TIM3_DMA_RMP)
157 /** @defgroup SYSTEM_LL_EC_TIM16_RMP_DMA1 SYSCFG TIM DMA Remap
158 * @{
159 */
160 #if defined(SYSCFG_CFGR1_TIM16_DMA_RMP)
161 #if defined (SYSCFG_CFGR1_TIM16_DMA_RMP2)
162 #define LL_SYSCFG_TIM16_RMP_DMA1_CH3 (((SYSCFG_CFGR1_TIM16_DMA_RMP | SYSCFG_CFGR1_TIM16_DMA_RMP2) >> 8U) | (uint32_t)0x00000000U) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 */
163 #define LL_SYSCFG_TIM16_RMP_DMA1_CH4 (((SYSCFG_CFGR1_TIM16_DMA_RMP | SYSCFG_CFGR1_TIM16_DMA_RMP2) >> 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 */
164 #define LL_SYSCFG_TIM16_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM16_DMA_RMP2 >> 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6 */
165 #else
166 #define LL_SYSCFG_TIM16_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM16_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 */
167 #define LL_SYSCFG_TIM16_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM16_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 */
168 #endif /* SYSCFG_CFGR1_TIM16_DMA_RMP2 */
169 #endif /* SYSCFG_CFGR1_TIM16_DMA_RMP */
170 #if defined(SYSCFG_CFGR1_TIM17_DMA_RMP)
171 #if defined (SYSCFG_CFGR1_TIM17_DMA_RMP2)
172 #define LL_SYSCFG_TIM17_RMP_DMA1_CH1 (((SYSCFG_CFGR1_TIM17_DMA_RMP | SYSCFG_CFGR1_TIM17_DMA_RMP2) >> 8U) | (uint32_t)0x00000000U) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 */
173 #define LL_SYSCFG_TIM17_RMP_DMA1_CH2 (((SYSCFG_CFGR1_TIM17_DMA_RMP | SYSCFG_CFGR1_TIM17_DMA_RMP2) >> 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 */
174 #define LL_SYSCFG_TIM17_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM17_DMA_RMP2 >> 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7 */
175 #else
176 #define LL_SYSCFG_TIM17_RMP_DMA1_CH1 ((SYSCFG_CFGR1_TIM17_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 */
177 #define LL_SYSCFG_TIM17_RMP_DMA1_CH2 ((SYSCFG_CFGR1_TIM17_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 */
178 #endif /* SYSCFG_CFGR1_TIM17_DMA_RMP2 */
179 #endif /* SYSCFG_CFGR1_TIM17_DMA_RMP */
180 #if defined (SYSCFG_CFGR1_TIM1_DMA_RMP)
181 #define LL_SYSCFG_TIM1_RMP_DMA1_CH234 ((SYSCFG_CFGR1_TIM1_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMAchannel 2, 3 and 4 respectively */
182 #define LL_SYSCFG_TIM1_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM1_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */
183 #endif /*SYSCFG_CFGR1_TIM1_DMA_RMP*/
184 #if defined (SYSCFG_CFGR1_TIM2_DMA_RMP)
185 #define LL_SYSCFG_TIM2_RMP_DMA1_CH34 ((SYSCFG_CFGR1_TIM2_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively */
186 #define LL_SYSCFG_TIM2_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM2_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */
187 #endif /*SYSCFG_CFGR1_TIM2_DMA_RMP*/
188 #if defined (SYSCFG_CFGR1_TIM3_DMA_RMP)
189 #define LL_SYSCFG_TIM3_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM3_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4 */
190 #define LL_SYSCFG_TIM3_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM3_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6 */
191 #endif /*SYSCFG_CFGR1_TIM3_DMA_RMP*/
192 /**
193 * @}
194 */
195
196 #endif /* SYSCFG_CFGR1_TIM16_DMA_RMP || SYSCFG_CFGR1_TIM17_DMA_RMP || SYSCFG_CFGR1_TIM1_DMA_RMP || SYSCFG_CFGR1_TIM2_DMA_RMP || SYSCFG_CFGR1_TIM3_DMA_RMP */
197
198 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
199 * @{
200 */
201 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< I2C PB6 Fast mode plus */
202 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< I2C PB7 Fast mode plus */
203 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< I2C PB8 Fast mode plus */
204 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< I2C PB9 Fast mode plus */
205 #if defined(SYSCFG_CFGR1_I2C_FMP_I2C1)
206 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
207 #endif /*SYSCFG_CFGR1_I2C_FMP_I2C1*/
208 #if defined(SYSCFG_CFGR1_I2C_FMP_I2C2)
209 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /*!< Enable I2C2 Fast mode plus */
210 #endif /*SYSCFG_CFGR1_I2C_FMP_I2C2*/
211 #if defined(SYSCFG_CFGR1_I2C_FMP_PA9)
212 #define LL_SYSCFG_I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast Mode Plus on PA9 */
213 #endif /*SYSCFG_CFGR1_I2C_FMP_PA9*/
214 #if defined(SYSCFG_CFGR1_I2C_FMP_PA10)
215 #define LL_SYSCFG_I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast Mode Plus on PA10 */
216 #endif /*SYSCFG_CFGR1_I2C_FMP_PA10*/
217 /**
218 * @}
219 */
220
221 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
222 * @{
223 */
224 #define LL_SYSCFG_EXTI_PORTA (uint32_t)0U /*!< EXTI PORT A */
225 #define LL_SYSCFG_EXTI_PORTB (uint32_t)1U /*!< EXTI PORT B */
226 #define LL_SYSCFG_EXTI_PORTC (uint32_t)2U /*!< EXTI PORT C */
227 #if defined(GPIOD_BASE)
228 #define LL_SYSCFG_EXTI_PORTD (uint32_t)3U /*!< EXTI PORT D */
229 #endif /*GPIOD_BASE*/
230 #if defined(GPIOE_BASE)
231 #define LL_SYSCFG_EXTI_PORTE (uint32_t)4U /*!< EXTI PORT E */
232 #endif /*GPIOE_BASE*/
233 #define LL_SYSCFG_EXTI_PORTF (uint32_t)5U /*!< EXTI PORT F */
234 /**
235 * @}
236 */
237
238 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
239 * @{
240 */
241 #define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0U << 16U | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */
242 #define LL_SYSCFG_EXTI_LINE1 (uint32_t)(4U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */
243 #define LL_SYSCFG_EXTI_LINE2 (uint32_t)(8U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */
244 #define LL_SYSCFG_EXTI_LINE3 (uint32_t)(12U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */
245 #define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0U << 16U | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */
246 #define LL_SYSCFG_EXTI_LINE5 (uint32_t)(4U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */
247 #define LL_SYSCFG_EXTI_LINE6 (uint32_t)(8U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */
248 #define LL_SYSCFG_EXTI_LINE7 (uint32_t)(12U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */
249 #define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0U << 16U | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */
250 #define LL_SYSCFG_EXTI_LINE9 (uint32_t)(4U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */
251 #define LL_SYSCFG_EXTI_LINE10 (uint32_t)(8U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */
252 #define LL_SYSCFG_EXTI_LINE11 (uint32_t)(12U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */
253 #define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0U << 16U | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */
254 #define LL_SYSCFG_EXTI_LINE13 (uint32_t)(4U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */
255 #define LL_SYSCFG_EXTI_LINE14 (uint32_t)(8U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */
256 #define LL_SYSCFG_EXTI_LINE15 (uint32_t)(12U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */
257 /**
258 * @}
259 */
260
261 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
262 * @{
263 */
264 #if defined(SYSCFG_CFGR2_PVD_LOCK)
265 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection
266 with TIM1/15/16U/17 Break Input and also
267 the PVDE and PLS bits of the Power Control Interface */
268 #endif /*SYSCFG_CFGR2_PVD_LOCK*/
269 #define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Enables and locks the SRAM_PARITY error signal
270 with Break Input of TIM1/15/16/17 */
271 #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP (Hardfault) output of
272 CortexM0 with Break Input of TIM1/15/16/17 */
273 /**
274 * @}
275 */
276
277 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
278 * @{
279 */
280 #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
281 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
282 #endif /*DBGMCU_APB1_FZ_DBG_TIM2_STOP*/
283 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
284 #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
285 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
286 #endif /*DBGMCU_APB1_FZ_DBG_TIM6_STOP*/
287 #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
288 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
289 #endif /*DBGMCU_APB1_FZ_DBG_TIM7_STOP*/
290 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
291 #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC Calendar frozen when core is halted */
292 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
293 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
294 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
295 #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
296 #define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP /*!< CAN debug stopped when Core is halted */
297 #endif /*DBGMCU_APB1_FZ_DBG_CAN_STOP*/
298 /**
299 * @}
300 */
301
302 /** @defgroup SYSTEM_LL_EC_APB1 GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
303 * @{
304 */
305 #define LL_DBGMCU_APB1_GRP2_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
306 #if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
307 #define LL_DBGMCU_APB1_GRP2_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */
308 #endif /*DBGMCU_APB2_FZ_DBG_TIM15_STOP*/
309 #define LL_DBGMCU_APB1_GRP2_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */
310 #define LL_DBGMCU_APB1_GRP2_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */
311 /**
312 * @}
313 */
314
315 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
316 * @{
317 */
318 #define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
319 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */
320 /**
321 * @}
322 */
323
324 /**
325 * @}
326 */
327
328 /* Exported macro ------------------------------------------------------------*/
329
330 /* Exported functions --------------------------------------------------------*/
331 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
332 * @{
333 */
334
335 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
336 * @{
337 */
338
339 /**
340 * @brief Set memory mapping at address 0x00000000
341 * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory
342 * @param Memory This parameter can be one of the following values:
343 * @arg @ref LL_SYSCFG_REMAP_FLASH
344 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
345 * @arg @ref LL_SYSCFG_REMAP_SRAM
346 * @retval None
347 */
LL_SYSCFG_SetRemapMemory(uint32_t Memory)348 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
349 {
350 MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory);
351 }
352
353 /**
354 * @brief Get memory mapping at address 0x00000000
355 * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory
356 * @retval Returned value can be one of the following values:
357 * @arg @ref LL_SYSCFG_REMAP_FLASH
358 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
359 * @arg @ref LL_SYSCFG_REMAP_SRAM
360 */
LL_SYSCFG_GetRemapMemory(void)361 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
362 {
363 return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE));
364 }
365
366 #if defined(SYSCFG_CFGR1_IR_MOD)
367 /**
368 * @brief Set IR Modulation Envelope signal source.
369 * @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_SetIRModEnvelopeSignal
370 * @param Source This parameter can be one of the following values:
371 * @arg @ref LL_SYSCFG_IR_MOD_TIM16
372 * @arg @ref LL_SYSCFG_IR_MOD_USART1
373 * @arg @ref LL_SYSCFG_IR_MOD_USART4
374 * @retval None
375 */
LL_SYSCFG_SetIRModEnvelopeSignal(uint32_t Source)376 __STATIC_INLINE void LL_SYSCFG_SetIRModEnvelopeSignal(uint32_t Source)
377 {
378 MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD, Source);
379 }
380
381 /**
382 * @brief Get IR Modulation Envelope signal source.
383 * @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_GetIRModEnvelopeSignal
384 * @retval Returned value can be one of the following values:
385 * @arg @ref LL_SYSCFG_IR_MOD_TIM16
386 * @arg @ref LL_SYSCFG_IR_MOD_USART1
387 * @arg @ref LL_SYSCFG_IR_MOD_USART4
388 */
LL_SYSCFG_GetIRModEnvelopeSignal(void)389 __STATIC_INLINE uint32_t LL_SYSCFG_GetIRModEnvelopeSignal(void)
390 {
391 return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD));
392 }
393 #endif /* SYSCFG_CFGR1_IR_MOD */
394
395 #if defined(SYSCFG_CFGR1_USART1TX_DMA_RMP) || defined(SYSCFG_CFGR1_USART1RX_DMA_RMP) || defined(SYSCFG_CFGR1_USART2_DMA_RMP) || defined(SYSCFG_CFGR1_USART3_DMA_RMP)
396 /**
397 * @brief Set DMA request remapping bits for USART
398 * @rmtoll SYSCFG_CFGR1 USART1TX_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n
399 * SYSCFG_CFGR1 USART1RX_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n
400 * SYSCFG_CFGR1 USART2_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n
401 * SYSCFG_CFGR1 USART3_DMA_RMP LL_SYSCFG_SetRemapDMA_USART
402 * @param Remap This parameter can be one of the following values:
403 * @arg @ref LL_SYSCFG_USART1TX_RMP_DMA1CH2 (*)
404 * @arg @ref LL_SYSCFG_USART1TX_RMP_DMA1CH4 (*)
405 * @arg @ref LL_SYSCFG_USART1RX_RMP_DMA1CH3 (*)
406 * @arg @ref LL_SYSCFG_USART1RX_RMP_DMA1CH5 (*)
407 * @arg @ref LL_SYSCFG_USART2_RMP_DMA1CH54 (*)
408 * @arg @ref LL_SYSCFG_USART2_RMP_DMA1CH67 (*)
409 * @arg @ref LL_SYSCFG_USART3_RMP_DMA1CH67 (*)
410 * @arg @ref LL_SYSCFG_USART3_RMP_DMA1CH32 (*)
411 *
412 * (*) value not defined in all devices.
413 * @retval None
414 */
LL_SYSCFG_SetRemapDMA_USART(uint32_t Remap)415 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_USART(uint32_t Remap)
416 {
417 MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF00FFU) << 8U, (Remap & 0xFF00FF00U));
418 }
419 #endif /* SYSCFG_CFGR1_USART1TX_DMA_RMP || SYSCFG_CFGR1_USART1RX_DMA_RMP || SYSCFG_CFGR1_USART2_DMA_RMP || SYSCFG_CFGR1_USART3_DMA_RMP */
420
421 #if defined(SYSCFG_CFGR1_SPI2_DMA_RMP)
422 /**
423 * @brief Set DMA request remapping bits for SPI
424 * @rmtoll SYSCFG_CFGR1 SPI2_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI
425 * @param Remap This parameter can be one of the following values:
426 * @arg @ref LL_SYSCFG_SPI2_RMP_DMA1_CH45
427 * @arg @ref LL_SYSCFG_SPI2_RMP_DMA1_CH67
428 * @retval None
429 */
LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap)430 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap)
431 {
432 MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_SPI2_DMA_RMP, Remap);
433 }
434 #endif /* SYSCFG_CFGR1_SPI2_DMA_RMP */
435
436 #if defined(SYSCFG_CFGR1_I2C1_DMA_RMP)
437 /**
438 * @brief Set DMA request remapping bits for I2C
439 * @rmtoll SYSCFG_CFGR1 I2C1_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C
440 * @param Remap This parameter can be one of the following values:
441 * @arg @ref LL_SYSCFG_I2C1_RMP_DMA1_CH32
442 * @arg @ref LL_SYSCFG_I2C1_RMP_DMA1_CH76
443 * @retval None
444 */
LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap)445 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap)
446 {
447 MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_I2C1_DMA_RMP, Remap);
448 }
449 #endif /* SYSCFG_CFGR1_I2C1_DMA_RMP */
450
451 #if defined(SYSCFG_CFGR1_ADC_DMA_RMP)
452 /**
453 * @brief Set DMA request remapping bits for ADC
454 * @rmtoll SYSCFG_CFGR1 ADC_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC
455 * @param Remap This parameter can be one of the following values:
456 * @arg @ref LL_SYSCFG_ADC1_RMP_DMA1_CH1
457 * @arg @ref LL_SYSCFG_ADC1_RMP_DMA1_CH2
458 * @retval None
459 */
LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap)460 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap)
461 {
462 MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_ADC_DMA_RMP, Remap);
463 }
464 #endif /* SYSCFG_CFGR1_ADC_DMA_RMP */
465
466 #if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) || defined(SYSCFG_CFGR1_TIM17_DMA_RMP) || defined(SYSCFG_CFGR1_TIM1_DMA_RMP) || defined(SYSCFG_CFGR1_TIM2_DMA_RMP) || defined(SYSCFG_CFGR1_TIM3_DMA_RMP)
467 /**
468 * @brief Set DMA request remapping bits for TIM
469 * @rmtoll SYSCFG_CFGR1 TIM16_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
470 * SYSCFG_CFGR1 TIM17_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
471 * SYSCFG_CFGR1 TIM16_DMA_RMP2 LL_SYSCFG_SetRemapDMA_TIM\n
472 * SYSCFG_CFGR1 TIM17_DMA_RMP2 LL_SYSCFG_SetRemapDMA_TIM\n
473 * SYSCFG_CFGR1 TIM1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
474 * SYSCFG_CFGR1 TIM2_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
475 * SYSCFG_CFGR1 TIM3_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM
476 * @param Remap This parameter can be one of the following values:
477 * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH3 (*)
478 * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH4 (*)
479 * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH6 (*)
480 * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH1 (*)
481 * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH2 (*)
482 * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH7 (*)
483 * @arg @ref LL_SYSCFG_TIM1_RMP_DMA1_CH234 (*)
484 * @arg @ref LL_SYSCFG_TIM1_RMP_DMA1_CH6 (*)
485 * @arg @ref LL_SYSCFG_TIM2_RMP_DMA1_CH34 (*)
486 * @arg @ref LL_SYSCFG_TIM2_RMP_DMA1_CH7 (*)
487 * @arg @ref LL_SYSCFG_TIM3_RMP_DMA1_CH4 (*)
488 * @arg @ref LL_SYSCFG_TIM3_RMP_DMA1_CH6 (*)
489 *
490 * (*) value not defined in all devices.
491 * @retval None
492 */
LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap)493 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap)
494 {
495 MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF00FFU) << 8U, (Remap & 0xFF00FF00U));
496 }
497 #endif /* SYSCFG_CFGR1_TIM16_DMA_RMP || SYSCFG_CFGR1_TIM17_DMA_RMP || SYSCFG_CFGR1_TIM1_DMA_RMP || SYSCFG_CFGR1_TIM2_DMA_RMP || SYSCFG_CFGR1_TIM3_DMA_RMP */
498
499 #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
500 /**
501 * @brief Enable PIN pair PA11/12 mapped instead of PA9/10 (control the mapping of either
502 * PA9/10 or PA11/12 pin pair on small pin-count packages)
503 * @rmtoll SYSCFG_CFGR1 PA11_PA12_RMP LL_SYSCFG_EnablePinRemap
504 * @retval None
505 */
LL_SYSCFG_EnablePinRemap(void)506 __STATIC_INLINE void LL_SYSCFG_EnablePinRemap(void)
507 {
508 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_PA11_PA12_RMP);
509 }
510
511 /**
512 * @brief Disable PIN pair PA11/12 mapped instead of PA9/10 (control the mapping of either
513 * PA9/10 or PA11/12 pin pair on small pin-count packages)
514 * @rmtoll SYSCFG_CFGR1 PA11_PA12_RMP LL_SYSCFG_DisablePinRemap
515 * @retval None
516 */
LL_SYSCFG_DisablePinRemap(void)517 __STATIC_INLINE void LL_SYSCFG_DisablePinRemap(void)
518 {
519 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_PA11_PA12_RMP);
520 }
521 #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
522
523 /**
524 * @brief Enable the I2C fast mode plus driving capability.
525 * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_EnableFastModePlus\n
526 * SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_EnableFastModePlus\n
527 * SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_EnableFastModePlus\n
528 * SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_EnableFastModePlus\n
529 * SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_EnableFastModePlus\n
530 * SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_EnableFastModePlus\n
531 * SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_EnableFastModePlus\n
532 * SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_EnableFastModePlus
533 * @param ConfigFastModePlus This parameter can be a combination of the following values:
534 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
535 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
536 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
537 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
538 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*)
539 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
540 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*)
541 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*)
542 *
543 * (*) value not defined in all devices
544 * @retval None
545 */
LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)546 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
547 {
548 SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
549 }
550
551 /**
552 * @brief Disable the I2C fast mode plus driving capability.
553 * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_DisableFastModePlus\n
554 * SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_DisableFastModePlus\n
555 * SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_DisableFastModePlus\n
556 * SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_DisableFastModePlus\n
557 * SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_DisableFastModePlus\n
558 * SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_DisableFastModePlus\n
559 * SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_DisableFastModePlus\n
560 * SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_DisableFastModePlus
561 * @param ConfigFastModePlus This parameter can be a combination of the following values:
562 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
563 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
564 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
565 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
566 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*)
567 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
568 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*)
569 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*)
570 *
571 * (*) value not defined in all devices
572 * @retval None
573 */
LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)574 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
575 {
576 CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
577 }
578
579 /**
580 * @brief Configure source input for the EXTI external interrupt.
581 * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n
582 * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n
583 * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n
584 * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n
585 * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n
586 * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n
587 * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n
588 * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n
589 * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n
590 * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n
591 * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n
592 * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n
593 * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n
594 * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n
595 * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n
596 * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource
597 * @param Port This parameter can be one of the following values:
598 * @arg @ref LL_SYSCFG_EXTI_PORTA
599 * @arg @ref LL_SYSCFG_EXTI_PORTB
600 * @arg @ref LL_SYSCFG_EXTI_PORTC
601 * @arg @ref LL_SYSCFG_EXTI_PORTD (*)
602 * @arg @ref LL_SYSCFG_EXTI_PORTE (*)
603 * @arg @ref LL_SYSCFG_EXTI_PORTF
604 *
605 * (*) value not defined in all devices
606 * @param Line This parameter can be one of the following values:
607 * @arg @ref LL_SYSCFG_EXTI_LINE0
608 * @arg @ref LL_SYSCFG_EXTI_LINE1
609 * @arg @ref LL_SYSCFG_EXTI_LINE2
610 * @arg @ref LL_SYSCFG_EXTI_LINE3
611 * @arg @ref LL_SYSCFG_EXTI_LINE4
612 * @arg @ref LL_SYSCFG_EXTI_LINE5
613 * @arg @ref LL_SYSCFG_EXTI_LINE6
614 * @arg @ref LL_SYSCFG_EXTI_LINE7
615 * @arg @ref LL_SYSCFG_EXTI_LINE8
616 * @arg @ref LL_SYSCFG_EXTI_LINE9
617 * @arg @ref LL_SYSCFG_EXTI_LINE10
618 * @arg @ref LL_SYSCFG_EXTI_LINE11
619 * @arg @ref LL_SYSCFG_EXTI_LINE12
620 * @arg @ref LL_SYSCFG_EXTI_LINE13
621 * @arg @ref LL_SYSCFG_EXTI_LINE14
622 * @arg @ref LL_SYSCFG_EXTI_LINE15
623 * @retval None
624 */
LL_SYSCFG_SetEXTISource(uint32_t Port,uint32_t Line)625 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
626 {
627 MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], SYSCFG_EXTICR1_EXTI0 << (Line >> 16), Port << (Line >> 16));
628 }
629
630 /**
631 * @brief Get the configured defined for specific EXTI Line
632 * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n
633 * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n
634 * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n
635 * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n
636 * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n
637 * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n
638 * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n
639 * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n
640 * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n
641 * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n
642 * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n
643 * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n
644 * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n
645 * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n
646 * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n
647 * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource
648 * @param Line This parameter can be one of the following values:
649 * @arg @ref LL_SYSCFG_EXTI_LINE0
650 * @arg @ref LL_SYSCFG_EXTI_LINE1
651 * @arg @ref LL_SYSCFG_EXTI_LINE2
652 * @arg @ref LL_SYSCFG_EXTI_LINE3
653 * @arg @ref LL_SYSCFG_EXTI_LINE4
654 * @arg @ref LL_SYSCFG_EXTI_LINE5
655 * @arg @ref LL_SYSCFG_EXTI_LINE6
656 * @arg @ref LL_SYSCFG_EXTI_LINE7
657 * @arg @ref LL_SYSCFG_EXTI_LINE8
658 * @arg @ref LL_SYSCFG_EXTI_LINE9
659 * @arg @ref LL_SYSCFG_EXTI_LINE10
660 * @arg @ref LL_SYSCFG_EXTI_LINE11
661 * @arg @ref LL_SYSCFG_EXTI_LINE12
662 * @arg @ref LL_SYSCFG_EXTI_LINE13
663 * @arg @ref LL_SYSCFG_EXTI_LINE14
664 * @arg @ref LL_SYSCFG_EXTI_LINE15
665 * @retval Returned value can be one of the following values:
666 * @arg @ref LL_SYSCFG_EXTI_PORTA
667 * @arg @ref LL_SYSCFG_EXTI_PORTB
668 * @arg @ref LL_SYSCFG_EXTI_PORTC
669 * @arg @ref LL_SYSCFG_EXTI_PORTD (*)
670 * @arg @ref LL_SYSCFG_EXTI_PORTE (*)
671 * @arg @ref LL_SYSCFG_EXTI_PORTF
672 *
673 * (*) value not defined in all devices
674 */
LL_SYSCFG_GetEXTISource(uint32_t Line)675 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
676 {
677 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (SYSCFG_EXTICR1_EXTI0 << (Line >> 16))) >> (Line >> 16));
678 }
679
680 #if defined(SYSCFG_ITLINE0_SR_EWDG)
681 /**
682 * @brief Check if Window watchdog interrupt occurred or not.
683 * @rmtoll SYSCFG_ITLINE0 SR_EWDG LL_SYSCFG_IsActiveFlag_WWDG
684 * @retval State of bit (1 or 0).
685 */
LL_SYSCFG_IsActiveFlag_WWDG(void)686 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_WWDG(void)
687 {
688 return (READ_BIT(SYSCFG->IT_LINE_SR[0], SYSCFG_ITLINE0_SR_EWDG) == (SYSCFG_ITLINE0_SR_EWDG));
689 }
690 #endif /* SYSCFG_ITLINE0_SR_EWDG */
691
692 #if defined(SYSCFG_ITLINE1_SR_PVDOUT)
693 /**
694 * @brief Check if PVD supply monitoring interrupt occurred or not (EXTI line 16).
695 * @rmtoll SYSCFG_ITLINE1 SR_PVDOUT LL_SYSCFG_IsActiveFlag_PVDOUT
696 * @retval State of bit (1 or 0).
697 */
LL_SYSCFG_IsActiveFlag_PVDOUT(void)698 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_PVDOUT(void)
699 {
700 return (READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_PVDOUT) == (SYSCFG_ITLINE1_SR_PVDOUT));
701 }
702 #endif /* SYSCFG_ITLINE1_SR_PVDOUT */
703
704 #if defined(SYSCFG_ITLINE1_SR_VDDIO2)
705 /**
706 * @brief Check if VDDIO2 supply monitoring interrupt occurred or not (EXTI line 31).
707 * @rmtoll SYSCFG_ITLINE1 SR_VDDIO2 LL_SYSCFG_IsActiveFlag_VDDIO2
708 * @retval State of bit (1 or 0).
709 */
LL_SYSCFG_IsActiveFlag_VDDIO2(void)710 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VDDIO2(void)
711 {
712 return (READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_VDDIO2) == (SYSCFG_ITLINE1_SR_VDDIO2));
713 }
714 #endif /* SYSCFG_ITLINE1_SR_VDDIO2 */
715
716 #if defined(SYSCFG_ITLINE2_SR_RTC_WAKEUP)
717 /**
718 * @brief Check if RTC Wake Up interrupt occurred or not (EXTI line 20).
719 * @rmtoll SYSCFG_ITLINE2 SR_RTC_WAKEUP LL_SYSCFG_IsActiveFlag_RTC_WAKEUP
720 * @retval State of bit (1 or 0).
721 */
LL_SYSCFG_IsActiveFlag_RTC_WAKEUP(void)722 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_WAKEUP(void)
723 {
724 return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_WAKEUP) == (SYSCFG_ITLINE2_SR_RTC_WAKEUP));
725 }
726 #endif /* SYSCFG_ITLINE2_SR_RTC_WAKEUP */
727
728 #if defined(SYSCFG_ITLINE2_SR_RTC_TSTAMP)
729 /**
730 * @brief Check if RTC Tamper and TimeStamp interrupt occurred or not (EXTI line 19).
731 * @rmtoll SYSCFG_ITLINE2 SR_RTC_TSTAMP LL_SYSCFG_IsActiveFlag_RTC_TSTAMP
732 * @retval State of bit (1 or 0).
733 */
LL_SYSCFG_IsActiveFlag_RTC_TSTAMP(void)734 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_TSTAMP(void)
735 {
736 return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_TSTAMP) == (SYSCFG_ITLINE2_SR_RTC_TSTAMP));
737 }
738 #endif /* SYSCFG_ITLINE2_SR_RTC_TSTAMP */
739
740 #if defined(SYSCFG_ITLINE2_SR_RTC_ALRA)
741 /**
742 * @brief Check if RTC Alarm interrupt occurred or not (EXTI line 17).
743 * @rmtoll SYSCFG_ITLINE2 SR_RTC_ALRA LL_SYSCFG_IsActiveFlag_RTC_ALRA
744 * @retval State of bit (1 or 0).
745 */
LL_SYSCFG_IsActiveFlag_RTC_ALRA(void)746 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_ALRA(void)
747 {
748 return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_ALRA) == (SYSCFG_ITLINE2_SR_RTC_ALRA));
749 }
750 #endif /* SYSCFG_ITLINE2_SR_RTC_ALRA */
751
752 #if defined(SYSCFG_ITLINE3_SR_FLASH_ITF)
753 /**
754 * @brief Check if Flash interface interrupt occurred or not.
755 * @rmtoll SYSCFG_ITLINE3 SR_FLASH_ITF LL_SYSCFG_IsActiveFlag_FLASH_ITF
756 * @retval State of bit (1 or 0).
757 */
LL_SYSCFG_IsActiveFlag_FLASH_ITF(void)758 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FLASH_ITF(void)
759 {
760 return (READ_BIT(SYSCFG->IT_LINE_SR[3], SYSCFG_ITLINE3_SR_FLASH_ITF) == (SYSCFG_ITLINE3_SR_FLASH_ITF));
761 }
762 #endif /* SYSCFG_ITLINE3_SR_FLASH_ITF */
763
764 #if defined(SYSCFG_ITLINE4_SR_CRS)
765 /**
766 * @brief Check if Clock recovery system interrupt occurred or not.
767 * @rmtoll SYSCFG_ITLINE4 SR_CRS LL_SYSCFG_IsActiveFlag_CRS
768 * @retval State of bit (1 or 0).
769 */
LL_SYSCFG_IsActiveFlag_CRS(void)770 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CRS(void)
771 {
772 return (READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CRS) == (SYSCFG_ITLINE4_SR_CRS));
773 }
774 #endif /* SYSCFG_ITLINE4_SR_CRS */
775
776 #if defined(SYSCFG_ITLINE4_SR_CLK_CTRL)
777 /**
778 * @brief Check if Reset and clock control interrupt occurred or not.
779 * @rmtoll SYSCFG_ITLINE4 SR_CLK_CTRL LL_SYSCFG_IsActiveFlag_CLK_CTRL
780 * @retval State of bit (1 or 0).
781 */
LL_SYSCFG_IsActiveFlag_CLK_CTRL(void)782 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CLK_CTRL(void)
783 {
784 return (READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CLK_CTRL) == (SYSCFG_ITLINE4_SR_CLK_CTRL));
785 }
786 #endif /* SYSCFG_ITLINE4_SR_CLK_CTRL */
787
788 #if defined(SYSCFG_ITLINE5_SR_EXTI0)
789 /**
790 * @brief Check if EXTI line 0 interrupt occurred or not.
791 * @rmtoll SYSCFG_ITLINE5 SR_EXTI0 LL_SYSCFG_IsActiveFlag_EXTI0
792 * @retval State of bit (1 or 0).
793 */
LL_SYSCFG_IsActiveFlag_EXTI0(void)794 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI0(void)
795 {
796 return (READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI0) == (SYSCFG_ITLINE5_SR_EXTI0));
797 }
798 #endif /* SYSCFG_ITLINE5_SR_EXTI0 */
799
800 #if defined(SYSCFG_ITLINE5_SR_EXTI1)
801 /**
802 * @brief Check if EXTI line 1 interrupt occurred or not.
803 * @rmtoll SYSCFG_ITLINE5 SR_EXTI1 LL_SYSCFG_IsActiveFlag_EXTI1
804 * @retval State of bit (1 or 0).
805 */
LL_SYSCFG_IsActiveFlag_EXTI1(void)806 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI1(void)
807 {
808 return (READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI1) == (SYSCFG_ITLINE5_SR_EXTI1));
809 }
810 #endif /* SYSCFG_ITLINE5_SR_EXTI1 */
811
812 #if defined(SYSCFG_ITLINE6_SR_EXTI2)
813 /**
814 * @brief Check if EXTI line 2 interrupt occurred or not.
815 * @rmtoll SYSCFG_ITLINE6 SR_EXTI2 LL_SYSCFG_IsActiveFlag_EXTI2
816 * @retval State of bit (1 or 0).
817 */
LL_SYSCFG_IsActiveFlag_EXTI2(void)818 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI2(void)
819 {
820 return (READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI2) == (SYSCFG_ITLINE6_SR_EXTI2));
821 }
822 #endif /* SYSCFG_ITLINE6_SR_EXTI2 */
823
824 #if defined(SYSCFG_ITLINE6_SR_EXTI3)
825 /**
826 * @brief Check if EXTI line 3 interrupt occurred or not.
827 * @rmtoll SYSCFG_ITLINE6 SR_EXTI3 LL_SYSCFG_IsActiveFlag_EXTI3
828 * @retval State of bit (1 or 0).
829 */
LL_SYSCFG_IsActiveFlag_EXTI3(void)830 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI3(void)
831 {
832 return (READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI3) == (SYSCFG_ITLINE6_SR_EXTI3));
833 }
834 #endif /* SYSCFG_ITLINE6_SR_EXTI3 */
835
836 #if defined(SYSCFG_ITLINE7_SR_EXTI4)
837 /**
838 * @brief Check if EXTI line 4 interrupt occurred or not.
839 * @rmtoll SYSCFG_ITLINE7 SR_EXTI4 LL_SYSCFG_IsActiveFlag_EXTI4
840 * @retval State of bit (1 or 0).
841 */
LL_SYSCFG_IsActiveFlag_EXTI4(void)842 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI4(void)
843 {
844 return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI4) == (SYSCFG_ITLINE7_SR_EXTI4));
845 }
846 #endif /* SYSCFG_ITLINE7_SR_EXTI4 */
847
848 #if defined(SYSCFG_ITLINE7_SR_EXTI5)
849 /**
850 * @brief Check if EXTI line 5 interrupt occurred or not.
851 * @rmtoll SYSCFG_ITLINE7 SR_EXTI5 LL_SYSCFG_IsActiveFlag_EXTI5
852 * @retval State of bit (1 or 0).
853 */
LL_SYSCFG_IsActiveFlag_EXTI5(void)854 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI5(void)
855 {
856 return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI5) == (SYSCFG_ITLINE7_SR_EXTI5));
857 }
858 #endif /* SYSCFG_ITLINE7_SR_EXTI5 */
859
860 #if defined(SYSCFG_ITLINE7_SR_EXTI6)
861 /**
862 * @brief Check if EXTI line 6 interrupt occurred or not.
863 * @rmtoll SYSCFG_ITLINE7 SR_EXTI6 LL_SYSCFG_IsActiveFlag_EXTI6
864 * @retval State of bit (1 or 0).
865 */
LL_SYSCFG_IsActiveFlag_EXTI6(void)866 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI6(void)
867 {
868 return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI6) == (SYSCFG_ITLINE7_SR_EXTI6));
869 }
870 #endif /* SYSCFG_ITLINE7_SR_EXTI6 */
871
872 #if defined(SYSCFG_ITLINE7_SR_EXTI7)
873 /**
874 * @brief Check if EXTI line 7 interrupt occurred or not.
875 * @rmtoll SYSCFG_ITLINE7 SR_EXTI7 LL_SYSCFG_IsActiveFlag_EXTI7
876 * @retval State of bit (1 or 0).
877 */
LL_SYSCFG_IsActiveFlag_EXTI7(void)878 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI7(void)
879 {
880 return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI7) == (SYSCFG_ITLINE7_SR_EXTI7));
881 }
882 #endif /* SYSCFG_ITLINE7_SR_EXTI7 */
883
884 #if defined(SYSCFG_ITLINE7_SR_EXTI8)
885 /**
886 * @brief Check if EXTI line 8 interrupt occurred or not.
887 * @rmtoll SYSCFG_ITLINE7 SR_EXTI8 LL_SYSCFG_IsActiveFlag_EXTI8
888 * @retval State of bit (1 or 0).
889 */
LL_SYSCFG_IsActiveFlag_EXTI8(void)890 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI8(void)
891 {
892 return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI8) == (SYSCFG_ITLINE7_SR_EXTI8));
893 }
894 #endif /* SYSCFG_ITLINE7_SR_EXTI8 */
895
896 #if defined(SYSCFG_ITLINE7_SR_EXTI9)
897 /**
898 * @brief Check if EXTI line 9 interrupt occurred or not.
899 * @rmtoll SYSCFG_ITLINE7 SR_EXTI9 LL_SYSCFG_IsActiveFlag_EXTI9
900 * @retval State of bit (1 or 0).
901 */
LL_SYSCFG_IsActiveFlag_EXTI9(void)902 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI9(void)
903 {
904 return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI9) == (SYSCFG_ITLINE7_SR_EXTI9));
905 }
906 #endif /* SYSCFG_ITLINE7_SR_EXTI9 */
907
908 #if defined(SYSCFG_ITLINE7_SR_EXTI10)
909 /**
910 * @brief Check if EXTI line 10 interrupt occurred or not.
911 * @rmtoll SYSCFG_ITLINE7 SR_EXTI10 LL_SYSCFG_IsActiveFlag_EXTI10
912 * @retval State of bit (1 or 0).
913 */
LL_SYSCFG_IsActiveFlag_EXTI10(void)914 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI10(void)
915 {
916 return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI10) == (SYSCFG_ITLINE7_SR_EXTI10));
917 }
918 #endif /* SYSCFG_ITLINE7_SR_EXTI10 */
919
920 #if defined(SYSCFG_ITLINE7_SR_EXTI11)
921 /**
922 * @brief Check if EXTI line 11 interrupt occurred or not.
923 * @rmtoll SYSCFG_ITLINE7 SR_EXTI11 LL_SYSCFG_IsActiveFlag_EXTI11
924 * @retval State of bit (1 or 0).
925 */
LL_SYSCFG_IsActiveFlag_EXTI11(void)926 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI11(void)
927 {
928 return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI11) == (SYSCFG_ITLINE7_SR_EXTI11));
929 }
930 #endif /* SYSCFG_ITLINE7_SR_EXTI11 */
931
932 #if defined(SYSCFG_ITLINE7_SR_EXTI12)
933 /**
934 * @brief Check if EXTI line 12 interrupt occurred or not.
935 * @rmtoll SYSCFG_ITLINE7 SR_EXTI12 LL_SYSCFG_IsActiveFlag_EXTI12
936 * @retval State of bit (1 or 0).
937 */
LL_SYSCFG_IsActiveFlag_EXTI12(void)938 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI12(void)
939 {
940 return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI12) == (SYSCFG_ITLINE7_SR_EXTI12));
941 }
942 #endif /* SYSCFG_ITLINE7_SR_EXTI12 */
943
944 #if defined(SYSCFG_ITLINE7_SR_EXTI13)
945 /**
946 * @brief Check if EXTI line 13 interrupt occurred or not.
947 * @rmtoll SYSCFG_ITLINE7 SR_EXTI13 LL_SYSCFG_IsActiveFlag_EXTI13
948 * @retval State of bit (1 or 0).
949 */
LL_SYSCFG_IsActiveFlag_EXTI13(void)950 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI13(void)
951 {
952 return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI13) == (SYSCFG_ITLINE7_SR_EXTI13));
953 }
954 #endif /* SYSCFG_ITLINE7_SR_EXTI13 */
955
956 #if defined(SYSCFG_ITLINE7_SR_EXTI14)
957 /**
958 * @brief Check if EXTI line 14 interrupt occurred or not.
959 * @rmtoll SYSCFG_ITLINE7 SR_EXTI14 LL_SYSCFG_IsActiveFlag_EXTI14
960 * @retval State of bit (1 or 0).
961 */
LL_SYSCFG_IsActiveFlag_EXTI14(void)962 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI14(void)
963 {
964 return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI14) == (SYSCFG_ITLINE7_SR_EXTI14));
965 }
966 #endif /* SYSCFG_ITLINE7_SR_EXTI14 */
967
968 #if defined(SYSCFG_ITLINE7_SR_EXTI15)
969 /**
970 * @brief Check if EXTI line 15 interrupt occurred or not.
971 * @rmtoll SYSCFG_ITLINE7 SR_EXTI15 LL_SYSCFG_IsActiveFlag_EXTI15
972 * @retval State of bit (1 or 0).
973 */
LL_SYSCFG_IsActiveFlag_EXTI15(void)974 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI15(void)
975 {
976 return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI15) == (SYSCFG_ITLINE7_SR_EXTI15));
977 }
978 #endif /* SYSCFG_ITLINE7_SR_EXTI15 */
979
980 #if defined(SYSCFG_ITLINE8_SR_TSC_EOA)
981 /**
982 * @brief Check if Touch sensing controller end of acquisition interrupt occurred or not.
983 * @rmtoll SYSCFG_ITLINE8 SR_TSC_EOA LL_SYSCFG_IsActiveFlag_TSC_EOA
984 * @retval State of bit (1 or 0).
985 */
LL_SYSCFG_IsActiveFlag_TSC_EOA(void)986 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_EOA(void)
987 {
988 return (READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_TSC_EOA) == (SYSCFG_ITLINE8_SR_TSC_EOA));
989 }
990 #endif /* SYSCFG_ITLINE8_SR_TSC_EOA */
991
992 #if defined(SYSCFG_ITLINE8_SR_TSC_MCE)
993 /**
994 * @brief Check if Touch sensing controller max counterror interrupt occurred or not.
995 * @rmtoll SYSCFG_ITLINE8 SR_TSC_MCE LL_SYSCFG_IsActiveFlag_TSC_MCE
996 * @retval State of bit (1 or 0).
997 */
LL_SYSCFG_IsActiveFlag_TSC_MCE(void)998 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_MCE(void)
999 {
1000 return (READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_TSC_MCE) == (SYSCFG_ITLINE8_SR_TSC_MCE));
1001 }
1002 #endif /* SYSCFG_ITLINE8_SR_TSC_MCE */
1003
1004 #if defined(SYSCFG_ITLINE9_SR_DMA1_CH1)
1005 /**
1006 * @brief Check if DMA1 channel 1 interrupt occurred or not.
1007 * @rmtoll SYSCFG_ITLINE9 SR_DMA1_CH1 LL_SYSCFG_IsActiveFlag_DMA1_CH1
1008 * @retval State of bit (1 or 0).
1009 */
LL_SYSCFG_IsActiveFlag_DMA1_CH1(void)1010 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH1(void)
1011 {
1012 return (READ_BIT(SYSCFG->IT_LINE_SR[9], SYSCFG_ITLINE9_SR_DMA1_CH1) == (SYSCFG_ITLINE9_SR_DMA1_CH1));
1013 }
1014 #endif /* SYSCFG_ITLINE9_SR_DMA1_CH1 */
1015
1016 #if defined(SYSCFG_ITLINE10_SR_DMA1_CH2)
1017 /**
1018 * @brief Check if DMA1 channel 2 interrupt occurred or not.
1019 * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH2 LL_SYSCFG_IsActiveFlag_DMA1_CH2
1020 * @retval State of bit (1 or 0).
1021 */
LL_SYSCFG_IsActiveFlag_DMA1_CH2(void)1022 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH2(void)
1023 {
1024 return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH2) == (SYSCFG_ITLINE10_SR_DMA1_CH2));
1025 }
1026 #endif /* SYSCFG_ITLINE10_SR_DMA1_CH2 */
1027
1028 #if defined(SYSCFG_ITLINE10_SR_DMA1_CH3)
1029 /**
1030 * @brief Check if DMA1 channel 3 interrupt occurred or not.
1031 * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH3 LL_SYSCFG_IsActiveFlag_DMA1_CH3
1032 * @retval State of bit (1 or 0).
1033 */
LL_SYSCFG_IsActiveFlag_DMA1_CH3(void)1034 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH3(void)
1035 {
1036 return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH3) == (SYSCFG_ITLINE10_SR_DMA1_CH3));
1037 }
1038 #endif /* SYSCFG_ITLINE10_SR_DMA1_CH3 */
1039
1040 #if defined(SYSCFG_ITLINE10_SR_DMA2_CH1)
1041 /**
1042 * @brief Check if DMA2 channel 1 interrupt occurred or not.
1043 * @rmtoll SYSCFG_ITLINE10 SR_DMA2_CH1 LL_SYSCFG_IsActiveFlag_DMA2_CH1
1044 * @retval State of bit (1 or 0).
1045 */
LL_SYSCFG_IsActiveFlag_DMA2_CH1(void)1046 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH1(void)
1047 {
1048 return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA2_CH1) == (SYSCFG_ITLINE10_SR_DMA2_CH1));
1049 }
1050 #endif /* SYSCFG_ITLINE10_SR_DMA2_CH1 */
1051
1052 #if defined(SYSCFG_ITLINE10_SR_DMA2_CH2)
1053 /**
1054 * @brief Check if DMA2 channel 2 interrupt occurred or not.
1055 * @rmtoll SYSCFG_ITLINE10 SR_DMA2_CH2 LL_SYSCFG_IsActiveFlag_DMA2_CH2
1056 * @retval State of bit (1 or 0).
1057 */
LL_SYSCFG_IsActiveFlag_DMA2_CH2(void)1058 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH2(void)
1059 {
1060 return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA2_CH2) == (SYSCFG_ITLINE10_SR_DMA2_CH2));
1061 }
1062 #endif /* SYSCFG_ITLINE10_SR_DMA2_CH2 */
1063
1064 #if defined(SYSCFG_ITLINE11_SR_DMA1_CH4)
1065 /**
1066 * @brief Check if DMA1 channel 4 interrupt occurred or not.
1067 * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH4 LL_SYSCFG_IsActiveFlag_DMA1_CH4
1068 * @retval State of bit (1 or 0).
1069 */
LL_SYSCFG_IsActiveFlag_DMA1_CH4(void)1070 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH4(void)
1071 {
1072 return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH4) == (SYSCFG_ITLINE11_SR_DMA1_CH4));
1073 }
1074 #endif /* SYSCFG_ITLINE11_SR_DMA1_CH4 */
1075
1076 #if defined(SYSCFG_ITLINE11_SR_DMA1_CH5)
1077 /**
1078 * @brief Check if DMA1 channel 5 interrupt occurred or not.
1079 * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH5 LL_SYSCFG_IsActiveFlag_DMA1_CH5
1080 * @retval State of bit (1 or 0).
1081 */
LL_SYSCFG_IsActiveFlag_DMA1_CH5(void)1082 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH5(void)
1083 {
1084 return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH5) == (SYSCFG_ITLINE11_SR_DMA1_CH5));
1085 }
1086 #endif /* SYSCFG_ITLINE11_SR_DMA1_CH5 */
1087
1088 #if defined(SYSCFG_ITLINE11_SR_DMA1_CH6)
1089 /**
1090 * @brief Check if DMA1 channel 6 interrupt occurred or not.
1091 * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH6 LL_SYSCFG_IsActiveFlag_DMA1_CH6
1092 * @retval State of bit (1 or 0).
1093 */
LL_SYSCFG_IsActiveFlag_DMA1_CH6(void)1094 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH6(void)
1095 {
1096 return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH6) == (SYSCFG_ITLINE11_SR_DMA1_CH6));
1097 }
1098 #endif /* SYSCFG_ITLINE11_SR_DMA1_CH6 */
1099
1100 #if defined(SYSCFG_ITLINE11_SR_DMA1_CH7)
1101 /**
1102 * @brief Check if DMA1 channel 7 interrupt occurred or not.
1103 * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH7 LL_SYSCFG_IsActiveFlag_DMA1_CH7
1104 * @retval State of bit (1 or 0).
1105 */
LL_SYSCFG_IsActiveFlag_DMA1_CH7(void)1106 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH7(void)
1107 {
1108 return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH7) == (SYSCFG_ITLINE11_SR_DMA1_CH7));
1109 }
1110 #endif /* SYSCFG_ITLINE11_SR_DMA1_CH7 */
1111
1112 #if defined(SYSCFG_ITLINE11_SR_DMA2_CH3)
1113 /**
1114 * @brief Check if DMA2 channel 3 interrupt occurred or not.
1115 * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH3 LL_SYSCFG_IsActiveFlag_DMA2_CH3
1116 * @retval State of bit (1 or 0).
1117 */
LL_SYSCFG_IsActiveFlag_DMA2_CH3(void)1118 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH3(void)
1119 {
1120 return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH3) == (SYSCFG_ITLINE11_SR_DMA2_CH3));
1121 }
1122 #endif /* SYSCFG_ITLINE11_SR_DMA2_CH3 */
1123
1124 #if defined(SYSCFG_ITLINE11_SR_DMA2_CH4)
1125 /**
1126 * @brief Check if DMA2 channel 4 interrupt occurred or not.
1127 * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH4 LL_SYSCFG_IsActiveFlag_DMA2_CH4
1128 * @retval State of bit (1 or 0).
1129 */
LL_SYSCFG_IsActiveFlag_DMA2_CH4(void)1130 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH4(void)
1131 {
1132 return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH4) == (SYSCFG_ITLINE11_SR_DMA2_CH4));
1133 }
1134 #endif /* SYSCFG_ITLINE11_SR_DMA2_CH4 */
1135
1136 #if defined(SYSCFG_ITLINE11_SR_DMA2_CH5)
1137 /**
1138 * @brief Check if DMA2 channel 5 interrupt occurred or not.
1139 * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH5 LL_SYSCFG_IsActiveFlag_DMA2_CH5
1140 * @retval State of bit (1 or 0).
1141 */
LL_SYSCFG_IsActiveFlag_DMA2_CH5(void)1142 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH5(void)
1143 {
1144 return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH5) == (SYSCFG_ITLINE11_SR_DMA2_CH5));
1145 }
1146 #endif /* SYSCFG_ITLINE11_SR_DMA2_CH5 */
1147
1148 #if defined(SYSCFG_ITLINE12_SR_ADC)
1149 /**
1150 * @brief Check if ADC interrupt occurred or not.
1151 * @rmtoll SYSCFG_ITLINE12 SR_ADC LL_SYSCFG_IsActiveFlag_ADC
1152 * @retval State of bit (1 or 0).
1153 */
LL_SYSCFG_IsActiveFlag_ADC(void)1154 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_ADC(void)
1155 {
1156 return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_ADC) == (SYSCFG_ITLINE12_SR_ADC));
1157 }
1158 #endif /* SYSCFG_ITLINE12_SR_ADC */
1159
1160 #if defined(SYSCFG_ITLINE12_SR_COMP1)
1161 /**
1162 * @brief Check if Comparator 1 interrupt occurred or not (EXTI line 21).
1163 * @rmtoll SYSCFG_ITLINE12 SR_COMP1 LL_SYSCFG_IsActiveFlag_COMP1
1164 * @retval State of bit (1 or 0).
1165 */
LL_SYSCFG_IsActiveFlag_COMP1(void)1166 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP1(void)
1167 {
1168 return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP1) == (SYSCFG_ITLINE12_SR_COMP1));
1169 }
1170 #endif /* SYSCFG_ITLINE12_SR_COMP1 */
1171
1172 #if defined(SYSCFG_ITLINE12_SR_COMP2)
1173 /**
1174 * @brief Check if Comparator 2 interrupt occurred or not (EXTI line 22).
1175 * @rmtoll SYSCFG_ITLINE12 SR_COMP2 LL_SYSCFG_IsActiveFlag_COMP2
1176 * @retval State of bit (1 or 0).
1177 */
LL_SYSCFG_IsActiveFlag_COMP2(void)1178 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP2(void)
1179 {
1180 return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP2) == (SYSCFG_ITLINE12_SR_COMP2));
1181 }
1182 #endif /* SYSCFG_ITLINE12_SR_COMP2 */
1183
1184 #if defined(SYSCFG_ITLINE13_SR_TIM1_BRK)
1185 /**
1186 * @brief Check if Timer 1 break interrupt occurred or not.
1187 * @rmtoll SYSCFG_ITLINE13 SR_TIM1_BRK LL_SYSCFG_IsActiveFlag_TIM1_BRK
1188 * @retval State of bit (1 or 0).
1189 */
LL_SYSCFG_IsActiveFlag_TIM1_BRK(void)1190 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_BRK(void)
1191 {
1192 return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_BRK) == (SYSCFG_ITLINE13_SR_TIM1_BRK));
1193 }
1194 #endif /* SYSCFG_ITLINE13_SR_TIM1_BRK */
1195
1196 #if defined(SYSCFG_ITLINE13_SR_TIM1_UPD)
1197 /**
1198 * @brief Check if Timer 1 update interrupt occurred or not.
1199 * @rmtoll SYSCFG_ITLINE13 SR_TIM1_UPD LL_SYSCFG_IsActiveFlag_TIM1_UPD
1200 * @retval State of bit (1 or 0).
1201 */
LL_SYSCFG_IsActiveFlag_TIM1_UPD(void)1202 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_UPD(void)
1203 {
1204 return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_UPD) == (SYSCFG_ITLINE13_SR_TIM1_UPD));
1205 }
1206 #endif /* SYSCFG_ITLINE13_SR_TIM1_UPD */
1207
1208 #if defined(SYSCFG_ITLINE13_SR_TIM1_TRG)
1209 /**
1210 * @brief Check if Timer 1 trigger interrupt occurred or not.
1211 * @rmtoll SYSCFG_ITLINE13 SR_TIM1_TRG LL_SYSCFG_IsActiveFlag_TIM1_TRG
1212 * @retval State of bit (1 or 0).
1213 */
LL_SYSCFG_IsActiveFlag_TIM1_TRG(void)1214 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_TRG(void)
1215 {
1216 return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_TRG) == (SYSCFG_ITLINE13_SR_TIM1_TRG));
1217 }
1218 #endif /* SYSCFG_ITLINE13_SR_TIM1_TRG */
1219
1220 #if defined(SYSCFG_ITLINE13_SR_TIM1_CCU)
1221 /**
1222 * @brief Check if Timer 1 commutation interrupt occurred or not.
1223 * @rmtoll SYSCFG_ITLINE13 SR_TIM1_CCU LL_SYSCFG_IsActiveFlag_TIM1_CCU
1224 * @retval State of bit (1 or 0).
1225 */
LL_SYSCFG_IsActiveFlag_TIM1_CCU(void)1226 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CCU(void)
1227 {
1228 return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_CCU) == (SYSCFG_ITLINE13_SR_TIM1_CCU));
1229 }
1230 #endif /* SYSCFG_ITLINE13_SR_TIM1_CCU */
1231
1232 #if defined(SYSCFG_ITLINE14_SR_TIM1_CC)
1233 /**
1234 * @brief Check if Timer 1 capture compare interrupt occurred or not.
1235 * @rmtoll SYSCFG_ITLINE14 SR_TIM1_CC LL_SYSCFG_IsActiveFlag_TIM1_CC
1236 * @retval State of bit (1 or 0).
1237 */
LL_SYSCFG_IsActiveFlag_TIM1_CC(void)1238 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CC(void)
1239 {
1240 return (READ_BIT(SYSCFG->IT_LINE_SR[14], SYSCFG_ITLINE14_SR_TIM1_CC) == (SYSCFG_ITLINE14_SR_TIM1_CC));
1241 }
1242 #endif /* SYSCFG_ITLINE14_SR_TIM1_CC */
1243
1244 #if defined(SYSCFG_ITLINE15_SR_TIM2_GLB)
1245 /**
1246 * @brief Check if Timer 2 interrupt occurred or not.
1247 * @rmtoll SYSCFG_ITLINE15 SR_TIM2_GLB LL_SYSCFG_IsActiveFlag_TIM2
1248 * @retval State of bit (1 or 0).
1249 */
LL_SYSCFG_IsActiveFlag_TIM2(void)1250 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM2(void)
1251 {
1252 return (READ_BIT(SYSCFG->IT_LINE_SR[15], SYSCFG_ITLINE15_SR_TIM2_GLB) == (SYSCFG_ITLINE15_SR_TIM2_GLB));
1253 }
1254 #endif /* SYSCFG_ITLINE15_SR_TIM2_GLB */
1255
1256 #if defined(SYSCFG_ITLINE16_SR_TIM3_GLB)
1257 /**
1258 * @brief Check if Timer 3 interrupt occurred or not.
1259 * @rmtoll SYSCFG_ITLINE16 SR_TIM3_GLB LL_SYSCFG_IsActiveFlag_TIM3
1260 * @retval State of bit (1 or 0).
1261 */
LL_SYSCFG_IsActiveFlag_TIM3(void)1262 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM3(void)
1263 {
1264 return (READ_BIT(SYSCFG->IT_LINE_SR[16], SYSCFG_ITLINE16_SR_TIM3_GLB) == (SYSCFG_ITLINE16_SR_TIM3_GLB));
1265 }
1266 #endif /* SYSCFG_ITLINE16_SR_TIM3_GLB */
1267
1268 #if defined(SYSCFG_ITLINE17_SR_DAC)
1269 /**
1270 * @brief Check if DAC underrun interrupt occurred or not.
1271 * @rmtoll SYSCFG_ITLINE17 SR_DAC LL_SYSCFG_IsActiveFlag_DAC
1272 * @retval State of bit (1 or 0).
1273 */
LL_SYSCFG_IsActiveFlag_DAC(void)1274 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DAC(void)
1275 {
1276 return (READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_DAC) == (SYSCFG_ITLINE17_SR_DAC));
1277 }
1278 #endif /* SYSCFG_ITLINE17_SR_DAC */
1279
1280 #if defined(SYSCFG_ITLINE17_SR_TIM6_GLB)
1281 /**
1282 * @brief Check if Timer 6 interrupt occurred or not.
1283 * @rmtoll SYSCFG_ITLINE17 SR_TIM6_GLB LL_SYSCFG_IsActiveFlag_TIM6
1284 * @retval State of bit (1 or 0).
1285 */
LL_SYSCFG_IsActiveFlag_TIM6(void)1286 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM6(void)
1287 {
1288 return (READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_TIM6_GLB) == (SYSCFG_ITLINE17_SR_TIM6_GLB));
1289 }
1290 #endif /* SYSCFG_ITLINE17_SR_TIM6_GLB */
1291
1292 #if defined(SYSCFG_ITLINE18_SR_TIM7_GLB)
1293 /**
1294 * @brief Check if Timer 7 interrupt occurred or not.
1295 * @rmtoll SYSCFG_ITLINE18 SR_TIM7_GLB LL_SYSCFG_IsActiveFlag_TIM7
1296 * @retval State of bit (1 or 0).
1297 */
LL_SYSCFG_IsActiveFlag_TIM7(void)1298 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM7(void)
1299 {
1300 return (READ_BIT(SYSCFG->IT_LINE_SR[18], SYSCFG_ITLINE18_SR_TIM7_GLB) == (SYSCFG_ITLINE18_SR_TIM7_GLB));
1301 }
1302 #endif /* SYSCFG_ITLINE18_SR_TIM7_GLB */
1303
1304 #if defined(SYSCFG_ITLINE19_SR_TIM14_GLB)
1305 /**
1306 * @brief Check if Timer 14 interrupt occurred or not.
1307 * @rmtoll SYSCFG_ITLINE19 SR_TIM14_GLB LL_SYSCFG_IsActiveFlag_TIM14
1308 * @retval State of bit (1 or 0).
1309 */
LL_SYSCFG_IsActiveFlag_TIM14(void)1310 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM14(void)
1311 {
1312 return (READ_BIT(SYSCFG->IT_LINE_SR[19], SYSCFG_ITLINE19_SR_TIM14_GLB) == (SYSCFG_ITLINE19_SR_TIM14_GLB));
1313 }
1314 #endif /* SYSCFG_ITLINE19_SR_TIM14_GLB */
1315
1316 #if defined(SYSCFG_ITLINE20_SR_TIM15_GLB)
1317 /**
1318 * @brief Check if Timer 15 interrupt occurred or not.
1319 * @rmtoll SYSCFG_ITLINE20 SR_TIM15_GLB LL_SYSCFG_IsActiveFlag_TIM15
1320 * @retval State of bit (1 or 0).
1321 */
LL_SYSCFG_IsActiveFlag_TIM15(void)1322 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM15(void)
1323 {
1324 return (READ_BIT(SYSCFG->IT_LINE_SR[20], SYSCFG_ITLINE20_SR_TIM15_GLB) == (SYSCFG_ITLINE20_SR_TIM15_GLB));
1325 }
1326 #endif /* SYSCFG_ITLINE20_SR_TIM15_GLB */
1327
1328 #if defined(SYSCFG_ITLINE21_SR_TIM16_GLB)
1329 /**
1330 * @brief Check if Timer 16 interrupt occurred or not.
1331 * @rmtoll SYSCFG_ITLINE21 SR_TIM16_GLB LL_SYSCFG_IsActiveFlag_TIM16
1332 * @retval State of bit (1 or 0).
1333 */
LL_SYSCFG_IsActiveFlag_TIM16(void)1334 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM16(void)
1335 {
1336 return (READ_BIT(SYSCFG->IT_LINE_SR[21], SYSCFG_ITLINE21_SR_TIM16_GLB) == (SYSCFG_ITLINE21_SR_TIM16_GLB));
1337 }
1338 #endif /* SYSCFG_ITLINE21_SR_TIM16_GLB */
1339
1340 #if defined(SYSCFG_ITLINE22_SR_TIM17_GLB)
1341 /**
1342 * @brief Check if Timer 17 interrupt occurred or not.
1343 * @rmtoll SYSCFG_ITLINE22 SR_TIM17_GLB LL_SYSCFG_IsActiveFlag_TIM17
1344 * @retval State of bit (1 or 0).
1345 */
LL_SYSCFG_IsActiveFlag_TIM17(void)1346 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM17(void)
1347 {
1348 return (READ_BIT(SYSCFG->IT_LINE_SR[22], SYSCFG_ITLINE22_SR_TIM17_GLB) == (SYSCFG_ITLINE22_SR_TIM17_GLB));
1349 }
1350 #endif /* SYSCFG_ITLINE22_SR_TIM17_GLB */
1351
1352 #if defined(SYSCFG_ITLINE23_SR_I2C1_GLB)
1353 /**
1354 * @brief Check if I2C1 interrupt occurred or not, combined with EXTI line 23.
1355 * @rmtoll SYSCFG_ITLINE23 SR_I2C1_GLB LL_SYSCFG_IsActiveFlag_I2C1
1356 * @retval State of bit (1 or 0).
1357 */
LL_SYSCFG_IsActiveFlag_I2C1(void)1358 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C1(void)
1359 {
1360 return (READ_BIT(SYSCFG->IT_LINE_SR[23], SYSCFG_ITLINE23_SR_I2C1_GLB) == (SYSCFG_ITLINE23_SR_I2C1_GLB));
1361 }
1362 #endif /* SYSCFG_ITLINE23_SR_I2C1_GLB */
1363
1364 #if defined(SYSCFG_ITLINE24_SR_I2C2_GLB)
1365 /**
1366 * @brief Check if I2C2 interrupt occurred or not.
1367 * @rmtoll SYSCFG_ITLINE24 SR_I2C2_GLB LL_SYSCFG_IsActiveFlag_I2C2
1368 * @retval State of bit (1 or 0).
1369 */
LL_SYSCFG_IsActiveFlag_I2C2(void)1370 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C2(void)
1371 {
1372 return (READ_BIT(SYSCFG->IT_LINE_SR[24], SYSCFG_ITLINE24_SR_I2C2_GLB) == (SYSCFG_ITLINE24_SR_I2C2_GLB));
1373 }
1374 #endif /* SYSCFG_ITLINE24_SR_I2C2_GLB */
1375
1376 #if defined(SYSCFG_ITLINE25_SR_SPI1)
1377 /**
1378 * @brief Check if SPI1 interrupt occurred or not.
1379 * @rmtoll SYSCFG_ITLINE25 SR_SPI1 LL_SYSCFG_IsActiveFlag_SPI1
1380 * @retval State of bit (1 or 0).
1381 */
LL_SYSCFG_IsActiveFlag_SPI1(void)1382 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI1(void)
1383 {
1384 return (READ_BIT(SYSCFG->IT_LINE_SR[25], SYSCFG_ITLINE25_SR_SPI1) == (SYSCFG_ITLINE25_SR_SPI1));
1385 }
1386 #endif /* SYSCFG_ITLINE25_SR_SPI1 */
1387
1388 #if defined(SYSCFG_ITLINE26_SR_SPI2)
1389 /**
1390 * @brief Check if SPI2 interrupt occurred or not.
1391 * @rmtoll SYSCFG_ITLINE26 SR_SPI2 LL_SYSCFG_IsActiveFlag_SPI2
1392 * @retval State of bit (1 or 0).
1393 */
LL_SYSCFG_IsActiveFlag_SPI2(void)1394 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI2(void)
1395 {
1396 return (READ_BIT(SYSCFG->IT_LINE_SR[26], SYSCFG_ITLINE26_SR_SPI2) == (SYSCFG_ITLINE26_SR_SPI2));
1397 }
1398 #endif /* SYSCFG_ITLINE26_SR_SPI2 */
1399
1400 #if defined(SYSCFG_ITLINE27_SR_USART1_GLB)
1401 /**
1402 * @brief Check if USART1 interrupt occurred or not, combined with EXTI line 25.
1403 * @rmtoll SYSCFG_ITLINE27 SR_USART1_GLB LL_SYSCFG_IsActiveFlag_USART1
1404 * @retval State of bit (1 or 0).
1405 */
LL_SYSCFG_IsActiveFlag_USART1(void)1406 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART1(void)
1407 {
1408 return (READ_BIT(SYSCFG->IT_LINE_SR[27], SYSCFG_ITLINE27_SR_USART1_GLB) == (SYSCFG_ITLINE27_SR_USART1_GLB));
1409 }
1410 #endif /* SYSCFG_ITLINE27_SR_USART1_GLB */
1411
1412 #if defined(SYSCFG_ITLINE28_SR_USART2_GLB)
1413 /**
1414 * @brief Check if USART2 interrupt occurred or not, combined with EXTI line 26.
1415 * @rmtoll SYSCFG_ITLINE28 SR_USART2_GLB LL_SYSCFG_IsActiveFlag_USART2
1416 * @retval State of bit (1 or 0).
1417 */
LL_SYSCFG_IsActiveFlag_USART2(void)1418 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART2(void)
1419 {
1420 return (READ_BIT(SYSCFG->IT_LINE_SR[28], SYSCFG_ITLINE28_SR_USART2_GLB) == (SYSCFG_ITLINE28_SR_USART2_GLB));
1421 }
1422 #endif /* SYSCFG_ITLINE28_SR_USART2_GLB */
1423
1424 #if defined(SYSCFG_ITLINE29_SR_USART3_GLB)
1425 /**
1426 * @brief Check if USART3 interrupt occurred or not, combined with EXTI line 28.
1427 * @rmtoll SYSCFG_ITLINE29 SR_USART3_GLB LL_SYSCFG_IsActiveFlag_USART3
1428 * @retval State of bit (1 or 0).
1429 */
LL_SYSCFG_IsActiveFlag_USART3(void)1430 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART3(void)
1431 {
1432 return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART3_GLB) == (SYSCFG_ITLINE29_SR_USART3_GLB));
1433 }
1434 #endif /* SYSCFG_ITLINE29_SR_USART3_GLB */
1435
1436 #if defined(SYSCFG_ITLINE29_SR_USART4_GLB)
1437 /**
1438 * @brief Check if USART4 interrupt occurred or not.
1439 * @rmtoll SYSCFG_ITLINE29 SR_USART4_GLB LL_SYSCFG_IsActiveFlag_USART4
1440 * @retval State of bit (1 or 0).
1441 */
LL_SYSCFG_IsActiveFlag_USART4(void)1442 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART4(void)
1443 {
1444 return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART4_GLB) == (SYSCFG_ITLINE29_SR_USART4_GLB));
1445 }
1446 #endif /* SYSCFG_ITLINE29_SR_USART4_GLB */
1447
1448 #if defined(SYSCFG_ITLINE29_SR_USART5_GLB)
1449 /**
1450 * @brief Check if USART5 interrupt occurred or not.
1451 * @rmtoll SYSCFG_ITLINE29 SR_USART5_GLB LL_SYSCFG_IsActiveFlag_USART5
1452 * @retval State of bit (1 or 0).
1453 */
LL_SYSCFG_IsActiveFlag_USART5(void)1454 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART5(void)
1455 {
1456 return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART5_GLB) == (SYSCFG_ITLINE29_SR_USART5_GLB));
1457 }
1458 #endif /* SYSCFG_ITLINE29_SR_USART5_GLB */
1459
1460 #if defined(SYSCFG_ITLINE29_SR_USART6_GLB)
1461 /**
1462 * @brief Check if USART6 interrupt occurred or not.
1463 * @rmtoll SYSCFG_ITLINE29 SR_USART6_GLB LL_SYSCFG_IsActiveFlag_USART6
1464 * @retval State of bit (1 or 0).
1465 */
LL_SYSCFG_IsActiveFlag_USART6(void)1466 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART6(void)
1467 {
1468 return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART6_GLB) == (SYSCFG_ITLINE29_SR_USART6_GLB));
1469 }
1470 #endif /* SYSCFG_ITLINE29_SR_USART6_GLB */
1471
1472 #if defined(SYSCFG_ITLINE29_SR_USART7_GLB)
1473 /**
1474 * @brief Check if USART7 interrupt occurred or not.
1475 * @rmtoll SYSCFG_ITLINE29 SR_USART7_GLB LL_SYSCFG_IsActiveFlag_USART7
1476 * @retval State of bit (1 or 0).
1477 */
LL_SYSCFG_IsActiveFlag_USART7(void)1478 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART7(void)
1479 {
1480 return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART7_GLB) == (SYSCFG_ITLINE29_SR_USART7_GLB));
1481 }
1482 #endif /* SYSCFG_ITLINE29_SR_USART7_GLB */
1483
1484 #if defined(SYSCFG_ITLINE29_SR_USART8_GLB)
1485 /**
1486 * @brief Check if USART8 interrupt occurred or not.
1487 * @rmtoll SYSCFG_ITLINE29 SR_USART8_GLB LL_SYSCFG_IsActiveFlag_USART8
1488 * @retval State of bit (1 or 0).
1489 */
LL_SYSCFG_IsActiveFlag_USART8(void)1490 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART8(void)
1491 {
1492 return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART8_GLB) == (SYSCFG_ITLINE29_SR_USART8_GLB));
1493 }
1494 #endif /* SYSCFG_ITLINE29_SR_USART8_GLB */
1495
1496 #if defined(SYSCFG_ITLINE30_SR_CAN)
1497 /**
1498 * @brief Check if CAN interrupt occurred or not.
1499 * @rmtoll SYSCFG_ITLINE30 SR_CAN LL_SYSCFG_IsActiveFlag_CAN
1500 * @retval State of bit (1 or 0).
1501 */
LL_SYSCFG_IsActiveFlag_CAN(void)1502 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CAN(void)
1503 {
1504 return (READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CAN) == (SYSCFG_ITLINE30_SR_CAN));
1505 }
1506 #endif /* SYSCFG_ITLINE30_SR_CAN */
1507
1508 #if defined(SYSCFG_ITLINE30_SR_CEC)
1509 /**
1510 * @brief Check if CEC interrupt occurred or not, combined with EXTI line 27.
1511 * @rmtoll SYSCFG_ITLINE30 SR_CEC LL_SYSCFG_IsActiveFlag_CEC
1512 * @retval State of bit (1 or 0).
1513 */
LL_SYSCFG_IsActiveFlag_CEC(void)1514 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CEC(void)
1515 {
1516 return (READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CEC) == (SYSCFG_ITLINE30_SR_CEC));
1517 }
1518 #endif /* SYSCFG_ITLINE30_SR_CEC */
1519
1520 /**
1521 * @brief Set connections to TIMx Break inputs
1522 * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_SetTIMBreakInputs\n
1523 * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_SetTIMBreakInputs\n
1524 * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_SetTIMBreakInputs
1525 * @param Break This parameter can be a combination of the following values:
1526 * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
1527 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
1528 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
1529 *
1530 * (*) value not defined in all devices
1531 * @retval None
1532 */
LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)1533 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
1534 {
1535 #if defined(SYSCFG_CFGR2_PVD_LOCK)
1536 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_PVD_LOCK, Break);
1537 #else
1538 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK, Break);
1539 #endif /*SYSCFG_CFGR2_PVD_LOCK*/
1540 }
1541
1542 /**
1543 * @brief Get connections to TIMx Break inputs
1544 * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_GetTIMBreakInputs\n
1545 * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_GetTIMBreakInputs\n
1546 * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_GetTIMBreakInputs
1547 * @retval Returned value can be can be a combination of the following values:
1548 * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
1549 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
1550 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
1551 *
1552 * (*) value not defined in all devices
1553 */
LL_SYSCFG_GetTIMBreakInputs(void)1554 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
1555 {
1556 #if defined(SYSCFG_CFGR2_PVD_LOCK)
1557 return (uint32_t)(READ_BIT(SYSCFG->CFGR2,
1558 SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_PVD_LOCK));
1559 #else
1560 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK));
1561 #endif /*SYSCFG_CFGR2_PVD_LOCK*/
1562 }
1563
1564 /**
1565 * @brief Check if SRAM parity error detected
1566 * @rmtoll SYSCFG_CFGR2 SRAM_PEF LL_SYSCFG_IsActiveFlag_SP
1567 * @retval State of bit (1 or 0).
1568 */
LL_SYSCFG_IsActiveFlag_SP(void)1569 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
1570 {
1571 return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF) == (SYSCFG_CFGR2_SRAM_PEF));
1572 }
1573
1574 /**
1575 * @brief Clear SRAM parity error flag
1576 * @rmtoll SYSCFG_CFGR2 SRAM_PEF LL_SYSCFG_ClearFlag_SP
1577 * @retval None
1578 */
LL_SYSCFG_ClearFlag_SP(void)1579 __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
1580 {
1581 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF);
1582 }
1583
1584 /**
1585 * @}
1586 */
1587
1588 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
1589 * @{
1590 */
1591
1592 /**
1593 * @brief Return the device identifier
1594 * @note For STM32F03x devices, the device ID is 0x444
1595 * @note For STM32F04x devices, the device ID is 0x445.
1596 * @note For STM32F05x devices, the device ID is 0x440
1597 * @note For STM32F07x devices, the device ID is 0x448
1598 * @note For STM32F09x devices, the device ID is 0x442
1599 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
1600 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
1601 */
LL_DBGMCU_GetDeviceID(void)1602 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1603 {
1604 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
1605 }
1606
1607 /**
1608 * @brief Return the device revision identifier
1609 * @note This field indicates the revision of the device.
1610 For example, it is read as 0x1000 for Revision 1.0.
1611 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
1612 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
1613 */
LL_DBGMCU_GetRevisionID(void)1614 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1615 {
1616 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
1617 }
1618
1619 /**
1620 * @brief Enable the Debug Module during STOP mode
1621 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
1622 * @retval None
1623 */
LL_DBGMCU_EnableDBGStopMode(void)1624 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
1625 {
1626 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1627 }
1628
1629 /**
1630 * @brief Disable the Debug Module during STOP mode
1631 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
1632 * @retval None
1633 */
LL_DBGMCU_DisableDBGStopMode(void)1634 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
1635 {
1636 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1637 }
1638
1639 /**
1640 * @brief Enable the Debug Module during STANDBY mode
1641 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
1642 * @retval None
1643 */
LL_DBGMCU_EnableDBGStandbyMode(void)1644 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
1645 {
1646 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1647 }
1648
1649 /**
1650 * @brief Disable the Debug Module during STANDBY mode
1651 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
1652 * @retval None
1653 */
LL_DBGMCU_DisableDBGStandbyMode(void)1654 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
1655 {
1656 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1657 }
1658
1659 /**
1660 * @brief Freeze APB1 peripherals (group1 peripherals)
1661 * @rmtoll DBGMCU_APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1662 * DBGMCU_APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1663 * DBGMCU_APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1664 * DBGMCU_APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1665 * DBGMCU_APB1FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1666 * DBGMCU_APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1667 * DBGMCU_APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1668 * DBGMCU_APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1669 * DBGMCU_APB1FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1670 * DBGMCU_APB1FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
1671 * @param Periphs This parameter can be a combination of the following values:
1672 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
1673 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1674 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
1675 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
1676 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
1677 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1678 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1679 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1680 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1681 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
1682 *
1683 * (*) value not defined in all devices
1684 * @retval None
1685 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)1686 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1687 {
1688 SET_BIT(DBGMCU->APB1FZ, Periphs);
1689 }
1690
1691 /**
1692 * @brief Unfreeze APB1 peripherals (group1 peripherals)
1693 * @rmtoll DBGMCU_APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1694 * DBGMCU_APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1695 * DBGMCU_APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1696 * DBGMCU_APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1697 * DBGMCU_APB1FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1698 * DBGMCU_APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1699 * DBGMCU_APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1700 * DBGMCU_APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1701 * DBGMCU_APB1FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1702 * DBGMCU_APB1FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
1703 * @param Periphs This parameter can be a combination of the following values:
1704 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
1705 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1706 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
1707 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
1708 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
1709 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1710 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1711 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1712 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1713 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
1714 *
1715 * (*) value not defined in all devices
1716 * @retval None
1717 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)1718 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1719 {
1720 CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
1721 }
1722
1723 /**
1724 * @brief Freeze APB1 peripherals (group2 peripherals)
1725 * @rmtoll DBGMCU_APB2FZ DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n
1726 * DBGMCU_APB2FZ DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n
1727 * DBGMCU_APB2FZ DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n
1728 * DBGMCU_APB2FZ DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
1729 * @param Periphs This parameter can be a combination of the following values:
1730 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP
1731 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP (*)
1732 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP
1733 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP
1734 *
1735 * (*) value not defined in all devices
1736 * @retval None
1737 */
LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)1738 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
1739 {
1740 SET_BIT(DBGMCU->APB2FZ, Periphs);
1741 }
1742
1743 /**
1744 * @brief Unfreeze APB1 peripherals (group2 peripherals)
1745 * @rmtoll DBGMCU_APB2FZ DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
1746 * DBGMCU_APB2FZ DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
1747 * DBGMCU_APB2FZ DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
1748 * DBGMCU_APB2FZ DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
1749 * @param Periphs This parameter can be a combination of the following values:
1750 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP
1751 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP (*)
1752 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP
1753 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP
1754 *
1755 * (*) value not defined in all devices
1756 * @retval None
1757 */
LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)1758 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
1759 {
1760 CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
1761 }
1762 /**
1763 * @}
1764 */
1765
1766 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
1767 * @{
1768 */
1769
1770 /**
1771 * @brief Set FLASH Latency
1772 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
1773 * @param Latency This parameter can be one of the following values:
1774 * @arg @ref LL_FLASH_LATENCY_0
1775 * @arg @ref LL_FLASH_LATENCY_1
1776 * @retval None
1777 */
LL_FLASH_SetLatency(uint32_t Latency)1778 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1779 {
1780 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1781 }
1782
1783 /**
1784 * @brief Get FLASH Latency
1785 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
1786 * @retval Returned value can be one of the following values:
1787 * @arg @ref LL_FLASH_LATENCY_0
1788 * @arg @ref LL_FLASH_LATENCY_1
1789 */
LL_FLASH_GetLatency(void)1790 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1791 {
1792 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1793 }
1794
1795 /**
1796 * @brief Enable Prefetch
1797 * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
1798 * @retval None
1799 */
LL_FLASH_EnablePrefetch(void)1800 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
1801 {
1802 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
1803 }
1804
1805 /**
1806 * @brief Disable Prefetch
1807 * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
1808 * @retval None
1809 */
LL_FLASH_DisablePrefetch(void)1810 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
1811 {
1812 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
1813 }
1814
1815 /**
1816 * @brief Check if Prefetch buffer is enabled
1817 * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
1818 * @retval State of bit (1 or 0).
1819 */
LL_FLASH_IsPrefetchEnabled(void)1820 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
1821 {
1822 return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
1823 }
1824
1825
1826
1827 /**
1828 * @}
1829 */
1830
1831 /**
1832 * @}
1833 */
1834
1835 /**
1836 * @}
1837 */
1838
1839 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
1840
1841 /**
1842 * @}
1843 */
1844
1845 #ifdef __cplusplus
1846 }
1847 #endif
1848
1849 #endif /* __STM32F0xx_LL_SYSTEM_H */
1850
1851
