1 /**
2 ******************************************************************************
3 * @file stm32f0xx_ll_cortex.h
4 * @author MCD Application Team
5 * @brief Header file of CORTEX LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL CORTEX driver contains a set of generic APIs that can be
12 used by user:
13 (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
14 functions
15 (+) Low power mode configuration (SCB register of Cortex-MCU)
16 (+) API to access to MCU info (CPUID register)
17
18 @endverbatim
19 ******************************************************************************
20 * @attention
21 *
22 * Copyright (c) 2016 STMicroelectronics.
23 * All rights reserved.
24 *
25 * This software is licensed under terms that can be found in the LICENSE file in
26 * the root directory of this software component.
27 * If no LICENSE file comes with this software, it is provided AS-IS.
28 *
29 ******************************************************************************
30 */
31
32 /* Define to prevent recursive inclusion -------------------------------------*/
33 #ifndef __STM32F0xx_LL_CORTEX_H
34 #define __STM32F0xx_LL_CORTEX_H
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /* Includes ------------------------------------------------------------------*/
41 #include "stm32f0xx.h"
42
43 /** @addtogroup STM32F0xx_LL_Driver
44 * @{
45 */
46
47 /** @defgroup CORTEX_LL CORTEX
48 * @{
49 */
50
51 /* Private types -------------------------------------------------------------*/
52 /* Private variables ---------------------------------------------------------*/
53
54 /* Private constants ---------------------------------------------------------*/
55
56 /* Private macros ------------------------------------------------------------*/
57
58 /* Exported types ------------------------------------------------------------*/
59 /* Exported constants --------------------------------------------------------*/
60 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
61 * @{
62 */
63
64 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
65 * @{
66 */
67 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
68 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
69 /**
70 * @}
71 */
72
73 /**
74 * @}
75 */
76
77 /* Exported macro ------------------------------------------------------------*/
78
79 /* Exported functions --------------------------------------------------------*/
80 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
81 * @{
82 */
83
84 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
85 * @{
86 */
87
88 /**
89 * @brief This function checks if the Systick counter flag is active or not.
90 * @note It can be used in timeout function on application side.
91 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
92 * @retval State of bit (1 or 0).
93 */
LL_SYSTICK_IsActiveCounterFlag(void)94 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
95 {
96 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
97 }
98
99 /**
100 * @brief Configures the SysTick clock source
101 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
102 * @param Source This parameter can be one of the following values:
103 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
104 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
105 * @retval None
106 */
LL_SYSTICK_SetClkSource(uint32_t Source)107 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
108 {
109 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
110 {
111 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
112 }
113 else
114 {
115 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
116 }
117 }
118
119 /**
120 * @brief Get the SysTick clock source
121 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
122 * @retval Returned value can be one of the following values:
123 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
124 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
125 */
LL_SYSTICK_GetClkSource(void)126 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
127 {
128 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
129 }
130
131 /**
132 * @brief Enable SysTick exception request
133 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
134 * @retval None
135 */
LL_SYSTICK_EnableIT(void)136 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
137 {
138 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
139 }
140
141 /**
142 * @brief Disable SysTick exception request
143 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
144 * @retval None
145 */
LL_SYSTICK_DisableIT(void)146 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
147 {
148 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
149 }
150
151 /**
152 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
153 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
154 * @retval State of bit (1 or 0).
155 */
LL_SYSTICK_IsEnabledIT(void)156 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
157 {
158 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
159 }
160
161 /**
162 * @}
163 */
164
165 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
166 * @{
167 */
168
169 /**
170 * @brief Processor uses sleep as its low power mode
171 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
172 * @retval None
173 */
LL_LPM_EnableSleep(void)174 __STATIC_INLINE void LL_LPM_EnableSleep(void)
175 {
176 /* Clear SLEEPDEEP bit of Cortex System Control Register */
177 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
178 }
179
180 /**
181 * @brief Processor uses deep sleep as its low power mode
182 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
183 * @retval None
184 */
LL_LPM_EnableDeepSleep(void)185 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
186 {
187 /* Set SLEEPDEEP bit of Cortex System Control Register */
188 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
189 }
190
191 /**
192 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
193 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
194 * empty main application.
195 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
196 * @retval None
197 */
LL_LPM_EnableSleepOnExit(void)198 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
199 {
200 /* Set SLEEPONEXIT bit of Cortex System Control Register */
201 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
202 }
203
204 /**
205 * @brief Do not sleep when returning to Thread mode.
206 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
207 * @retval None
208 */
LL_LPM_DisableSleepOnExit(void)209 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
210 {
211 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
212 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
213 }
214
215 /**
216 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
217 * processor.
218 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
219 * @retval None
220 */
LL_LPM_EnableEventOnPend(void)221 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
222 {
223 /* Set SEVEONPEND bit of Cortex System Control Register */
224 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
225 }
226
227 /**
228 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
229 * excluded
230 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
231 * @retval None
232 */
LL_LPM_DisableEventOnPend(void)233 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
234 {
235 /* Clear SEVEONPEND bit of Cortex System Control Register */
236 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
237 }
238
239 /**
240 * @}
241 */
242
243 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
244 * @{
245 */
246
247 /**
248 * @brief Get Implementer code
249 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
250 * @retval Value should be equal to 0x41 for ARM
251 */
LL_CPUID_GetImplementer(void)252 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
253 {
254 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
255 }
256
257 /**
258 * @brief Get Variant number (The r value in the rnpn product revision identifier)
259 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
260 * @retval Value between 0 and 255 (0x0: revision 0)
261 */
LL_CPUID_GetVariant(void)262 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
263 {
264 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
265 }
266
267 /**
268 * @brief Get Architecture number
269 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
270 * @retval Value should be equal to 0xC for Cortex-M0 devices
271 */
LL_CPUID_GetArchitecture(void)272 __STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
273 {
274 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
275 }
276
277 /**
278 * @brief Get Part number
279 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
280 * @retval Value should be equal to 0xC20 for Cortex-M0
281 */
LL_CPUID_GetParNo(void)282 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
283 {
284 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
285 }
286
287 /**
288 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
289 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
290 * @retval Value between 0 and 255 (0x1: patch 1)
291 */
LL_CPUID_GetRevision(void)292 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
293 {
294 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
295 }
296
297 /**
298 * @}
299 */
300
301 /**
302 * @}
303 */
304
305 /**
306 * @}
307 */
308
309 /**
310 * @}
311 */
312
313 #ifdef __cplusplus
314 }
315 #endif
316
317 #endif /* __STM32F0xx_LL_CORTEX_H */
318
319
