1 /**
2 ******************************************************************************
3 * @file stm32f0xx_hal_i2c.c
4 * @author MCD Application Team
5 * @brief I2C HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Inter Integrated Circuit (I2C) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State and Errors functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2016 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 ==============================================================================
25 ##### How to use this driver #####
26 ==============================================================================
27 [..]
28 The I2C HAL driver can be used as follows:
29
30 (#) Declare a I2C_HandleTypeDef handle structure, for example:
31 I2C_HandleTypeDef hi2c;
32
33 (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
34 (##) Enable the I2Cx interface clock
35 (##) I2C pins configuration
36 (+++) Enable the clock for the I2C GPIOs
37 (+++) Configure I2C pins as alternate function open-drain
38 (##) NVIC configuration if you need to use interrupt process
39 (+++) Configure the I2Cx interrupt priority
40 (+++) Enable the NVIC I2C IRQ Channel
41 (##) DMA Configuration if you need to use DMA process
42 (+++) Declare a DMA_HandleTypeDef handle structure for
43 the transmit or receive channel
44 (+++) Enable the DMAx interface clock using
45 (+++) Configure the DMA handle parameters
46 (+++) Configure the DMA Tx or Rx channel
47 (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
48 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
49 the DMA Tx or Rx channel
50
51 (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
52 Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
53
54 (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
55 (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
56
57 (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
58
59 (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
60
61 *** Polling mode IO operation ***
62 =================================
63 [..]
64 (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
65 (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
66 (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
67 (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
68
69 *** Polling mode IO MEM operation ***
70 =====================================
71 [..]
72 (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
73 (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
74
75
76 *** Interrupt mode IO operation ***
77 ===================================
78 [..]
79 (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
80 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
81 add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
82 (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
83 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
84 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
85 (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
86 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
87 add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
88 (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
89 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
90 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
91 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
92 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
93 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
94 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
95 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
96 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
97 This action will inform Master to generate a Stop condition to discard the communication.
98
99
100 *** Interrupt mode or DMA mode IO sequential operation ***
101 ==========================================================
102 [..]
103 (@) These interfaces allow to manage a sequential transfer with a repeated start condition
104 when a direction change during transfer
105 [..]
106 (+) A specific option field manage the different steps of a sequential transfer
107 (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
108 (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in
109 no sequential mode
110 (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
111 and data to transfer without a final stop condition
112 (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with
113 start condition, address and data to transfer without a final stop condition,
114 an then permit a call the same master sequential interface several times
115 (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
116 or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
117 (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
118 and with new data to transfer if the direction change or manage only the new data to
119 transfer
120 if no direction change and without a final stop condition in both cases
121 (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
122 and with new data to transfer if the direction change or manage only the new data to
123 transfer
124 if no direction change and with a final stop condition in both cases
125 (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
126 after several call of the same master sequential interface several times
127 (link with option I2C_FIRST_AND_NEXT_FRAME).
128 Usage can, transfer several bytes one by one using
129 HAL_I2C_Master_Seq_Transmit_IT
130 or HAL_I2C_Master_Seq_Receive_IT
131 or HAL_I2C_Master_Seq_Transmit_DMA
132 or HAL_I2C_Master_Seq_Receive_DMA
133 with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
134 Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or
135 Receive sequence permit to call the opposite interface Receive or Transmit
136 without stopping the communication and so generate a restart condition.
137 (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
138 each call of the same master sequential
139 interface.
140 Usage can, transfer several bytes one by one with a restart with slave address between
141 each bytes using
142 HAL_I2C_Master_Seq_Transmit_IT
143 or HAL_I2C_Master_Seq_Receive_IT
144 or HAL_I2C_Master_Seq_Transmit_DMA
145 or HAL_I2C_Master_Seq_Receive_DMA
146 with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
147 Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
148 generation of STOP condition.
149
150 (+) Different sequential I2C interfaces are listed below:
151 (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
152 HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
153 (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and
154 users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
155 (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
156 HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
157 (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
158 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
159 (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
160 (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
161 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
162 (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
163 HAL_I2C_DisableListen_IT()
164 (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
165 add their own code to check the Address Match Code and the transmission direction request by master
166 (Write/Read).
167 (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
168 add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
169 (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
170 HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
171 (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and
172 users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
173 (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
174 HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
175 (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
176 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
177 (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
178 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
179 (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
180 This action will inform Master to generate a Stop condition to discard the communication.
181
182 *** Interrupt mode IO MEM operation ***
183 =======================================
184 [..]
185 (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
186 HAL_I2C_Mem_Write_IT()
187 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
188 add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
189 (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
190 HAL_I2C_Mem_Read_IT()
191 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
192 add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
193 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
194 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
195
196 *** DMA mode IO operation ***
197 ==============================
198 [..]
199 (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
200 HAL_I2C_Master_Transmit_DMA()
201 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
202 add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
203 (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
204 HAL_I2C_Master_Receive_DMA()
205 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
206 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
207 (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
208 HAL_I2C_Slave_Transmit_DMA()
209 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
210 add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
211 (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
212 HAL_I2C_Slave_Receive_DMA()
213 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
214 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
215 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
216 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
217 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
218 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
219 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
220 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
221 This action will inform Master to generate a Stop condition to discard the communication.
222
223 *** DMA mode IO MEM operation ***
224 =================================
225 [..]
226 (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
227 HAL_I2C_Mem_Write_DMA()
228 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
229 add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
230 (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
231 HAL_I2C_Mem_Read_DMA()
232 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
233 add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
234 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
235 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
236
237
238 *** I2C HAL driver macros list ***
239 ==================================
240 [..]
241 Below the list of most used macros in I2C HAL driver.
242
243 (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
244 (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
245 (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
246 (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
247 (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
248 (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
249 (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
250
251 *** Callback registration ***
252 =============================================
253 [..]
254 The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
255 allows the user to configure dynamically the driver callbacks.
256 Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
257 to register an interrupt callback.
258 [..]
259 Function HAL_I2C_RegisterCallback() allows to register following callbacks:
260 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
261 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
262 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
263 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
264 (+) ListenCpltCallback : callback for end of listen mode.
265 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
266 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
267 (+) ErrorCallback : callback for error detection.
268 (+) AbortCpltCallback : callback for abort completion process.
269 (+) MspInitCallback : callback for Msp Init.
270 (+) MspDeInitCallback : callback for Msp DeInit.
271 This function takes as parameters the HAL peripheral handle, the Callback ID
272 and a pointer to the user callback function.
273 [..]
274 For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
275 [..]
276 Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
277 weak function.
278 HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
279 and the Callback ID.
280 This function allows to reset following callbacks:
281 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
282 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
283 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
284 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
285 (+) ListenCpltCallback : callback for end of listen mode.
286 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
287 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
288 (+) ErrorCallback : callback for error detection.
289 (+) AbortCpltCallback : callback for abort completion process.
290 (+) MspInitCallback : callback for Msp Init.
291 (+) MspDeInitCallback : callback for Msp DeInit.
292 [..]
293 For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
294 [..]
295 By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
296 all callbacks are set to the corresponding weak functions:
297 examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
298 Exception done for MspInit and MspDeInit functions that are
299 reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
300 these callbacks are null (not registered beforehand).
301 If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
302 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
303 [..]
304 Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
305 Exception done MspInit/MspDeInit functions that can be registered/unregistered
306 in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
307 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
308 Then, the user first registers the MspInit/MspDeInit user callbacks
309 using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
310 or HAL_I2C_Init() function.
311 [..]
312 When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
313 not defined, the callback registration feature is not available and all callbacks
314 are set to the corresponding weak functions.
315
316 [..]
317 (@) You can refer to the I2C HAL driver header file for more useful macros
318
319 @endverbatim
320 */
321
322 /* Includes ------------------------------------------------------------------*/
323 #include "stm32f0xx_hal.h"
324
325 /** @addtogroup STM32F0xx_HAL_Driver
326 * @{
327 */
328
329 /** @defgroup I2C I2C
330 * @brief I2C HAL module driver
331 * @{
332 */
333
334 #ifdef HAL_I2C_MODULE_ENABLED
335
336 /* Private typedef -----------------------------------------------------------*/
337 /* Private define ------------------------------------------------------------*/
338
339 /** @defgroup I2C_Private_Define I2C Private Define
340 * @{
341 */
342 #define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */
343 #define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */
344 #define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */
345 #define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */
346 #define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */
347 #define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */
348 #define I2C_TIMEOUT_TC (25U) /*!< 25 ms */
349 #define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */
350 #define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */
351 #define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */
352
353 #define MAX_NBYTE_SIZE 255U
354 #define SLAVE_ADDR_SHIFT 7U
355 #define SLAVE_ADDR_MSK 0x06U
356
357 /* Private define for @ref PreviousState usage */
358 #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
359 (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
360 (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
361 /*!< Mask State define, keep only RX and TX bits */
362 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
363 /*!< Default Value */
364 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
365 (uint32_t)HAL_I2C_MODE_MASTER))
366 /*!< Master Busy TX, combinaison of State LSB and Mode enum */
367 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
368 (uint32_t)HAL_I2C_MODE_MASTER))
369 /*!< Master Busy RX, combinaison of State LSB and Mode enum */
370 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
371 (uint32_t)HAL_I2C_MODE_SLAVE))
372 /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
373 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
374 (uint32_t)HAL_I2C_MODE_SLAVE))
375 /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
376 #define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
377 (uint32_t)HAL_I2C_MODE_MEM))
378 /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
379 #define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
380 (uint32_t)HAL_I2C_MODE_MEM))
381 /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
382
383
384 /* Private define to centralize the enable/disable of Interrupts */
385 #define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with
386 @ref I2C_XFER_LISTEN_IT */
387 #define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with
388 @ref I2C_XFER_LISTEN_IT */
389 #define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT
390 and @ref I2C_XFER_RX_IT */
391
392 #define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error
393 and NACK treatment */
394 #define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */
395 #define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */
396
397 /* Private define Sequential Transfer Options default/reset value */
398 #define I2C_NO_OPTION_FRAME (0xFFFF0000U)
399 /**
400 * @}
401 */
402
403 /* Private macros ------------------------------------------------------------*/
404 /** @addtogroup I2C_Private_Macro
405 * @{
406 */
407 /* Macro to get remaining data to transfer on DMA side */
408 #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)
409 /**
410 * @}
411 */
412
413 /* Private variables ---------------------------------------------------------*/
414 /* Private function prototypes -----------------------------------------------*/
415
416 /** @defgroup I2C_Private_Functions I2C Private Functions
417 * @{
418 */
419 /* Private functions to handle DMA transfer */
420 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
421 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
422 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
423 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
424 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
425 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
426
427
428 /* Private functions to handle IT transfer */
429 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
430 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
431 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
432 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
433 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
434 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
435 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
436
437 /* Private functions to handle IT transfer */
438 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
439 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
440 uint32_t Tickstart);
441 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
442 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
443 uint32_t Tickstart);
444
445 /* Private functions for I2C transfer IRQ handler */
446 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
447 uint32_t ITSources);
448 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
449 uint32_t ITSources);
450 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
451 uint32_t ITSources);
452 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
453 uint32_t ITSources);
454 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
455 uint32_t ITSources);
456 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
457 uint32_t ITSources);
458
459 /* Private functions to handle flags during polling transfer */
460 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
461 uint32_t Timeout, uint32_t Tickstart);
462 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
463 uint32_t Tickstart);
464 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
465 uint32_t Tickstart);
466 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
467 uint32_t Tickstart);
468 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
469 uint32_t Tickstart);
470
471 /* Private functions to centralize the enable/disable of Interrupts */
472 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
473 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
474
475 /* Private function to treat different error callback */
476 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
477
478 /* Private function to flush TXDR register */
479 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
480
481 /* Private function to handle start, restart or stop a transfer */
482 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
483 uint32_t Request);
484
485 /* Private function to Convert Specific options */
486 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
487 /**
488 * @}
489 */
490
491 /* Exported functions --------------------------------------------------------*/
492
493 /** @defgroup I2C_Exported_Functions I2C Exported Functions
494 * @{
495 */
496
497 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
498 * @brief Initialization and Configuration functions
499 *
500 @verbatim
501 ===============================================================================
502 ##### Initialization and de-initialization functions #####
503 ===============================================================================
504 [..] This subsection provides a set of functions allowing to initialize and
505 deinitialize the I2Cx peripheral:
506
507 (+) User must Implement HAL_I2C_MspInit() function in which he configures
508 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
509
510 (+) Call the function HAL_I2C_Init() to configure the selected device with
511 the selected configuration:
512 (++) Clock Timing
513 (++) Own Address 1
514 (++) Addressing mode (Master, Slave)
515 (++) Dual Addressing mode
516 (++) Own Address 2
517 (++) Own Address 2 Mask
518 (++) General call mode
519 (++) Nostretch mode
520
521 (+) Call the function HAL_I2C_DeInit() to restore the default configuration
522 of the selected I2Cx peripheral.
523
524 @endverbatim
525 * @{
526 */
527
528 /**
529 * @brief Initializes the I2C according to the specified parameters
530 * in the I2C_InitTypeDef and initialize the associated handle.
531 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
532 * the configuration information for the specified I2C.
533 * @retval HAL status
534 */
HAL_I2C_Init(I2C_HandleTypeDef * hi2c)535 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
536 {
537 /* Check the I2C handle allocation */
538 if (hi2c == NULL)
539 {
540 return HAL_ERROR;
541 }
542
543 /* Check the parameters */
544 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
545 assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
546 assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
547 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
548 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
549 assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
550 assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
551 assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
552
553 if (hi2c->State == HAL_I2C_STATE_RESET)
554 {
555 /* Allocate lock resource and initialize it */
556 hi2c->Lock = HAL_UNLOCKED;
557
558 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
559 /* Init the I2C Callback settings */
560 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
561 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
562 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
563 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
564 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
565 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
566 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
567 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
568 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
569 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
570
571 if (hi2c->MspInitCallback == NULL)
572 {
573 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
574 }
575
576 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
577 hi2c->MspInitCallback(hi2c);
578 #else
579 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
580 HAL_I2C_MspInit(hi2c);
581 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
582 }
583
584 hi2c->State = HAL_I2C_STATE_BUSY;
585
586 /* Disable the selected I2C peripheral */
587 __HAL_I2C_DISABLE(hi2c);
588
589 /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
590 /* Configure I2Cx: Frequency range */
591 hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
592
593 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
594 /* Disable Own Address1 before set the Own Address1 configuration */
595 hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
596
597 /* Configure I2Cx: Own Address1 and ack own address1 mode */
598 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
599 {
600 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
601 }
602 else /* I2C_ADDRESSINGMODE_10BIT */
603 {
604 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
605 }
606
607 /*---------------------------- I2Cx CR2 Configuration ----------------------*/
608 /* Configure I2Cx: Addressing Master mode */
609 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
610 {
611 hi2c->Instance->CR2 = (I2C_CR2_ADD10);
612 }
613 /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
614 hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
615
616 /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
617 /* Disable Own Address2 before set the Own Address2 configuration */
618 hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
619
620 /* Configure I2Cx: Dual mode and Own Address2 */
621 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
622 (hi2c->Init.OwnAddress2Masks << 8));
623
624 /*---------------------------- I2Cx CR1 Configuration ----------------------*/
625 /* Configure I2Cx: Generalcall and NoStretch mode */
626 hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
627
628 /* Enable the selected I2C peripheral */
629 __HAL_I2C_ENABLE(hi2c);
630
631 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
632 hi2c->State = HAL_I2C_STATE_READY;
633 hi2c->PreviousState = I2C_STATE_NONE;
634 hi2c->Mode = HAL_I2C_MODE_NONE;
635
636 return HAL_OK;
637 }
638
639 /**
640 * @brief DeInitialize the I2C peripheral.
641 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
642 * the configuration information for the specified I2C.
643 * @retval HAL status
644 */
HAL_I2C_DeInit(I2C_HandleTypeDef * hi2c)645 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
646 {
647 /* Check the I2C handle allocation */
648 if (hi2c == NULL)
649 {
650 return HAL_ERROR;
651 }
652
653 /* Check the parameters */
654 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
655
656 hi2c->State = HAL_I2C_STATE_BUSY;
657
658 /* Disable the I2C Peripheral Clock */
659 __HAL_I2C_DISABLE(hi2c);
660
661 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
662 if (hi2c->MspDeInitCallback == NULL)
663 {
664 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
665 }
666
667 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
668 hi2c->MspDeInitCallback(hi2c);
669 #else
670 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
671 HAL_I2C_MspDeInit(hi2c);
672 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
673
674 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
675 hi2c->State = HAL_I2C_STATE_RESET;
676 hi2c->PreviousState = I2C_STATE_NONE;
677 hi2c->Mode = HAL_I2C_MODE_NONE;
678
679 /* Release Lock */
680 __HAL_UNLOCK(hi2c);
681
682 return HAL_OK;
683 }
684
685 /**
686 * @brief Initialize the I2C MSP.
687 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
688 * the configuration information for the specified I2C.
689 * @retval None
690 */
HAL_I2C_MspInit(I2C_HandleTypeDef * hi2c)691 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
692 {
693 /* Prevent unused argument(s) compilation warning */
694 UNUSED(hi2c);
695
696 /* NOTE : This function should not be modified, when the callback is needed,
697 the HAL_I2C_MspInit could be implemented in the user file
698 */
699 }
700
701 /**
702 * @brief DeInitialize the I2C MSP.
703 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
704 * the configuration information for the specified I2C.
705 * @retval None
706 */
HAL_I2C_MspDeInit(I2C_HandleTypeDef * hi2c)707 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
708 {
709 /* Prevent unused argument(s) compilation warning */
710 UNUSED(hi2c);
711
712 /* NOTE : This function should not be modified, when the callback is needed,
713 the HAL_I2C_MspDeInit could be implemented in the user file
714 */
715 }
716
717 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
718 /**
719 * @brief Register a User I2C Callback
720 * To be used instead of the weak predefined callback
721 * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
722 * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
723 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
724 * the configuration information for the specified I2C.
725 * @param CallbackID ID of the callback to be registered
726 * This parameter can be one of the following values:
727 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
728 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
729 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
730 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
731 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
732 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
733 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
734 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
735 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
736 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
737 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
738 * @param pCallback pointer to the Callback function
739 * @retval HAL status
740 */
HAL_I2C_RegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID,pI2C_CallbackTypeDef pCallback)741 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
742 pI2C_CallbackTypeDef pCallback)
743 {
744 HAL_StatusTypeDef status = HAL_OK;
745
746 if (pCallback == NULL)
747 {
748 /* Update the error code */
749 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
750
751 return HAL_ERROR;
752 }
753
754 if (HAL_I2C_STATE_READY == hi2c->State)
755 {
756 switch (CallbackID)
757 {
758 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
759 hi2c->MasterTxCpltCallback = pCallback;
760 break;
761
762 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
763 hi2c->MasterRxCpltCallback = pCallback;
764 break;
765
766 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
767 hi2c->SlaveTxCpltCallback = pCallback;
768 break;
769
770 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
771 hi2c->SlaveRxCpltCallback = pCallback;
772 break;
773
774 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
775 hi2c->ListenCpltCallback = pCallback;
776 break;
777
778 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
779 hi2c->MemTxCpltCallback = pCallback;
780 break;
781
782 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
783 hi2c->MemRxCpltCallback = pCallback;
784 break;
785
786 case HAL_I2C_ERROR_CB_ID :
787 hi2c->ErrorCallback = pCallback;
788 break;
789
790 case HAL_I2C_ABORT_CB_ID :
791 hi2c->AbortCpltCallback = pCallback;
792 break;
793
794 case HAL_I2C_MSPINIT_CB_ID :
795 hi2c->MspInitCallback = pCallback;
796 break;
797
798 case HAL_I2C_MSPDEINIT_CB_ID :
799 hi2c->MspDeInitCallback = pCallback;
800 break;
801
802 default :
803 /* Update the error code */
804 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
805
806 /* Return error status */
807 status = HAL_ERROR;
808 break;
809 }
810 }
811 else if (HAL_I2C_STATE_RESET == hi2c->State)
812 {
813 switch (CallbackID)
814 {
815 case HAL_I2C_MSPINIT_CB_ID :
816 hi2c->MspInitCallback = pCallback;
817 break;
818
819 case HAL_I2C_MSPDEINIT_CB_ID :
820 hi2c->MspDeInitCallback = pCallback;
821 break;
822
823 default :
824 /* Update the error code */
825 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
826
827 /* Return error status */
828 status = HAL_ERROR;
829 break;
830 }
831 }
832 else
833 {
834 /* Update the error code */
835 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
836
837 /* Return error status */
838 status = HAL_ERROR;
839 }
840
841 return status;
842 }
843
844 /**
845 * @brief Unregister an I2C Callback
846 * I2C callback is redirected to the weak predefined callback
847 * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
848 * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
849 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
850 * the configuration information for the specified I2C.
851 * @param CallbackID ID of the callback to be unregistered
852 * This parameter can be one of the following values:
853 * This parameter can be one of the following values:
854 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
855 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
856 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
857 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
858 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
859 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
860 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
861 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
862 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
863 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
864 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
865 * @retval HAL status
866 */
HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID)867 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
868 {
869 HAL_StatusTypeDef status = HAL_OK;
870
871 if (HAL_I2C_STATE_READY == hi2c->State)
872 {
873 switch (CallbackID)
874 {
875 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
876 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
877 break;
878
879 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
880 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
881 break;
882
883 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
884 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
885 break;
886
887 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
888 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
889 break;
890
891 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
892 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
893 break;
894
895 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
896 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
897 break;
898
899 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
900 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
901 break;
902
903 case HAL_I2C_ERROR_CB_ID :
904 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
905 break;
906
907 case HAL_I2C_ABORT_CB_ID :
908 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
909 break;
910
911 case HAL_I2C_MSPINIT_CB_ID :
912 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
913 break;
914
915 case HAL_I2C_MSPDEINIT_CB_ID :
916 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
917 break;
918
919 default :
920 /* Update the error code */
921 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
922
923 /* Return error status */
924 status = HAL_ERROR;
925 break;
926 }
927 }
928 else if (HAL_I2C_STATE_RESET == hi2c->State)
929 {
930 switch (CallbackID)
931 {
932 case HAL_I2C_MSPINIT_CB_ID :
933 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
934 break;
935
936 case HAL_I2C_MSPDEINIT_CB_ID :
937 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
938 break;
939
940 default :
941 /* Update the error code */
942 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
943
944 /* Return error status */
945 status = HAL_ERROR;
946 break;
947 }
948 }
949 else
950 {
951 /* Update the error code */
952 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
953
954 /* Return error status */
955 status = HAL_ERROR;
956 }
957
958 return status;
959 }
960
961 /**
962 * @brief Register the Slave Address Match I2C Callback
963 * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
964 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
965 * the configuration information for the specified I2C.
966 * @param pCallback pointer to the Address Match Callback function
967 * @retval HAL status
968 */
HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef * hi2c,pI2C_AddrCallbackTypeDef pCallback)969 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
970 {
971 HAL_StatusTypeDef status = HAL_OK;
972
973 if (pCallback == NULL)
974 {
975 /* Update the error code */
976 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
977
978 return HAL_ERROR;
979 }
980
981 if (HAL_I2C_STATE_READY == hi2c->State)
982 {
983 hi2c->AddrCallback = pCallback;
984 }
985 else
986 {
987 /* Update the error code */
988 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
989
990 /* Return error status */
991 status = HAL_ERROR;
992 }
993
994 return status;
995 }
996
997 /**
998 * @brief UnRegister the Slave Address Match I2C Callback
999 * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
1000 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1001 * the configuration information for the specified I2C.
1002 * @retval HAL status
1003 */
HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef * hi2c)1004 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
1005 {
1006 HAL_StatusTypeDef status = HAL_OK;
1007
1008 if (HAL_I2C_STATE_READY == hi2c->State)
1009 {
1010 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
1011 }
1012 else
1013 {
1014 /* Update the error code */
1015 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
1016
1017 /* Return error status */
1018 status = HAL_ERROR;
1019 }
1020
1021 return status;
1022 }
1023
1024 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
1025
1026 /**
1027 * @}
1028 */
1029
1030 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
1031 * @brief Data transfers functions
1032 *
1033 @verbatim
1034 ===============================================================================
1035 ##### IO operation functions #####
1036 ===============================================================================
1037 [..]
1038 This subsection provides a set of functions allowing to manage the I2C data
1039 transfers.
1040
1041 (#) There are two modes of transfer:
1042 (++) Blocking mode : The communication is performed in the polling mode.
1043 The status of all data processing is returned by the same function
1044 after finishing transfer.
1045 (++) No-Blocking mode : The communication is performed using Interrupts
1046 or DMA. These functions return the status of the transfer startup.
1047 The end of the data processing will be indicated through the
1048 dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
1049 using DMA mode.
1050
1051 (#) Blocking mode functions are :
1052 (++) HAL_I2C_Master_Transmit()
1053 (++) HAL_I2C_Master_Receive()
1054 (++) HAL_I2C_Slave_Transmit()
1055 (++) HAL_I2C_Slave_Receive()
1056 (++) HAL_I2C_Mem_Write()
1057 (++) HAL_I2C_Mem_Read()
1058 (++) HAL_I2C_IsDeviceReady()
1059
1060 (#) No-Blocking mode functions with Interrupt are :
1061 (++) HAL_I2C_Master_Transmit_IT()
1062 (++) HAL_I2C_Master_Receive_IT()
1063 (++) HAL_I2C_Slave_Transmit_IT()
1064 (++) HAL_I2C_Slave_Receive_IT()
1065 (++) HAL_I2C_Mem_Write_IT()
1066 (++) HAL_I2C_Mem_Read_IT()
1067 (++) HAL_I2C_Master_Seq_Transmit_IT()
1068 (++) HAL_I2C_Master_Seq_Receive_IT()
1069 (++) HAL_I2C_Slave_Seq_Transmit_IT()
1070 (++) HAL_I2C_Slave_Seq_Receive_IT()
1071 (++) HAL_I2C_EnableListen_IT()
1072 (++) HAL_I2C_DisableListen_IT()
1073 (++) HAL_I2C_Master_Abort_IT()
1074
1075 (#) No-Blocking mode functions with DMA are :
1076 (++) HAL_I2C_Master_Transmit_DMA()
1077 (++) HAL_I2C_Master_Receive_DMA()
1078 (++) HAL_I2C_Slave_Transmit_DMA()
1079 (++) HAL_I2C_Slave_Receive_DMA()
1080 (++) HAL_I2C_Mem_Write_DMA()
1081 (++) HAL_I2C_Mem_Read_DMA()
1082 (++) HAL_I2C_Master_Seq_Transmit_DMA()
1083 (++) HAL_I2C_Master_Seq_Receive_DMA()
1084 (++) HAL_I2C_Slave_Seq_Transmit_DMA()
1085 (++) HAL_I2C_Slave_Seq_Receive_DMA()
1086
1087 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
1088 (++) HAL_I2C_MasterTxCpltCallback()
1089 (++) HAL_I2C_MasterRxCpltCallback()
1090 (++) HAL_I2C_SlaveTxCpltCallback()
1091 (++) HAL_I2C_SlaveRxCpltCallback()
1092 (++) HAL_I2C_MemTxCpltCallback()
1093 (++) HAL_I2C_MemRxCpltCallback()
1094 (++) HAL_I2C_AddrCallback()
1095 (++) HAL_I2C_ListenCpltCallback()
1096 (++) HAL_I2C_ErrorCallback()
1097 (++) HAL_I2C_AbortCpltCallback()
1098
1099 @endverbatim
1100 * @{
1101 */
1102
1103 /**
1104 * @brief Transmits in master mode an amount of data in blocking mode.
1105 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1106 * the configuration information for the specified I2C.
1107 * @param DevAddress Target device address: The device 7 bits address value
1108 * in datasheet must be shifted to the left before calling the interface
1109 * @param pData Pointer to data buffer
1110 * @param Size Amount of data to be sent
1111 * @param Timeout Timeout duration
1112 * @retval HAL status
1113 */
HAL_I2C_Master_Transmit(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1114 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1115 uint16_t Size, uint32_t Timeout)
1116 {
1117 uint32_t tickstart;
1118
1119 if (hi2c->State == HAL_I2C_STATE_READY)
1120 {
1121 /* Process Locked */
1122 __HAL_LOCK(hi2c);
1123
1124 /* Init tickstart for timeout management*/
1125 tickstart = HAL_GetTick();
1126
1127 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1128 {
1129 return HAL_ERROR;
1130 }
1131
1132 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1133 hi2c->Mode = HAL_I2C_MODE_MASTER;
1134 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1135
1136 /* Prepare transfer parameters */
1137 hi2c->pBuffPtr = pData;
1138 hi2c->XferCount = Size;
1139 hi2c->XferISR = NULL;
1140
1141 /* Send Slave Address */
1142 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1143 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1144 {
1145 hi2c->XferSize = MAX_NBYTE_SIZE;
1146 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1147 I2C_GENERATE_START_WRITE);
1148 }
1149 else
1150 {
1151 hi2c->XferSize = hi2c->XferCount;
1152 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1153 I2C_GENERATE_START_WRITE);
1154 }
1155
1156 while (hi2c->XferCount > 0U)
1157 {
1158 /* Wait until TXIS flag is set */
1159 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1160 {
1161 return HAL_ERROR;
1162 }
1163 /* Write data to TXDR */
1164 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1165
1166 /* Increment Buffer pointer */
1167 hi2c->pBuffPtr++;
1168
1169 hi2c->XferCount--;
1170 hi2c->XferSize--;
1171
1172 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1173 {
1174 /* Wait until TCR flag is set */
1175 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1176 {
1177 return HAL_ERROR;
1178 }
1179
1180 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1181 {
1182 hi2c->XferSize = MAX_NBYTE_SIZE;
1183 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1184 I2C_NO_STARTSTOP);
1185 }
1186 else
1187 {
1188 hi2c->XferSize = hi2c->XferCount;
1189 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1190 I2C_NO_STARTSTOP);
1191 }
1192 }
1193 }
1194
1195 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1196 /* Wait until STOPF flag is set */
1197 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1198 {
1199 return HAL_ERROR;
1200 }
1201
1202 /* Clear STOP Flag */
1203 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1204
1205 /* Clear Configuration Register 2 */
1206 I2C_RESET_CR2(hi2c);
1207
1208 hi2c->State = HAL_I2C_STATE_READY;
1209 hi2c->Mode = HAL_I2C_MODE_NONE;
1210
1211 /* Process Unlocked */
1212 __HAL_UNLOCK(hi2c);
1213
1214 return HAL_OK;
1215 }
1216 else
1217 {
1218 return HAL_BUSY;
1219 }
1220 }
1221
1222 /**
1223 * @brief Receives in master mode an amount of data in blocking mode.
1224 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1225 * the configuration information for the specified I2C.
1226 * @param DevAddress Target device address: The device 7 bits address value
1227 * in datasheet must be shifted to the left before calling the interface
1228 * @param pData Pointer to data buffer
1229 * @param Size Amount of data to be sent
1230 * @param Timeout Timeout duration
1231 * @retval HAL status
1232 */
HAL_I2C_Master_Receive(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1233 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1234 uint16_t Size, uint32_t Timeout)
1235 {
1236 uint32_t tickstart;
1237
1238 if (hi2c->State == HAL_I2C_STATE_READY)
1239 {
1240 /* Process Locked */
1241 __HAL_LOCK(hi2c);
1242
1243 /* Init tickstart for timeout management*/
1244 tickstart = HAL_GetTick();
1245
1246 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1247 {
1248 return HAL_ERROR;
1249 }
1250
1251 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1252 hi2c->Mode = HAL_I2C_MODE_MASTER;
1253 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1254
1255 /* Prepare transfer parameters */
1256 hi2c->pBuffPtr = pData;
1257 hi2c->XferCount = Size;
1258 hi2c->XferISR = NULL;
1259
1260 /* Send Slave Address */
1261 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1262 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1263 {
1264 hi2c->XferSize = MAX_NBYTE_SIZE;
1265 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1266 I2C_GENERATE_START_READ);
1267 }
1268 else
1269 {
1270 hi2c->XferSize = hi2c->XferCount;
1271 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1272 I2C_GENERATE_START_READ);
1273 }
1274
1275 while (hi2c->XferCount > 0U)
1276 {
1277 /* Wait until RXNE flag is set */
1278 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1279 {
1280 return HAL_ERROR;
1281 }
1282
1283 /* Read data from RXDR */
1284 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1285
1286 /* Increment Buffer pointer */
1287 hi2c->pBuffPtr++;
1288
1289 hi2c->XferSize--;
1290 hi2c->XferCount--;
1291
1292 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1293 {
1294 /* Wait until TCR flag is set */
1295 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1296 {
1297 return HAL_ERROR;
1298 }
1299
1300 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1301 {
1302 hi2c->XferSize = MAX_NBYTE_SIZE;
1303 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1304 I2C_NO_STARTSTOP);
1305 }
1306 else
1307 {
1308 hi2c->XferSize = hi2c->XferCount;
1309 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1310 I2C_NO_STARTSTOP);
1311 }
1312 }
1313 }
1314
1315 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1316 /* Wait until STOPF flag is set */
1317 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1318 {
1319 return HAL_ERROR;
1320 }
1321
1322 /* Clear STOP Flag */
1323 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1324
1325 /* Clear Configuration Register 2 */
1326 I2C_RESET_CR2(hi2c);
1327
1328 hi2c->State = HAL_I2C_STATE_READY;
1329 hi2c->Mode = HAL_I2C_MODE_NONE;
1330
1331 /* Process Unlocked */
1332 __HAL_UNLOCK(hi2c);
1333
1334 return HAL_OK;
1335 }
1336 else
1337 {
1338 return HAL_BUSY;
1339 }
1340 }
1341
1342 /**
1343 * @brief Transmits in slave mode an amount of data in blocking mode.
1344 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1345 * the configuration information for the specified I2C.
1346 * @param pData Pointer to data buffer
1347 * @param Size Amount of data to be sent
1348 * @param Timeout Timeout duration
1349 * @retval HAL status
1350 */
HAL_I2C_Slave_Transmit(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1351 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
1352 uint32_t Timeout)
1353 {
1354 uint32_t tickstart;
1355
1356 if (hi2c->State == HAL_I2C_STATE_READY)
1357 {
1358 if ((pData == NULL) || (Size == 0U))
1359 {
1360 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1361 return HAL_ERROR;
1362 }
1363 /* Process Locked */
1364 __HAL_LOCK(hi2c);
1365
1366 /* Init tickstart for timeout management*/
1367 tickstart = HAL_GetTick();
1368
1369 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1370 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1371 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1372
1373 /* Prepare transfer parameters */
1374 hi2c->pBuffPtr = pData;
1375 hi2c->XferCount = Size;
1376 hi2c->XferISR = NULL;
1377
1378 /* Enable Address Acknowledge */
1379 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1380
1381 /* Wait until ADDR flag is set */
1382 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1383 {
1384 /* Disable Address Acknowledge */
1385 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1386 return HAL_ERROR;
1387 }
1388
1389 /* Preload TX data if no stretch enable */
1390 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
1391 {
1392 /* Preload TX register */
1393 /* Write data to TXDR */
1394 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1395
1396 /* Increment Buffer pointer */
1397 hi2c->pBuffPtr++;
1398
1399 hi2c->XferCount--;
1400 }
1401
1402 /* Clear ADDR flag */
1403 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1404
1405 /* If 10bit addressing mode is selected */
1406 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
1407 {
1408 /* Wait until ADDR flag is set */
1409 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1410 {
1411 /* Disable Address Acknowledge */
1412 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1413 return HAL_ERROR;
1414 }
1415
1416 /* Clear ADDR flag */
1417 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1418 }
1419
1420 /* Wait until DIR flag is set Transmitter mode */
1421 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
1422 {
1423 /* Disable Address Acknowledge */
1424 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1425 return HAL_ERROR;
1426 }
1427
1428 while (hi2c->XferCount > 0U)
1429 {
1430 /* Wait until TXIS flag is set */
1431 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1432 {
1433 /* Disable Address Acknowledge */
1434 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1435 return HAL_ERROR;
1436 }
1437
1438 /* Write data to TXDR */
1439 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1440
1441 /* Increment Buffer pointer */
1442 hi2c->pBuffPtr++;
1443
1444 hi2c->XferCount--;
1445 }
1446
1447 /* Wait until AF flag is set */
1448 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
1449 {
1450 /* Disable Address Acknowledge */
1451 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1452 return HAL_ERROR;
1453 }
1454
1455 /* Flush TX register */
1456 I2C_Flush_TXDR(hi2c);
1457
1458 /* Clear AF flag */
1459 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
1460
1461 /* Wait until STOP flag is set */
1462 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1463 {
1464 /* Disable Address Acknowledge */
1465 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1466
1467 return HAL_ERROR;
1468 }
1469
1470 /* Clear STOP flag */
1471 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1472
1473 /* Wait until BUSY flag is reset */
1474 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1475 {
1476 /* Disable Address Acknowledge */
1477 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1478 return HAL_ERROR;
1479 }
1480
1481 /* Disable Address Acknowledge */
1482 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1483
1484 hi2c->State = HAL_I2C_STATE_READY;
1485 hi2c->Mode = HAL_I2C_MODE_NONE;
1486
1487 /* Process Unlocked */
1488 __HAL_UNLOCK(hi2c);
1489
1490 return HAL_OK;
1491 }
1492 else
1493 {
1494 return HAL_BUSY;
1495 }
1496 }
1497
1498 /**
1499 * @brief Receive in slave mode an amount of data in blocking mode
1500 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1501 * the configuration information for the specified I2C.
1502 * @param pData Pointer to data buffer
1503 * @param Size Amount of data to be sent
1504 * @param Timeout Timeout duration
1505 * @retval HAL status
1506 */
HAL_I2C_Slave_Receive(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1507 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
1508 uint32_t Timeout)
1509 {
1510 uint32_t tickstart;
1511
1512 if (hi2c->State == HAL_I2C_STATE_READY)
1513 {
1514 if ((pData == NULL) || (Size == 0U))
1515 {
1516 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1517 return HAL_ERROR;
1518 }
1519 /* Process Locked */
1520 __HAL_LOCK(hi2c);
1521
1522 /* Init tickstart for timeout management*/
1523 tickstart = HAL_GetTick();
1524
1525 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1526 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1527 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1528
1529 /* Prepare transfer parameters */
1530 hi2c->pBuffPtr = pData;
1531 hi2c->XferCount = Size;
1532 hi2c->XferSize = hi2c->XferCount;
1533 hi2c->XferISR = NULL;
1534
1535 /* Enable Address Acknowledge */
1536 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1537
1538 /* Wait until ADDR flag is set */
1539 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1540 {
1541 /* Disable Address Acknowledge */
1542 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1543 return HAL_ERROR;
1544 }
1545
1546 /* Clear ADDR flag */
1547 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1548
1549 /* Wait until DIR flag is reset Receiver mode */
1550 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
1551 {
1552 /* Disable Address Acknowledge */
1553 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1554 return HAL_ERROR;
1555 }
1556
1557 while (hi2c->XferCount > 0U)
1558 {
1559 /* Wait until RXNE flag is set */
1560 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1561 {
1562 /* Disable Address Acknowledge */
1563 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1564
1565 /* Store Last receive data if any */
1566 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
1567 {
1568 /* Read data from RXDR */
1569 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1570
1571 /* Increment Buffer pointer */
1572 hi2c->pBuffPtr++;
1573
1574 hi2c->XferCount--;
1575 hi2c->XferSize--;
1576 }
1577
1578 return HAL_ERROR;
1579 }
1580
1581 /* Read data from RXDR */
1582 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1583
1584 /* Increment Buffer pointer */
1585 hi2c->pBuffPtr++;
1586
1587 hi2c->XferCount--;
1588 hi2c->XferSize--;
1589 }
1590
1591 /* Wait until STOP flag is set */
1592 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1593 {
1594 /* Disable Address Acknowledge */
1595 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1596 return HAL_ERROR;
1597 }
1598
1599 /* Clear STOP flag */
1600 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1601
1602 /* Wait until BUSY flag is reset */
1603 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1604 {
1605 /* Disable Address Acknowledge */
1606 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1607 return HAL_ERROR;
1608 }
1609
1610 /* Disable Address Acknowledge */
1611 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1612
1613 hi2c->State = HAL_I2C_STATE_READY;
1614 hi2c->Mode = HAL_I2C_MODE_NONE;
1615
1616 /* Process Unlocked */
1617 __HAL_UNLOCK(hi2c);
1618
1619 return HAL_OK;
1620 }
1621 else
1622 {
1623 return HAL_BUSY;
1624 }
1625 }
1626
1627 /**
1628 * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
1629 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1630 * the configuration information for the specified I2C.
1631 * @param DevAddress Target device address: The device 7 bits address value
1632 * in datasheet must be shifted to the left before calling the interface
1633 * @param pData Pointer to data buffer
1634 * @param Size Amount of data to be sent
1635 * @retval HAL status
1636 */
HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1637 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1638 uint16_t Size)
1639 {
1640 uint32_t xfermode;
1641
1642 if (hi2c->State == HAL_I2C_STATE_READY)
1643 {
1644 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1645 {
1646 return HAL_BUSY;
1647 }
1648
1649 /* Process Locked */
1650 __HAL_LOCK(hi2c);
1651
1652 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1653 hi2c->Mode = HAL_I2C_MODE_MASTER;
1654 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1655
1656 /* Prepare transfer parameters */
1657 hi2c->pBuffPtr = pData;
1658 hi2c->XferCount = Size;
1659 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1660 hi2c->XferISR = I2C_Master_ISR_IT;
1661
1662 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1663 {
1664 hi2c->XferSize = MAX_NBYTE_SIZE;
1665 xfermode = I2C_RELOAD_MODE;
1666 }
1667 else
1668 {
1669 hi2c->XferSize = hi2c->XferCount;
1670 xfermode = I2C_AUTOEND_MODE;
1671 }
1672
1673 /* Send Slave Address */
1674 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1675 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
1676
1677 /* Process Unlocked */
1678 __HAL_UNLOCK(hi2c);
1679
1680 /* Note : The I2C interrupts must be enabled after unlocking current process
1681 to avoid the risk of I2C interrupt handle execution before current
1682 process unlock */
1683
1684 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1685 /* possible to enable all of these */
1686 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1687 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1688 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
1689
1690 return HAL_OK;
1691 }
1692 else
1693 {
1694 return HAL_BUSY;
1695 }
1696 }
1697
1698 /**
1699 * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
1700 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1701 * the configuration information for the specified I2C.
1702 * @param DevAddress Target device address: The device 7 bits address value
1703 * in datasheet must be shifted to the left before calling the interface
1704 * @param pData Pointer to data buffer
1705 * @param Size Amount of data to be sent
1706 * @retval HAL status
1707 */
HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1708 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1709 uint16_t Size)
1710 {
1711 uint32_t xfermode;
1712
1713 if (hi2c->State == HAL_I2C_STATE_READY)
1714 {
1715 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1716 {
1717 return HAL_BUSY;
1718 }
1719
1720 /* Process Locked */
1721 __HAL_LOCK(hi2c);
1722
1723 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1724 hi2c->Mode = HAL_I2C_MODE_MASTER;
1725 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1726
1727 /* Prepare transfer parameters */
1728 hi2c->pBuffPtr = pData;
1729 hi2c->XferCount = Size;
1730 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1731 hi2c->XferISR = I2C_Master_ISR_IT;
1732
1733 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1734 {
1735 hi2c->XferSize = MAX_NBYTE_SIZE;
1736 xfermode = I2C_RELOAD_MODE;
1737 }
1738 else
1739 {
1740 hi2c->XferSize = hi2c->XferCount;
1741 xfermode = I2C_AUTOEND_MODE;
1742 }
1743
1744 /* Send Slave Address */
1745 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1746 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
1747
1748 /* Process Unlocked */
1749 __HAL_UNLOCK(hi2c);
1750
1751 /* Note : The I2C interrupts must be enabled after unlocking current process
1752 to avoid the risk of I2C interrupt handle execution before current
1753 process unlock */
1754
1755 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1756 /* possible to enable all of these */
1757 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1758 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1759 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
1760
1761 return HAL_OK;
1762 }
1763 else
1764 {
1765 return HAL_BUSY;
1766 }
1767 }
1768
1769 /**
1770 * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
1771 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1772 * the configuration information for the specified I2C.
1773 * @param pData Pointer to data buffer
1774 * @param Size Amount of data to be sent
1775 * @retval HAL status
1776 */
HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1777 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1778 {
1779 if (hi2c->State == HAL_I2C_STATE_READY)
1780 {
1781 /* Process Locked */
1782 __HAL_LOCK(hi2c);
1783
1784 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1785 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1786 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1787
1788 /* Enable Address Acknowledge */
1789 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1790
1791 /* Prepare transfer parameters */
1792 hi2c->pBuffPtr = pData;
1793 hi2c->XferCount = Size;
1794 hi2c->XferSize = hi2c->XferCount;
1795 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1796 hi2c->XferISR = I2C_Slave_ISR_IT;
1797
1798 /* Preload TX data if no stretch enable */
1799 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
1800 {
1801 /* Preload TX register */
1802 /* Write data to TXDR */
1803 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1804
1805 /* Increment Buffer pointer */
1806 hi2c->pBuffPtr++;
1807
1808 hi2c->XferCount--;
1809 hi2c->XferSize--;
1810 }
1811
1812 /* Process Unlocked */
1813 __HAL_UNLOCK(hi2c);
1814
1815 /* Note : The I2C interrupts must be enabled after unlocking current process
1816 to avoid the risk of I2C interrupt handle execution before current
1817 process unlock */
1818
1819 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1820 /* possible to enable all of these */
1821 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1822 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1823 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
1824
1825 return HAL_OK;
1826 }
1827 else
1828 {
1829 return HAL_BUSY;
1830 }
1831 }
1832
1833 /**
1834 * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
1835 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1836 * the configuration information for the specified I2C.
1837 * @param pData Pointer to data buffer
1838 * @param Size Amount of data to be sent
1839 * @retval HAL status
1840 */
HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1841 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1842 {
1843 if (hi2c->State == HAL_I2C_STATE_READY)
1844 {
1845 /* Process Locked */
1846 __HAL_LOCK(hi2c);
1847
1848 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1849 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1850 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1851
1852 /* Enable Address Acknowledge */
1853 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1854
1855 /* Prepare transfer parameters */
1856 hi2c->pBuffPtr = pData;
1857 hi2c->XferCount = Size;
1858 hi2c->XferSize = hi2c->XferCount;
1859 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1860 hi2c->XferISR = I2C_Slave_ISR_IT;
1861
1862 /* Process Unlocked */
1863 __HAL_UNLOCK(hi2c);
1864
1865 /* Note : The I2C interrupts must be enabled after unlocking current process
1866 to avoid the risk of I2C interrupt handle execution before current
1867 process unlock */
1868
1869 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1870 /* possible to enable all of these */
1871 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1872 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1873 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
1874
1875 return HAL_OK;
1876 }
1877 else
1878 {
1879 return HAL_BUSY;
1880 }
1881 }
1882
1883 /**
1884 * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
1885 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1886 * the configuration information for the specified I2C.
1887 * @param DevAddress Target device address: The device 7 bits address value
1888 * in datasheet must be shifted to the left before calling the interface
1889 * @param pData Pointer to data buffer
1890 * @param Size Amount of data to be sent
1891 * @retval HAL status
1892 */
HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1893 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1894 uint16_t Size)
1895 {
1896 uint32_t xfermode;
1897 HAL_StatusTypeDef dmaxferstatus;
1898
1899 if (hi2c->State == HAL_I2C_STATE_READY)
1900 {
1901 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1902 {
1903 return HAL_BUSY;
1904 }
1905
1906 /* Process Locked */
1907 __HAL_LOCK(hi2c);
1908
1909 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1910 hi2c->Mode = HAL_I2C_MODE_MASTER;
1911 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1912
1913 /* Prepare transfer parameters */
1914 hi2c->pBuffPtr = pData;
1915 hi2c->XferCount = Size;
1916 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1917 hi2c->XferISR = I2C_Master_ISR_DMA;
1918
1919 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1920 {
1921 hi2c->XferSize = MAX_NBYTE_SIZE;
1922 xfermode = I2C_RELOAD_MODE;
1923 }
1924 else
1925 {
1926 hi2c->XferSize = hi2c->XferCount;
1927 xfermode = I2C_AUTOEND_MODE;
1928 }
1929
1930 if (hi2c->XferSize > 0U)
1931 {
1932 if (hi2c->hdmatx != NULL)
1933 {
1934 /* Set the I2C DMA transfer complete callback */
1935 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
1936
1937 /* Set the DMA error callback */
1938 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
1939
1940 /* Set the unused DMA callbacks to NULL */
1941 hi2c->hdmatx->XferHalfCpltCallback = NULL;
1942 hi2c->hdmatx->XferAbortCallback = NULL;
1943
1944 /* Enable the DMA channel */
1945 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
1946 hi2c->XferSize);
1947 }
1948 else
1949 {
1950 /* Update I2C state */
1951 hi2c->State = HAL_I2C_STATE_READY;
1952 hi2c->Mode = HAL_I2C_MODE_NONE;
1953
1954 /* Update I2C error code */
1955 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
1956
1957 /* Process Unlocked */
1958 __HAL_UNLOCK(hi2c);
1959
1960 return HAL_ERROR;
1961 }
1962
1963 if (dmaxferstatus == HAL_OK)
1964 {
1965 /* Send Slave Address */
1966 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1967 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
1968
1969 /* Update XferCount value */
1970 hi2c->XferCount -= hi2c->XferSize;
1971
1972 /* Process Unlocked */
1973 __HAL_UNLOCK(hi2c);
1974
1975 /* Note : The I2C interrupts must be enabled after unlocking current process
1976 to avoid the risk of I2C interrupt handle execution before current
1977 process unlock */
1978 /* Enable ERR and NACK interrupts */
1979 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
1980
1981 /* Enable DMA Request */
1982 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
1983 }
1984 else
1985 {
1986 /* Update I2C state */
1987 hi2c->State = HAL_I2C_STATE_READY;
1988 hi2c->Mode = HAL_I2C_MODE_NONE;
1989
1990 /* Update I2C error code */
1991 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
1992
1993 /* Process Unlocked */
1994 __HAL_UNLOCK(hi2c);
1995
1996 return HAL_ERROR;
1997 }
1998 }
1999 else
2000 {
2001 /* Update Transfer ISR function pointer */
2002 hi2c->XferISR = I2C_Master_ISR_IT;
2003
2004 /* Send Slave Address */
2005 /* Set NBYTES to write and generate START condition */
2006 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2007 I2C_GENERATE_START_WRITE);
2008
2009 /* Process Unlocked */
2010 __HAL_UNLOCK(hi2c);
2011
2012 /* Note : The I2C interrupts must be enabled after unlocking current process
2013 to avoid the risk of I2C interrupt handle execution before current
2014 process unlock */
2015 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2016 /* possible to enable all of these */
2017 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2018 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2019 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2020 }
2021
2022 return HAL_OK;
2023 }
2024 else
2025 {
2026 return HAL_BUSY;
2027 }
2028 }
2029
2030 /**
2031 * @brief Receive in master mode an amount of data in non-blocking mode with DMA
2032 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2033 * the configuration information for the specified I2C.
2034 * @param DevAddress Target device address: The device 7 bits address value
2035 * in datasheet must be shifted to the left before calling the interface
2036 * @param pData Pointer to data buffer
2037 * @param Size Amount of data to be sent
2038 * @retval HAL status
2039 */
HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)2040 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
2041 uint16_t Size)
2042 {
2043 uint32_t xfermode;
2044 HAL_StatusTypeDef dmaxferstatus;
2045
2046 if (hi2c->State == HAL_I2C_STATE_READY)
2047 {
2048 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2049 {
2050 return HAL_BUSY;
2051 }
2052
2053 /* Process Locked */
2054 __HAL_LOCK(hi2c);
2055
2056 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2057 hi2c->Mode = HAL_I2C_MODE_MASTER;
2058 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2059
2060 /* Prepare transfer parameters */
2061 hi2c->pBuffPtr = pData;
2062 hi2c->XferCount = Size;
2063 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2064 hi2c->XferISR = I2C_Master_ISR_DMA;
2065
2066 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2067 {
2068 hi2c->XferSize = MAX_NBYTE_SIZE;
2069 xfermode = I2C_RELOAD_MODE;
2070 }
2071 else
2072 {
2073 hi2c->XferSize = hi2c->XferCount;
2074 xfermode = I2C_AUTOEND_MODE;
2075 }
2076
2077 if (hi2c->XferSize > 0U)
2078 {
2079 if (hi2c->hdmarx != NULL)
2080 {
2081 /* Set the I2C DMA transfer complete callback */
2082 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
2083
2084 /* Set the DMA error callback */
2085 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2086
2087 /* Set the unused DMA callbacks to NULL */
2088 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2089 hi2c->hdmarx->XferAbortCallback = NULL;
2090
2091 /* Enable the DMA channel */
2092 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2093 hi2c->XferSize);
2094 }
2095 else
2096 {
2097 /* Update I2C state */
2098 hi2c->State = HAL_I2C_STATE_READY;
2099 hi2c->Mode = HAL_I2C_MODE_NONE;
2100
2101 /* Update I2C error code */
2102 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2103
2104 /* Process Unlocked */
2105 __HAL_UNLOCK(hi2c);
2106
2107 return HAL_ERROR;
2108 }
2109
2110 if (dmaxferstatus == HAL_OK)
2111 {
2112 /* Send Slave Address */
2113 /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2114 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
2115
2116 /* Update XferCount value */
2117 hi2c->XferCount -= hi2c->XferSize;
2118
2119 /* Process Unlocked */
2120 __HAL_UNLOCK(hi2c);
2121
2122 /* Note : The I2C interrupts must be enabled after unlocking current process
2123 to avoid the risk of I2C interrupt handle execution before current
2124 process unlock */
2125 /* Enable ERR and NACK interrupts */
2126 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2127
2128 /* Enable DMA Request */
2129 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2130 }
2131 else
2132 {
2133 /* Update I2C state */
2134 hi2c->State = HAL_I2C_STATE_READY;
2135 hi2c->Mode = HAL_I2C_MODE_NONE;
2136
2137 /* Update I2C error code */
2138 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2139
2140 /* Process Unlocked */
2141 __HAL_UNLOCK(hi2c);
2142
2143 return HAL_ERROR;
2144 }
2145 }
2146 else
2147 {
2148 /* Update Transfer ISR function pointer */
2149 hi2c->XferISR = I2C_Master_ISR_IT;
2150
2151 /* Send Slave Address */
2152 /* Set NBYTES to read and generate START condition */
2153 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2154 I2C_GENERATE_START_READ);
2155
2156 /* Process Unlocked */
2157 __HAL_UNLOCK(hi2c);
2158
2159 /* Note : The I2C interrupts must be enabled after unlocking current process
2160 to avoid the risk of I2C interrupt handle execution before current
2161 process unlock */
2162 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2163 /* possible to enable all of these */
2164 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2165 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2166 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2167 }
2168
2169 return HAL_OK;
2170 }
2171 else
2172 {
2173 return HAL_BUSY;
2174 }
2175 }
2176
2177 /**
2178 * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
2179 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2180 * the configuration information for the specified I2C.
2181 * @param pData Pointer to data buffer
2182 * @param Size Amount of data to be sent
2183 * @retval HAL status
2184 */
HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2185 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2186 {
2187 HAL_StatusTypeDef dmaxferstatus;
2188
2189 if (hi2c->State == HAL_I2C_STATE_READY)
2190 {
2191 if ((pData == NULL) || (Size == 0U))
2192 {
2193 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2194 return HAL_ERROR;
2195 }
2196 /* Process Locked */
2197 __HAL_LOCK(hi2c);
2198
2199 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2200 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2201 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2202
2203 /* Prepare transfer parameters */
2204 hi2c->pBuffPtr = pData;
2205 hi2c->XferCount = Size;
2206 hi2c->XferSize = hi2c->XferCount;
2207 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2208 hi2c->XferISR = I2C_Slave_ISR_DMA;
2209
2210 /* Preload TX data if no stretch enable */
2211 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
2212 {
2213 /* Preload TX register */
2214 /* Write data to TXDR */
2215 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
2216
2217 /* Increment Buffer pointer */
2218 hi2c->pBuffPtr++;
2219
2220 hi2c->XferCount--;
2221 hi2c->XferSize--;
2222 }
2223
2224 if (hi2c->XferCount != 0U)
2225 {
2226 if (hi2c->hdmatx != NULL)
2227 {
2228 /* Set the I2C DMA transfer complete callback */
2229 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
2230
2231 /* Set the DMA error callback */
2232 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2233
2234 /* Set the unused DMA callbacks to NULL */
2235 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2236 hi2c->hdmatx->XferAbortCallback = NULL;
2237
2238 /* Enable the DMA channel */
2239 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx,
2240 (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
2241 hi2c->XferSize);
2242 }
2243 else
2244 {
2245 /* Update I2C state */
2246 hi2c->State = HAL_I2C_STATE_LISTEN;
2247 hi2c->Mode = HAL_I2C_MODE_NONE;
2248
2249 /* Update I2C error code */
2250 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2251
2252 /* Process Unlocked */
2253 __HAL_UNLOCK(hi2c);
2254
2255 return HAL_ERROR;
2256 }
2257
2258 if (dmaxferstatus == HAL_OK)
2259 {
2260 /* Enable Address Acknowledge */
2261 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2262
2263 /* Process Unlocked */
2264 __HAL_UNLOCK(hi2c);
2265
2266 /* Note : The I2C interrupts must be enabled after unlocking current process
2267 to avoid the risk of I2C interrupt handle execution before current
2268 process unlock */
2269 /* Enable ERR, STOP, NACK, ADDR interrupts */
2270 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2271
2272 /* Enable DMA Request */
2273 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
2274 }
2275 else
2276 {
2277 /* Update I2C state */
2278 hi2c->State = HAL_I2C_STATE_LISTEN;
2279 hi2c->Mode = HAL_I2C_MODE_NONE;
2280
2281 /* Update I2C error code */
2282 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2283
2284 /* Process Unlocked */
2285 __HAL_UNLOCK(hi2c);
2286
2287 return HAL_ERROR;
2288 }
2289 }
2290 else
2291 {
2292 /* Enable Address Acknowledge */
2293 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2294
2295 /* Process Unlocked */
2296 __HAL_UNLOCK(hi2c);
2297
2298 /* Note : The I2C interrupts must be enabled after unlocking current process
2299 to avoid the risk of I2C interrupt handle execution before current
2300 process unlock */
2301 /* Enable ERR, STOP, NACK, ADDR interrupts */
2302 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2303 }
2304
2305 return HAL_OK;
2306 }
2307 else
2308 {
2309 return HAL_BUSY;
2310 }
2311 }
2312
2313 /**
2314 * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
2315 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2316 * the configuration information for the specified I2C.
2317 * @param pData Pointer to data buffer
2318 * @param Size Amount of data to be sent
2319 * @retval HAL status
2320 */
HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2321 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2322 {
2323 HAL_StatusTypeDef dmaxferstatus;
2324
2325 if (hi2c->State == HAL_I2C_STATE_READY)
2326 {
2327 if ((pData == NULL) || (Size == 0U))
2328 {
2329 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2330 return HAL_ERROR;
2331 }
2332 /* Process Locked */
2333 __HAL_LOCK(hi2c);
2334
2335 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2336 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2337 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2338
2339 /* Prepare transfer parameters */
2340 hi2c->pBuffPtr = pData;
2341 hi2c->XferCount = Size;
2342 hi2c->XferSize = hi2c->XferCount;
2343 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2344 hi2c->XferISR = I2C_Slave_ISR_DMA;
2345
2346 if (hi2c->hdmarx != NULL)
2347 {
2348 /* Set the I2C DMA transfer complete callback */
2349 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
2350
2351 /* Set the DMA error callback */
2352 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2353
2354 /* Set the unused DMA callbacks to NULL */
2355 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2356 hi2c->hdmarx->XferAbortCallback = NULL;
2357
2358 /* Enable the DMA channel */
2359 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2360 hi2c->XferSize);
2361 }
2362 else
2363 {
2364 /* Update I2C state */
2365 hi2c->State = HAL_I2C_STATE_LISTEN;
2366 hi2c->Mode = HAL_I2C_MODE_NONE;
2367
2368 /* Update I2C error code */
2369 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2370
2371 /* Process Unlocked */
2372 __HAL_UNLOCK(hi2c);
2373
2374 return HAL_ERROR;
2375 }
2376
2377 if (dmaxferstatus == HAL_OK)
2378 {
2379 /* Enable Address Acknowledge */
2380 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2381
2382 /* Process Unlocked */
2383 __HAL_UNLOCK(hi2c);
2384
2385 /* Note : The I2C interrupts must be enabled after unlocking current process
2386 to avoid the risk of I2C interrupt handle execution before current
2387 process unlock */
2388 /* Enable ERR, STOP, NACK, ADDR interrupts */
2389 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2390
2391 /* Enable DMA Request */
2392 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2393 }
2394 else
2395 {
2396 /* Update I2C state */
2397 hi2c->State = HAL_I2C_STATE_LISTEN;
2398 hi2c->Mode = HAL_I2C_MODE_NONE;
2399
2400 /* Update I2C error code */
2401 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2402
2403 /* Process Unlocked */
2404 __HAL_UNLOCK(hi2c);
2405
2406 return HAL_ERROR;
2407 }
2408
2409 return HAL_OK;
2410 }
2411 else
2412 {
2413 return HAL_BUSY;
2414 }
2415 }
2416
2417 /**
2418 * @brief Write an amount of data in blocking mode to a specific memory address
2419 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2420 * the configuration information for the specified I2C.
2421 * @param DevAddress Target device address: The device 7 bits address value
2422 * in datasheet must be shifted to the left before calling the interface
2423 * @param MemAddress Internal memory address
2424 * @param MemAddSize Size of internal memory address
2425 * @param pData Pointer to data buffer
2426 * @param Size Amount of data to be sent
2427 * @param Timeout Timeout duration
2428 * @retval HAL status
2429 */
HAL_I2C_Mem_Write(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2430 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2431 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2432 {
2433 uint32_t tickstart;
2434
2435 /* Check the parameters */
2436 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2437
2438 if (hi2c->State == HAL_I2C_STATE_READY)
2439 {
2440 if ((pData == NULL) || (Size == 0U))
2441 {
2442 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2443 return HAL_ERROR;
2444 }
2445
2446 /* Process Locked */
2447 __HAL_LOCK(hi2c);
2448
2449 /* Init tickstart for timeout management*/
2450 tickstart = HAL_GetTick();
2451
2452 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2453 {
2454 return HAL_ERROR;
2455 }
2456
2457 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2458 hi2c->Mode = HAL_I2C_MODE_MEM;
2459 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2460
2461 /* Prepare transfer parameters */
2462 hi2c->pBuffPtr = pData;
2463 hi2c->XferCount = Size;
2464 hi2c->XferISR = NULL;
2465
2466 /* Send Slave Address and Memory Address */
2467 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2468 {
2469 /* Process Unlocked */
2470 __HAL_UNLOCK(hi2c);
2471 return HAL_ERROR;
2472 }
2473
2474 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
2475 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2476 {
2477 hi2c->XferSize = MAX_NBYTE_SIZE;
2478 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
2479 }
2480 else
2481 {
2482 hi2c->XferSize = hi2c->XferCount;
2483 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
2484 }
2485
2486 do
2487 {
2488 /* Wait until TXIS flag is set */
2489 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2490 {
2491 return HAL_ERROR;
2492 }
2493
2494 /* Write data to TXDR */
2495 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
2496
2497 /* Increment Buffer pointer */
2498 hi2c->pBuffPtr++;
2499
2500 hi2c->XferCount--;
2501 hi2c->XferSize--;
2502
2503 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2504 {
2505 /* Wait until TCR flag is set */
2506 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2507 {
2508 return HAL_ERROR;
2509 }
2510
2511 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2512 {
2513 hi2c->XferSize = MAX_NBYTE_SIZE;
2514 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
2515 I2C_NO_STARTSTOP);
2516 }
2517 else
2518 {
2519 hi2c->XferSize = hi2c->XferCount;
2520 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2521 I2C_NO_STARTSTOP);
2522 }
2523 }
2524
2525 } while (hi2c->XferCount > 0U);
2526
2527 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2528 /* Wait until STOPF flag is reset */
2529 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2530 {
2531 return HAL_ERROR;
2532 }
2533
2534 /* Clear STOP Flag */
2535 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2536
2537 /* Clear Configuration Register 2 */
2538 I2C_RESET_CR2(hi2c);
2539
2540 hi2c->State = HAL_I2C_STATE_READY;
2541 hi2c->Mode = HAL_I2C_MODE_NONE;
2542
2543 /* Process Unlocked */
2544 __HAL_UNLOCK(hi2c);
2545
2546 return HAL_OK;
2547 }
2548 else
2549 {
2550 return HAL_BUSY;
2551 }
2552 }
2553
2554 /**
2555 * @brief Read an amount of data in blocking mode from a specific memory address
2556 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2557 * the configuration information for the specified I2C.
2558 * @param DevAddress Target device address: The device 7 bits address value
2559 * in datasheet must be shifted to the left before calling the interface
2560 * @param MemAddress Internal memory address
2561 * @param MemAddSize Size of internal memory address
2562 * @param pData Pointer to data buffer
2563 * @param Size Amount of data to be sent
2564 * @param Timeout Timeout duration
2565 * @retval HAL status
2566 */
HAL_I2C_Mem_Read(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2567 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2568 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2569 {
2570 uint32_t tickstart;
2571
2572 /* Check the parameters */
2573 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2574
2575 if (hi2c->State == HAL_I2C_STATE_READY)
2576 {
2577 if ((pData == NULL) || (Size == 0U))
2578 {
2579 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2580 return HAL_ERROR;
2581 }
2582
2583 /* Process Locked */
2584 __HAL_LOCK(hi2c);
2585
2586 /* Init tickstart for timeout management*/
2587 tickstart = HAL_GetTick();
2588
2589 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2590 {
2591 return HAL_ERROR;
2592 }
2593
2594 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2595 hi2c->Mode = HAL_I2C_MODE_MEM;
2596 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2597
2598 /* Prepare transfer parameters */
2599 hi2c->pBuffPtr = pData;
2600 hi2c->XferCount = Size;
2601 hi2c->XferISR = NULL;
2602
2603 /* Send Slave Address and Memory Address */
2604 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2605 {
2606 /* Process Unlocked */
2607 __HAL_UNLOCK(hi2c);
2608 return HAL_ERROR;
2609 }
2610
2611 /* Send Slave Address */
2612 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2613 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2614 {
2615 hi2c->XferSize = MAX_NBYTE_SIZE;
2616 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
2617 I2C_GENERATE_START_READ);
2618 }
2619 else
2620 {
2621 hi2c->XferSize = hi2c->XferCount;
2622 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2623 I2C_GENERATE_START_READ);
2624 }
2625
2626 do
2627 {
2628 /* Wait until RXNE flag is set */
2629 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
2630 {
2631 return HAL_ERROR;
2632 }
2633
2634 /* Read data from RXDR */
2635 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
2636
2637 /* Increment Buffer pointer */
2638 hi2c->pBuffPtr++;
2639
2640 hi2c->XferSize--;
2641 hi2c->XferCount--;
2642
2643 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2644 {
2645 /* Wait until TCR flag is set */
2646 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2647 {
2648 return HAL_ERROR;
2649 }
2650
2651 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2652 {
2653 hi2c->XferSize = MAX_NBYTE_SIZE;
2654 I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
2655 I2C_NO_STARTSTOP);
2656 }
2657 else
2658 {
2659 hi2c->XferSize = hi2c->XferCount;
2660 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2661 I2C_NO_STARTSTOP);
2662 }
2663 }
2664 } while (hi2c->XferCount > 0U);
2665
2666 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2667 /* Wait until STOPF flag is reset */
2668 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2669 {
2670 return HAL_ERROR;
2671 }
2672
2673 /* Clear STOP Flag */
2674 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2675
2676 /* Clear Configuration Register 2 */
2677 I2C_RESET_CR2(hi2c);
2678
2679 hi2c->State = HAL_I2C_STATE_READY;
2680 hi2c->Mode = HAL_I2C_MODE_NONE;
2681
2682 /* Process Unlocked */
2683 __HAL_UNLOCK(hi2c);
2684
2685 return HAL_OK;
2686 }
2687 else
2688 {
2689 return HAL_BUSY;
2690 }
2691 }
2692 /**
2693 * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
2694 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2695 * the configuration information for the specified I2C.
2696 * @param DevAddress Target device address: The device 7 bits address value
2697 * in datasheet must be shifted to the left before calling the interface
2698 * @param MemAddress Internal memory address
2699 * @param MemAddSize Size of internal memory address
2700 * @param pData Pointer to data buffer
2701 * @param Size Amount of data to be sent
2702 * @retval HAL status
2703 */
HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2704 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2705 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2706 {
2707 /* Check the parameters */
2708 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2709
2710 if (hi2c->State == HAL_I2C_STATE_READY)
2711 {
2712 if ((pData == NULL) || (Size == 0U))
2713 {
2714 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2715 return HAL_ERROR;
2716 }
2717
2718 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2719 {
2720 return HAL_BUSY;
2721 }
2722
2723 /* Process Locked */
2724 __HAL_LOCK(hi2c);
2725
2726 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2727 hi2c->Mode = HAL_I2C_MODE_MEM;
2728 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2729
2730 /* Prepare transfer parameters */
2731 hi2c->pBuffPtr = pData;
2732 hi2c->XferCount = Size;
2733 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2734 hi2c->XferISR = I2C_Mem_ISR_IT;
2735 hi2c->Devaddress = DevAddress;
2736
2737 /* If Memory address size is 8Bit */
2738 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
2739 {
2740 /* Prefetch Memory Address */
2741 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
2742
2743 /* Reset Memaddress content */
2744 hi2c->Memaddress = 0xFFFFFFFFU;
2745 }
2746 /* If Memory address size is 16Bit */
2747 else
2748 {
2749 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
2750 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
2751
2752 /* Prepare Memaddress buffer for LSB part */
2753 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
2754 }
2755 /* Send Slave Address and Memory Address */
2756 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
2757
2758 /* Process Unlocked */
2759 __HAL_UNLOCK(hi2c);
2760
2761 /* Note : The I2C interrupts must be enabled after unlocking current process
2762 to avoid the risk of I2C interrupt handle execution before current
2763 process unlock */
2764
2765 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2766 /* possible to enable all of these */
2767 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2768 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2769 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2770
2771 return HAL_OK;
2772 }
2773 else
2774 {
2775 return HAL_BUSY;
2776 }
2777 }
2778
2779 /**
2780 * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
2781 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2782 * the configuration information for the specified I2C.
2783 * @param DevAddress Target device address: The device 7 bits address value
2784 * in datasheet must be shifted to the left before calling the interface
2785 * @param MemAddress Internal memory address
2786 * @param MemAddSize Size of internal memory address
2787 * @param pData Pointer to data buffer
2788 * @param Size Amount of data to be sent
2789 * @retval HAL status
2790 */
HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2791 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2792 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2793 {
2794 /* Check the parameters */
2795 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2796
2797 if (hi2c->State == HAL_I2C_STATE_READY)
2798 {
2799 if ((pData == NULL) || (Size == 0U))
2800 {
2801 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2802 return HAL_ERROR;
2803 }
2804
2805 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2806 {
2807 return HAL_BUSY;
2808 }
2809
2810 /* Process Locked */
2811 __HAL_LOCK(hi2c);
2812
2813 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2814 hi2c->Mode = HAL_I2C_MODE_MEM;
2815 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2816
2817 /* Prepare transfer parameters */
2818 hi2c->pBuffPtr = pData;
2819 hi2c->XferCount = Size;
2820 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2821 hi2c->XferISR = I2C_Mem_ISR_IT;
2822 hi2c->Devaddress = DevAddress;
2823
2824 /* If Memory address size is 8Bit */
2825 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
2826 {
2827 /* Prefetch Memory Address */
2828 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
2829
2830 /* Reset Memaddress content */
2831 hi2c->Memaddress = 0xFFFFFFFFU;
2832 }
2833 /* If Memory address size is 16Bit */
2834 else
2835 {
2836 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
2837 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
2838
2839 /* Prepare Memaddress buffer for LSB part */
2840 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
2841 }
2842 /* Send Slave Address and Memory Address */
2843 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
2844
2845 /* Process Unlocked */
2846 __HAL_UNLOCK(hi2c);
2847
2848 /* Note : The I2C interrupts must be enabled after unlocking current process
2849 to avoid the risk of I2C interrupt handle execution before current
2850 process unlock */
2851
2852 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
2853 /* possible to enable all of these */
2854 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2855 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2856 I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT));
2857
2858 return HAL_OK;
2859 }
2860 else
2861 {
2862 return HAL_BUSY;
2863 }
2864 }
2865
2866 /**
2867 * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
2868 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2869 * the configuration information for the specified I2C.
2870 * @param DevAddress Target device address: The device 7 bits address value
2871 * in datasheet must be shifted to the left before calling the interface
2872 * @param MemAddress Internal memory address
2873 * @param MemAddSize Size of internal memory address
2874 * @param pData Pointer to data buffer
2875 * @param Size Amount of data to be sent
2876 * @retval HAL status
2877 */
HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2878 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2879 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2880 {
2881 HAL_StatusTypeDef dmaxferstatus;
2882
2883 /* Check the parameters */
2884 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2885
2886 if (hi2c->State == HAL_I2C_STATE_READY)
2887 {
2888 if ((pData == NULL) || (Size == 0U))
2889 {
2890 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2891 return HAL_ERROR;
2892 }
2893
2894 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2895 {
2896 return HAL_BUSY;
2897 }
2898
2899 /* Process Locked */
2900 __HAL_LOCK(hi2c);
2901
2902 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2903 hi2c->Mode = HAL_I2C_MODE_MEM;
2904 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2905
2906 /* Prepare transfer parameters */
2907 hi2c->pBuffPtr = pData;
2908 hi2c->XferCount = Size;
2909 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2910 hi2c->XferISR = I2C_Mem_ISR_DMA;
2911 hi2c->Devaddress = DevAddress;
2912
2913 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2914 {
2915 hi2c->XferSize = MAX_NBYTE_SIZE;
2916 }
2917 else
2918 {
2919 hi2c->XferSize = hi2c->XferCount;
2920 }
2921
2922 /* If Memory address size is 8Bit */
2923 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
2924 {
2925 /* Prefetch Memory Address */
2926 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
2927
2928 /* Reset Memaddress content */
2929 hi2c->Memaddress = 0xFFFFFFFFU;
2930 }
2931 /* If Memory address size is 16Bit */
2932 else
2933 {
2934 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
2935 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
2936
2937 /* Prepare Memaddress buffer for LSB part */
2938 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
2939 }
2940
2941 if (hi2c->hdmatx != NULL)
2942 {
2943 /* Set the I2C DMA transfer complete callback */
2944 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
2945
2946 /* Set the DMA error callback */
2947 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2948
2949 /* Set the unused DMA callbacks to NULL */
2950 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2951 hi2c->hdmatx->XferAbortCallback = NULL;
2952
2953 /* Enable the DMA channel */
2954 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
2955 hi2c->XferSize);
2956 }
2957 else
2958 {
2959 /* Update I2C state */
2960 hi2c->State = HAL_I2C_STATE_READY;
2961 hi2c->Mode = HAL_I2C_MODE_NONE;
2962
2963 /* Update I2C error code */
2964 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2965
2966 /* Process Unlocked */
2967 __HAL_UNLOCK(hi2c);
2968
2969 return HAL_ERROR;
2970 }
2971
2972 if (dmaxferstatus == HAL_OK)
2973 {
2974 /* Send Slave Address and Memory Address */
2975 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
2976
2977 /* Process Unlocked */
2978 __HAL_UNLOCK(hi2c);
2979
2980 /* Note : The I2C interrupts must be enabled after unlocking current process
2981 to avoid the risk of I2C interrupt handle execution before current
2982 process unlock */
2983 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2984 /* possible to enable all of these */
2985 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2986 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2987 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2988 }
2989 else
2990 {
2991 /* Update I2C state */
2992 hi2c->State = HAL_I2C_STATE_READY;
2993 hi2c->Mode = HAL_I2C_MODE_NONE;
2994
2995 /* Update I2C error code */
2996 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2997
2998 /* Process Unlocked */
2999 __HAL_UNLOCK(hi2c);
3000
3001 return HAL_ERROR;
3002 }
3003
3004 return HAL_OK;
3005 }
3006 else
3007 {
3008 return HAL_BUSY;
3009 }
3010 }
3011
3012 /**
3013 * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
3014 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3015 * the configuration information for the specified I2C.
3016 * @param DevAddress Target device address: The device 7 bits address value
3017 * in datasheet must be shifted to the left before calling the interface
3018 * @param MemAddress Internal memory address
3019 * @param MemAddSize Size of internal memory address
3020 * @param pData Pointer to data buffer
3021 * @param Size Amount of data to be read
3022 * @retval HAL status
3023 */
HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)3024 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
3025 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3026 {
3027 HAL_StatusTypeDef dmaxferstatus;
3028
3029 /* Check the parameters */
3030 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3031
3032 if (hi2c->State == HAL_I2C_STATE_READY)
3033 {
3034 if ((pData == NULL) || (Size == 0U))
3035 {
3036 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3037 return HAL_ERROR;
3038 }
3039
3040 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3041 {
3042 return HAL_BUSY;
3043 }
3044
3045 /* Process Locked */
3046 __HAL_LOCK(hi2c);
3047
3048 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3049 hi2c->Mode = HAL_I2C_MODE_MEM;
3050 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3051
3052 /* Prepare transfer parameters */
3053 hi2c->pBuffPtr = pData;
3054 hi2c->XferCount = Size;
3055 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3056 hi2c->XferISR = I2C_Mem_ISR_DMA;
3057 hi2c->Devaddress = DevAddress;
3058
3059 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3060 {
3061 hi2c->XferSize = MAX_NBYTE_SIZE;
3062 }
3063 else
3064 {
3065 hi2c->XferSize = hi2c->XferCount;
3066 }
3067
3068 /* If Memory address size is 8Bit */
3069 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
3070 {
3071 /* Prefetch Memory Address */
3072 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3073
3074 /* Reset Memaddress content */
3075 hi2c->Memaddress = 0xFFFFFFFFU;
3076 }
3077 /* If Memory address size is 16Bit */
3078 else
3079 {
3080 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
3081 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3082
3083 /* Prepare Memaddress buffer for LSB part */
3084 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
3085 }
3086
3087 if (hi2c->hdmarx != NULL)
3088 {
3089 /* Set the I2C DMA transfer complete callback */
3090 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
3091
3092 /* Set the DMA error callback */
3093 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3094
3095 /* Set the unused DMA callbacks to NULL */
3096 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3097 hi2c->hdmarx->XferAbortCallback = NULL;
3098
3099 /* Enable the DMA channel */
3100 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
3101 hi2c->XferSize);
3102 }
3103 else
3104 {
3105 /* Update I2C state */
3106 hi2c->State = HAL_I2C_STATE_READY;
3107 hi2c->Mode = HAL_I2C_MODE_NONE;
3108
3109 /* Update I2C error code */
3110 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3111
3112 /* Process Unlocked */
3113 __HAL_UNLOCK(hi2c);
3114
3115 return HAL_ERROR;
3116 }
3117
3118 if (dmaxferstatus == HAL_OK)
3119 {
3120 /* Send Slave Address and Memory Address */
3121 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
3122
3123 /* Process Unlocked */
3124 __HAL_UNLOCK(hi2c);
3125
3126 /* Note : The I2C interrupts must be enabled after unlocking current process
3127 to avoid the risk of I2C interrupt handle execution before current
3128 process unlock */
3129 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3130 /* possible to enable all of these */
3131 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3132 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3133 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3134 }
3135 else
3136 {
3137 /* Update I2C state */
3138 hi2c->State = HAL_I2C_STATE_READY;
3139 hi2c->Mode = HAL_I2C_MODE_NONE;
3140
3141 /* Update I2C error code */
3142 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3143
3144 /* Process Unlocked */
3145 __HAL_UNLOCK(hi2c);
3146
3147 return HAL_ERROR;
3148 }
3149
3150 return HAL_OK;
3151 }
3152 else
3153 {
3154 return HAL_BUSY;
3155 }
3156 }
3157
3158 /**
3159 * @brief Checks if target device is ready for communication.
3160 * @note This function is used with Memory devices
3161 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3162 * the configuration information for the specified I2C.
3163 * @param DevAddress Target device address: The device 7 bits address value
3164 * in datasheet must be shifted to the left before calling the interface
3165 * @param Trials Number of trials
3166 * @param Timeout Timeout duration
3167 * @retval HAL status
3168 */
HAL_I2C_IsDeviceReady(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Trials,uint32_t Timeout)3169 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
3170 uint32_t Timeout)
3171 {
3172 uint32_t tickstart;
3173
3174 __IO uint32_t I2C_Trials = 0UL;
3175
3176 FlagStatus tmp1;
3177 FlagStatus tmp2;
3178
3179 if (hi2c->State == HAL_I2C_STATE_READY)
3180 {
3181 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3182 {
3183 return HAL_BUSY;
3184 }
3185
3186 /* Process Locked */
3187 __HAL_LOCK(hi2c);
3188
3189 hi2c->State = HAL_I2C_STATE_BUSY;
3190 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3191
3192 do
3193 {
3194 /* Generate Start */
3195 hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
3196
3197 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
3198 /* Wait until STOPF flag is set or a NACK flag is set*/
3199 tickstart = HAL_GetTick();
3200
3201 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3202 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3203
3204 while ((tmp1 == RESET) && (tmp2 == RESET))
3205 {
3206 if (Timeout != HAL_MAX_DELAY)
3207 {
3208 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3209 {
3210 /* Update I2C state */
3211 hi2c->State = HAL_I2C_STATE_READY;
3212
3213 /* Update I2C error code */
3214 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3215
3216 /* Process Unlocked */
3217 __HAL_UNLOCK(hi2c);
3218
3219 return HAL_ERROR;
3220 }
3221 }
3222
3223 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3224 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3225 }
3226
3227 /* Check if the NACKF flag has not been set */
3228 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
3229 {
3230 /* Wait until STOPF flag is reset */
3231 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3232 {
3233 return HAL_ERROR;
3234 }
3235
3236 /* Clear STOP Flag */
3237 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3238
3239 /* Device is ready */
3240 hi2c->State = HAL_I2C_STATE_READY;
3241
3242 /* Process Unlocked */
3243 __HAL_UNLOCK(hi2c);
3244
3245 return HAL_OK;
3246 }
3247 else
3248 {
3249 /* Wait until STOPF flag is reset */
3250 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3251 {
3252 return HAL_ERROR;
3253 }
3254
3255 /* Clear NACK Flag */
3256 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3257
3258 /* Clear STOP Flag, auto generated with autoend*/
3259 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3260 }
3261
3262 /* Check if the maximum allowed number of trials has been reached */
3263 if (I2C_Trials == Trials)
3264 {
3265 /* Generate Stop */
3266 hi2c->Instance->CR2 |= I2C_CR2_STOP;
3267
3268 /* Wait until STOPF flag is reset */
3269 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3270 {
3271 return HAL_ERROR;
3272 }
3273
3274 /* Clear STOP Flag */
3275 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3276 }
3277
3278 /* Increment Trials */
3279 I2C_Trials++;
3280 } while (I2C_Trials < Trials);
3281
3282 /* Update I2C state */
3283 hi2c->State = HAL_I2C_STATE_READY;
3284
3285 /* Update I2C error code */
3286 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3287
3288 /* Process Unlocked */
3289 __HAL_UNLOCK(hi2c);
3290
3291 return HAL_ERROR;
3292 }
3293 else
3294 {
3295 return HAL_BUSY;
3296 }
3297 }
3298
3299 /**
3300 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
3301 * @note This interface allow to manage repeated start condition when a direction change during transfer
3302 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3303 * the configuration information for the specified I2C.
3304 * @param DevAddress Target device address: The device 7 bits address value
3305 * in datasheet must be shifted to the left before calling the interface
3306 * @param pData Pointer to data buffer
3307 * @param Size Amount of data to be sent
3308 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3309 * @retval HAL status
3310 */
HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3311 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3312 uint16_t Size, uint32_t XferOptions)
3313 {
3314 uint32_t xfermode;
3315 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3316
3317 /* Check the parameters */
3318 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3319
3320 if (hi2c->State == HAL_I2C_STATE_READY)
3321 {
3322 /* Process Locked */
3323 __HAL_LOCK(hi2c);
3324
3325 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3326 hi2c->Mode = HAL_I2C_MODE_MASTER;
3327 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3328
3329 /* Prepare transfer parameters */
3330 hi2c->pBuffPtr = pData;
3331 hi2c->XferCount = Size;
3332 hi2c->XferOptions = XferOptions;
3333 hi2c->XferISR = I2C_Master_ISR_IT;
3334
3335 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3336 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3337 {
3338 hi2c->XferSize = MAX_NBYTE_SIZE;
3339 xfermode = I2C_RELOAD_MODE;
3340 }
3341 else
3342 {
3343 hi2c->XferSize = hi2c->XferCount;
3344 xfermode = hi2c->XferOptions;
3345 }
3346
3347 /* If transfer direction not change and there is no request to start another frame,
3348 do not generate Restart Condition */
3349 /* Mean Previous state is same as current state */
3350 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
3351 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3352 {
3353 xferrequest = I2C_NO_STARTSTOP;
3354 }
3355 else
3356 {
3357 /* Convert OTHER_xxx XferOptions if any */
3358 I2C_ConvertOtherXferOptions(hi2c);
3359
3360 /* Update xfermode accordingly if no reload is necessary */
3361 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3362 {
3363 xfermode = hi2c->XferOptions;
3364 }
3365 }
3366
3367 /* Send Slave Address and set NBYTES to write */
3368 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3369
3370 /* Process Unlocked */
3371 __HAL_UNLOCK(hi2c);
3372
3373 /* Note : The I2C interrupts must be enabled after unlocking current process
3374 to avoid the risk of I2C interrupt handle execution before current
3375 process unlock */
3376 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3377 /* possible to enable all of these */
3378 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3379 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3380 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3381
3382 return HAL_OK;
3383 }
3384 else
3385 {
3386 return HAL_BUSY;
3387 }
3388 }
3389
3390 /**
3391 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
3392 * @note This interface allow to manage repeated start condition when a direction change during transfer
3393 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3394 * the configuration information for the specified I2C.
3395 * @param DevAddress Target device address: The device 7 bits address value
3396 * in datasheet must be shifted to the left before calling the interface
3397 * @param pData Pointer to data buffer
3398 * @param Size Amount of data to be sent
3399 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3400 * @retval HAL status
3401 */
HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3402 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3403 uint16_t Size, uint32_t XferOptions)
3404 {
3405 uint32_t xfermode;
3406 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3407 HAL_StatusTypeDef dmaxferstatus;
3408
3409 /* Check the parameters */
3410 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3411
3412 if (hi2c->State == HAL_I2C_STATE_READY)
3413 {
3414 /* Process Locked */
3415 __HAL_LOCK(hi2c);
3416
3417 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3418 hi2c->Mode = HAL_I2C_MODE_MASTER;
3419 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3420
3421 /* Prepare transfer parameters */
3422 hi2c->pBuffPtr = pData;
3423 hi2c->XferCount = Size;
3424 hi2c->XferOptions = XferOptions;
3425 hi2c->XferISR = I2C_Master_ISR_DMA;
3426
3427 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3428 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3429 {
3430 hi2c->XferSize = MAX_NBYTE_SIZE;
3431 xfermode = I2C_RELOAD_MODE;
3432 }
3433 else
3434 {
3435 hi2c->XferSize = hi2c->XferCount;
3436 xfermode = hi2c->XferOptions;
3437 }
3438
3439 /* If transfer direction not change and there is no request to start another frame,
3440 do not generate Restart Condition */
3441 /* Mean Previous state is same as current state */
3442 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
3443 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3444 {
3445 xferrequest = I2C_NO_STARTSTOP;
3446 }
3447 else
3448 {
3449 /* Convert OTHER_xxx XferOptions if any */
3450 I2C_ConvertOtherXferOptions(hi2c);
3451
3452 /* Update xfermode accordingly if no reload is necessary */
3453 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3454 {
3455 xfermode = hi2c->XferOptions;
3456 }
3457 }
3458
3459 if (hi2c->XferSize > 0U)
3460 {
3461 if (hi2c->hdmatx != NULL)
3462 {
3463 /* Set the I2C DMA transfer complete callback */
3464 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
3465
3466 /* Set the DMA error callback */
3467 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3468
3469 /* Set the unused DMA callbacks to NULL */
3470 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3471 hi2c->hdmatx->XferAbortCallback = NULL;
3472
3473 /* Enable the DMA channel */
3474 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
3475 hi2c->XferSize);
3476 }
3477 else
3478 {
3479 /* Update I2C state */
3480 hi2c->State = HAL_I2C_STATE_READY;
3481 hi2c->Mode = HAL_I2C_MODE_NONE;
3482
3483 /* Update I2C error code */
3484 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3485
3486 /* Process Unlocked */
3487 __HAL_UNLOCK(hi2c);
3488
3489 return HAL_ERROR;
3490 }
3491
3492 if (dmaxferstatus == HAL_OK)
3493 {
3494 /* Send Slave Address and set NBYTES to write */
3495 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3496
3497 /* Update XferCount value */
3498 hi2c->XferCount -= hi2c->XferSize;
3499
3500 /* Process Unlocked */
3501 __HAL_UNLOCK(hi2c);
3502
3503 /* Note : The I2C interrupts must be enabled after unlocking current process
3504 to avoid the risk of I2C interrupt handle execution before current
3505 process unlock */
3506 /* Enable ERR and NACK interrupts */
3507 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
3508
3509 /* Enable DMA Request */
3510 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
3511 }
3512 else
3513 {
3514 /* Update I2C state */
3515 hi2c->State = HAL_I2C_STATE_READY;
3516 hi2c->Mode = HAL_I2C_MODE_NONE;
3517
3518 /* Update I2C error code */
3519 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3520
3521 /* Process Unlocked */
3522 __HAL_UNLOCK(hi2c);
3523
3524 return HAL_ERROR;
3525 }
3526 }
3527 else
3528 {
3529 /* Update Transfer ISR function pointer */
3530 hi2c->XferISR = I2C_Master_ISR_IT;
3531
3532 /* Send Slave Address */
3533 /* Set NBYTES to write and generate START condition */
3534 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
3535 I2C_GENERATE_START_WRITE);
3536
3537 /* Process Unlocked */
3538 __HAL_UNLOCK(hi2c);
3539
3540 /* Note : The I2C interrupts must be enabled after unlocking current process
3541 to avoid the risk of I2C interrupt handle execution before current
3542 process unlock */
3543 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3544 /* possible to enable all of these */
3545 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3546 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3547 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3548 }
3549
3550 return HAL_OK;
3551 }
3552 else
3553 {
3554 return HAL_BUSY;
3555 }
3556 }
3557
3558 /**
3559 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
3560 * @note This interface allow to manage repeated start condition when a direction change during transfer
3561 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3562 * the configuration information for the specified I2C.
3563 * @param DevAddress Target device address: The device 7 bits address value
3564 * in datasheet must be shifted to the left before calling the interface
3565 * @param pData Pointer to data buffer
3566 * @param Size Amount of data to be sent
3567 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3568 * @retval HAL status
3569 */
HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3570 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3571 uint16_t Size, uint32_t XferOptions)
3572 {
3573 uint32_t xfermode;
3574 uint32_t xferrequest = I2C_GENERATE_START_READ;
3575
3576 /* Check the parameters */
3577 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3578
3579 if (hi2c->State == HAL_I2C_STATE_READY)
3580 {
3581 /* Process Locked */
3582 __HAL_LOCK(hi2c);
3583
3584 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3585 hi2c->Mode = HAL_I2C_MODE_MASTER;
3586 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3587
3588 /* Prepare transfer parameters */
3589 hi2c->pBuffPtr = pData;
3590 hi2c->XferCount = Size;
3591 hi2c->XferOptions = XferOptions;
3592 hi2c->XferISR = I2C_Master_ISR_IT;
3593
3594 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3595 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3596 {
3597 hi2c->XferSize = MAX_NBYTE_SIZE;
3598 xfermode = I2C_RELOAD_MODE;
3599 }
3600 else
3601 {
3602 hi2c->XferSize = hi2c->XferCount;
3603 xfermode = hi2c->XferOptions;
3604 }
3605
3606 /* If transfer direction not change and there is no request to start another frame,
3607 do not generate Restart Condition */
3608 /* Mean Previous state is same as current state */
3609 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
3610 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3611 {
3612 xferrequest = I2C_NO_STARTSTOP;
3613 }
3614 else
3615 {
3616 /* Convert OTHER_xxx XferOptions if any */
3617 I2C_ConvertOtherXferOptions(hi2c);
3618
3619 /* Update xfermode accordingly if no reload is necessary */
3620 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3621 {
3622 xfermode = hi2c->XferOptions;
3623 }
3624 }
3625
3626 /* Send Slave Address and set NBYTES to read */
3627 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3628
3629 /* Process Unlocked */
3630 __HAL_UNLOCK(hi2c);
3631
3632 /* Note : The I2C interrupts must be enabled after unlocking current process
3633 to avoid the risk of I2C interrupt handle execution before current
3634 process unlock */
3635 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
3636
3637 return HAL_OK;
3638 }
3639 else
3640 {
3641 return HAL_BUSY;
3642 }
3643 }
3644
3645 /**
3646 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
3647 * @note This interface allow to manage repeated start condition when a direction change during transfer
3648 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3649 * the configuration information for the specified I2C.
3650 * @param DevAddress Target device address: The device 7 bits address value
3651 * in datasheet must be shifted to the left before calling the interface
3652 * @param pData Pointer to data buffer
3653 * @param Size Amount of data to be sent
3654 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3655 * @retval HAL status
3656 */
HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3657 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3658 uint16_t Size, uint32_t XferOptions)
3659 {
3660 uint32_t xfermode;
3661 uint32_t xferrequest = I2C_GENERATE_START_READ;
3662 HAL_StatusTypeDef dmaxferstatus;
3663
3664 /* Check the parameters */
3665 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3666
3667 if (hi2c->State == HAL_I2C_STATE_READY)
3668 {
3669 /* Process Locked */
3670 __HAL_LOCK(hi2c);
3671
3672 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3673 hi2c->Mode = HAL_I2C_MODE_MASTER;
3674 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3675
3676 /* Prepare transfer parameters */
3677 hi2c->pBuffPtr = pData;
3678 hi2c->XferCount = Size;
3679 hi2c->XferOptions = XferOptions;
3680 hi2c->XferISR = I2C_Master_ISR_DMA;
3681
3682 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3683 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3684 {
3685 hi2c->XferSize = MAX_NBYTE_SIZE;
3686 xfermode = I2C_RELOAD_MODE;
3687 }
3688 else
3689 {
3690 hi2c->XferSize = hi2c->XferCount;
3691 xfermode = hi2c->XferOptions;
3692 }
3693
3694 /* If transfer direction not change and there is no request to start another frame,
3695 do not generate Restart Condition */
3696 /* Mean Previous state is same as current state */
3697 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
3698 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3699 {
3700 xferrequest = I2C_NO_STARTSTOP;
3701 }
3702 else
3703 {
3704 /* Convert OTHER_xxx XferOptions if any */
3705 I2C_ConvertOtherXferOptions(hi2c);
3706
3707 /* Update xfermode accordingly if no reload is necessary */
3708 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3709 {
3710 xfermode = hi2c->XferOptions;
3711 }
3712 }
3713
3714 if (hi2c->XferSize > 0U)
3715 {
3716 if (hi2c->hdmarx != NULL)
3717 {
3718 /* Set the I2C DMA transfer complete callback */
3719 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
3720
3721 /* Set the DMA error callback */
3722 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3723
3724 /* Set the unused DMA callbacks to NULL */
3725 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3726 hi2c->hdmarx->XferAbortCallback = NULL;
3727
3728 /* Enable the DMA channel */
3729 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
3730 hi2c->XferSize);
3731 }
3732 else
3733 {
3734 /* Update I2C state */
3735 hi2c->State = HAL_I2C_STATE_READY;
3736 hi2c->Mode = HAL_I2C_MODE_NONE;
3737
3738 /* Update I2C error code */
3739 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3740
3741 /* Process Unlocked */
3742 __HAL_UNLOCK(hi2c);
3743
3744 return HAL_ERROR;
3745 }
3746
3747 if (dmaxferstatus == HAL_OK)
3748 {
3749 /* Send Slave Address and set NBYTES to read */
3750 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3751
3752 /* Update XferCount value */
3753 hi2c->XferCount -= hi2c->XferSize;
3754
3755 /* Process Unlocked */
3756 __HAL_UNLOCK(hi2c);
3757
3758 /* Note : The I2C interrupts must be enabled after unlocking current process
3759 to avoid the risk of I2C interrupt handle execution before current
3760 process unlock */
3761 /* Enable ERR and NACK interrupts */
3762 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
3763
3764 /* Enable DMA Request */
3765 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
3766 }
3767 else
3768 {
3769 /* Update I2C state */
3770 hi2c->State = HAL_I2C_STATE_READY;
3771 hi2c->Mode = HAL_I2C_MODE_NONE;
3772
3773 /* Update I2C error code */
3774 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3775
3776 /* Process Unlocked */
3777 __HAL_UNLOCK(hi2c);
3778
3779 return HAL_ERROR;
3780 }
3781 }
3782 else
3783 {
3784 /* Update Transfer ISR function pointer */
3785 hi2c->XferISR = I2C_Master_ISR_IT;
3786
3787 /* Send Slave Address */
3788 /* Set NBYTES to read and generate START condition */
3789 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
3790 I2C_GENERATE_START_READ);
3791
3792 /* Process Unlocked */
3793 __HAL_UNLOCK(hi2c);
3794
3795 /* Note : The I2C interrupts must be enabled after unlocking current process
3796 to avoid the risk of I2C interrupt handle execution before current
3797 process unlock */
3798 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3799 /* possible to enable all of these */
3800 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3801 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3802 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3803 }
3804
3805 return HAL_OK;
3806 }
3807 else
3808 {
3809 return HAL_BUSY;
3810 }
3811 }
3812
3813 /**
3814 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
3815 * @note This interface allow to manage repeated start condition when a direction change during transfer
3816 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3817 * the configuration information for the specified I2C.
3818 * @param pData Pointer to data buffer
3819 * @param Size Amount of data to be sent
3820 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3821 * @retval HAL status
3822 */
HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3823 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
3824 uint32_t XferOptions)
3825 {
3826 /* Declaration of tmp to prevent undefined behavior of volatile usage */
3827 FlagStatus tmp;
3828
3829 /* Check the parameters */
3830 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3831
3832 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
3833 {
3834 if ((pData == NULL) || (Size == 0U))
3835 {
3836 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3837 return HAL_ERROR;
3838 }
3839
3840 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
3841 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
3842
3843 /* Process Locked */
3844 __HAL_LOCK(hi2c);
3845
3846 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
3847 /* and then toggle the HAL slave RX state to TX state */
3848 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
3849 {
3850 /* Disable associated Interrupts */
3851 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
3852
3853 /* Abort DMA Xfer if any */
3854 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
3855 {
3856 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
3857
3858 if (hi2c->hdmarx != NULL)
3859 {
3860 /* Set the I2C DMA Abort callback :
3861 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
3862 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
3863
3864 /* Abort DMA RX */
3865 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
3866 {
3867 /* Call Directly XferAbortCallback function in case of error */
3868 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
3869 }
3870 }
3871 }
3872 }
3873
3874 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
3875 hi2c->Mode = HAL_I2C_MODE_SLAVE;
3876 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3877
3878 /* Enable Address Acknowledge */
3879 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
3880
3881 /* Prepare transfer parameters */
3882 hi2c->pBuffPtr = pData;
3883 hi2c->XferCount = Size;
3884 hi2c->XferSize = hi2c->XferCount;
3885 hi2c->XferOptions = XferOptions;
3886 hi2c->XferISR = I2C_Slave_ISR_IT;
3887
3888 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
3889 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
3890 {
3891 /* Clear ADDR flag after prepare the transfer parameters */
3892 /* This action will generate an acknowledge to the Master */
3893 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
3894 }
3895
3896 /* Process Unlocked */
3897 __HAL_UNLOCK(hi2c);
3898
3899 /* Note : The I2C interrupts must be enabled after unlocking current process
3900 to avoid the risk of I2C interrupt handle execution before current
3901 process unlock */
3902 /* REnable ADDR interrupt */
3903 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
3904
3905 return HAL_OK;
3906 }
3907 else
3908 {
3909 return HAL_ERROR;
3910 }
3911 }
3912
3913 /**
3914 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
3915 * @note This interface allow to manage repeated start condition when a direction change during transfer
3916 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3917 * the configuration information for the specified I2C.
3918 * @param pData Pointer to data buffer
3919 * @param Size Amount of data to be sent
3920 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3921 * @retval HAL status
3922 */
HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3923 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
3924 uint32_t XferOptions)
3925 {
3926 /* Declaration of tmp to prevent undefined behavior of volatile usage */
3927 FlagStatus tmp;
3928 HAL_StatusTypeDef dmaxferstatus;
3929
3930 /* Check the parameters */
3931 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3932
3933 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
3934 {
3935 if ((pData == NULL) || (Size == 0U))
3936 {
3937 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3938 return HAL_ERROR;
3939 }
3940
3941 /* Process Locked */
3942 __HAL_LOCK(hi2c);
3943
3944 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
3945 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
3946
3947 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
3948 /* and then toggle the HAL slave RX state to TX state */
3949 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
3950 {
3951 /* Disable associated Interrupts */
3952 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
3953
3954 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
3955 {
3956 /* Abort DMA Xfer if any */
3957 if (hi2c->hdmarx != NULL)
3958 {
3959 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
3960
3961 /* Set the I2C DMA Abort callback :
3962 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
3963 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
3964
3965 /* Abort DMA RX */
3966 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
3967 {
3968 /* Call Directly XferAbortCallback function in case of error */
3969 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
3970 }
3971 }
3972 }
3973 }
3974 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
3975 {
3976 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
3977 {
3978 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
3979
3980 /* Abort DMA Xfer if any */
3981 if (hi2c->hdmatx != NULL)
3982 {
3983 /* Set the I2C DMA Abort callback :
3984 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
3985 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
3986
3987 /* Abort DMA TX */
3988 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
3989 {
3990 /* Call Directly XferAbortCallback function in case of error */
3991 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
3992 }
3993 }
3994 }
3995 }
3996 else
3997 {
3998 /* Nothing to do */
3999 }
4000
4001 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4002 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4003 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4004
4005 /* Enable Address Acknowledge */
4006 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4007
4008 /* Prepare transfer parameters */
4009 hi2c->pBuffPtr = pData;
4010 hi2c->XferCount = Size;
4011 hi2c->XferSize = hi2c->XferCount;
4012 hi2c->XferOptions = XferOptions;
4013 hi2c->XferISR = I2C_Slave_ISR_DMA;
4014
4015 if (hi2c->hdmatx != NULL)
4016 {
4017 /* Set the I2C DMA transfer complete callback */
4018 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
4019
4020 /* Set the DMA error callback */
4021 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
4022
4023 /* Set the unused DMA callbacks to NULL */
4024 hi2c->hdmatx->XferHalfCpltCallback = NULL;
4025 hi2c->hdmatx->XferAbortCallback = NULL;
4026
4027 /* Enable the DMA channel */
4028 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
4029 hi2c->XferSize);
4030 }
4031 else
4032 {
4033 /* Update I2C state */
4034 hi2c->State = HAL_I2C_STATE_LISTEN;
4035 hi2c->Mode = HAL_I2C_MODE_NONE;
4036
4037 /* Update I2C error code */
4038 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4039
4040 /* Process Unlocked */
4041 __HAL_UNLOCK(hi2c);
4042
4043 return HAL_ERROR;
4044 }
4045
4046 if (dmaxferstatus == HAL_OK)
4047 {
4048 /* Update XferCount value */
4049 hi2c->XferCount -= hi2c->XferSize;
4050
4051 /* Reset XferSize */
4052 hi2c->XferSize = 0;
4053 }
4054 else
4055 {
4056 /* Update I2C state */
4057 hi2c->State = HAL_I2C_STATE_LISTEN;
4058 hi2c->Mode = HAL_I2C_MODE_NONE;
4059
4060 /* Update I2C error code */
4061 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4062
4063 /* Process Unlocked */
4064 __HAL_UNLOCK(hi2c);
4065
4066 return HAL_ERROR;
4067 }
4068
4069 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4070 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
4071 {
4072 /* Clear ADDR flag after prepare the transfer parameters */
4073 /* This action will generate an acknowledge to the Master */
4074 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4075 }
4076
4077 /* Process Unlocked */
4078 __HAL_UNLOCK(hi2c);
4079
4080 /* Enable DMA Request */
4081 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
4082
4083 /* Note : The I2C interrupts must be enabled after unlocking current process
4084 to avoid the risk of I2C interrupt handle execution before current
4085 process unlock */
4086 /* Enable ERR, STOP, NACK, ADDR interrupts */
4087 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4088
4089 return HAL_OK;
4090 }
4091 else
4092 {
4093 return HAL_ERROR;
4094 }
4095 }
4096
4097 /**
4098 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
4099 * @note This interface allow to manage repeated start condition when a direction change during transfer
4100 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4101 * the configuration information for the specified I2C.
4102 * @param pData Pointer to data buffer
4103 * @param Size Amount of data to be sent
4104 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4105 * @retval HAL status
4106 */
HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4107 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4108 uint32_t XferOptions)
4109 {
4110 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4111 FlagStatus tmp;
4112
4113 /* Check the parameters */
4114 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4115
4116 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4117 {
4118 if ((pData == NULL) || (Size == 0U))
4119 {
4120 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4121 return HAL_ERROR;
4122 }
4123
4124 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4125 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
4126
4127 /* Process Locked */
4128 __HAL_LOCK(hi2c);
4129
4130 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4131 /* and then toggle the HAL slave TX state to RX state */
4132 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4133 {
4134 /* Disable associated Interrupts */
4135 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4136
4137 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4138 {
4139 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4140
4141 /* Abort DMA Xfer if any */
4142 if (hi2c->hdmatx != NULL)
4143 {
4144 /* Set the I2C DMA Abort callback :
4145 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4146 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4147
4148 /* Abort DMA TX */
4149 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4150 {
4151 /* Call Directly XferAbortCallback function in case of error */
4152 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4153 }
4154 }
4155 }
4156 }
4157
4158 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4159 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4160 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4161
4162 /* Enable Address Acknowledge */
4163 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4164
4165 /* Prepare transfer parameters */
4166 hi2c->pBuffPtr = pData;
4167 hi2c->XferCount = Size;
4168 hi2c->XferSize = hi2c->XferCount;
4169 hi2c->XferOptions = XferOptions;
4170 hi2c->XferISR = I2C_Slave_ISR_IT;
4171
4172 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4173 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
4174 {
4175 /* Clear ADDR flag after prepare the transfer parameters */
4176 /* This action will generate an acknowledge to the Master */
4177 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4178 }
4179
4180 /* Process Unlocked */
4181 __HAL_UNLOCK(hi2c);
4182
4183 /* Note : The I2C interrupts must be enabled after unlocking current process
4184 to avoid the risk of I2C interrupt handle execution before current
4185 process unlock */
4186 /* REnable ADDR interrupt */
4187 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
4188
4189 return HAL_OK;
4190 }
4191 else
4192 {
4193 return HAL_ERROR;
4194 }
4195 }
4196
4197 /**
4198 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
4199 * @note This interface allow to manage repeated start condition when a direction change during transfer
4200 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4201 * the configuration information for the specified I2C.
4202 * @param pData Pointer to data buffer
4203 * @param Size Amount of data to be sent
4204 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4205 * @retval HAL status
4206 */
HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4207 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4208 uint32_t XferOptions)
4209 {
4210 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4211 FlagStatus tmp;
4212 HAL_StatusTypeDef dmaxferstatus;
4213
4214 /* Check the parameters */
4215 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4216
4217 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4218 {
4219 if ((pData == NULL) || (Size == 0U))
4220 {
4221 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4222 return HAL_ERROR;
4223 }
4224
4225 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4226 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
4227
4228 /* Process Locked */
4229 __HAL_LOCK(hi2c);
4230
4231 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4232 /* and then toggle the HAL slave TX state to RX state */
4233 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4234 {
4235 /* Disable associated Interrupts */
4236 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4237
4238 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4239 {
4240 /* Abort DMA Xfer if any */
4241 if (hi2c->hdmatx != NULL)
4242 {
4243 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4244
4245 /* Set the I2C DMA Abort callback :
4246 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4247 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4248
4249 /* Abort DMA TX */
4250 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4251 {
4252 /* Call Directly XferAbortCallback function in case of error */
4253 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4254 }
4255 }
4256 }
4257 }
4258 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4259 {
4260 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4261 {
4262 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4263
4264 /* Abort DMA Xfer if any */
4265 if (hi2c->hdmarx != NULL)
4266 {
4267 /* Set the I2C DMA Abort callback :
4268 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4269 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4270
4271 /* Abort DMA RX */
4272 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4273 {
4274 /* Call Directly XferAbortCallback function in case of error */
4275 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4276 }
4277 }
4278 }
4279 }
4280 else
4281 {
4282 /* Nothing to do */
4283 }
4284
4285 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4286 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4287 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4288
4289 /* Enable Address Acknowledge */
4290 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4291
4292 /* Prepare transfer parameters */
4293 hi2c->pBuffPtr = pData;
4294 hi2c->XferCount = Size;
4295 hi2c->XferSize = hi2c->XferCount;
4296 hi2c->XferOptions = XferOptions;
4297 hi2c->XferISR = I2C_Slave_ISR_DMA;
4298
4299 if (hi2c->hdmarx != NULL)
4300 {
4301 /* Set the I2C DMA transfer complete callback */
4302 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
4303
4304 /* Set the DMA error callback */
4305 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4306
4307 /* Set the unused DMA callbacks to NULL */
4308 hi2c->hdmarx->XferHalfCpltCallback = NULL;
4309 hi2c->hdmarx->XferAbortCallback = NULL;
4310
4311 /* Enable the DMA channel */
4312 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR,
4313 (uint32_t)pData, hi2c->XferSize);
4314 }
4315 else
4316 {
4317 /* Update I2C state */
4318 hi2c->State = HAL_I2C_STATE_LISTEN;
4319 hi2c->Mode = HAL_I2C_MODE_NONE;
4320
4321 /* Update I2C error code */
4322 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4323
4324 /* Process Unlocked */
4325 __HAL_UNLOCK(hi2c);
4326
4327 return HAL_ERROR;
4328 }
4329
4330 if (dmaxferstatus == HAL_OK)
4331 {
4332 /* Update XferCount value */
4333 hi2c->XferCount -= hi2c->XferSize;
4334
4335 /* Reset XferSize */
4336 hi2c->XferSize = 0;
4337 }
4338 else
4339 {
4340 /* Update I2C state */
4341 hi2c->State = HAL_I2C_STATE_LISTEN;
4342 hi2c->Mode = HAL_I2C_MODE_NONE;
4343
4344 /* Update I2C error code */
4345 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4346
4347 /* Process Unlocked */
4348 __HAL_UNLOCK(hi2c);
4349
4350 return HAL_ERROR;
4351 }
4352
4353 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4354 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
4355 {
4356 /* Clear ADDR flag after prepare the transfer parameters */
4357 /* This action will generate an acknowledge to the Master */
4358 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4359 }
4360
4361 /* Process Unlocked */
4362 __HAL_UNLOCK(hi2c);
4363
4364 /* Enable DMA Request */
4365 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
4366
4367 /* Note : The I2C interrupts must be enabled after unlocking current process
4368 to avoid the risk of I2C interrupt handle execution before current
4369 process unlock */
4370 /* REnable ADDR interrupt */
4371 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
4372
4373 return HAL_OK;
4374 }
4375 else
4376 {
4377 return HAL_ERROR;
4378 }
4379 }
4380
4381 /**
4382 * @brief Enable the Address listen mode with Interrupt.
4383 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4384 * the configuration information for the specified I2C.
4385 * @retval HAL status
4386 */
HAL_I2C_EnableListen_IT(I2C_HandleTypeDef * hi2c)4387 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
4388 {
4389 if (hi2c->State == HAL_I2C_STATE_READY)
4390 {
4391 hi2c->State = HAL_I2C_STATE_LISTEN;
4392 hi2c->XferISR = I2C_Slave_ISR_IT;
4393
4394 /* Enable the Address Match interrupt */
4395 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4396
4397 return HAL_OK;
4398 }
4399 else
4400 {
4401 return HAL_BUSY;
4402 }
4403 }
4404
4405 /**
4406 * @brief Disable the Address listen mode with Interrupt.
4407 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4408 * the configuration information for the specified I2C
4409 * @retval HAL status
4410 */
HAL_I2C_DisableListen_IT(I2C_HandleTypeDef * hi2c)4411 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
4412 {
4413 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4414 uint32_t tmp;
4415
4416 /* Disable Address listen mode only if a transfer is not ongoing */
4417 if (hi2c->State == HAL_I2C_STATE_LISTEN)
4418 {
4419 tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
4420 hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
4421 hi2c->State = HAL_I2C_STATE_READY;
4422 hi2c->Mode = HAL_I2C_MODE_NONE;
4423 hi2c->XferISR = NULL;
4424
4425 /* Disable the Address Match interrupt */
4426 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4427
4428 return HAL_OK;
4429 }
4430 else
4431 {
4432 return HAL_BUSY;
4433 }
4434 }
4435
4436 /**
4437 * @brief Abort a master I2C IT or DMA process communication with Interrupt.
4438 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4439 * the configuration information for the specified I2C.
4440 * @param DevAddress Target device address: The device 7 bits address value
4441 * in datasheet must be shifted to the left before calling the interface
4442 * @retval HAL status
4443 */
HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress)4444 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
4445 {
4446 if (hi2c->Mode == HAL_I2C_MODE_MASTER)
4447 {
4448 /* Process Locked */
4449 __HAL_LOCK(hi2c);
4450
4451 /* Disable Interrupts and Store Previous state */
4452 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
4453 {
4454 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4455 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
4456 }
4457 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
4458 {
4459 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4460 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
4461 }
4462 else
4463 {
4464 /* Do nothing */
4465 }
4466
4467 /* Set State at HAL_I2C_STATE_ABORT */
4468 hi2c->State = HAL_I2C_STATE_ABORT;
4469
4470 /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
4471 /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
4472 I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
4473
4474 /* Process Unlocked */
4475 __HAL_UNLOCK(hi2c);
4476
4477 /* Note : The I2C interrupts must be enabled after unlocking current process
4478 to avoid the risk of I2C interrupt handle execution before current
4479 process unlock */
4480 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
4481
4482 return HAL_OK;
4483 }
4484 else
4485 {
4486 /* Wrong usage of abort function */
4487 /* This function should be used only in case of abort monitored by master device */
4488 return HAL_ERROR;
4489 }
4490 }
4491
4492 /**
4493 * @}
4494 */
4495
4496 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
4497 * @{
4498 */
4499
4500 /**
4501 * @brief This function handles I2C event interrupt request.
4502 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4503 * the configuration information for the specified I2C.
4504 * @retval None
4505 */
HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef * hi2c)4506 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */
4507 {
4508 /* Get current IT Flags and IT sources value */
4509 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4510 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4511
4512 /* I2C events treatment -------------------------------------*/
4513 if (hi2c->XferISR != NULL)
4514 {
4515 hi2c->XferISR(hi2c, itflags, itsources);
4516 }
4517 }
4518
4519 /**
4520 * @brief This function handles I2C error interrupt request.
4521 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4522 * the configuration information for the specified I2C.
4523 * @retval None
4524 */
HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef * hi2c)4525 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
4526 {
4527 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4528 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4529 uint32_t tmperror;
4530
4531 /* I2C Bus error interrupt occurred ------------------------------------*/
4532 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
4533 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4534 {
4535 hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
4536
4537 /* Clear BERR flag */
4538 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
4539 }
4540
4541 /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
4542 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
4543 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4544 {
4545 hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
4546
4547 /* Clear OVR flag */
4548 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
4549 }
4550
4551 /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
4552 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
4553 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4554 {
4555 hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
4556
4557 /* Clear ARLO flag */
4558 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
4559 }
4560
4561 /* Store current volatile hi2c->ErrorCode, misra rule */
4562 tmperror = hi2c->ErrorCode;
4563
4564 /* Call the Error Callback in case of Error detected */
4565 if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
4566 {
4567 I2C_ITError(hi2c, tmperror);
4568 }
4569 }
4570
4571 /**
4572 * @brief Master Tx Transfer completed callback.
4573 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4574 * the configuration information for the specified I2C.
4575 * @retval None
4576 */
HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef * hi2c)4577 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
4578 {
4579 /* Prevent unused argument(s) compilation warning */
4580 UNUSED(hi2c);
4581
4582 /* NOTE : This function should not be modified, when the callback is needed,
4583 the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
4584 */
4585 }
4586
4587 /**
4588 * @brief Master Rx Transfer completed callback.
4589 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4590 * the configuration information for the specified I2C.
4591 * @retval None
4592 */
HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef * hi2c)4593 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
4594 {
4595 /* Prevent unused argument(s) compilation warning */
4596 UNUSED(hi2c);
4597
4598 /* NOTE : This function should not be modified, when the callback is needed,
4599 the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
4600 */
4601 }
4602
4603 /** @brief Slave Tx Transfer completed callback.
4604 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4605 * the configuration information for the specified I2C.
4606 * @retval None
4607 */
HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef * hi2c)4608 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
4609 {
4610 /* Prevent unused argument(s) compilation warning */
4611 UNUSED(hi2c);
4612
4613 /* NOTE : This function should not be modified, when the callback is needed,
4614 the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
4615 */
4616 }
4617
4618 /**
4619 * @brief Slave Rx Transfer completed callback.
4620 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4621 * the configuration information for the specified I2C.
4622 * @retval None
4623 */
HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef * hi2c)4624 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
4625 {
4626 /* Prevent unused argument(s) compilation warning */
4627 UNUSED(hi2c);
4628
4629 /* NOTE : This function should not be modified, when the callback is needed,
4630 the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
4631 */
4632 }
4633
4634 /**
4635 * @brief Slave Address Match callback.
4636 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4637 * the configuration information for the specified I2C.
4638 * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
4639 * @param AddrMatchCode Address Match Code
4640 * @retval None
4641 */
HAL_I2C_AddrCallback(I2C_HandleTypeDef * hi2c,uint8_t TransferDirection,uint16_t AddrMatchCode)4642 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
4643 {
4644 /* Prevent unused argument(s) compilation warning */
4645 UNUSED(hi2c);
4646 UNUSED(TransferDirection);
4647 UNUSED(AddrMatchCode);
4648
4649 /* NOTE : This function should not be modified, when the callback is needed,
4650 the HAL_I2C_AddrCallback() could be implemented in the user file
4651 */
4652 }
4653
4654 /**
4655 * @brief Listen Complete callback.
4656 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4657 * the configuration information for the specified I2C.
4658 * @retval None
4659 */
HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef * hi2c)4660 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
4661 {
4662 /* Prevent unused argument(s) compilation warning */
4663 UNUSED(hi2c);
4664
4665 /* NOTE : This function should not be modified, when the callback is needed,
4666 the HAL_I2C_ListenCpltCallback() could be implemented in the user file
4667 */
4668 }
4669
4670 /**
4671 * @brief Memory Tx Transfer completed callback.
4672 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4673 * the configuration information for the specified I2C.
4674 * @retval None
4675 */
HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef * hi2c)4676 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
4677 {
4678 /* Prevent unused argument(s) compilation warning */
4679 UNUSED(hi2c);
4680
4681 /* NOTE : This function should not be modified, when the callback is needed,
4682 the HAL_I2C_MemTxCpltCallback could be implemented in the user file
4683 */
4684 }
4685
4686 /**
4687 * @brief Memory Rx Transfer completed callback.
4688 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4689 * the configuration information for the specified I2C.
4690 * @retval None
4691 */
HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef * hi2c)4692 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
4693 {
4694 /* Prevent unused argument(s) compilation warning */
4695 UNUSED(hi2c);
4696
4697 /* NOTE : This function should not be modified, when the callback is needed,
4698 the HAL_I2C_MemRxCpltCallback could be implemented in the user file
4699 */
4700 }
4701
4702 /**
4703 * @brief I2C error callback.
4704 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4705 * the configuration information for the specified I2C.
4706 * @retval None
4707 */
HAL_I2C_ErrorCallback(I2C_HandleTypeDef * hi2c)4708 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
4709 {
4710 /* Prevent unused argument(s) compilation warning */
4711 UNUSED(hi2c);
4712
4713 /* NOTE : This function should not be modified, when the callback is needed,
4714 the HAL_I2C_ErrorCallback could be implemented in the user file
4715 */
4716 }
4717
4718 /**
4719 * @brief I2C abort callback.
4720 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4721 * the configuration information for the specified I2C.
4722 * @retval None
4723 */
HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef * hi2c)4724 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
4725 {
4726 /* Prevent unused argument(s) compilation warning */
4727 UNUSED(hi2c);
4728
4729 /* NOTE : This function should not be modified, when the callback is needed,
4730 the HAL_I2C_AbortCpltCallback could be implemented in the user file
4731 */
4732 }
4733
4734 /**
4735 * @}
4736 */
4737
4738 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
4739 * @brief Peripheral State, Mode and Error functions
4740 *
4741 @verbatim
4742 ===============================================================================
4743 ##### Peripheral State, Mode and Error functions #####
4744 ===============================================================================
4745 [..]
4746 This subsection permit to get in run-time the status of the peripheral
4747 and the data flow.
4748
4749 @endverbatim
4750 * @{
4751 */
4752
4753 /**
4754 * @brief Return the I2C handle state.
4755 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4756 * the configuration information for the specified I2C.
4757 * @retval HAL state
4758 */
HAL_I2C_GetState(const I2C_HandleTypeDef * hi2c)4759 HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c)
4760 {
4761 /* Return I2C handle state */
4762 return hi2c->State;
4763 }
4764
4765 /**
4766 * @brief Returns the I2C Master, Slave, Memory or no mode.
4767 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4768 * the configuration information for I2C module
4769 * @retval HAL mode
4770 */
HAL_I2C_GetMode(const I2C_HandleTypeDef * hi2c)4771 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c)
4772 {
4773 return hi2c->Mode;
4774 }
4775
4776 /**
4777 * @brief Return the I2C error code.
4778 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4779 * the configuration information for the specified I2C.
4780 * @retval I2C Error Code
4781 */
HAL_I2C_GetError(const I2C_HandleTypeDef * hi2c)4782 uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c)
4783 {
4784 return hi2c->ErrorCode;
4785 }
4786
4787 /**
4788 * @}
4789 */
4790
4791 /**
4792 * @}
4793 */
4794
4795 /** @addtogroup I2C_Private_Functions
4796 * @{
4797 */
4798
4799 /**
4800 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
4801 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4802 * the configuration information for the specified I2C.
4803 * @param ITFlags Interrupt flags to handle.
4804 * @param ITSources Interrupt sources enabled.
4805 * @retval HAL status
4806 */
I2C_Master_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)4807 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
4808 uint32_t ITSources)
4809 {
4810 uint16_t devaddress;
4811 uint32_t tmpITFlags = ITFlags;
4812
4813 /* Process Locked */
4814 __HAL_LOCK(hi2c);
4815
4816 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
4817 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
4818 {
4819 /* Clear NACK Flag */
4820 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4821
4822 /* Set corresponding Error Code */
4823 /* No need to generate STOP, it is automatically done */
4824 /* Error callback will be send during stop flag treatment */
4825 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
4826
4827 /* Flush TX register */
4828 I2C_Flush_TXDR(hi2c);
4829 }
4830 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
4831 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
4832 {
4833 /* Remove RXNE flag on temporary variable as read done */
4834 tmpITFlags &= ~I2C_FLAG_RXNE;
4835
4836 /* Read data from RXDR */
4837 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
4838
4839 /* Increment Buffer pointer */
4840 hi2c->pBuffPtr++;
4841
4842 hi2c->XferSize--;
4843 hi2c->XferCount--;
4844 }
4845 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
4846 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
4847 {
4848 /* Write data to TXDR */
4849 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
4850
4851 /* Increment Buffer pointer */
4852 hi2c->pBuffPtr++;
4853
4854 hi2c->XferSize--;
4855 hi2c->XferCount--;
4856 }
4857 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
4858 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
4859 {
4860 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
4861 {
4862 devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
4863
4864 if (hi2c->XferCount > MAX_NBYTE_SIZE)
4865 {
4866 hi2c->XferSize = MAX_NBYTE_SIZE;
4867 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
4868 }
4869 else
4870 {
4871 hi2c->XferSize = hi2c->XferCount;
4872 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
4873 {
4874 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
4875 hi2c->XferOptions, I2C_NO_STARTSTOP);
4876 }
4877 else
4878 {
4879 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
4880 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
4881 }
4882 }
4883 }
4884 else
4885 {
4886 /* Call TxCpltCallback() if no stop mode is set */
4887 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
4888 {
4889 /* Call I2C Master Sequential complete process */
4890 I2C_ITMasterSeqCplt(hi2c);
4891 }
4892 else
4893 {
4894 /* Wrong size Status regarding TCR flag event */
4895 /* Call the corresponding callback to inform upper layer of End of Transfer */
4896 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
4897 }
4898 }
4899 }
4900 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
4901 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
4902 {
4903 if (hi2c->XferCount == 0U)
4904 {
4905 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
4906 {
4907 /* Generate a stop condition in case of no transfer option */
4908 if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
4909 {
4910 /* Generate Stop */
4911 hi2c->Instance->CR2 |= I2C_CR2_STOP;
4912 }
4913 else
4914 {
4915 /* Call I2C Master Sequential complete process */
4916 I2C_ITMasterSeqCplt(hi2c);
4917 }
4918 }
4919 }
4920 else
4921 {
4922 /* Wrong size Status regarding TC flag event */
4923 /* Call the corresponding callback to inform upper layer of End of Transfer */
4924 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
4925 }
4926 }
4927 else
4928 {
4929 /* Nothing to do */
4930 }
4931
4932 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
4933 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
4934 {
4935 /* Call I2C Master complete process */
4936 I2C_ITMasterCplt(hi2c, tmpITFlags);
4937 }
4938
4939 /* Process Unlocked */
4940 __HAL_UNLOCK(hi2c);
4941
4942 return HAL_OK;
4943 }
4944
4945 /**
4946 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
4947 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4948 * the configuration information for the specified I2C.
4949 * @param ITFlags Interrupt flags to handle.
4950 * @param ITSources Interrupt sources enabled.
4951 * @retval HAL status
4952 */
I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)4953 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
4954 uint32_t ITSources)
4955 {
4956 uint32_t direction = I2C_GENERATE_START_WRITE;
4957 uint32_t tmpITFlags = ITFlags;
4958
4959 /* Process Locked */
4960 __HAL_LOCK(hi2c);
4961
4962 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
4963 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
4964 {
4965 /* Clear NACK Flag */
4966 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4967
4968 /* Set corresponding Error Code */
4969 /* No need to generate STOP, it is automatically done */
4970 /* Error callback will be send during stop flag treatment */
4971 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
4972
4973 /* Flush TX register */
4974 I2C_Flush_TXDR(hi2c);
4975 }
4976 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
4977 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
4978 {
4979 /* Remove RXNE flag on temporary variable as read done */
4980 tmpITFlags &= ~I2C_FLAG_RXNE;
4981
4982 /* Read data from RXDR */
4983 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
4984
4985 /* Increment Buffer pointer */
4986 hi2c->pBuffPtr++;
4987
4988 hi2c->XferSize--;
4989 hi2c->XferCount--;
4990 }
4991 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
4992 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
4993 {
4994 if (hi2c->Memaddress == 0xFFFFFFFFU)
4995 {
4996 /* Write data to TXDR */
4997 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
4998
4999 /* Increment Buffer pointer */
5000 hi2c->pBuffPtr++;
5001
5002 hi2c->XferSize--;
5003 hi2c->XferCount--;
5004 }
5005 else
5006 {
5007 /* Write LSB part of Memory Address */
5008 hi2c->Instance->TXDR = hi2c->Memaddress;
5009
5010 /* Reset Memaddress content */
5011 hi2c->Memaddress = 0xFFFFFFFFU;
5012 }
5013 }
5014 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
5015 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5016 {
5017 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
5018 {
5019 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5020 {
5021 hi2c->XferSize = MAX_NBYTE_SIZE;
5022 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5023 I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5024 }
5025 else
5026 {
5027 hi2c->XferSize = hi2c->XferCount;
5028 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5029 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5030 }
5031 }
5032 else
5033 {
5034 /* Wrong size Status regarding TCR flag event */
5035 /* Call the corresponding callback to inform upper layer of End of Transfer */
5036 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5037 }
5038 }
5039 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
5040 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5041 {
5042 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5043 {
5044 direction = I2C_GENERATE_START_READ;
5045 }
5046
5047 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5048 {
5049 hi2c->XferSize = MAX_NBYTE_SIZE;
5050
5051 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
5052 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5053 I2C_RELOAD_MODE, direction);
5054 }
5055 else
5056 {
5057 hi2c->XferSize = hi2c->XferCount;
5058
5059 /* Set NBYTES to write and generate RESTART */
5060 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5061 I2C_AUTOEND_MODE, direction);
5062 }
5063 }
5064 else
5065 {
5066 /* Nothing to do */
5067 }
5068
5069 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5070 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5071 {
5072 /* Call I2C Master complete process */
5073 I2C_ITMasterCplt(hi2c, tmpITFlags);
5074 }
5075
5076 /* Process Unlocked */
5077 __HAL_UNLOCK(hi2c);
5078
5079 return HAL_OK;
5080 }
5081
5082 /**
5083 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
5084 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5085 * the configuration information for the specified I2C.
5086 * @param ITFlags Interrupt flags to handle.
5087 * @param ITSources Interrupt sources enabled.
5088 * @retval HAL status
5089 */
I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5090 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5091 uint32_t ITSources)
5092 {
5093 uint32_t tmpoptions = hi2c->XferOptions;
5094 uint32_t tmpITFlags = ITFlags;
5095
5096 /* Process locked */
5097 __HAL_LOCK(hi2c);
5098
5099 /* Check if STOPF is set */
5100 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5101 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5102 {
5103 /* Call I2C Slave complete process */
5104 I2C_ITSlaveCplt(hi2c, tmpITFlags);
5105 }
5106
5107 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
5108 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5109 {
5110 /* Check that I2C transfer finished */
5111 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
5112 /* Mean XferCount == 0*/
5113 /* So clear Flag NACKF only */
5114 if (hi2c->XferCount == 0U)
5115 {
5116 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
5117 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
5118 Warning[Pa134]: left and right operands are identical */
5119 {
5120 /* Call I2C Listen complete process */
5121 I2C_ITListenCplt(hi2c, tmpITFlags);
5122 }
5123 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
5124 {
5125 /* Clear NACK Flag */
5126 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5127
5128 /* Flush TX register */
5129 I2C_Flush_TXDR(hi2c);
5130
5131 /* Last Byte is Transmitted */
5132 /* Call I2C Slave Sequential complete process */
5133 I2C_ITSlaveSeqCplt(hi2c);
5134 }
5135 else
5136 {
5137 /* Clear NACK Flag */
5138 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5139 }
5140 }
5141 else
5142 {
5143 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
5144 /* Clear NACK Flag */
5145 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5146
5147 /* Set ErrorCode corresponding to a Non-Acknowledge */
5148 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5149
5150 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
5151 {
5152 /* Call the corresponding callback to inform upper layer of End of Transfer */
5153 I2C_ITError(hi2c, hi2c->ErrorCode);
5154 }
5155 }
5156 }
5157 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
5158 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
5159 {
5160 if (hi2c->XferCount > 0U)
5161 {
5162 /* Read data from RXDR */
5163 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5164
5165 /* Increment Buffer pointer */
5166 hi2c->pBuffPtr++;
5167
5168 hi2c->XferSize--;
5169 hi2c->XferCount--;
5170 }
5171
5172 if ((hi2c->XferCount == 0U) && \
5173 (tmpoptions != I2C_NO_OPTION_FRAME))
5174 {
5175 /* Call I2C Slave Sequential complete process */
5176 I2C_ITSlaveSeqCplt(hi2c);
5177 }
5178 }
5179 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
5180 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
5181 {
5182 I2C_ITAddrCplt(hi2c, tmpITFlags);
5183 }
5184 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5185 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5186 {
5187 /* Write data to TXDR only if XferCount not reach "0" */
5188 /* A TXIS flag can be set, during STOP treatment */
5189 /* Check if all Data have already been sent */
5190 /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
5191 if (hi2c->XferCount > 0U)
5192 {
5193 /* Write data to TXDR */
5194 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5195
5196 /* Increment Buffer pointer */
5197 hi2c->pBuffPtr++;
5198
5199 hi2c->XferCount--;
5200 hi2c->XferSize--;
5201 }
5202 else
5203 {
5204 if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
5205 {
5206 /* Last Byte is Transmitted */
5207 /* Call I2C Slave Sequential complete process */
5208 I2C_ITSlaveSeqCplt(hi2c);
5209 }
5210 }
5211 }
5212 else
5213 {
5214 /* Nothing to do */
5215 }
5216
5217 /* Process Unlocked */
5218 __HAL_UNLOCK(hi2c);
5219
5220 return HAL_OK;
5221 }
5222
5223 /**
5224 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
5225 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5226 * the configuration information for the specified I2C.
5227 * @param ITFlags Interrupt flags to handle.
5228 * @param ITSources Interrupt sources enabled.
5229 * @retval HAL status
5230 */
I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5231 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5232 uint32_t ITSources)
5233 {
5234 uint16_t devaddress;
5235 uint32_t xfermode;
5236
5237 /* Process Locked */
5238 __HAL_LOCK(hi2c);
5239
5240 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5241 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5242 {
5243 /* Clear NACK Flag */
5244 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5245
5246 /* Set corresponding Error Code */
5247 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5248
5249 /* No need to generate STOP, it is automatically done */
5250 /* But enable STOP interrupt, to treat it */
5251 /* Error callback will be send during stop flag treatment */
5252 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
5253
5254 /* Flush TX register */
5255 I2C_Flush_TXDR(hi2c);
5256 }
5257 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
5258 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5259 {
5260 /* Disable TC interrupt */
5261 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
5262
5263 if (hi2c->XferCount != 0U)
5264 {
5265 /* Recover Slave address */
5266 devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
5267
5268 /* Prepare the new XferSize to transfer */
5269 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5270 {
5271 hi2c->XferSize = MAX_NBYTE_SIZE;
5272 xfermode = I2C_RELOAD_MODE;
5273 }
5274 else
5275 {
5276 hi2c->XferSize = hi2c->XferCount;
5277 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
5278 {
5279 xfermode = hi2c->XferOptions;
5280 }
5281 else
5282 {
5283 xfermode = I2C_AUTOEND_MODE;
5284 }
5285 }
5286
5287 /* Set the new XferSize in Nbytes register */
5288 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
5289
5290 /* Update XferCount value */
5291 hi2c->XferCount -= hi2c->XferSize;
5292
5293 /* Enable DMA Request */
5294 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5295 {
5296 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5297 }
5298 else
5299 {
5300 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5301 }
5302 }
5303 else
5304 {
5305 /* Call TxCpltCallback() if no stop mode is set */
5306 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5307 {
5308 /* Call I2C Master Sequential complete process */
5309 I2C_ITMasterSeqCplt(hi2c);
5310 }
5311 else
5312 {
5313 /* Wrong size Status regarding TCR flag event */
5314 /* Call the corresponding callback to inform upper layer of End of Transfer */
5315 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5316 }
5317 }
5318 }
5319 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
5320 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5321 {
5322 if (hi2c->XferCount == 0U)
5323 {
5324 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5325 {
5326 /* Generate a stop condition in case of no transfer option */
5327 if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
5328 {
5329 /* Generate Stop */
5330 hi2c->Instance->CR2 |= I2C_CR2_STOP;
5331 }
5332 else
5333 {
5334 /* Call I2C Master Sequential complete process */
5335 I2C_ITMasterSeqCplt(hi2c);
5336 }
5337 }
5338 }
5339 else
5340 {
5341 /* Wrong size Status regarding TC flag event */
5342 /* Call the corresponding callback to inform upper layer of End of Transfer */
5343 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5344 }
5345 }
5346 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5347 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5348 {
5349 /* Call I2C Master complete process */
5350 I2C_ITMasterCplt(hi2c, ITFlags);
5351 }
5352 else
5353 {
5354 /* Nothing to do */
5355 }
5356
5357 /* Process Unlocked */
5358 __HAL_UNLOCK(hi2c);
5359
5360 return HAL_OK;
5361 }
5362
5363 /**
5364 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
5365 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5366 * the configuration information for the specified I2C.
5367 * @param ITFlags Interrupt flags to handle.
5368 * @param ITSources Interrupt sources enabled.
5369 * @retval HAL status
5370 */
I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5371 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5372 uint32_t ITSources)
5373 {
5374 uint32_t direction = I2C_GENERATE_START_WRITE;
5375
5376 /* Process Locked */
5377 __HAL_LOCK(hi2c);
5378
5379 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5380 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5381 {
5382 /* Clear NACK Flag */
5383 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5384
5385 /* Set corresponding Error Code */
5386 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5387
5388 /* No need to generate STOP, it is automatically done */
5389 /* But enable STOP interrupt, to treat it */
5390 /* Error callback will be send during stop flag treatment */
5391 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
5392
5393 /* Flush TX register */
5394 I2C_Flush_TXDR(hi2c);
5395 }
5396 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
5397 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5398 {
5399 /* Write LSB part of Memory Address */
5400 hi2c->Instance->TXDR = hi2c->Memaddress;
5401
5402 /* Reset Memaddress content */
5403 hi2c->Memaddress = 0xFFFFFFFFU;
5404 }
5405 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
5406 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5407 {
5408 /* Enable only Error interrupt */
5409 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
5410
5411 if (hi2c->XferCount != 0U)
5412 {
5413 /* Prepare the new XferSize to transfer */
5414 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5415 {
5416 hi2c->XferSize = MAX_NBYTE_SIZE;
5417 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5418 I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5419 }
5420 else
5421 {
5422 hi2c->XferSize = hi2c->XferCount;
5423 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5424 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5425 }
5426
5427 /* Update XferCount value */
5428 hi2c->XferCount -= hi2c->XferSize;
5429
5430 /* Enable DMA Request */
5431 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5432 {
5433 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5434 }
5435 else
5436 {
5437 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5438 }
5439 }
5440 else
5441 {
5442 /* Wrong size Status regarding TCR flag event */
5443 /* Call the corresponding callback to inform upper layer of End of Transfer */
5444 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5445 }
5446 }
5447 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
5448 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5449 {
5450 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5451 {
5452 direction = I2C_GENERATE_START_READ;
5453 }
5454
5455 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5456 {
5457 hi2c->XferSize = MAX_NBYTE_SIZE;
5458
5459 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
5460 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5461 I2C_RELOAD_MODE, direction);
5462 }
5463 else
5464 {
5465 hi2c->XferSize = hi2c->XferCount;
5466
5467 /* Set NBYTES to write and generate RESTART */
5468 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5469 I2C_AUTOEND_MODE, direction);
5470 }
5471
5472 /* Update XferCount value */
5473 hi2c->XferCount -= hi2c->XferSize;
5474
5475 /* Enable DMA Request */
5476 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5477 {
5478 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5479 }
5480 else
5481 {
5482 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5483 }
5484 }
5485 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5486 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5487 {
5488 /* Call I2C Master complete process */
5489 I2C_ITMasterCplt(hi2c, ITFlags);
5490 }
5491 else
5492 {
5493 /* Nothing to do */
5494 }
5495
5496 /* Process Unlocked */
5497 __HAL_UNLOCK(hi2c);
5498
5499 return HAL_OK;
5500 }
5501
5502 /**
5503 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
5504 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5505 * the configuration information for the specified I2C.
5506 * @param ITFlags Interrupt flags to handle.
5507 * @param ITSources Interrupt sources enabled.
5508 * @retval HAL status
5509 */
I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5510 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5511 uint32_t ITSources)
5512 {
5513 uint32_t tmpoptions = hi2c->XferOptions;
5514 uint32_t treatdmanack = 0U;
5515 HAL_I2C_StateTypeDef tmpstate;
5516
5517 /* Process locked */
5518 __HAL_LOCK(hi2c);
5519
5520 /* Check if STOPF is set */
5521 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5522 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5523 {
5524 /* Call I2C Slave complete process */
5525 I2C_ITSlaveCplt(hi2c, ITFlags);
5526 }
5527
5528 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5529 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5530 {
5531 /* Check that I2C transfer finished */
5532 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
5533 /* Mean XferCount == 0 */
5534 /* So clear Flag NACKF only */
5535 if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
5536 (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
5537 {
5538 /* Split check of hdmarx, for MISRA compliance */
5539 if (hi2c->hdmarx != NULL)
5540 {
5541 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
5542 {
5543 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
5544 {
5545 treatdmanack = 1U;
5546 }
5547 }
5548 }
5549
5550 /* Split check of hdmatx, for MISRA compliance */
5551 if (hi2c->hdmatx != NULL)
5552 {
5553 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
5554 {
5555 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
5556 {
5557 treatdmanack = 1U;
5558 }
5559 }
5560 }
5561
5562 if (treatdmanack == 1U)
5563 {
5564 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
5565 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
5566 Warning[Pa134]: left and right operands are identical */
5567 {
5568 /* Call I2C Listen complete process */
5569 I2C_ITListenCplt(hi2c, ITFlags);
5570 }
5571 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
5572 {
5573 /* Clear NACK Flag */
5574 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5575
5576 /* Flush TX register */
5577 I2C_Flush_TXDR(hi2c);
5578
5579 /* Last Byte is Transmitted */
5580 /* Call I2C Slave Sequential complete process */
5581 I2C_ITSlaveSeqCplt(hi2c);
5582 }
5583 else
5584 {
5585 /* Clear NACK Flag */
5586 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5587 }
5588 }
5589 else
5590 {
5591 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
5592 /* Clear NACK Flag */
5593 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5594
5595 /* Set ErrorCode corresponding to a Non-Acknowledge */
5596 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5597
5598 /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
5599 tmpstate = hi2c->State;
5600
5601 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
5602 {
5603 if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
5604 {
5605 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
5606 }
5607 else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
5608 {
5609 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
5610 }
5611 else
5612 {
5613 /* Do nothing */
5614 }
5615
5616 /* Call the corresponding callback to inform upper layer of End of Transfer */
5617 I2C_ITError(hi2c, hi2c->ErrorCode);
5618 }
5619 }
5620 }
5621 else
5622 {
5623 /* Only Clear NACK Flag, no DMA treatment is pending */
5624 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5625 }
5626 }
5627 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
5628 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
5629 {
5630 I2C_ITAddrCplt(hi2c, ITFlags);
5631 }
5632 else
5633 {
5634 /* Nothing to do */
5635 }
5636
5637 /* Process Unlocked */
5638 __HAL_UNLOCK(hi2c);
5639
5640 return HAL_OK;
5641 }
5642
5643 /**
5644 * @brief Master sends target device address followed by internal memory address for write request.
5645 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5646 * the configuration information for the specified I2C.
5647 * @param DevAddress Target device address: The device 7 bits address value
5648 * in datasheet must be shifted to the left before calling the interface
5649 * @param MemAddress Internal memory address
5650 * @param MemAddSize Size of internal memory address
5651 * @param Timeout Timeout duration
5652 * @param Tickstart Tick start value
5653 * @retval HAL status
5654 */
I2C_RequestMemoryWrite(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)5655 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
5656 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
5657 uint32_t Tickstart)
5658 {
5659 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
5660
5661 /* Wait until TXIS flag is set */
5662 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5663 {
5664 return HAL_ERROR;
5665 }
5666
5667 /* If Memory address size is 8Bit */
5668 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
5669 {
5670 /* Send Memory Address */
5671 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5672 }
5673 /* If Memory address size is 16Bit */
5674 else
5675 {
5676 /* Send MSB of Memory Address */
5677 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
5678
5679 /* Wait until TXIS flag is set */
5680 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5681 {
5682 return HAL_ERROR;
5683 }
5684
5685 /* Send LSB of Memory Address */
5686 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5687 }
5688
5689 /* Wait until TCR flag is set */
5690 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
5691 {
5692 return HAL_ERROR;
5693 }
5694
5695 return HAL_OK;
5696 }
5697
5698 /**
5699 * @brief Master sends target device address followed by internal memory address for read request.
5700 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5701 * the configuration information for the specified I2C.
5702 * @param DevAddress Target device address: The device 7 bits address value
5703 * in datasheet must be shifted to the left before calling the interface
5704 * @param MemAddress Internal memory address
5705 * @param MemAddSize Size of internal memory address
5706 * @param Timeout Timeout duration
5707 * @param Tickstart Tick start value
5708 * @retval HAL status
5709 */
I2C_RequestMemoryRead(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)5710 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
5711 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
5712 uint32_t Tickstart)
5713 {
5714 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
5715
5716 /* Wait until TXIS flag is set */
5717 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5718 {
5719 return HAL_ERROR;
5720 }
5721
5722 /* If Memory address size is 8Bit */
5723 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
5724 {
5725 /* Send Memory Address */
5726 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5727 }
5728 /* If Memory address size is 16Bit */
5729 else
5730 {
5731 /* Send MSB of Memory Address */
5732 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
5733
5734 /* Wait until TXIS flag is set */
5735 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5736 {
5737 return HAL_ERROR;
5738 }
5739
5740 /* Send LSB of Memory Address */
5741 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5742 }
5743
5744 /* Wait until TC flag is set */
5745 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
5746 {
5747 return HAL_ERROR;
5748 }
5749
5750 return HAL_OK;
5751 }
5752
5753 /**
5754 * @brief I2C Address complete process callback.
5755 * @param hi2c I2C handle.
5756 * @param ITFlags Interrupt flags to handle.
5757 * @retval None
5758 */
I2C_ITAddrCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)5759 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
5760 {
5761 uint8_t transferdirection;
5762 uint16_t slaveaddrcode;
5763 uint16_t ownadd1code;
5764 uint16_t ownadd2code;
5765
5766 /* Prevent unused argument(s) compilation warning */
5767 UNUSED(ITFlags);
5768
5769 /* In case of Listen state, need to inform upper layer of address match code event */
5770 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
5771 {
5772 transferdirection = I2C_GET_DIR(hi2c);
5773 slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
5774 ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
5775 ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
5776
5777 /* If 10bits addressing mode is selected */
5778 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
5779 {
5780 if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
5781 {
5782 slaveaddrcode = ownadd1code;
5783 hi2c->AddrEventCount++;
5784 if (hi2c->AddrEventCount == 2U)
5785 {
5786 /* Reset Address Event counter */
5787 hi2c->AddrEventCount = 0U;
5788
5789 /* Clear ADDR flag */
5790 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
5791
5792 /* Process Unlocked */
5793 __HAL_UNLOCK(hi2c);
5794
5795 /* Call Slave Addr callback */
5796 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5797 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
5798 #else
5799 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
5800 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5801 }
5802 }
5803 else
5804 {
5805 slaveaddrcode = ownadd2code;
5806
5807 /* Disable ADDR Interrupts */
5808 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
5809
5810 /* Process Unlocked */
5811 __HAL_UNLOCK(hi2c);
5812
5813 /* Call Slave Addr callback */
5814 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5815 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
5816 #else
5817 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
5818 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5819 }
5820 }
5821 /* else 7 bits addressing mode is selected */
5822 else
5823 {
5824 /* Disable ADDR Interrupts */
5825 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
5826
5827 /* Process Unlocked */
5828 __HAL_UNLOCK(hi2c);
5829
5830 /* Call Slave Addr callback */
5831 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5832 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
5833 #else
5834 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
5835 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5836 }
5837 }
5838 /* Else clear address flag only */
5839 else
5840 {
5841 /* Clear ADDR flag */
5842 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
5843
5844 /* Process Unlocked */
5845 __HAL_UNLOCK(hi2c);
5846 }
5847 }
5848
5849 /**
5850 * @brief I2C Master sequential complete process.
5851 * @param hi2c I2C handle.
5852 * @retval None
5853 */
I2C_ITMasterSeqCplt(I2C_HandleTypeDef * hi2c)5854 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
5855 {
5856 /* Reset I2C handle mode */
5857 hi2c->Mode = HAL_I2C_MODE_NONE;
5858
5859 /* No Generate Stop, to permit restart mode */
5860 /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
5861 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5862 {
5863 hi2c->State = HAL_I2C_STATE_READY;
5864 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
5865 hi2c->XferISR = NULL;
5866
5867 /* Disable Interrupts */
5868 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5869
5870 /* Process Unlocked */
5871 __HAL_UNLOCK(hi2c);
5872
5873 /* Call the corresponding callback to inform upper layer of End of Transfer */
5874 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5875 hi2c->MasterTxCpltCallback(hi2c);
5876 #else
5877 HAL_I2C_MasterTxCpltCallback(hi2c);
5878 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5879 }
5880 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
5881 else
5882 {
5883 hi2c->State = HAL_I2C_STATE_READY;
5884 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
5885 hi2c->XferISR = NULL;
5886
5887 /* Disable Interrupts */
5888 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
5889
5890 /* Process Unlocked */
5891 __HAL_UNLOCK(hi2c);
5892
5893 /* Call the corresponding callback to inform upper layer of End of Transfer */
5894 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5895 hi2c->MasterRxCpltCallback(hi2c);
5896 #else
5897 HAL_I2C_MasterRxCpltCallback(hi2c);
5898 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5899 }
5900 }
5901
5902 /**
5903 * @brief I2C Slave sequential complete process.
5904 * @param hi2c I2C handle.
5905 * @retval None
5906 */
I2C_ITSlaveSeqCplt(I2C_HandleTypeDef * hi2c)5907 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
5908 {
5909 uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
5910
5911 /* Reset I2C handle mode */
5912 hi2c->Mode = HAL_I2C_MODE_NONE;
5913
5914 /* If a DMA is ongoing, Update handle size context */
5915 if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
5916 {
5917 /* Disable DMA Request */
5918 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
5919 }
5920 else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
5921 {
5922 /* Disable DMA Request */
5923 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
5924 }
5925 else
5926 {
5927 /* Do nothing */
5928 }
5929
5930 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
5931 {
5932 /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
5933 hi2c->State = HAL_I2C_STATE_LISTEN;
5934 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
5935
5936 /* Disable Interrupts */
5937 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5938
5939 /* Process Unlocked */
5940 __HAL_UNLOCK(hi2c);
5941
5942 /* Call the corresponding callback to inform upper layer of End of Transfer */
5943 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5944 hi2c->SlaveTxCpltCallback(hi2c);
5945 #else
5946 HAL_I2C_SlaveTxCpltCallback(hi2c);
5947 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5948 }
5949
5950 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
5951 {
5952 /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
5953 hi2c->State = HAL_I2C_STATE_LISTEN;
5954 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
5955
5956 /* Disable Interrupts */
5957 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
5958
5959 /* Process Unlocked */
5960 __HAL_UNLOCK(hi2c);
5961
5962 /* Call the corresponding callback to inform upper layer of End of Transfer */
5963 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5964 hi2c->SlaveRxCpltCallback(hi2c);
5965 #else
5966 HAL_I2C_SlaveRxCpltCallback(hi2c);
5967 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5968 }
5969 else
5970 {
5971 /* Nothing to do */
5972 }
5973 }
5974
5975 /**
5976 * @brief I2C Master complete process.
5977 * @param hi2c I2C handle.
5978 * @param ITFlags Interrupt flags to handle.
5979 * @retval None
5980 */
I2C_ITMasterCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)5981 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
5982 {
5983 uint32_t tmperror;
5984 uint32_t tmpITFlags = ITFlags;
5985 __IO uint32_t tmpreg;
5986
5987 /* Clear STOP Flag */
5988 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
5989
5990 /* Disable Interrupts and Store Previous state */
5991 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5992 {
5993 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5994 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
5995 }
5996 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5997 {
5998 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
5999 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
6000 }
6001 else
6002 {
6003 /* Do nothing */
6004 }
6005
6006 /* Clear Configuration Register 2 */
6007 I2C_RESET_CR2(hi2c);
6008
6009 /* Reset handle parameters */
6010 hi2c->XferISR = NULL;
6011 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6012
6013 if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
6014 {
6015 /* Clear NACK Flag */
6016 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6017
6018 /* Set acknowledge error code */
6019 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6020 }
6021
6022 /* Fetch Last receive data if any */
6023 if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
6024 {
6025 /* Read data from RXDR */
6026 tmpreg = (uint8_t)hi2c->Instance->RXDR;
6027 UNUSED(tmpreg);
6028 }
6029
6030 /* Flush TX register */
6031 I2C_Flush_TXDR(hi2c);
6032
6033 /* Store current volatile hi2c->ErrorCode, misra rule */
6034 tmperror = hi2c->ErrorCode;
6035
6036 /* Call the corresponding callback to inform upper layer of End of Transfer */
6037 if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
6038 {
6039 /* Call the corresponding callback to inform upper layer of End of Transfer */
6040 I2C_ITError(hi2c, hi2c->ErrorCode);
6041 }
6042 /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
6043 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
6044 {
6045 hi2c->State = HAL_I2C_STATE_READY;
6046 hi2c->PreviousState = I2C_STATE_NONE;
6047
6048 if (hi2c->Mode == HAL_I2C_MODE_MEM)
6049 {
6050 hi2c->Mode = HAL_I2C_MODE_NONE;
6051
6052 /* Process Unlocked */
6053 __HAL_UNLOCK(hi2c);
6054
6055 /* Call the corresponding callback to inform upper layer of End of Transfer */
6056 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6057 hi2c->MemTxCpltCallback(hi2c);
6058 #else
6059 HAL_I2C_MemTxCpltCallback(hi2c);
6060 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6061 }
6062 else
6063 {
6064 hi2c->Mode = HAL_I2C_MODE_NONE;
6065
6066 /* Process Unlocked */
6067 __HAL_UNLOCK(hi2c);
6068
6069 /* Call the corresponding callback to inform upper layer of End of Transfer */
6070 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6071 hi2c->MasterTxCpltCallback(hi2c);
6072 #else
6073 HAL_I2C_MasterTxCpltCallback(hi2c);
6074 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6075 }
6076 }
6077 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
6078 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6079 {
6080 hi2c->State = HAL_I2C_STATE_READY;
6081 hi2c->PreviousState = I2C_STATE_NONE;
6082
6083 if (hi2c->Mode == HAL_I2C_MODE_MEM)
6084 {
6085 hi2c->Mode = HAL_I2C_MODE_NONE;
6086
6087 /* Process Unlocked */
6088 __HAL_UNLOCK(hi2c);
6089
6090 /* Call the corresponding callback to inform upper layer of End of Transfer */
6091 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6092 hi2c->MemRxCpltCallback(hi2c);
6093 #else
6094 HAL_I2C_MemRxCpltCallback(hi2c);
6095 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6096 }
6097 else
6098 {
6099 hi2c->Mode = HAL_I2C_MODE_NONE;
6100
6101 /* Process Unlocked */
6102 __HAL_UNLOCK(hi2c);
6103
6104 /* Call the corresponding callback to inform upper layer of End of Transfer */
6105 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6106 hi2c->MasterRxCpltCallback(hi2c);
6107 #else
6108 HAL_I2C_MasterRxCpltCallback(hi2c);
6109 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6110 }
6111 }
6112 else
6113 {
6114 /* Nothing to do */
6115 }
6116 }
6117
6118 /**
6119 * @brief I2C Slave complete process.
6120 * @param hi2c I2C handle.
6121 * @param ITFlags Interrupt flags to handle.
6122 * @retval None
6123 */
I2C_ITSlaveCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6124 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6125 {
6126 uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
6127 uint32_t tmpITFlags = ITFlags;
6128 HAL_I2C_StateTypeDef tmpstate = hi2c->State;
6129
6130 /* Clear STOP Flag */
6131 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6132
6133 /* Disable Interrupts and Store Previous state */
6134 if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
6135 {
6136 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
6137 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6138 }
6139 else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6140 {
6141 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
6142 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6143 }
6144 else
6145 {
6146 /* Do nothing */
6147 }
6148
6149 /* Disable Address Acknowledge */
6150 hi2c->Instance->CR2 |= I2C_CR2_NACK;
6151
6152 /* Clear Configuration Register 2 */
6153 I2C_RESET_CR2(hi2c);
6154
6155 /* Flush TX register */
6156 I2C_Flush_TXDR(hi2c);
6157
6158 /* If a DMA is ongoing, Update handle size context */
6159 if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
6160 {
6161 /* Disable DMA Request */
6162 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6163
6164 if (hi2c->hdmatx != NULL)
6165 {
6166 hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
6167 }
6168 }
6169 else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
6170 {
6171 /* Disable DMA Request */
6172 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6173
6174 if (hi2c->hdmarx != NULL)
6175 {
6176 hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
6177 }
6178 }
6179 else
6180 {
6181 /* Do nothing */
6182 }
6183
6184 /* Store Last receive data if any */
6185 if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
6186 {
6187 /* Remove RXNE flag on temporary variable as read done */
6188 tmpITFlags &= ~I2C_FLAG_RXNE;
6189
6190 /* Read data from RXDR */
6191 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
6192
6193 /* Increment Buffer pointer */
6194 hi2c->pBuffPtr++;
6195
6196 if ((hi2c->XferSize > 0U))
6197 {
6198 hi2c->XferSize--;
6199 hi2c->XferCount--;
6200 }
6201 }
6202
6203 /* All data are not transferred, so set error code accordingly */
6204 if (hi2c->XferCount != 0U)
6205 {
6206 /* Set ErrorCode corresponding to a Non-Acknowledge */
6207 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6208 }
6209
6210 hi2c->Mode = HAL_I2C_MODE_NONE;
6211 hi2c->XferISR = NULL;
6212
6213 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
6214 {
6215 /* Call the corresponding callback to inform upper layer of End of Transfer */
6216 I2C_ITError(hi2c, hi2c->ErrorCode);
6217
6218 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6219 if (hi2c->State == HAL_I2C_STATE_LISTEN)
6220 {
6221 /* Call I2C Listen complete process */
6222 I2C_ITListenCplt(hi2c, tmpITFlags);
6223 }
6224 }
6225 else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
6226 {
6227 /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
6228 I2C_ITSlaveSeqCplt(hi2c);
6229
6230 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6231 hi2c->State = HAL_I2C_STATE_READY;
6232 hi2c->PreviousState = I2C_STATE_NONE;
6233
6234 /* Process Unlocked */
6235 __HAL_UNLOCK(hi2c);
6236
6237 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6238 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6239 hi2c->ListenCpltCallback(hi2c);
6240 #else
6241 HAL_I2C_ListenCpltCallback(hi2c);
6242 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6243 }
6244 /* Call the corresponding callback to inform upper layer of End of Transfer */
6245 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6246 {
6247 hi2c->State = HAL_I2C_STATE_READY;
6248 hi2c->PreviousState = I2C_STATE_NONE;
6249
6250 /* Process Unlocked */
6251 __HAL_UNLOCK(hi2c);
6252
6253 /* Call the corresponding callback to inform upper layer of End of Transfer */
6254 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6255 hi2c->SlaveRxCpltCallback(hi2c);
6256 #else
6257 HAL_I2C_SlaveRxCpltCallback(hi2c);
6258 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6259 }
6260 else
6261 {
6262 hi2c->State = HAL_I2C_STATE_READY;
6263 hi2c->PreviousState = I2C_STATE_NONE;
6264
6265 /* Process Unlocked */
6266 __HAL_UNLOCK(hi2c);
6267
6268 /* Call the corresponding callback to inform upper layer of End of Transfer */
6269 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6270 hi2c->SlaveTxCpltCallback(hi2c);
6271 #else
6272 HAL_I2C_SlaveTxCpltCallback(hi2c);
6273 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6274 }
6275 }
6276
6277 /**
6278 * @brief I2C Listen complete process.
6279 * @param hi2c I2C handle.
6280 * @param ITFlags Interrupt flags to handle.
6281 * @retval None
6282 */
I2C_ITListenCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6283 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6284 {
6285 /* Reset handle parameters */
6286 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6287 hi2c->PreviousState = I2C_STATE_NONE;
6288 hi2c->State = HAL_I2C_STATE_READY;
6289 hi2c->Mode = HAL_I2C_MODE_NONE;
6290 hi2c->XferISR = NULL;
6291
6292 /* Store Last receive data if any */
6293 if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
6294 {
6295 /* Read data from RXDR */
6296 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
6297
6298 /* Increment Buffer pointer */
6299 hi2c->pBuffPtr++;
6300
6301 if ((hi2c->XferSize > 0U))
6302 {
6303 hi2c->XferSize--;
6304 hi2c->XferCount--;
6305
6306 /* Set ErrorCode corresponding to a Non-Acknowledge */
6307 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6308 }
6309 }
6310
6311 /* Disable all Interrupts*/
6312 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6313
6314 /* Clear NACK Flag */
6315 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6316
6317 /* Process Unlocked */
6318 __HAL_UNLOCK(hi2c);
6319
6320 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6321 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6322 hi2c->ListenCpltCallback(hi2c);
6323 #else
6324 HAL_I2C_ListenCpltCallback(hi2c);
6325 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6326 }
6327
6328 /**
6329 * @brief I2C interrupts error process.
6330 * @param hi2c I2C handle.
6331 * @param ErrorCode Error code to handle.
6332 * @retval None
6333 */
I2C_ITError(I2C_HandleTypeDef * hi2c,uint32_t ErrorCode)6334 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
6335 {
6336 HAL_I2C_StateTypeDef tmpstate = hi2c->State;
6337
6338 uint32_t tmppreviousstate;
6339
6340 /* Reset handle parameters */
6341 hi2c->Mode = HAL_I2C_MODE_NONE;
6342 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6343 hi2c->XferCount = 0U;
6344
6345 /* Set new error code */
6346 hi2c->ErrorCode |= ErrorCode;
6347
6348 /* Disable Interrupts */
6349 if ((tmpstate == HAL_I2C_STATE_LISTEN) ||
6350 (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
6351 (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6352 {
6353 /* Disable all interrupts, except interrupts related to LISTEN state */
6354 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6355
6356 /* keep HAL_I2C_STATE_LISTEN if set */
6357 hi2c->State = HAL_I2C_STATE_LISTEN;
6358 hi2c->XferISR = I2C_Slave_ISR_IT;
6359 }
6360 else
6361 {
6362 /* Disable all interrupts */
6363 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6364
6365 /* Flush TX register */
6366 I2C_Flush_TXDR(hi2c);
6367
6368 /* If state is an abort treatment on going, don't change state */
6369 /* This change will be do later */
6370 if (hi2c->State != HAL_I2C_STATE_ABORT)
6371 {
6372 /* Set HAL_I2C_STATE_READY */
6373 hi2c->State = HAL_I2C_STATE_READY;
6374
6375 /* Check if a STOPF is detected */
6376 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
6377 {
6378 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
6379 {
6380 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6381 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6382 }
6383
6384 /* Clear STOP Flag */
6385 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6386 }
6387
6388 }
6389 hi2c->XferISR = NULL;
6390 }
6391
6392 /* Abort DMA TX transfer if any */
6393 tmppreviousstate = hi2c->PreviousState;
6394
6395 if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
6396 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
6397 {
6398 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
6399 {
6400 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6401 }
6402
6403 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
6404 {
6405 /* Set the I2C DMA Abort callback :
6406 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6407 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6408
6409 /* Process Unlocked */
6410 __HAL_UNLOCK(hi2c);
6411
6412 /* Abort DMA TX */
6413 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6414 {
6415 /* Call Directly XferAbortCallback function in case of error */
6416 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6417 }
6418 }
6419 else
6420 {
6421 I2C_TreatErrorCallback(hi2c);
6422 }
6423 }
6424 /* Abort DMA RX transfer if any */
6425 else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
6426 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
6427 {
6428 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
6429 {
6430 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6431 }
6432
6433 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
6434 {
6435 /* Set the I2C DMA Abort callback :
6436 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6437 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6438
6439 /* Process Unlocked */
6440 __HAL_UNLOCK(hi2c);
6441
6442 /* Abort DMA RX */
6443 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6444 {
6445 /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
6446 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6447 }
6448 }
6449 else
6450 {
6451 I2C_TreatErrorCallback(hi2c);
6452 }
6453 }
6454 else
6455 {
6456 I2C_TreatErrorCallback(hi2c);
6457 }
6458 }
6459
6460 /**
6461 * @brief I2C Error callback treatment.
6462 * @param hi2c I2C handle.
6463 * @retval None
6464 */
I2C_TreatErrorCallback(I2C_HandleTypeDef * hi2c)6465 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
6466 {
6467 if (hi2c->State == HAL_I2C_STATE_ABORT)
6468 {
6469 hi2c->State = HAL_I2C_STATE_READY;
6470 hi2c->PreviousState = I2C_STATE_NONE;
6471
6472 /* Process Unlocked */
6473 __HAL_UNLOCK(hi2c);
6474
6475 /* Call the corresponding callback to inform upper layer of End of Transfer */
6476 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6477 hi2c->AbortCpltCallback(hi2c);
6478 #else
6479 HAL_I2C_AbortCpltCallback(hi2c);
6480 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6481 }
6482 else
6483 {
6484 hi2c->PreviousState = I2C_STATE_NONE;
6485
6486 /* Process Unlocked */
6487 __HAL_UNLOCK(hi2c);
6488
6489 /* Call the corresponding callback to inform upper layer of End of Transfer */
6490 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6491 hi2c->ErrorCallback(hi2c);
6492 #else
6493 HAL_I2C_ErrorCallback(hi2c);
6494 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6495 }
6496 }
6497
6498 /**
6499 * @brief I2C Tx data register flush process.
6500 * @param hi2c I2C handle.
6501 * @retval None
6502 */
I2C_Flush_TXDR(I2C_HandleTypeDef * hi2c)6503 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
6504 {
6505 /* If a pending TXIS flag is set */
6506 /* Write a dummy data in TXDR to clear it */
6507 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
6508 {
6509 hi2c->Instance->TXDR = 0x00U;
6510 }
6511
6512 /* Flush TX register if not empty */
6513 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
6514 {
6515 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
6516 }
6517 }
6518
6519 /**
6520 * @brief DMA I2C master transmit process complete callback.
6521 * @param hdma DMA handle
6522 * @retval None
6523 */
I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef * hdma)6524 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
6525 {
6526 /* Derogation MISRAC2012-Rule-11.5 */
6527 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6528
6529 /* Disable DMA Request */
6530 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6531
6532 /* If last transfer, enable STOP interrupt */
6533 if (hi2c->XferCount == 0U)
6534 {
6535 /* Enable STOP interrupt */
6536 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
6537 }
6538 /* else prepare a new DMA transfer and enable TCReload interrupt */
6539 else
6540 {
6541 /* Update Buffer pointer */
6542 hi2c->pBuffPtr += hi2c->XferSize;
6543
6544 /* Set the XferSize to transfer */
6545 if (hi2c->XferCount > MAX_NBYTE_SIZE)
6546 {
6547 hi2c->XferSize = MAX_NBYTE_SIZE;
6548 }
6549 else
6550 {
6551 hi2c->XferSize = hi2c->XferCount;
6552 }
6553
6554 /* Enable the DMA channel */
6555 if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
6556 hi2c->XferSize) != HAL_OK)
6557 {
6558 /* Call the corresponding callback to inform upper layer of End of Transfer */
6559 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6560 }
6561 else
6562 {
6563 /* Enable TC interrupts */
6564 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
6565 }
6566 }
6567 }
6568
6569
6570 /**
6571 * @brief DMA I2C slave transmit process complete callback.
6572 * @param hdma DMA handle
6573 * @retval None
6574 */
I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef * hdma)6575 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
6576 {
6577 /* Derogation MISRAC2012-Rule-11.5 */
6578 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6579 uint32_t tmpoptions = hi2c->XferOptions;
6580
6581 if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
6582 {
6583 /* Disable DMA Request */
6584 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6585
6586 /* Last Byte is Transmitted */
6587 /* Call I2C Slave Sequential complete process */
6588 I2C_ITSlaveSeqCplt(hi2c);
6589 }
6590 else
6591 {
6592 /* No specific action, Master fully manage the generation of STOP condition */
6593 /* Mean that this generation can arrive at any time, at the end or during DMA process */
6594 /* So STOP condition should be manage through Interrupt treatment */
6595 }
6596 }
6597
6598
6599 /**
6600 * @brief DMA I2C master receive process complete callback.
6601 * @param hdma DMA handle
6602 * @retval None
6603 */
I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef * hdma)6604 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
6605 {
6606 /* Derogation MISRAC2012-Rule-11.5 */
6607 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6608
6609 /* Disable DMA Request */
6610 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6611
6612 /* If last transfer, enable STOP interrupt */
6613 if (hi2c->XferCount == 0U)
6614 {
6615 /* Enable STOP interrupt */
6616 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
6617 }
6618 /* else prepare a new DMA transfer and enable TCReload interrupt */
6619 else
6620 {
6621 /* Update Buffer pointer */
6622 hi2c->pBuffPtr += hi2c->XferSize;
6623
6624 /* Set the XferSize to transfer */
6625 if (hi2c->XferCount > MAX_NBYTE_SIZE)
6626 {
6627 hi2c->XferSize = MAX_NBYTE_SIZE;
6628 }
6629 else
6630 {
6631 hi2c->XferSize = hi2c->XferCount;
6632 }
6633
6634 /* Enable the DMA channel */
6635 if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
6636 hi2c->XferSize) != HAL_OK)
6637 {
6638 /* Call the corresponding callback to inform upper layer of End of Transfer */
6639 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6640 }
6641 else
6642 {
6643 /* Enable TC interrupts */
6644 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
6645 }
6646 }
6647 }
6648
6649
6650 /**
6651 * @brief DMA I2C slave receive process complete callback.
6652 * @param hdma DMA handle
6653 * @retval None
6654 */
I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef * hdma)6655 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
6656 {
6657 /* Derogation MISRAC2012-Rule-11.5 */
6658 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6659 uint32_t tmpoptions = hi2c->XferOptions;
6660
6661 if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
6662 (tmpoptions != I2C_NO_OPTION_FRAME))
6663 {
6664 /* Disable DMA Request */
6665 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6666
6667 /* Call I2C Slave Sequential complete process */
6668 I2C_ITSlaveSeqCplt(hi2c);
6669 }
6670 else
6671 {
6672 /* No specific action, Master fully manage the generation of STOP condition */
6673 /* Mean that this generation can arrive at any time, at the end or during DMA process */
6674 /* So STOP condition should be manage through Interrupt treatment */
6675 }
6676 }
6677
6678
6679 /**
6680 * @brief DMA I2C communication error callback.
6681 * @param hdma DMA handle
6682 * @retval None
6683 */
I2C_DMAError(DMA_HandleTypeDef * hdma)6684 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
6685 {
6686 /* Derogation MISRAC2012-Rule-11.5 */
6687 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6688
6689 /* Disable Acknowledge */
6690 hi2c->Instance->CR2 |= I2C_CR2_NACK;
6691
6692 /* Call the corresponding callback to inform upper layer of End of Transfer */
6693 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6694 }
6695
6696
6697 /**
6698 * @brief DMA I2C communication abort callback
6699 * (To be called at end of DMA Abort procedure).
6700 * @param hdma DMA handle.
6701 * @retval None
6702 */
I2C_DMAAbort(DMA_HandleTypeDef * hdma)6703 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
6704 {
6705 /* Derogation MISRAC2012-Rule-11.5 */
6706 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6707
6708 /* Reset AbortCpltCallback */
6709 if (hi2c->hdmatx != NULL)
6710 {
6711 hi2c->hdmatx->XferAbortCallback = NULL;
6712 }
6713 if (hi2c->hdmarx != NULL)
6714 {
6715 hi2c->hdmarx->XferAbortCallback = NULL;
6716 }
6717
6718 I2C_TreatErrorCallback(hi2c);
6719 }
6720
6721
6722 /**
6723 * @brief This function handles I2C Communication Timeout. It waits
6724 * until a flag is no longer in the specified status.
6725 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6726 * the configuration information for the specified I2C.
6727 * @param Flag Specifies the I2C flag to check.
6728 * @param Status The actual Flag status (SET or RESET).
6729 * @param Timeout Timeout duration
6730 * @param Tickstart Tick start value
6731 * @retval HAL status
6732 */
I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Flag,FlagStatus Status,uint32_t Timeout,uint32_t Tickstart)6733 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
6734 uint32_t Timeout, uint32_t Tickstart)
6735 {
6736 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
6737 {
6738 /* Check for the Timeout */
6739 if (Timeout != HAL_MAX_DELAY)
6740 {
6741 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6742 {
6743 if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
6744 {
6745 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6746 hi2c->State = HAL_I2C_STATE_READY;
6747 hi2c->Mode = HAL_I2C_MODE_NONE;
6748
6749 /* Process Unlocked */
6750 __HAL_UNLOCK(hi2c);
6751 return HAL_ERROR;
6752 }
6753 }
6754 }
6755 }
6756 return HAL_OK;
6757 }
6758
6759 /**
6760 * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
6761 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6762 * the configuration information for the specified I2C.
6763 * @param Timeout Timeout duration
6764 * @param Tickstart Tick start value
6765 * @retval HAL status
6766 */
I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)6767 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
6768 uint32_t Tickstart)
6769 {
6770 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
6771 {
6772 /* Check if an error is detected */
6773 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
6774 {
6775 return HAL_ERROR;
6776 }
6777
6778 /* Check for the Timeout */
6779 if (Timeout != HAL_MAX_DELAY)
6780 {
6781 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6782 {
6783 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET))
6784 {
6785 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6786 hi2c->State = HAL_I2C_STATE_READY;
6787 hi2c->Mode = HAL_I2C_MODE_NONE;
6788
6789 /* Process Unlocked */
6790 __HAL_UNLOCK(hi2c);
6791
6792 return HAL_ERROR;
6793 }
6794 }
6795 }
6796 }
6797 return HAL_OK;
6798 }
6799
6800 /**
6801 * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
6802 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6803 * the configuration information for the specified I2C.
6804 * @param Timeout Timeout duration
6805 * @param Tickstart Tick start value
6806 * @retval HAL status
6807 */
I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)6808 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
6809 uint32_t Tickstart)
6810 {
6811 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
6812 {
6813 /* Check if an error is detected */
6814 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
6815 {
6816 return HAL_ERROR;
6817 }
6818
6819 /* Check for the Timeout */
6820 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6821 {
6822 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
6823 {
6824 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6825 hi2c->State = HAL_I2C_STATE_READY;
6826 hi2c->Mode = HAL_I2C_MODE_NONE;
6827
6828 /* Process Unlocked */
6829 __HAL_UNLOCK(hi2c);
6830
6831 return HAL_ERROR;
6832 }
6833 }
6834 }
6835 return HAL_OK;
6836 }
6837
6838 /**
6839 * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
6840 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6841 * the configuration information for the specified I2C.
6842 * @param Timeout Timeout duration
6843 * @param Tickstart Tick start value
6844 * @retval HAL status
6845 */
I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)6846 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
6847 uint32_t Tickstart)
6848 {
6849 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
6850 {
6851 /* Check if an error is detected */
6852 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
6853 {
6854 return HAL_ERROR;
6855 }
6856
6857 /* Check if a STOPF is detected */
6858 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
6859 {
6860 /* Check if an RXNE is pending */
6861 /* Store Last receive data if any */
6862 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
6863 {
6864 /* Return HAL_OK */
6865 /* The Reading of data from RXDR will be done in caller function */
6866 return HAL_OK;
6867 }
6868 else
6869 {
6870 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
6871 {
6872 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6873 hi2c->ErrorCode = HAL_I2C_ERROR_AF;
6874 }
6875 else
6876 {
6877 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
6878 }
6879
6880 /* Clear STOP Flag */
6881 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6882
6883 /* Clear Configuration Register 2 */
6884 I2C_RESET_CR2(hi2c);
6885
6886 hi2c->State = HAL_I2C_STATE_READY;
6887 hi2c->Mode = HAL_I2C_MODE_NONE;
6888
6889 /* Process Unlocked */
6890 __HAL_UNLOCK(hi2c);
6891
6892 return HAL_ERROR;
6893 }
6894 }
6895
6896 /* Check for the Timeout */
6897 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6898 {
6899 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
6900 {
6901 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6902 hi2c->State = HAL_I2C_STATE_READY;
6903
6904 /* Process Unlocked */
6905 __HAL_UNLOCK(hi2c);
6906
6907 return HAL_ERROR;
6908 }
6909 }
6910 }
6911 return HAL_OK;
6912 }
6913
6914 /**
6915 * @brief This function handles errors detection during an I2C Communication.
6916 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6917 * the configuration information for the specified I2C.
6918 * @param Timeout Timeout duration
6919 * @param Tickstart Tick start value
6920 * @retval HAL status
6921 */
I2C_IsErrorOccurred(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)6922 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
6923 {
6924 HAL_StatusTypeDef status = HAL_OK;
6925 uint32_t itflag = hi2c->Instance->ISR;
6926 uint32_t error_code = 0;
6927 uint32_t tickstart = Tickstart;
6928 uint32_t tmp1;
6929 HAL_I2C_ModeTypeDef tmp2;
6930
6931 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
6932 {
6933 /* Clear NACKF Flag */
6934 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6935
6936 /* Wait until STOP Flag is set or timeout occurred */
6937 /* AutoEnd should be initiate after AF */
6938 while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
6939 {
6940 /* Check for the Timeout */
6941 if (Timeout != HAL_MAX_DELAY)
6942 {
6943 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
6944 {
6945 tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
6946 tmp2 = hi2c->Mode;
6947
6948 /* In case of I2C still busy, try to regenerate a STOP manually */
6949 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
6950 (tmp1 != I2C_CR2_STOP) && \
6951 (tmp2 != HAL_I2C_MODE_SLAVE))
6952 {
6953 /* Generate Stop */
6954 hi2c->Instance->CR2 |= I2C_CR2_STOP;
6955
6956 /* Update Tick with new reference */
6957 tickstart = HAL_GetTick();
6958 }
6959
6960 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
6961 {
6962 /* Check for the Timeout */
6963 if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
6964 {
6965 error_code |= HAL_I2C_ERROR_TIMEOUT;
6966
6967 status = HAL_ERROR;
6968
6969 break;
6970 }
6971 }
6972 }
6973 }
6974 }
6975
6976 /* In case STOP Flag is detected, clear it */
6977 if (status == HAL_OK)
6978 {
6979 /* Clear STOP Flag */
6980 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6981 }
6982
6983 error_code |= HAL_I2C_ERROR_AF;
6984
6985 status = HAL_ERROR;
6986 }
6987
6988 /* Refresh Content of Status register */
6989 itflag = hi2c->Instance->ISR;
6990
6991 /* Then verify if an additional errors occurs */
6992 /* Check if a Bus error occurred */
6993 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
6994 {
6995 error_code |= HAL_I2C_ERROR_BERR;
6996
6997 /* Clear BERR flag */
6998 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
6999
7000 status = HAL_ERROR;
7001 }
7002
7003 /* Check if an Over-Run/Under-Run error occurred */
7004 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
7005 {
7006 error_code |= HAL_I2C_ERROR_OVR;
7007
7008 /* Clear OVR flag */
7009 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
7010
7011 status = HAL_ERROR;
7012 }
7013
7014 /* Check if an Arbitration Loss error occurred */
7015 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
7016 {
7017 error_code |= HAL_I2C_ERROR_ARLO;
7018
7019 /* Clear ARLO flag */
7020 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
7021
7022 status = HAL_ERROR;
7023 }
7024
7025 if (status != HAL_OK)
7026 {
7027 /* Flush TX register */
7028 I2C_Flush_TXDR(hi2c);
7029
7030 /* Clear Configuration Register 2 */
7031 I2C_RESET_CR2(hi2c);
7032
7033 hi2c->ErrorCode |= error_code;
7034 hi2c->State = HAL_I2C_STATE_READY;
7035 hi2c->Mode = HAL_I2C_MODE_NONE;
7036
7037 /* Process Unlocked */
7038 __HAL_UNLOCK(hi2c);
7039 }
7040
7041 return status;
7042 }
7043
7044 /**
7045 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
7046 * @param hi2c I2C handle.
7047 * @param DevAddress Specifies the slave address to be programmed.
7048 * @param Size Specifies the number of bytes to be programmed.
7049 * This parameter must be a value between 0 and 255.
7050 * @param Mode New state of the I2C START condition generation.
7051 * This parameter can be one of the following values:
7052 * @arg @ref I2C_RELOAD_MODE Enable Reload mode .
7053 * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
7054 * @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
7055 * @param Request New state of the I2C START condition generation.
7056 * This parameter can be one of the following values:
7057 * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
7058 * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
7059 * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
7060 * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
7061 * @retval None
7062 */
I2C_TransferConfig(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t Size,uint32_t Mode,uint32_t Request)7063 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
7064 uint32_t Request)
7065 {
7066 /* Check the parameters */
7067 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
7068 assert_param(IS_TRANSFER_MODE(Mode));
7069 assert_param(IS_TRANSFER_REQUEST(Request));
7070
7071 /* Declaration of tmp to prevent undefined behavior of volatile usage */
7072 uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
7073 (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
7074 (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
7075
7076 /* update CR2 register */
7077 MODIFY_REG(hi2c->Instance->CR2, \
7078 ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
7079 (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
7080 I2C_CR2_START | I2C_CR2_STOP)), tmp);
7081 }
7082
7083 /**
7084 * @brief Manage the enabling of Interrupts.
7085 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7086 * the configuration information for the specified I2C.
7087 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
7088 * @retval None
7089 */
I2C_Enable_IRQ(I2C_HandleTypeDef * hi2c,uint16_t InterruptRequest)7090 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
7091 {
7092 uint32_t tmpisr = 0U;
7093
7094 if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \
7095 (hi2c->XferISR != I2C_Slave_ISR_DMA) && \
7096 (hi2c->XferISR != I2C_Mem_ISR_DMA))
7097 {
7098 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7099 {
7100 /* Enable ERR, STOP, NACK and ADDR interrupts */
7101 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7102 }
7103
7104 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7105 {
7106 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
7107 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
7108 }
7109
7110 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7111 {
7112 /* Enable ERR, TC, STOP, NACK and TXI interrupts */
7113 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
7114 }
7115
7116 if (InterruptRequest == I2C_XFER_ERROR_IT)
7117 {
7118 /* Enable ERR and NACK interrupts */
7119 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7120 }
7121
7122 if (InterruptRequest == I2C_XFER_CPLT_IT)
7123 {
7124 /* Enable STOP interrupts */
7125 tmpisr |= I2C_IT_STOPI;
7126 }
7127 }
7128
7129 else
7130 {
7131 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7132 {
7133 /* Enable ERR, STOP, NACK and ADDR interrupts */
7134 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7135 }
7136
7137 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7138 {
7139 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
7140 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
7141 }
7142
7143 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7144 {
7145 /* Enable ERR, TC, STOP, NACK and TXI interrupts */
7146 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
7147 }
7148
7149 if (InterruptRequest == I2C_XFER_ERROR_IT)
7150 {
7151 /* Enable ERR and NACK interrupts */
7152 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7153 }
7154
7155 if (InterruptRequest == I2C_XFER_CPLT_IT)
7156 {
7157 /* Enable STOP interrupts */
7158 tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
7159 }
7160
7161 if ((hi2c->XferISR != I2C_Mem_ISR_DMA) && (InterruptRequest == I2C_XFER_RELOAD_IT))
7162 {
7163 /* Enable TC interrupts */
7164 tmpisr |= I2C_IT_TCI;
7165 }
7166 }
7167
7168 /* Enable interrupts only at the end */
7169 /* to avoid the risk of I2C interrupt handle execution before */
7170 /* all interrupts requested done */
7171 __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
7172 }
7173
7174 /**
7175 * @brief Manage the disabling of Interrupts.
7176 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7177 * the configuration information for the specified I2C.
7178 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
7179 * @retval None
7180 */
I2C_Disable_IRQ(I2C_HandleTypeDef * hi2c,uint16_t InterruptRequest)7181 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
7182 {
7183 uint32_t tmpisr = 0U;
7184
7185 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7186 {
7187 /* Disable TC and TXI interrupts */
7188 tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
7189
7190 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
7191 {
7192 /* Disable NACK and STOP interrupts */
7193 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7194 }
7195 }
7196
7197 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7198 {
7199 /* Disable TC and RXI interrupts */
7200 tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
7201
7202 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
7203 {
7204 /* Disable NACK and STOP interrupts */
7205 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7206 }
7207 }
7208
7209 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7210 {
7211 /* Disable ADDR, NACK and STOP interrupts */
7212 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7213 }
7214
7215 if (InterruptRequest == I2C_XFER_ERROR_IT)
7216 {
7217 /* Enable ERR and NACK interrupts */
7218 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7219 }
7220
7221 if (InterruptRequest == I2C_XFER_CPLT_IT)
7222 {
7223 /* Enable STOP interrupts */
7224 tmpisr |= I2C_IT_STOPI;
7225 }
7226
7227 if (InterruptRequest == I2C_XFER_RELOAD_IT)
7228 {
7229 /* Enable TC interrupts */
7230 tmpisr |= I2C_IT_TCI;
7231 }
7232
7233 /* Disable interrupts only at the end */
7234 /* to avoid a breaking situation like at "t" time */
7235 /* all disable interrupts request are not done */
7236 __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
7237 }
7238
7239 /**
7240 * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
7241 * @param hi2c I2C handle.
7242 * @retval None
7243 */
I2C_ConvertOtherXferOptions(I2C_HandleTypeDef * hi2c)7244 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
7245 {
7246 /* if user set XferOptions to I2C_OTHER_FRAME */
7247 /* it request implicitly to generate a restart condition */
7248 /* set XferOptions to I2C_FIRST_FRAME */
7249 if (hi2c->XferOptions == I2C_OTHER_FRAME)
7250 {
7251 hi2c->XferOptions = I2C_FIRST_FRAME;
7252 }
7253 /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
7254 /* it request implicitly to generate a restart condition */
7255 /* then generate a stop condition at the end of transfer */
7256 /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
7257 else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
7258 {
7259 hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
7260 }
7261 else
7262 {
7263 /* Nothing to do */
7264 }
7265 }
7266
7267 /**
7268 * @}
7269 */
7270
7271 #endif /* HAL_I2C_MODULE_ENABLED */
7272 /**
7273 * @}
7274 */
7275
7276 /**
7277 * @}
7278 */
7279
