1 /** 2 ****************************************************************************** 3 * @file stm32f0xx_hal_can_legacy.h 4 * @author MCD Application Team 5 * @brief Header file of CAN HAL Legacy module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32F0xx_HAL_CAN_LEGACY_H 21 #define __STM32F0xx_HAL_CAN_LEGACY_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 #if defined(STM32F072xB) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include "stm32f0xx_hal_def.h" 31 32 /** @addtogroup STM32F0xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup CAN 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup CAN_Exported_Types CAN Exported Types 42 * @{ 43 */ 44 /** 45 * @brief HAL State structures definition 46 */ 47 typedef enum 48 { 49 HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ 50 HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ 51 HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */ 52 HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */ 53 HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */ 54 HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */ 55 HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */ 56 HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */ 57 HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */ 58 HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */ 59 HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */ 60 HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */ 61 62 }HAL_CAN_StateTypeDef; 63 64 /** 65 * @brief CAN init structure definition 66 */ 67 typedef struct 68 { 69 uint32_t Prescaler; /*!< Specifies the length of a time quantum. 70 This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */ 71 72 uint32_t Mode; /*!< Specifies the CAN operating mode. 73 This parameter can be a value of @ref CAN_operating_mode */ 74 75 uint32_t SJW; /*!< Specifies the maximum number of time quanta 76 the CAN hardware is allowed to lengthen or 77 shorten a bit to perform resynchronization. 78 This parameter can be a value of @ref CAN_synchronisation_jump_width */ 79 80 uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1. 81 This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ 82 83 uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2. 84 This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ 85 86 uint32_t TTCM; /*!< Enable or disable the time triggered communication mode. 87 This parameter can be set to ENABLE or DISABLE. */ 88 89 uint32_t ABOM; /*!< Enable or disable the automatic bus-off management. 90 This parameter can be set to ENABLE or DISABLE. */ 91 92 uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode. 93 This parameter can be set to ENABLE or DISABLE. */ 94 95 uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode. 96 This parameter can be set to ENABLE or DISABLE. */ 97 98 uint32_t RFLM; /*!< Enable or disable the Receive FIFO Locked mode. 99 This parameter can be set to ENABLE or DISABLE. */ 100 101 uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority. 102 This parameter can be set to ENABLE or DISABLE. */ 103 }CAN_InitTypeDef; 104 105 /** 106 * @brief CAN filter configuration structure definition 107 */ 108 typedef struct 109 { 110 uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit 111 configuration, first one for a 16-bit configuration). 112 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 113 114 uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit 115 configuration, second one for a 16-bit configuration). 116 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 117 118 uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, 119 according to the mode (MSBs for a 32-bit configuration, 120 first one for a 16-bit configuration). 121 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 122 123 uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, 124 according to the mode (LSBs for a 32-bit configuration, 125 second one for a 16-bit configuration). 126 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 127 128 uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter. 129 This parameter can be a value of @ref CAN_filter_FIFO */ 130 131 uint32_t FilterNumber; /*!< Specifies the filter which will be initialized. 132 This parameter must be a number between Min_Data = 0 and Max_Data = 27. */ 133 134 uint32_t FilterMode; /*!< Specifies the filter mode to be initialized. 135 This parameter can be a value of @ref CAN_filter_mode */ 136 137 uint32_t FilterScale; /*!< Specifies the filter scale. 138 This parameter can be a value of @ref CAN_filter_scale */ 139 140 uint32_t FilterActivation; /*!< Enable or disable the filter. 141 This parameter can be set to ENABLE or DISABLE. */ 142 143 uint32_t BankNumber; /*!< Select the start slave bank filter 144 This parameter must be a number between Min_Data = 0 and Max_Data = 28. */ 145 146 }CAN_FilterConfTypeDef; 147 148 /** 149 * @brief CAN Tx message structure definition 150 */ 151 typedef struct 152 { 153 uint32_t StdId; /*!< Specifies the standard identifier. 154 This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ 155 156 uint32_t ExtId; /*!< Specifies the extended identifier. 157 This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ 158 159 uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. 160 This parameter can be a value of @ref CAN_identifier_type */ 161 162 uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. 163 This parameter can be a value of @ref CAN_remote_transmission_request */ 164 165 uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. 166 This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ 167 168 uint8_t Data[8]; /*!< Contains the data to be transmitted. 169 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ 170 171 }CanTxMsgTypeDef; 172 173 /** 174 * @brief CAN Rx message structure definition 175 */ 176 typedef struct 177 { 178 uint32_t StdId; /*!< Specifies the standard identifier. 179 This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ 180 181 uint32_t ExtId; /*!< Specifies the extended identifier. 182 This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ 183 184 uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received. 185 This parameter can be a value of @ref CAN_identifier_type */ 186 187 uint32_t RTR; /*!< Specifies the type of frame for the received message. 188 This parameter can be a value of @ref CAN_remote_transmission_request */ 189 190 uint32_t DLC; /*!< Specifies the length of the frame that will be received. 191 This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ 192 193 uint8_t Data[8]; /*!< Contains the data to be received. 194 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ 195 196 uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. 197 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ 198 199 uint32_t FIFONumber; /*!< Specifies the receive FIFO number. 200 This parameter can be CAN_FIFO0 or CAN_FIFO1 */ 201 202 }CanRxMsgTypeDef; 203 204 /** 205 * @brief CAN handle Structure definition 206 */ 207 typedef struct 208 { 209 CAN_TypeDef *Instance; /*!< Register base address */ 210 211 CAN_InitTypeDef Init; /*!< CAN required parameters */ 212 213 CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */ 214 215 CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */ 216 217 CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */ 218 219 HAL_LockTypeDef Lock; /*!< CAN locking object */ 220 221 __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ 222 223 __IO uint32_t ErrorCode; /*!< CAN Error code 224 This parameter can be a value of @ref CAN_Error_Code */ 225 226 }CAN_HandleTypeDef; 227 /** 228 * @} 229 */ 230 231 /* Exported constants --------------------------------------------------------*/ 232 233 /** @defgroup CAN_Exported_Constants CAN Exported Constants 234 * @{ 235 */ 236 237 /** @defgroup CAN_Error_Code CAN Error Code 238 * @{ 239 */ 240 #define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */ 241 #define HAL_CAN_ERROR_EWG (0x00000001U) /*!< EWG error */ 242 #define HAL_CAN_ERROR_EPV (0x00000002U) /*!< EPV error */ 243 #define HAL_CAN_ERROR_BOF (0x00000004U) /*!< BOF error */ 244 #define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */ 245 #define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */ 246 #define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */ 247 #define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive */ 248 #define HAL_CAN_ERROR_BD (0x00000080U) /*!< LEC dominant */ 249 #define HAL_CAN_ERROR_CRC (0x00000100U) /*!< LEC transfer error */ 250 #define HAL_CAN_ERROR_FOV0 (0x00000200U) /*!< FIFO0 overrun error */ 251 #define HAL_CAN_ERROR_FOV1 (0x00000400U) /*!< FIFO1 overrun error */ 252 #define HAL_CAN_ERROR_TXFAIL (0x00000800U) /*!< Transmit failure */ 253 /** 254 * @} 255 */ 256 257 /** @defgroup CAN_InitStatus CAN InitStatus 258 * @{ 259 */ 260 #define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */ 261 #define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */ 262 /** 263 * @} 264 */ 265 266 /** @defgroup CAN_operating_mode CAN Operating Mode 267 * @{ 268 */ 269 #define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ 270 #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ 271 #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ 272 #define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ 273 /** 274 * @} 275 */ 276 277 278 /** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width 279 * @{ 280 */ 281 #define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */ 282 #define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ 283 #define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ 284 #define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ 285 /** 286 * @} 287 */ 288 289 /** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1 290 * @{ 291 */ 292 #define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */ 293 #define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ 294 #define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ 295 #define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ 296 #define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */ 297 #define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */ 298 #define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */ 299 #define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */ 300 #define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */ 301 #define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */ 302 #define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */ 303 #define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */ 304 #define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */ 305 #define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */ 306 #define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ 307 #define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ 308 /** 309 * @} 310 */ 311 312 /** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2 313 * @{ 314 */ 315 #define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */ 316 #define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ 317 #define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ 318 #define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ 319 #define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */ 320 #define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */ 321 #define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ 322 #define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ 323 /** 324 * @} 325 */ 326 327 /** @defgroup CAN_filter_mode CAN Filter Mode 328 * @{ 329 */ 330 #define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) /*!< Identifier mask mode */ 331 #define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) /*!< Identifier list mode */ 332 /** 333 * @} 334 */ 335 336 /** @defgroup CAN_filter_scale CAN Filter Scale 337 * @{ 338 */ 339 #define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) /*!< Two 16-bit filters */ 340 #define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) /*!< One 32-bit filter */ 341 /** 342 * @} 343 */ 344 345 /** @defgroup CAN_filter_FIFO CAN Filter FIFO 346 * @{ 347 */ 348 #define CAN_FILTER_FIFO0 ((uint8_t)0x00U) /*!< Filter FIFO 0 assignment for filter x */ 349 #define CAN_FILTER_FIFO1 ((uint8_t)0x01U) /*!< Filter FIFO 1 assignment for filter x */ 350 /** 351 * @} 352 */ 353 354 /** @defgroup CAN_identifier_type CAN Identifier Type 355 * @{ 356 */ 357 #define CAN_ID_STD (0x00000000U) /*!< Standard Id */ 358 #define CAN_ID_EXT (0x00000004U) /*!< Extended Id */ 359 /** 360 * @} 361 */ 362 363 /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request 364 * @{ 365 */ 366 #define CAN_RTR_DATA (0x00000000U) /*!< Data frame */ 367 #define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */ 368 /** 369 * @} 370 */ 371 372 /** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number 373 * @{ 374 */ 375 #define CAN_FIFO0 ((uint8_t)0x00U) /*!< CAN FIFO 0 used to receive */ 376 #define CAN_FIFO1 ((uint8_t)0x01U) /*!< CAN FIFO 1 used to receive */ 377 /** 378 * @} 379 */ 380 381 /** @defgroup CAN_flags CAN Flags 382 * @{ 383 */ 384 /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() 385 and CAN_ClearFlag() functions. */ 386 /* If the flag is 0x1XXXXXXX, it means that it can only be used with 387 CAN_GetFlagStatus() function. */ 388 389 /* Transmit Flags */ 390 #define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request MailBox0 flag */ 391 #define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request MailBox1 flag */ 392 #define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request MailBox2 flag */ 393 #define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox0 flag */ 394 #define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox1 flag */ 395 #define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox2 flag */ 396 #define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */ 397 #define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 0 empty flag */ 398 #define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 0 empty flag */ 399 400 /* Receive Flags */ 401 #define CAN_FLAG_FF0 (0x00000203U) /*!< FIFO 0 Full flag */ 402 #define CAN_FLAG_FOV0 (0x00000204U) /*!< FIFO 0 Overrun flag */ 403 404 #define CAN_FLAG_FF1 (0x00000403U) /*!< FIFO 1 Full flag */ 405 #define CAN_FLAG_FOV1 (0x00000404U) /*!< FIFO 1 Overrun flag */ 406 407 /* Operating Mode Flags */ 408 #define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */ 409 #define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */ 410 #define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */ 411 #define CAN_FLAG_WKU (0x00000103U) /*!< Wake up flag */ 412 #define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge flag */ 413 /* @note When SLAK interrupt is disabled (SLKIE=0U), no polling on SLAKI is possible. 414 In this case the SLAK bit can be polled.*/ 415 416 /* Error Flags */ 417 #define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */ 418 #define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */ 419 #define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */ 420 421 /** 422 * @} 423 */ 424 425 426 /** @defgroup CAN_interrupts CAN Interrupts 427 * @{ 428 */ 429 #define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ 430 431 /* Receive Interrupts */ 432 #define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ 433 #define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ 434 #define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ 435 #define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ 436 #define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ 437 #define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ 438 439 /* Operating Mode Interrupts */ 440 #define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ 441 #define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ 442 443 /* Error Interrupts */ 444 #define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ 445 #define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ 446 #define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ 447 #define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ 448 #define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ 449 450 /** 451 * @} 452 */ 453 454 /** @defgroup CAN_Mailboxes CAN Mailboxes 455 * @{ 456 */ 457 /* Mailboxes definition */ 458 #define CAN_TXMAILBOX_0 ((uint8_t)0x00U) 459 #define CAN_TXMAILBOX_1 ((uint8_t)0x01U) 460 #define CAN_TXMAILBOX_2 ((uint8_t)0x02U) 461 /** 462 * @} 463 */ 464 465 /** 466 * @} 467 */ 468 469 /* Exported macros -----------------------------------------------------------*/ 470 /** @defgroup CAN_Exported_Macros CAN Exported Macros 471 * @{ 472 */ 473 474 /** @brief Reset CAN handle state 475 * @param __HANDLE__ CAN handle. 476 * @retval None 477 */ 478 #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) 479 480 /** 481 * @brief Enable the specified CAN interrupts. 482 * @param __HANDLE__ CAN handle. 483 * @param __INTERRUPT__ CAN Interrupt 484 * @retval None 485 */ 486 #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 487 488 /** 489 * @brief Disable the specified CAN interrupts. 490 * @param __HANDLE__ CAN handle. 491 * @param __INTERRUPT__ CAN Interrupt 492 * @retval None 493 */ 494 #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 495 496 /** 497 * @brief Return the number of pending received messages. 498 * @param __HANDLE__ CAN handle. 499 * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. 500 * @retval The number of pending message. 501 */ 502 #define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ 503 ((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&0x03U))) 504 505 /** @brief Check whether the specified CAN flag is set or not. 506 * @param __HANDLE__ specifies the CAN Handle. 507 * @param __FLAG__ specifies the flag to check. 508 * This parameter can be one of the following values: 509 * @arg CAN_TSR_RQCP0: Request MailBox0 Flag 510 * @arg CAN_TSR_RQCP1: Request MailBox1 Flag 511 * @arg CAN_TSR_RQCP2: Request MailBox2 Flag 512 * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag 513 * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag 514 * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag 515 * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag 516 * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag 517 * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag 518 * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag 519 * @arg CAN_FLAG_FF0: FIFO 0 Full Flag 520 * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag 521 * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag 522 * @arg CAN_FLAG_FF1: FIFO 1 Full Flag 523 * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag 524 * @arg CAN_FLAG_WKU: Wake up Flag 525 * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag 526 * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag 527 * @arg CAN_FLAG_EWG: Error Warning Flag 528 * @arg CAN_FLAG_EPV: Error Passive Flag 529 * @arg CAN_FLAG_BOF: Bus-Off Flag 530 * @retval The new state of __FLAG__ (TRUE or FALSE). 531 */ 532 #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ 533 ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ 534 (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ 535 (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ 536 (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ 537 ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK)))) 538 539 /** @brief Clear the specified CAN pending flag. 540 * @param __HANDLE__ specifies the CAN Handle. 541 * @param __FLAG__ specifies the flag to check. 542 * This parameter can be one of the following values: 543 * @arg CAN_TSR_RQCP0: Request MailBox0 Flag 544 * @arg CAN_TSR_RQCP1: Request MailBox1 Flag 545 * @arg CAN_TSR_RQCP2: Request MailBox2 Flag 546 * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag 547 * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag 548 * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag 549 * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag 550 * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag 551 * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag 552 * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag 553 * @arg CAN_FLAG_FF0: FIFO 0 Full Flag 554 * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag 555 * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag 556 * @arg CAN_FLAG_FF1: FIFO 1 Full Flag 557 * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag 558 * @arg CAN_FLAG_WKU: Wake up Flag 559 * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag 560 * @arg CAN_FLAG_EWG: Error Warning Flag 561 * @arg CAN_FLAG_EPV: Error Passive Flag 562 * @arg CAN_FLAG_BOF: Bus-Off Flag 563 * @retval The new state of __FLAG__ (TRUE or FALSE). 564 */ 565 #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 566 ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ 567 (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ 568 (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ 569 (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) 570 571 572 /** @brief Check if the specified CAN interrupt source is enabled or disabled. 573 * @param __HANDLE__ specifies the CAN Handle. 574 * @param __INTERRUPT__ specifies the CAN interrupt source to check. 575 * This parameter can be one of the following values: 576 * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable 577 * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev 578 * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable 579 * @retval The new state of __IT__ (TRUE or FALSE). 580 */ 581 #define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 582 583 /** 584 * @brief Check the transmission status of a CAN Frame. 585 * @param __HANDLE__ CAN handle. 586 * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission. 587 * @retval The new status of transmission (TRUE or FALSE). 588 */ 589 #define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\ 590 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\ 591 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\ 592 ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2))) 593 594 /** 595 * @brief Release the specified receive FIFO. 596 * @param __HANDLE__ CAN handle. 597 * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. 598 * @retval None 599 */ 600 #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ 601 ((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1)) 602 603 /** 604 * @brief Cancel a transmit request. 605 * @param __HANDLE__ specifies the CAN Handle. 606 * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission. 607 * @retval None 608 */ 609 #define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ 610 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\ 611 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\ 612 ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2)) 613 614 /** 615 * @brief Enable or disables the DBG Freeze for CAN. 616 * @param __HANDLE__ specifies the CAN Handle. 617 * @param __NEWSTATE__ new state of the CAN peripheral. 618 * This parameter can be: ENABLE (CAN reception/transmission is frozen 619 * during debug. Reception FIFOs can still be accessed/controlled normally) 620 * or DISABLE (CAN is working during debug). 621 * @retval None 622 */ 623 #define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \ 624 ((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) 625 626 /** 627 * @} 628 */ 629 630 /* Exported functions --------------------------------------------------------*/ 631 /** @addtogroup CAN_Exported_Functions CAN Exported Functions 632 * @{ 633 */ 634 635 /** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions 636 * @brief Initialization and Configuration functions 637 * @{ 638 */ 639 640 /* Initialization and de-initialization functions *****************************/ 641 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan); 642 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig); 643 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan); 644 void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan); 645 void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); 646 /** 647 * @} 648 */ 649 650 /** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions 651 * @brief I/O operation functions 652 * @{ 653 */ 654 /* IO operation functions *****************************************************/ 655 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout); 656 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan); 657 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout); 658 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber); 659 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); 660 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); 661 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan); 662 void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan); 663 void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); 664 void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); 665 /** 666 * @} 667 */ 668 669 /** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions 670 * @brief CAN Peripheral State functions 671 * @{ 672 */ 673 /* Peripheral State and Error functions ***************************************/ 674 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); 675 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); 676 /** 677 * @} 678 */ 679 680 /** 681 * @} 682 */ 683 684 /* Private types -------------------------------------------------------------*/ 685 /** @defgroup CAN_Private_Types CAN Private Types 686 * @{ 687 */ 688 689 /** 690 * @} 691 */ 692 693 /* Private variables ---------------------------------------------------------*/ 694 /** @defgroup CAN_Private_Variables CAN Private Variables 695 * @{ 696 */ 697 698 /** 699 * @} 700 */ 701 702 /* Private constants ---------------------------------------------------------*/ 703 /** @defgroup CAN_Private_Constants CAN Private Constants 704 * @{ 705 */ 706 #define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04U) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ 707 #define CAN_FLAG_MASK (0x000000FFU) 708 /** 709 * @} 710 */ 711 712 /* Private Macros -----------------------------------------------------------*/ 713 /** @defgroup CAN_Private_Macros CAN Private Macros 714 * @{ 715 */ 716 717 #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ 718 ((MODE) == CAN_MODE_LOOPBACK)|| \ 719 ((MODE) == CAN_MODE_SILENT) || \ 720 ((MODE) == CAN_MODE_SILENT_LOOPBACK)) 721 722 #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ 723 ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) 724 725 #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) 726 727 #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) 728 729 #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) 730 731 #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U) 732 733 #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ 734 ((MODE) == CAN_FILTERMODE_IDLIST)) 735 736 #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ 737 ((SCALE) == CAN_FILTERSCALE_32BIT)) 738 739 #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ 740 ((FIFO) == CAN_FILTER_FIFO1)) 741 742 #define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U) 743 744 #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U)) 745 #define IS_CAN_STDID(STDID) ((STDID) <= (0x7FFU)) 746 #define IS_CAN_EXTID(EXTID) ((EXTID) <= (0x1FFFFFFFU)) 747 #define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08U)) 748 749 #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ 750 ((IDTYPE) == CAN_ID_EXT)) 751 752 #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) 753 754 #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) 755 756 #define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ 757 ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ 758 ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ 759 ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ 760 ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ 761 ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ 762 ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) 763 764 #define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ 765 ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ 766 ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ 767 ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ 768 ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ 769 ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) 770 771 /** 772 * @} 773 */ 774 /* End of private macros -----------------------------------------------------*/ 775 776 /** 777 * @} 778 */ 779 780 /** 781 * @} 782 */ 783 784 #endif /* STM32F072xB || STM32F042x6 || STM32F048xx || STM32F078xx || STM32F091xC || STM32F098xx */ 785 786 #ifdef __cplusplus 787 } 788 #endif 789 790 #endif /* __STM32F0xx_HAL_CAN_LEGACY_H */ 791
