1 /**
2   ******************************************************************************
3   * @file    stm32f091xc.h
4   * @author  MCD Application Team
5   * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
6   *          This file contains all the peripheral register's definitions, bits
7   *          definitions and memory mapping for STM32F0xx devices.
8   *
9   *          This file contains:
10   *           - Data structures and the address mapping for all peripherals
11   *           - Peripheral's registers declarations and bits definition
12   *           - Macros to access peripheral's registers hardware
13   *
14   ******************************************************************************
15   * @attention
16   *
17   * Copyright (c) 2016 STMicroelectronics.
18   * All rights reserved.
19   *
20   * This software is licensed under terms that can be found in the LICENSE file
21   * in the root directory of this software component.
22   * If no LICENSE file comes with this software, it is provided AS-IS.
23   *
24   ******************************************************************************
25   */
26 /** @addtogroup CMSIS
27   * @{
28   */
29 
30 /** @addtogroup stm32f091xc
31   * @{
32   */
33 
34 #ifndef __STM32F091xC_H
35 #define __STM32F091xC_H
36 
37 #ifdef __cplusplus
38  extern "C" {
39 #endif /* __cplusplus */
40 
41 /** @addtogroup Configuration_section_for_CMSIS
42   * @{
43   */
44 /**
45  * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
46  */
47 #define __CM0_REV                 0 /*!< Core Revision r0p0                            */
48 #define __MPU_PRESENT             0 /*!< STM32F0xx do not provide MPU                  */
49 #define __NVIC_PRIO_BITS          2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
50 #define __Vendor_SysTickConfig    0     /*!< Set to 1 if different SysTick Config is used */
51 
52 /**
53   * @}
54   */
55 
56 /** @addtogroup Peripheral_interrupt_number_definition
57   * @{
58   */
59 
60 /**
61  * @brief STM32F0xx Interrupt Number Definition, according to the selected device
62  *        in @ref Library_configuration_section
63  */
64 
65 /*!< Interrupt Number Definition */
66 typedef enum
67 {
68 /******  Cortex-M0 Processor Exceptions Numbers **************************************************************/
69   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                        */
70   HardFault_IRQn              = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                                */
71   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                                  */
72   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                                  */
73   SysTick_IRQn                = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                              */
74 
75 /******  STM32F0 specific Interrupt Numbers ******************************************************************/
76   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
77   PVD_VDDIO2_IRQn             = 1,      /*!< PVD & VDDIO2 Interrupt through EXTI Lines 16 and 31             */
78   RTC_IRQn                    = 2,      /*!< RTC Interrupt through EXTI Lines 17, 19 and 20                  */
79   FLASH_IRQn                  = 3,      /*!< FLASH global Interrupt                                          */
80   RCC_CRS_IRQn                = 4,      /*!< RCC & CRS global Interrupt                                      */
81   EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupt                                     */
82   EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupt                                     */
83   EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupt                                     */
84   TSC_IRQn                    = 8,      /*!< Touch Sensing Controller Interrupts                             */
85   DMA1_Ch1_IRQn               = 9,      /*!< DMA1 Channel 1 Interrupt                                        */
86   DMA1_Ch2_3_DMA2_Ch1_2_IRQn  = 10,     /*!< DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2 Interrupts          */
87   DMA1_Ch4_7_DMA2_Ch3_5_IRQn  = 11,     /*!< DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5 Interrupt             */
88   ADC1_COMP_IRQn              = 12,     /*!< ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */
89   TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupt           */
90   TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                                  */
91   TIM2_IRQn                   = 15,     /*!< TIM2 global Interrupt                                           */
92   TIM3_IRQn                   = 16,     /*!< TIM3 global Interrupt                                           */
93   TIM6_DAC_IRQn               = 17,     /*!< TIM6 global and DAC channel underrun error Interrupt            */
94   TIM7_IRQn                   = 18,     /*!< TIM7 global Interrupt                                           */
95   TIM14_IRQn                  = 19,     /*!< TIM14 global Interrupt                                          */
96   TIM15_IRQn                  = 20,     /*!< TIM15 global Interrupt                                          */
97   TIM16_IRQn                  = 21,     /*!< TIM16 global Interrupt                                          */
98   TIM17_IRQn                  = 22,     /*!< TIM17 global Interrupt                                          */
99   I2C1_IRQn                   = 23,     /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup)      */
100   I2C2_IRQn                   = 24,     /*!< I2C2 Event Interrupt                                            */
101   SPI1_IRQn                   = 25,     /*!< SPI1 global Interrupt                                           */
102   SPI2_IRQn                   = 26,     /*!< SPI2 global Interrupt                                           */
103   USART1_IRQn                 = 27,     /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
104   USART2_IRQn                 = 28,     /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
105   USART3_8_IRQn               = 29,     /*!< USART3 to USART8 global Interrupt                               */
106   CEC_CAN_IRQn                = 30      /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt           */
107 } IRQn_Type;
108 
109 /**
110   * @}
111   */
112 
113 #include "core_cm0.h"            /* Cortex-M0 processor and core peripherals */
114 #include "system_stm32f0xx.h"    /* STM32F0xx System Header */
115 #include <stdint.h>
116 
117 /** @addtogroup Peripheral_registers_structures
118   * @{
119   */
120 
121 /**
122   * @brief Analog to Digital Converter
123   */
124 
125 typedef struct
126 {
127   __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
128   __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
129   __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
130   __IO uint32_t CFGR1;        /*!< ADC configuration register 1,                  Address offset: 0x0C */
131   __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
132   __IO uint32_t SMPR;         /*!< ADC sampling time register,                    Address offset: 0x14 */
133        uint32_t RESERVED1;    /*!< Reserved,                                                      0x18 */
134        uint32_t RESERVED2;    /*!< Reserved,                                                      0x1C */
135   __IO uint32_t TR;           /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
136        uint32_t RESERVED3;    /*!< Reserved,                                                      0x24 */
137   __IO uint32_t CHSELR;       /*!< ADC group regular sequencer register,          Address offset: 0x28 */
138        uint32_t RESERVED4[5]; /*!< Reserved,                                                      0x2C */
139   __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
140 } ADC_TypeDef;
141 
142 typedef struct
143 {
144   __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC1 base address + 0x308 */
145 } ADC_Common_TypeDef;
146 
147 /**
148   * @brief Controller Area Network TxMailBox
149   */
150 typedef struct
151 {
152   __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
153   __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
154   __IO uint32_t TDLR; /*!< CAN mailbox data low register */
155   __IO uint32_t TDHR; /*!< CAN mailbox data high register */
156 }CAN_TxMailBox_TypeDef;
157 
158 /**
159   * @brief Controller Area Network FIFOMailBox
160   */
161 typedef struct
162 {
163   __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
164   __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
165   __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
166   __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
167 }CAN_FIFOMailBox_TypeDef;
168 
169 /**
170   * @brief Controller Area Network FilterRegister
171   */
172 typedef struct
173 {
174   __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
175   __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
176 }CAN_FilterRegister_TypeDef;
177 
178 /**
179   * @brief Controller Area Network
180   */
181 typedef struct
182 {
183   __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
184   __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
185   __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
186   __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
187   __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
188   __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
189   __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
190   __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
191   uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
192   CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
193   CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
194   uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
195   __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
196   __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
197   uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
198   __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
199   uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
200   __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
201   uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
202   __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
203   uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
204   CAN_FilterRegister_TypeDef sFilterRegister[14]; /*!< CAN Filter Register,                 Address offset: 0x240-0x2AC   */
205 }CAN_TypeDef;
206 
207 /**
208   * @brief HDMI-CEC
209   */
210 
211 typedef struct
212 {
213   __IO uint32_t CR;           /*!< CEC control register,                                       Address offset:0x00 */
214   __IO uint32_t CFGR;         /*!< CEC configuration register,                                 Address offset:0x04 */
215   __IO uint32_t TXDR;         /*!< CEC Tx data register ,                                      Address offset:0x08 */
216   __IO uint32_t RXDR;         /*!< CEC Rx Data Register,                                       Address offset:0x0C */
217   __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register,                          Address offset:0x10 */
218   __IO uint32_t IER;          /*!< CEC interrupt enable register,                              Address offset:0x14 */
219 }CEC_TypeDef;
220 
221 /**
222   * @brief Comparator
223   */
224 
225 typedef struct
226 {
227   __IO uint16_t CSR;         /*!< COMP control and status register,                                                 Address offset: 0x00 */
228 } COMP_TypeDef;
229 
230 typedef struct
231 {
232   __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
233 } COMP_Common_TypeDef;
234 
235 /* Legacy defines */
236 typedef struct
237 {
238   __IO uint32_t CSR;         /*!< Kept for legacy purpose. Use structure 'COMP_Common_TypeDef'. */
239 }COMP1_2_TypeDef;
240 
241 /**
242   * @brief CRC calculation unit
243   */
244 
245 typedef struct
246 {
247   __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
248   __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
249   uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */
250   uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */
251   __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
252   uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
253   __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
254   __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
255 } CRC_TypeDef;
256 
257 /**
258   * @brief Clock Recovery System
259   */
260 typedef struct
261 {
262 __IO uint32_t CR;     /*!< CRS ccontrol register,              Address offset: 0x00 */
263 __IO uint32_t CFGR;   /*!< CRS configuration register,         Address offset: 0x04 */
264 __IO uint32_t ISR;    /*!< CRS interrupt and status register,  Address offset: 0x08 */
265 __IO uint32_t ICR;    /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
266 }CRS_TypeDef;
267 
268 /**
269   * @brief Digital to Analog Converter
270   */
271 
272 typedef struct
273 {
274   __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
275   __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
276   __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
277   __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
278   __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
279   __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
280   __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
281   __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
282   __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
283   __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
284   __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
285   __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
286   __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
287   __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
288 } DAC_TypeDef;
289 
290 /**
291   * @brief Debug MCU
292   */
293 
294 typedef struct
295 {
296   __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
297   __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
298   __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
299   __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
300 }DBGMCU_TypeDef;
301 
302 /**
303   * @brief DMA Controller
304   */
305 
306 typedef struct
307 {
308   __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
309   __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
310   __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
311   __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
312 } DMA_Channel_TypeDef;
313 
314 typedef struct
315 {
316   __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
317   __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
318   uint32_t      RESERVED0[40];/*!< Reserved as declared by channel typedef                   0x08 - 0xA4          */
319   __IO uint32_t CSELR;        /*!< Channel selection register,                               Address offset: 0xA8 */
320 } DMA_TypeDef;
321 
322 /**
323   * @brief External Interrupt/Event Controller
324   */
325 
326 typedef struct
327 {
328   __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
329   __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
330   __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
331   __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
332   __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
333   __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
334 } EXTI_TypeDef;
335 
336 /**
337   * @brief FLASH Registers
338   */
339 typedef struct
340 {
341   __IO uint32_t ACR;          /*!<FLASH access control register,                 Address offset: 0x00 */
342   __IO uint32_t KEYR;         /*!<FLASH key register,                            Address offset: 0x04 */
343   __IO uint32_t OPTKEYR;      /*!<FLASH OPT key register,                        Address offset: 0x08 */
344   __IO uint32_t SR;           /*!<FLASH status register,                         Address offset: 0x0C */
345   __IO uint32_t CR;           /*!<FLASH control register,                        Address offset: 0x10 */
346   __IO uint32_t AR;           /*!<FLASH address register,                        Address offset: 0x14 */
347   __IO uint32_t RESERVED;     /*!< Reserved,                                                     0x18 */
348   __IO uint32_t OBR;          /*!<FLASH option bytes register,                   Address offset: 0x1C */
349   __IO uint32_t WRPR;         /*!<FLASH option bytes register,                   Address offset: 0x20 */
350 } FLASH_TypeDef;
351 
352 /**
353   * @brief Option Bytes Registers
354   */
355 typedef struct
356 {
357   __IO uint16_t RDP;          /*!< FLASH option byte Read protection,             Address offset: 0x00 */
358   __IO uint16_t USER;         /*!< FLASH option byte user options,                Address offset: 0x02 */
359   __IO uint16_t DATA0;        /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
360   __IO uint16_t DATA1;        /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
361   __IO uint16_t WRP0;         /*!< FLASH option byte write protection 0,          Address offset: 0x08 */
362   __IO uint16_t WRP1;         /*!< FLASH option byte write protection 1,          Address offset: 0x0A */
363   __IO uint16_t WRP2;         /*!< FLASH option byte write protection 2,          Address offset: 0x0C */
364   __IO uint16_t WRP3;         /*!< FLASH option byte write protection 3,          Address offset: 0x0E */
365 } OB_TypeDef;
366 
367 /**
368   * @brief General Purpose I/O
369   */
370 
371 typedef struct
372 {
373   __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
374   __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
375   __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
376   __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
377   __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
378   __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
379   __IO uint32_t BSRR;         /*!< GPIO port bit set/reset register,      Address offset: 0x1A */
380   __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
381   __IO uint32_t AFR[2];       /*!< GPIO alternate function low register,  Address offset: 0x20-0x24 */
382   __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28      */
383 } GPIO_TypeDef;
384 
385 /**
386   * @brief SysTem Configuration
387   */
388 
389 typedef struct
390 {
391   __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                           Address offset: 0x00 */
392        uint32_t RESERVED;    /*!< Reserved,                                                                  0x04 */
393   __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration register,     Address offset: 0x14-0x08 */
394   __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                           Address offset: 0x18 */
395        uint32_t RESERVED1[25];    /*!< Reserved + COMP,                                                      0x1C */
396   __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register,                  Address offset: 0x80 */
397 } SYSCFG_TypeDef;
398 
399 /**
400   * @brief Inter-integrated Circuit Interface
401   */
402 
403 typedef struct
404 {
405   __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
406   __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
407   __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
408   __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
409   __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
410   __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
411   __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
412   __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
413   __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
414   __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
415   __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
416 } I2C_TypeDef;
417 
418 /**
419   * @brief Independent WATCHDOG
420   */
421 
422 typedef struct
423 {
424   __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
425   __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
426   __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
427   __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
428   __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
429 } IWDG_TypeDef;
430 
431 /**
432   * @brief Power Control
433   */
434 
435 typedef struct
436 {
437   __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
438   __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
439 } PWR_TypeDef;
440 
441 /**
442   * @brief Reset and Clock Control
443   */
444 
445 typedef struct
446 {
447   __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
448   __IO uint32_t CFGR;       /*!< RCC clock configuration register,                            Address offset: 0x04 */
449   __IO uint32_t CIR;        /*!< RCC clock interrupt register,                                Address offset: 0x08 */
450   __IO uint32_t APB2RSTR;   /*!< RCC APB2 peripheral reset register,                          Address offset: 0x0C */
451   __IO uint32_t APB1RSTR;   /*!< RCC APB1 peripheral reset register,                          Address offset: 0x10 */
452   __IO uint32_t AHBENR;     /*!< RCC AHB peripheral clock register,                           Address offset: 0x14 */
453   __IO uint32_t APB2ENR;    /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x18 */
454   __IO uint32_t APB1ENR;    /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x1C */
455   __IO uint32_t BDCR;       /*!< RCC Backup domain control register,                          Address offset: 0x20 */
456   __IO uint32_t CSR;        /*!< RCC clock control & status register,                         Address offset: 0x24 */
457   __IO uint32_t AHBRSTR;    /*!< RCC AHB peripheral reset register,                           Address offset: 0x28 */
458   __IO uint32_t CFGR2;      /*!< RCC clock configuration register 2,                          Address offset: 0x2C */
459   __IO uint32_t CFGR3;      /*!< RCC clock configuration register 3,                          Address offset: 0x30 */
460   __IO uint32_t CR2;        /*!< RCC clock control register 2,                                Address offset: 0x34 */
461 } RCC_TypeDef;
462 
463 /**
464   * @brief Real-Time Clock
465   */
466 typedef struct
467 {
468   __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
469   __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
470   __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
471   __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
472   __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
473   __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
474        uint32_t RESERVED1;  /*!< Reserved,                                                  Address offset: 0x18 */
475   __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
476        uint32_t RESERVED2;  /*!< Reserved,                                                  Address offset: 0x20 */
477   __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
478   __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
479   __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
480   __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
481   __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
482   __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
483   __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
484   __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
485   __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
486        uint32_t RESERVED3;  /*!< Reserved,                                                  Address offset: 0x48 */
487        uint32_t RESERVED4;  /*!< Reserved,                                                  Address offset: 0x4C */
488   __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
489   __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
490   __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
491   __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
492   __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
493 } RTC_TypeDef;
494 
495 /**
496   * @brief Serial Peripheral Interface
497   */
498 
499 typedef struct
500 {
501   __IO uint32_t CR1;        /*!< SPI Control register 1 (not used in I2S mode),      Address offset: 0x00 */
502   __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
503   __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
504   __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
505   __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
506   __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register (not used in I2S mode),         Address offset: 0x14 */
507   __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register (not used in I2S mode),         Address offset: 0x18 */
508   __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
509   __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
510 } SPI_TypeDef;
511 
512 /**
513   * @brief TIM
514   */
515 typedef struct
516 {
517   __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
518   __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
519   __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
520   __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
521   __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
522   __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
523   __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
524   __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
525   __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
526   __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
527   __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
528   __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
529   __IO uint32_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */
530   __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */
531   __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */
532   __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
533   __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
534   __IO uint32_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */
535   __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
536   __IO uint32_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */
537   __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
538 } TIM_TypeDef;
539 
540 /**
541   * @brief Touch Sensing Controller (TSC)
542   */
543 typedef struct
544 {
545   __IO uint32_t CR;        /*!< TSC control register,                                     Address offset: 0x00 */
546   __IO uint32_t IER;       /*!< TSC interrupt enable register,                            Address offset: 0x04 */
547   __IO uint32_t ICR;       /*!< TSC interrupt clear register,                             Address offset: 0x08 */
548   __IO uint32_t ISR;       /*!< TSC interrupt status register,                            Address offset: 0x0C */
549   __IO uint32_t IOHCR;     /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
550        uint32_t RESERVED1; /*!< Reserved,                                                 Address offset: 0x14 */
551   __IO uint32_t IOASCR;    /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
552        uint32_t RESERVED2; /*!< Reserved,                                                 Address offset: 0x1C */
553   __IO uint32_t IOSCR;     /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
554        uint32_t RESERVED3; /*!< Reserved,                                                 Address offset: 0x24 */
555   __IO uint32_t IOCCR;     /*!< TSC I/O channel control register,                         Address offset: 0x28 */
556        uint32_t RESERVED4; /*!< Reserved,                                                 Address offset: 0x2C */
557   __IO uint32_t IOGCSR;    /*!< TSC I/O group control status register,                    Address offset: 0x30 */
558   __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register,                         Address offset: 0x34-50 */
559 }TSC_TypeDef;
560 
561 /**
562   * @brief Universal Synchronous Asynchronous Receiver Transmitter
563   */
564 
565 typedef struct
566 {
567   __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
568   __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
569   __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
570   __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
571   __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
572   __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
573   __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
574   __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
575   __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
576   __IO uint16_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
577   uint16_t  RESERVED1;  /*!< Reserved, 0x26                                                 */
578   __IO uint16_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
579   uint16_t  RESERVED2;  /*!< Reserved, 0x2A                                                 */
580 } USART_TypeDef;
581 
582 /**
583   * @brief Window WATCHDOG
584   */
585 typedef struct
586 {
587   __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
588   __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
589   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
590 } WWDG_TypeDef;
591 
592 /**
593   * @}
594   */
595 
596 /** @addtogroup Peripheral_memory_map
597   * @{
598   */
599 
600 #define FLASH_BASE            0x08000000UL              /*!< FLASH base address in the alias region */
601 #define FLASH_BANK1_END       0x0803FFFFUL /*!< FLASH END address of bank1 */
602 #define SRAM_BASE             0x20000000UL              /*!< SRAM base address in the alias region */
603 #define PERIPH_BASE           0x40000000UL              /*!< Peripheral base address in the alias region */
604 
605 /*!< Peripheral memory map */
606 #define APBPERIPH_BASE        PERIPH_BASE
607 #define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
608 #define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)
609 
610 /*!< APB peripherals */
611 #define TIM2_BASE             (APBPERIPH_BASE + 0x00000000UL)
612 #define TIM3_BASE             (APBPERIPH_BASE + 0x00000400UL)
613 #define TIM6_BASE             (APBPERIPH_BASE + 0x00001000UL)
614 #define TIM7_BASE             (APBPERIPH_BASE + 0x00001400UL)
615 #define TIM14_BASE            (APBPERIPH_BASE + 0x00002000UL)
616 #define RTC_BASE              (APBPERIPH_BASE + 0x00002800UL)
617 #define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00UL)
618 #define IWDG_BASE             (APBPERIPH_BASE + 0x00003000UL)
619 #define SPI2_BASE             (APBPERIPH_BASE + 0x00003800UL)
620 #define USART2_BASE           (APBPERIPH_BASE + 0x00004400UL)
621 #define USART3_BASE           (APBPERIPH_BASE + 0x00004800UL)
622 #define USART4_BASE           (APBPERIPH_BASE + 0x00004C00UL)
623 #define USART5_BASE           (APBPERIPH_BASE + 0x00005000UL)
624 #define I2C1_BASE             (APBPERIPH_BASE + 0x00005400UL)
625 #define I2C2_BASE             (APBPERIPH_BASE + 0x00005800UL)
626 #define CAN_BASE              (APBPERIPH_BASE + 0x00006400UL)
627 #define CRS_BASE              (APBPERIPH_BASE + 0x00006C00UL)
628 #define PWR_BASE              (APBPERIPH_BASE + 0x00007000UL)
629 #define DAC_BASE              (APBPERIPH_BASE + 0x00007400UL)
630 
631 #define CEC_BASE              (APBPERIPH_BASE + 0x00007800UL)
632 
633 #define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000UL)
634 #define COMP_BASE             (APBPERIPH_BASE + 0x0001001CUL)
635 #define EXTI_BASE             (APBPERIPH_BASE + 0x00010400UL)
636 #define USART6_BASE           (APBPERIPH_BASE + 0x00011400UL)
637 #define USART7_BASE           (APBPERIPH_BASE + 0x00011800UL)
638 #define USART8_BASE           (APBPERIPH_BASE + 0x00011C00UL)
639 #define ADC1_BASE             (APBPERIPH_BASE + 0x00012400UL)
640 #define ADC_BASE              (APBPERIPH_BASE + 0x00012708UL)
641 #define TIM1_BASE             (APBPERIPH_BASE + 0x00012C00UL)
642 #define SPI1_BASE             (APBPERIPH_BASE + 0x00013000UL)
643 #define USART1_BASE           (APBPERIPH_BASE + 0x00013800UL)
644 #define TIM15_BASE            (APBPERIPH_BASE + 0x00014000UL)
645 #define TIM16_BASE            (APBPERIPH_BASE + 0x00014400UL)
646 #define TIM17_BASE            (APBPERIPH_BASE + 0x00014800UL)
647 #define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800UL)
648 
649 /*!< AHB peripherals */
650 #define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000UL)
651 #define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
652 #define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
653 #define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
654 #define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
655 #define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
656 #define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
657 #define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
658 #define DMA2_BASE             (AHBPERIPH_BASE + 0x00000400UL)
659 #define DMA2_Channel1_BASE    (DMA2_BASE + 0x00000008UL)
660 #define DMA2_Channel2_BASE    (DMA2_BASE + 0x0000001CUL)
661 #define DMA2_Channel3_BASE    (DMA2_BASE + 0x00000030UL)
662 #define DMA2_Channel4_BASE    (DMA2_BASE + 0x00000044UL)
663 #define DMA2_Channel5_BASE    (DMA2_BASE + 0x00000058UL)
664 
665 #define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
666 #define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
667 #define OB_BASE               0x1FFFF800UL       /*!< FLASH Option Bytes base address */
668 #define FLASHSIZE_BASE        0x1FFFF7CCUL       /*!< FLASH Size register base address */
669 #define UID_BASE              0x1FFFF7ACUL       /*!< Unique device ID register base address */
670 #define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
671 #define TSC_BASE              (AHBPERIPH_BASE + 0x00004000UL)
672 
673 /*!< AHB2 peripherals */
674 #define GPIOA_BASE            (AHB2PERIPH_BASE + 0x00000000UL)
675 #define GPIOB_BASE            (AHB2PERIPH_BASE + 0x00000400UL)
676 #define GPIOC_BASE            (AHB2PERIPH_BASE + 0x00000800UL)
677 #define GPIOD_BASE            (AHB2PERIPH_BASE + 0x00000C00UL)
678 #define GPIOE_BASE            (AHB2PERIPH_BASE + 0x00001000UL)
679 #define GPIOF_BASE            (AHB2PERIPH_BASE + 0x00001400UL)
680 
681 /**
682   * @}
683   */
684 
685 /** @addtogroup Peripheral_declaration
686   * @{
687   */
688 
689 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
690 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
691 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
692 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
693 #define TIM14               ((TIM_TypeDef *) TIM14_BASE)
694 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
695 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
696 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
697 #define USART2              ((USART_TypeDef *) USART2_BASE)
698 #define USART3              ((USART_TypeDef *) USART3_BASE)
699 #define USART4              ((USART_TypeDef *) USART4_BASE)
700 #define USART5              ((USART_TypeDef *) USART5_BASE)
701 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
702 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
703 #define CAN                 ((CAN_TypeDef *) CAN_BASE)
704 #define CRS                 ((CRS_TypeDef *) CRS_BASE)
705 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
706 #define DAC1                ((DAC_TypeDef *) DAC_BASE)
707 #define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
708 #define CEC                 ((CEC_TypeDef *) CEC_BASE)
709 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
710 #define COMP1               ((COMP_TypeDef *) COMP_BASE)
711 #define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000002))
712 #define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP_BASE)
713 #define COMP                ((COMP1_2_TypeDef *) COMP_BASE) /* Kept for legacy purpose */
714 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
715 #define USART6              ((USART_TypeDef *) USART6_BASE)
716 #define USART7              ((USART_TypeDef *) USART7_BASE)
717 #define USART8              ((USART_TypeDef *) USART8_BASE)
718 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
719 #define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
720 #define ADC                 ((ADC_Common_TypeDef *) ADC_BASE) /* Kept for legacy purpose */
721 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
722 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
723 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
724 #define USART1              ((USART_TypeDef *) USART1_BASE)
725 #define TIM15               ((TIM_TypeDef *) TIM15_BASE)
726 #define TIM16               ((TIM_TypeDef *) TIM16_BASE)
727 #define TIM17               ((TIM_TypeDef *) TIM17_BASE)
728 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
729 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
730 #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
731 #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
732 #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
733 #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
734 #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
735 #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
736 #define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
737 #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
738 #define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
739 #define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
740 #define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
741 #define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
742 #define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
743 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
744 #define OB                  ((OB_TypeDef *) OB_BASE)
745 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
746 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
747 #define TSC                 ((TSC_TypeDef *) TSC_BASE)
748 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
749 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
750 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
751 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
752 #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
753 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
754 /**
755   * @}
756   */
757 
758 /** @addtogroup Exported_constants
759   * @{
760   */
761 
762 /** @addtogroup Hardware_Constant_Definition
763   * @{
764   */
765 #define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */
766 
767 /**
768   * @}
769   */
770 
771 /** @addtogroup Peripheral_Registers_Bits_Definition
772   * @{
773   */
774 
775 /******************************************************************************/
776 /*                         Peripheral Registers Bits Definition               */
777 /******************************************************************************/
778 
779 /******************************************************************************/
780 /*                                                                            */
781 /*                      Analog to Digital Converter (ADC)                     */
782 /*                                                                            */
783 /******************************************************************************/
784 
785 /*
786  * @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
787  */
788 #define ADC_CHANNEL_VBAT_SUPPORT                       /*!< ADC feature available only on specific devices: ADC internal channel Vbat */
789 
790 /********************  Bits definition for ADC_ISR register  ******************/
791 #define ADC_ISR_ADRDY_Pos         (0U)
792 #define ADC_ISR_ADRDY_Msk         (0x1UL << ADC_ISR_ADRDY_Pos)                  /*!< 0x00000001 */
793 #define ADC_ISR_ADRDY             ADC_ISR_ADRDY_Msk                            /*!< ADC ready flag */
794 #define ADC_ISR_EOSMP_Pos         (1U)
795 #define ADC_ISR_EOSMP_Msk         (0x1UL << ADC_ISR_EOSMP_Pos)                  /*!< 0x00000002 */
796 #define ADC_ISR_EOSMP             ADC_ISR_EOSMP_Msk                            /*!< ADC group regular end of sampling flag */
797 #define ADC_ISR_EOC_Pos           (2U)
798 #define ADC_ISR_EOC_Msk           (0x1UL << ADC_ISR_EOC_Pos)                    /*!< 0x00000004 */
799 #define ADC_ISR_EOC               ADC_ISR_EOC_Msk                              /*!< ADC group regular end of unitary conversion flag */
800 #define ADC_ISR_EOS_Pos           (3U)
801 #define ADC_ISR_EOS_Msk           (0x1UL << ADC_ISR_EOS_Pos)                    /*!< 0x00000008 */
802 #define ADC_ISR_EOS               ADC_ISR_EOS_Msk                              /*!< ADC group regular end of sequence conversions flag */
803 #define ADC_ISR_OVR_Pos           (4U)
804 #define ADC_ISR_OVR_Msk           (0x1UL << ADC_ISR_OVR_Pos)                    /*!< 0x00000010 */
805 #define ADC_ISR_OVR               ADC_ISR_OVR_Msk                              /*!< ADC group regular overrun flag */
806 #define ADC_ISR_AWD1_Pos          (7U)
807 #define ADC_ISR_AWD1_Msk          (0x1UL << ADC_ISR_AWD1_Pos)                   /*!< 0x00000080 */
808 #define ADC_ISR_AWD1              ADC_ISR_AWD1_Msk                             /*!< ADC analog watchdog 1 flag */
809 
810 /* Legacy defines */
811 #define ADC_ISR_AWD             (ADC_ISR_AWD1)
812 #define ADC_ISR_EOSEQ           (ADC_ISR_EOS)
813 
814 /********************  Bits definition for ADC_IER register  ******************/
815 #define ADC_IER_ADRDYIE_Pos       (0U)
816 #define ADC_IER_ADRDYIE_Msk       (0x1UL << ADC_IER_ADRDYIE_Pos)                /*!< 0x00000001 */
817 #define ADC_IER_ADRDYIE           ADC_IER_ADRDYIE_Msk                          /*!< ADC ready interrupt */
818 #define ADC_IER_EOSMPIE_Pos       (1U)
819 #define ADC_IER_EOSMPIE_Msk       (0x1UL << ADC_IER_EOSMPIE_Pos)                /*!< 0x00000002 */
820 #define ADC_IER_EOSMPIE           ADC_IER_EOSMPIE_Msk                          /*!< ADC group regular end of sampling interrupt */
821 #define ADC_IER_EOCIE_Pos         (2U)
822 #define ADC_IER_EOCIE_Msk         (0x1UL << ADC_IER_EOCIE_Pos)                  /*!< 0x00000004 */
823 #define ADC_IER_EOCIE             ADC_IER_EOCIE_Msk                            /*!< ADC group regular end of unitary conversion interrupt */
824 #define ADC_IER_EOSIE_Pos         (3U)
825 #define ADC_IER_EOSIE_Msk         (0x1UL << ADC_IER_EOSIE_Pos)                  /*!< 0x00000008 */
826 #define ADC_IER_EOSIE             ADC_IER_EOSIE_Msk                            /*!< ADC group regular end of sequence conversions interrupt */
827 #define ADC_IER_OVRIE_Pos         (4U)
828 #define ADC_IER_OVRIE_Msk         (0x1UL << ADC_IER_OVRIE_Pos)                  /*!< 0x00000010 */
829 #define ADC_IER_OVRIE             ADC_IER_OVRIE_Msk                            /*!< ADC group regular overrun interrupt */
830 #define ADC_IER_AWD1IE_Pos        (7U)
831 #define ADC_IER_AWD1IE_Msk        (0x1UL << ADC_IER_AWD1IE_Pos)                 /*!< 0x00000080 */
832 #define ADC_IER_AWD1IE            ADC_IER_AWD1IE_Msk                           /*!< ADC analog watchdog 1 interrupt */
833 
834 /* Legacy defines */
835 #define ADC_IER_AWDIE           (ADC_IER_AWD1IE)
836 #define ADC_IER_EOSEQIE         (ADC_IER_EOSIE)
837 
838 /********************  Bits definition for ADC_CR register  *******************/
839 #define ADC_CR_ADEN_Pos           (0U)
840 #define ADC_CR_ADEN_Msk           (0x1UL << ADC_CR_ADEN_Pos)                    /*!< 0x00000001 */
841 #define ADC_CR_ADEN               ADC_CR_ADEN_Msk                              /*!< ADC enable */
842 #define ADC_CR_ADDIS_Pos          (1U)
843 #define ADC_CR_ADDIS_Msk          (0x1UL << ADC_CR_ADDIS_Pos)                   /*!< 0x00000002 */
844 #define ADC_CR_ADDIS              ADC_CR_ADDIS_Msk                             /*!< ADC disable */
845 #define ADC_CR_ADSTART_Pos        (2U)
846 #define ADC_CR_ADSTART_Msk        (0x1UL << ADC_CR_ADSTART_Pos)                 /*!< 0x00000004 */
847 #define ADC_CR_ADSTART            ADC_CR_ADSTART_Msk                           /*!< ADC group regular conversion start */
848 #define ADC_CR_ADSTP_Pos          (4U)
849 #define ADC_CR_ADSTP_Msk          (0x1UL << ADC_CR_ADSTP_Pos)                   /*!< 0x00000010 */
850 #define ADC_CR_ADSTP              ADC_CR_ADSTP_Msk                             /*!< ADC group regular conversion stop */
851 #define ADC_CR_ADCAL_Pos          (31U)
852 #define ADC_CR_ADCAL_Msk          (0x1UL << ADC_CR_ADCAL_Pos)                   /*!< 0x80000000 */
853 #define ADC_CR_ADCAL              ADC_CR_ADCAL_Msk                             /*!< ADC calibration */
854 
855 /*******************  Bits definition for ADC_CFGR1 register  *****************/
856 #define ADC_CFGR1_DMAEN_Pos       (0U)
857 #define ADC_CFGR1_DMAEN_Msk       (0x1UL << ADC_CFGR1_DMAEN_Pos)                /*!< 0x00000001 */
858 #define ADC_CFGR1_DMAEN           ADC_CFGR1_DMAEN_Msk                          /*!< ADC DMA transfer enable */
859 #define ADC_CFGR1_DMACFG_Pos      (1U)
860 #define ADC_CFGR1_DMACFG_Msk      (0x1UL << ADC_CFGR1_DMACFG_Pos)               /*!< 0x00000002 */
861 #define ADC_CFGR1_DMACFG          ADC_CFGR1_DMACFG_Msk                         /*!< ADC DMA transfer configuration */
862 #define ADC_CFGR1_SCANDIR_Pos     (2U)
863 #define ADC_CFGR1_SCANDIR_Msk     (0x1UL << ADC_CFGR1_SCANDIR_Pos)              /*!< 0x00000004 */
864 #define ADC_CFGR1_SCANDIR         ADC_CFGR1_SCANDIR_Msk                        /*!< ADC group regular sequencer scan direction */
865 
866 #define ADC_CFGR1_RES_Pos         (3U)
867 #define ADC_CFGR1_RES_Msk         (0x3UL << ADC_CFGR1_RES_Pos)                  /*!< 0x00000018 */
868 #define ADC_CFGR1_RES             ADC_CFGR1_RES_Msk                            /*!< ADC data resolution */
869 #define ADC_CFGR1_RES_0           (0x1UL << ADC_CFGR1_RES_Pos)                  /*!< 0x00000008 */
870 #define ADC_CFGR1_RES_1           (0x2UL << ADC_CFGR1_RES_Pos)                  /*!< 0x00000010 */
871 
872 #define ADC_CFGR1_ALIGN_Pos       (5U)
873 #define ADC_CFGR1_ALIGN_Msk       (0x1UL << ADC_CFGR1_ALIGN_Pos)                /*!< 0x00000020 */
874 #define ADC_CFGR1_ALIGN           ADC_CFGR1_ALIGN_Msk                          /*!< ADC data alignment */
875 
876 #define ADC_CFGR1_EXTSEL_Pos      (6U)
877 #define ADC_CFGR1_EXTSEL_Msk      (0x7UL << ADC_CFGR1_EXTSEL_Pos)               /*!< 0x000001C0 */
878 #define ADC_CFGR1_EXTSEL          ADC_CFGR1_EXTSEL_Msk                         /*!< ADC group regular external trigger source */
879 #define ADC_CFGR1_EXTSEL_0        (0x1UL << ADC_CFGR1_EXTSEL_Pos)               /*!< 0x00000040 */
880 #define ADC_CFGR1_EXTSEL_1        (0x2UL << ADC_CFGR1_EXTSEL_Pos)               /*!< 0x00000080 */
881 #define ADC_CFGR1_EXTSEL_2        (0x4UL << ADC_CFGR1_EXTSEL_Pos)               /*!< 0x00000100 */
882 
883 #define ADC_CFGR1_EXTEN_Pos       (10U)
884 #define ADC_CFGR1_EXTEN_Msk       (0x3UL << ADC_CFGR1_EXTEN_Pos)                /*!< 0x00000C00 */
885 #define ADC_CFGR1_EXTEN           ADC_CFGR1_EXTEN_Msk                          /*!< ADC group regular external trigger polarity */
886 #define ADC_CFGR1_EXTEN_0         (0x1UL << ADC_CFGR1_EXTEN_Pos)                /*!< 0x00000400 */
887 #define ADC_CFGR1_EXTEN_1         (0x2UL << ADC_CFGR1_EXTEN_Pos)                /*!< 0x00000800 */
888 
889 #define ADC_CFGR1_OVRMOD_Pos      (12U)
890 #define ADC_CFGR1_OVRMOD_Msk      (0x1UL << ADC_CFGR1_OVRMOD_Pos)               /*!< 0x00001000 */
891 #define ADC_CFGR1_OVRMOD          ADC_CFGR1_OVRMOD_Msk                         /*!< ADC group regular overrun configuration */
892 #define ADC_CFGR1_CONT_Pos        (13U)
893 #define ADC_CFGR1_CONT_Msk        (0x1UL << ADC_CFGR1_CONT_Pos)                 /*!< 0x00002000 */
894 #define ADC_CFGR1_CONT            ADC_CFGR1_CONT_Msk                           /*!< ADC group regular continuous conversion mode */
895 #define ADC_CFGR1_WAIT_Pos        (14U)
896 #define ADC_CFGR1_WAIT_Msk        (0x1UL << ADC_CFGR1_WAIT_Pos)                 /*!< 0x00004000 */
897 #define ADC_CFGR1_WAIT            ADC_CFGR1_WAIT_Msk                           /*!< ADC low power auto wait */
898 #define ADC_CFGR1_AUTOFF_Pos      (15U)
899 #define ADC_CFGR1_AUTOFF_Msk      (0x1UL << ADC_CFGR1_AUTOFF_Pos)               /*!< 0x00008000 */
900 #define ADC_CFGR1_AUTOFF          ADC_CFGR1_AUTOFF_Msk                         /*!< ADC low power auto power off */
901 #define ADC_CFGR1_DISCEN_Pos      (16U)
902 #define ADC_CFGR1_DISCEN_Msk      (0x1UL << ADC_CFGR1_DISCEN_Pos)               /*!< 0x00010000 */
903 #define ADC_CFGR1_DISCEN          ADC_CFGR1_DISCEN_Msk                         /*!< ADC group regular sequencer discontinuous mode */
904 
905 #define ADC_CFGR1_AWD1SGL_Pos     (22U)
906 #define ADC_CFGR1_AWD1SGL_Msk     (0x1UL << ADC_CFGR1_AWD1SGL_Pos)              /*!< 0x00400000 */
907 #define ADC_CFGR1_AWD1SGL         ADC_CFGR1_AWD1SGL_Msk                        /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
908 #define ADC_CFGR1_AWD1EN_Pos      (23U)
909 #define ADC_CFGR1_AWD1EN_Msk      (0x1UL << ADC_CFGR1_AWD1EN_Pos)               /*!< 0x00800000 */
910 #define ADC_CFGR1_AWD1EN          ADC_CFGR1_AWD1EN_Msk                         /*!< ADC analog watchdog 1 enable on scope ADC group regular */
911 
912 #define ADC_CFGR1_AWD1CH_Pos      (26U)
913 #define ADC_CFGR1_AWD1CH_Msk      (0x1FUL << ADC_CFGR1_AWD1CH_Pos)              /*!< 0x7C000000 */
914 #define ADC_CFGR1_AWD1CH          ADC_CFGR1_AWD1CH_Msk                         /*!< ADC analog watchdog 1 monitored channel selection */
915 #define ADC_CFGR1_AWD1CH_0        (0x01UL << ADC_CFGR1_AWD1CH_Pos)              /*!< 0x04000000 */
916 #define ADC_CFGR1_AWD1CH_1        (0x02UL << ADC_CFGR1_AWD1CH_Pos)              /*!< 0x08000000 */
917 #define ADC_CFGR1_AWD1CH_2        (0x04UL << ADC_CFGR1_AWD1CH_Pos)              /*!< 0x10000000 */
918 #define ADC_CFGR1_AWD1CH_3        (0x08UL << ADC_CFGR1_AWD1CH_Pos)              /*!< 0x20000000 */
919 #define ADC_CFGR1_AWD1CH_4        (0x10UL << ADC_CFGR1_AWD1CH_Pos)              /*!< 0x40000000 */
920 
921 /* Legacy defines */
922 #define ADC_CFGR1_AUTDLY        (ADC_CFGR1_WAIT)
923 #define ADC_CFGR1_AWDSGL        (ADC_CFGR1_AWD1SGL)
924 #define ADC_CFGR1_AWDEN         (ADC_CFGR1_AWD1EN)
925 #define ADC_CFGR1_AWDCH         (ADC_CFGR1_AWD1CH)
926 #define ADC_CFGR1_AWDCH_0       (ADC_CFGR1_AWD1CH_0)
927 #define ADC_CFGR1_AWDCH_1       (ADC_CFGR1_AWD1CH_1)
928 #define ADC_CFGR1_AWDCH_2       (ADC_CFGR1_AWD1CH_2)
929 #define ADC_CFGR1_AWDCH_3       (ADC_CFGR1_AWD1CH_3)
930 #define ADC_CFGR1_AWDCH_4       (ADC_CFGR1_AWD1CH_4)
931 
932 /*******************  Bits definition for ADC_CFGR2 register  *****************/
933 #define ADC_CFGR2_CKMODE_Pos      (30U)
934 #define ADC_CFGR2_CKMODE_Msk      (0x3UL << ADC_CFGR2_CKMODE_Pos)               /*!< 0xC0000000 */
935 #define ADC_CFGR2_CKMODE          ADC_CFGR2_CKMODE_Msk                         /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */
936 #define ADC_CFGR2_CKMODE_1        (0x2UL << ADC_CFGR2_CKMODE_Pos)               /*!< 0x80000000 */
937 #define ADC_CFGR2_CKMODE_0        (0x1UL << ADC_CFGR2_CKMODE_Pos)               /*!< 0x40000000 */
938 
939 /* Legacy defines */
940 #define  ADC_CFGR2_JITOFFDIV4   (ADC_CFGR2_CKMODE_1)   /*!< ADC clocked by PCLK div4 */
941 #define  ADC_CFGR2_JITOFFDIV2   (ADC_CFGR2_CKMODE_0)   /*!< ADC clocked by PCLK div2 */
942 
943 /******************  Bit definition for ADC_SMPR register  ********************/
944 #define ADC_SMPR_SMP_Pos          (0U)
945 #define ADC_SMPR_SMP_Msk          (0x7UL << ADC_SMPR_SMP_Pos)                   /*!< 0x00000007 */
946 #define ADC_SMPR_SMP              ADC_SMPR_SMP_Msk                             /*!< ADC group of channels sampling time 2 */
947 #define ADC_SMPR_SMP_0            (0x1UL << ADC_SMPR_SMP_Pos)                   /*!< 0x00000001 */
948 #define ADC_SMPR_SMP_1            (0x2UL << ADC_SMPR_SMP_Pos)                   /*!< 0x00000002 */
949 #define ADC_SMPR_SMP_2            (0x4UL << ADC_SMPR_SMP_Pos)                   /*!< 0x00000004 */
950 
951 /* Legacy defines */
952 #define  ADC_SMPR1_SMPR         (ADC_SMPR_SMP)         /*!< SMP[2:0] bits (Sampling time selection) */
953 #define  ADC_SMPR1_SMPR_0       (ADC_SMPR_SMP_0)       /*!< bit 0 */
954 #define  ADC_SMPR1_SMPR_1       (ADC_SMPR_SMP_1)       /*!< bit 1 */
955 #define  ADC_SMPR1_SMPR_2       (ADC_SMPR_SMP_2)       /*!< bit 2 */
956 
957 /*******************  Bit definition for ADC_TR register  ********************/
958 #define ADC_TR1_LT1_Pos           (0U)
959 #define ADC_TR1_LT1_Msk           (0xFFFUL << ADC_TR1_LT1_Pos)                  /*!< 0x00000FFF */
960 #define ADC_TR1_LT1               ADC_TR1_LT1_Msk                              /*!< ADC analog watchdog 1 threshold low */
961 #define ADC_TR1_LT1_0             (0x001UL << ADC_TR1_LT1_Pos)                  /*!< 0x00000001 */
962 #define ADC_TR1_LT1_1             (0x002UL << ADC_TR1_LT1_Pos)                  /*!< 0x00000002 */
963 #define ADC_TR1_LT1_2             (0x004UL << ADC_TR1_LT1_Pos)                  /*!< 0x00000004 */
964 #define ADC_TR1_LT1_3             (0x008UL << ADC_TR1_LT1_Pos)                  /*!< 0x00000008 */
965 #define ADC_TR1_LT1_4             (0x010UL << ADC_TR1_LT1_Pos)                  /*!< 0x00000010 */
966 #define ADC_TR1_LT1_5             (0x020UL << ADC_TR1_LT1_Pos)                  /*!< 0x00000020 */
967 #define ADC_TR1_LT1_6             (0x040UL << ADC_TR1_LT1_Pos)                  /*!< 0x00000040 */
968 #define ADC_TR1_LT1_7             (0x080UL << ADC_TR1_LT1_Pos)                  /*!< 0x00000080 */
969 #define ADC_TR1_LT1_8             (0x100UL << ADC_TR1_LT1_Pos)                  /*!< 0x00000100 */
970 #define ADC_TR1_LT1_9             (0x200UL << ADC_TR1_LT1_Pos)                  /*!< 0x00000200 */
971 #define ADC_TR1_LT1_10            (0x400UL << ADC_TR1_LT1_Pos)                  /*!< 0x00000400 */
972 #define ADC_TR1_LT1_11            (0x800UL << ADC_TR1_LT1_Pos)                  /*!< 0x00000800 */
973 
974 #define ADC_TR1_HT1_Pos           (16U)
975 #define ADC_TR1_HT1_Msk           (0xFFFUL << ADC_TR1_HT1_Pos)                  /*!< 0x0FFF0000 */
976 #define ADC_TR1_HT1               ADC_TR1_HT1_Msk                              /*!< ADC Analog watchdog 1 threshold high */
977 #define ADC_TR1_HT1_0             (0x001UL << ADC_TR1_HT1_Pos)                  /*!< 0x00010000 */
978 #define ADC_TR1_HT1_1             (0x002UL << ADC_TR1_HT1_Pos)                  /*!< 0x00020000 */
979 #define ADC_TR1_HT1_2             (0x004UL << ADC_TR1_HT1_Pos)                  /*!< 0x00040000 */
980 #define ADC_TR1_HT1_3             (0x008UL << ADC_TR1_HT1_Pos)                  /*!< 0x00080000 */
981 #define ADC_TR1_HT1_4             (0x010UL << ADC_TR1_HT1_Pos)                  /*!< 0x00100000 */
982 #define ADC_TR1_HT1_5             (0x020UL << ADC_TR1_HT1_Pos)                  /*!< 0x00200000 */
983 #define ADC_TR1_HT1_6             (0x040UL << ADC_TR1_HT1_Pos)                  /*!< 0x00400000 */
984 #define ADC_TR1_HT1_7             (0x080UL << ADC_TR1_HT1_Pos)                  /*!< 0x00800000 */
985 #define ADC_TR1_HT1_8             (0x100UL << ADC_TR1_HT1_Pos)                  /*!< 0x01000000 */
986 #define ADC_TR1_HT1_9             (0x200UL << ADC_TR1_HT1_Pos)                  /*!< 0x02000000 */
987 #define ADC_TR1_HT1_10            (0x400UL << ADC_TR1_HT1_Pos)                  /*!< 0x04000000 */
988 #define ADC_TR1_HT1_11            (0x800UL << ADC_TR1_HT1_Pos)                  /*!< 0x08000000 */
989 
990 /* Legacy defines */
991 #define  ADC_TR_HT              (ADC_TR1_HT1)
992 #define  ADC_TR_LT              (ADC_TR1_LT1)
993 #define  ADC_HTR_HT             (ADC_TR1_HT1)
994 #define  ADC_LTR_LT             (ADC_TR1_LT1)
995 
996 /******************  Bit definition for ADC_CHSELR register  ******************/
997 #define ADC_CHSELR_CHSEL_Pos      (0U)
998 #define ADC_CHSELR_CHSEL_Msk      (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)           /*!< 0x0007FFFF */
999 #define ADC_CHSELR_CHSEL          ADC_CHSELR_CHSEL_Msk                         /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
1000 #define ADC_CHSELR_CHSEL18_Pos    (18U)
1001 #define ADC_CHSELR_CHSEL18_Msk    (0x1UL << ADC_CHSELR_CHSEL18_Pos)             /*!< 0x00040000 */
1002 #define ADC_CHSELR_CHSEL18        ADC_CHSELR_CHSEL18_Msk                       /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
1003 #define ADC_CHSELR_CHSEL17_Pos    (17U)
1004 #define ADC_CHSELR_CHSEL17_Msk    (0x1UL << ADC_CHSELR_CHSEL17_Pos)             /*!< 0x00020000 */
1005 #define ADC_CHSELR_CHSEL17        ADC_CHSELR_CHSEL17_Msk                       /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
1006 #define ADC_CHSELR_CHSEL16_Pos    (16U)
1007 #define ADC_CHSELR_CHSEL16_Msk    (0x1UL << ADC_CHSELR_CHSEL16_Pos)             /*!< 0x00010000 */
1008 #define ADC_CHSELR_CHSEL16        ADC_CHSELR_CHSEL16_Msk                       /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
1009 #define ADC_CHSELR_CHSEL15_Pos    (15U)
1010 #define ADC_CHSELR_CHSEL15_Msk    (0x1UL << ADC_CHSELR_CHSEL15_Pos)             /*!< 0x00008000 */
1011 #define ADC_CHSELR_CHSEL15        ADC_CHSELR_CHSEL15_Msk                       /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
1012 #define ADC_CHSELR_CHSEL14_Pos    (14U)
1013 #define ADC_CHSELR_CHSEL14_Msk    (0x1UL << ADC_CHSELR_CHSEL14_Pos)             /*!< 0x00004000 */
1014 #define ADC_CHSELR_CHSEL14        ADC_CHSELR_CHSEL14_Msk                       /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
1015 #define ADC_CHSELR_CHSEL13_Pos    (13U)
1016 #define ADC_CHSELR_CHSEL13_Msk    (0x1UL << ADC_CHSELR_CHSEL13_Pos)             /*!< 0x00002000 */
1017 #define ADC_CHSELR_CHSEL13        ADC_CHSELR_CHSEL13_Msk                       /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
1018 #define ADC_CHSELR_CHSEL12_Pos    (12U)
1019 #define ADC_CHSELR_CHSEL12_Msk    (0x1UL << ADC_CHSELR_CHSEL12_Pos)             /*!< 0x00001000 */
1020 #define ADC_CHSELR_CHSEL12        ADC_CHSELR_CHSEL12_Msk                       /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
1021 #define ADC_CHSELR_CHSEL11_Pos    (11U)
1022 #define ADC_CHSELR_CHSEL11_Msk    (0x1UL << ADC_CHSELR_CHSEL11_Pos)             /*!< 0x00000800 */
1023 #define ADC_CHSELR_CHSEL11        ADC_CHSELR_CHSEL11_Msk                       /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
1024 #define ADC_CHSELR_CHSEL10_Pos    (10U)
1025 #define ADC_CHSELR_CHSEL10_Msk    (0x1UL << ADC_CHSELR_CHSEL10_Pos)             /*!< 0x00000400 */
1026 #define ADC_CHSELR_CHSEL10        ADC_CHSELR_CHSEL10_Msk                       /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
1027 #define ADC_CHSELR_CHSEL9_Pos     (9U)
1028 #define ADC_CHSELR_CHSEL9_Msk     (0x1UL << ADC_CHSELR_CHSEL9_Pos)              /*!< 0x00000200 */
1029 #define ADC_CHSELR_CHSEL9         ADC_CHSELR_CHSEL9_Msk                        /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
1030 #define ADC_CHSELR_CHSEL8_Pos     (8U)
1031 #define ADC_CHSELR_CHSEL8_Msk     (0x1UL << ADC_CHSELR_CHSEL8_Pos)              /*!< 0x00000100 */
1032 #define ADC_CHSELR_CHSEL8         ADC_CHSELR_CHSEL8_Msk                        /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
1033 #define ADC_CHSELR_CHSEL7_Pos     (7U)
1034 #define ADC_CHSELR_CHSEL7_Msk     (0x1UL << ADC_CHSELR_CHSEL7_Pos)              /*!< 0x00000080 */
1035 #define ADC_CHSELR_CHSEL7         ADC_CHSELR_CHSEL7_Msk                        /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
1036 #define ADC_CHSELR_CHSEL6_Pos     (6U)
1037 #define ADC_CHSELR_CHSEL6_Msk     (0x1UL << ADC_CHSELR_CHSEL6_Pos)              /*!< 0x00000040 */
1038 #define ADC_CHSELR_CHSEL6         ADC_CHSELR_CHSEL6_Msk                        /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
1039 #define ADC_CHSELR_CHSEL5_Pos     (5U)
1040 #define ADC_CHSELR_CHSEL5_Msk     (0x1UL << ADC_CHSELR_CHSEL5_Pos)              /*!< 0x00000020 */
1041 #define ADC_CHSELR_CHSEL5         ADC_CHSELR_CHSEL5_Msk                        /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
1042 #define ADC_CHSELR_CHSEL4_Pos     (4U)
1043 #define ADC_CHSELR_CHSEL4_Msk     (0x1UL << ADC_CHSELR_CHSEL4_Pos)              /*!< 0x00000010 */
1044 #define ADC_CHSELR_CHSEL4         ADC_CHSELR_CHSEL4_Msk                        /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
1045 #define ADC_CHSELR_CHSEL3_Pos     (3U)
1046 #define ADC_CHSELR_CHSEL3_Msk     (0x1UL << ADC_CHSELR_CHSEL3_Pos)              /*!< 0x00000008 */
1047 #define ADC_CHSELR_CHSEL3         ADC_CHSELR_CHSEL3_Msk                        /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
1048 #define ADC_CHSELR_CHSEL2_Pos     (2U)
1049 #define ADC_CHSELR_CHSEL2_Msk     (0x1UL << ADC_CHSELR_CHSEL2_Pos)              /*!< 0x00000004 */
1050 #define ADC_CHSELR_CHSEL2         ADC_CHSELR_CHSEL2_Msk                        /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
1051 #define ADC_CHSELR_CHSEL1_Pos     (1U)
1052 #define ADC_CHSELR_CHSEL1_Msk     (0x1UL << ADC_CHSELR_CHSEL1_Pos)              /*!< 0x00000002 */
1053 #define ADC_CHSELR_CHSEL1         ADC_CHSELR_CHSEL1_Msk                        /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
1054 #define ADC_CHSELR_CHSEL0_Pos     (0U)
1055 #define ADC_CHSELR_CHSEL0_Msk     (0x1UL << ADC_CHSELR_CHSEL0_Pos)              /*!< 0x00000001 */
1056 #define ADC_CHSELR_CHSEL0         ADC_CHSELR_CHSEL0_Msk                        /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
1057 
1058 /********************  Bit definition for ADC_DR register  ********************/
1059 #define ADC_DR_DATA_Pos           (0U)
1060 #define ADC_DR_DATA_Msk           (0xFFFFUL << ADC_DR_DATA_Pos)                 /*!< 0x0000FFFF */
1061 #define ADC_DR_DATA               ADC_DR_DATA_Msk                              /*!< ADC group regular conversion data */
1062 #define ADC_DR_DATA_0             (0x0001UL << ADC_DR_DATA_Pos)                 /*!< 0x00000001 */
1063 #define ADC_DR_DATA_1             (0x0002UL << ADC_DR_DATA_Pos)                 /*!< 0x00000002 */
1064 #define ADC_DR_DATA_2             (0x0004UL << ADC_DR_DATA_Pos)                 /*!< 0x00000004 */
1065 #define ADC_DR_DATA_3             (0x0008UL << ADC_DR_DATA_Pos)                 /*!< 0x00000008 */
1066 #define ADC_DR_DATA_4             (0x0010UL << ADC_DR_DATA_Pos)                 /*!< 0x00000010 */
1067 #define ADC_DR_DATA_5             (0x0020UL << ADC_DR_DATA_Pos)                 /*!< 0x00000020 */
1068 #define ADC_DR_DATA_6             (0x0040UL << ADC_DR_DATA_Pos)                 /*!< 0x00000040 */
1069 #define ADC_DR_DATA_7             (0x0080UL << ADC_DR_DATA_Pos)                 /*!< 0x00000080 */
1070 #define ADC_DR_DATA_8             (0x0100UL << ADC_DR_DATA_Pos)                 /*!< 0x00000100 */
1071 #define ADC_DR_DATA_9             (0x0200UL << ADC_DR_DATA_Pos)                 /*!< 0x00000200 */
1072 #define ADC_DR_DATA_10            (0x0400UL << ADC_DR_DATA_Pos)                 /*!< 0x00000400 */
1073 #define ADC_DR_DATA_11            (0x0800UL << ADC_DR_DATA_Pos)                 /*!< 0x00000800 */
1074 #define ADC_DR_DATA_12            (0x1000UL << ADC_DR_DATA_Pos)                 /*!< 0x00001000 */
1075 #define ADC_DR_DATA_13            (0x2000UL << ADC_DR_DATA_Pos)                 /*!< 0x00002000 */
1076 #define ADC_DR_DATA_14            (0x4000UL << ADC_DR_DATA_Pos)                 /*!< 0x00004000 */
1077 #define ADC_DR_DATA_15            (0x8000UL << ADC_DR_DATA_Pos)                 /*!< 0x00008000 */
1078 
1079 /*************************  ADC Common registers  *****************************/
1080 /*******************  Bit definition for ADC_CCR register  ********************/
1081 #define ADC_CCR_VREFEN_Pos        (22U)
1082 #define ADC_CCR_VREFEN_Msk        (0x1UL << ADC_CCR_VREFEN_Pos)                 /*!< 0x00400000 */
1083 #define ADC_CCR_VREFEN            ADC_CCR_VREFEN_Msk                           /*!< ADC internal path to VrefInt enable */
1084 #define ADC_CCR_TSEN_Pos          (23U)
1085 #define ADC_CCR_TSEN_Msk          (0x1UL << ADC_CCR_TSEN_Pos)                   /*!< 0x00800000 */
1086 #define ADC_CCR_TSEN              ADC_CCR_TSEN_Msk                             /*!< ADC internal path to temperature sensor enable */
1087 
1088 #define ADC_CCR_VBATEN_Pos        (24U)
1089 #define ADC_CCR_VBATEN_Msk        (0x1UL << ADC_CCR_VBATEN_Pos)                 /*!< 0x01000000 */
1090 #define ADC_CCR_VBATEN            ADC_CCR_VBATEN_Msk                           /*!< ADC internal path to battery voltage enable */
1091 
1092 /******************************************************************************/
1093 /*                                                                            */
1094 /*                   Controller Area Network (CAN )                           */
1095 /*                                                                            */
1096 /******************************************************************************/
1097 /*!<CAN control and status registers */
1098 /*******************  Bit definition for CAN_MCR register  ********************/
1099 #define CAN_MCR_INRQ_Pos       (0U)
1100 #define CAN_MCR_INRQ_Msk       (0x1UL << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */
1101 #define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */
1102 #define CAN_MCR_SLEEP_Pos      (1U)
1103 #define CAN_MCR_SLEEP_Msk      (0x1UL << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */
1104 #define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */
1105 #define CAN_MCR_TXFP_Pos       (2U)
1106 #define CAN_MCR_TXFP_Msk       (0x1UL << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */
1107 #define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */
1108 #define CAN_MCR_RFLM_Pos       (3U)
1109 #define CAN_MCR_RFLM_Msk       (0x1UL << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */
1110 #define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */
1111 #define CAN_MCR_NART_Pos       (4U)
1112 #define CAN_MCR_NART_Msk       (0x1UL << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */
1113 #define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */
1114 #define CAN_MCR_AWUM_Pos       (5U)
1115 #define CAN_MCR_AWUM_Msk       (0x1UL << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */
1116 #define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */
1117 #define CAN_MCR_ABOM_Pos       (6U)
1118 #define CAN_MCR_ABOM_Msk       (0x1UL << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */
1119 #define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */
1120 #define CAN_MCR_TTCM_Pos       (7U)
1121 #define CAN_MCR_TTCM_Msk       (0x1UL << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */
1122 #define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */
1123 #define CAN_MCR_RESET_Pos      (15U)
1124 #define CAN_MCR_RESET_Msk      (0x1UL << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */
1125 #define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */
1126 
1127 /*******************  Bit definition for CAN_MSR register  ********************/
1128 #define CAN_MSR_INAK_Pos       (0U)
1129 #define CAN_MSR_INAK_Msk       (0x1UL << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */
1130 #define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */
1131 #define CAN_MSR_SLAK_Pos       (1U)
1132 #define CAN_MSR_SLAK_Msk       (0x1UL << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */
1133 #define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */
1134 #define CAN_MSR_ERRI_Pos       (2U)
1135 #define CAN_MSR_ERRI_Msk       (0x1UL << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */
1136 #define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */
1137 #define CAN_MSR_WKUI_Pos       (3U)
1138 #define CAN_MSR_WKUI_Msk       (0x1UL << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */
1139 #define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */
1140 #define CAN_MSR_SLAKI_Pos      (4U)
1141 #define CAN_MSR_SLAKI_Msk      (0x1UL << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */
1142 #define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */
1143 #define CAN_MSR_TXM_Pos        (8U)
1144 #define CAN_MSR_TXM_Msk        (0x1UL << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */
1145 #define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */
1146 #define CAN_MSR_RXM_Pos        (9U)
1147 #define CAN_MSR_RXM_Msk        (0x1UL << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */
1148 #define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */
1149 #define CAN_MSR_SAMP_Pos       (10U)
1150 #define CAN_MSR_SAMP_Msk       (0x1UL << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */
1151 #define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */
1152 #define CAN_MSR_RX_Pos         (11U)
1153 #define CAN_MSR_RX_Msk         (0x1UL << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */
1154 #define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */
1155 
1156 /*******************  Bit definition for CAN_TSR register  ********************/
1157 #define CAN_TSR_RQCP0_Pos      (0U)
1158 #define CAN_TSR_RQCP0_Msk      (0x1UL << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */
1159 #define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */
1160 #define CAN_TSR_TXOK0_Pos      (1U)
1161 #define CAN_TSR_TXOK0_Msk      (0x1UL << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */
1162 #define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */
1163 #define CAN_TSR_ALST0_Pos      (2U)
1164 #define CAN_TSR_ALST0_Msk      (0x1UL << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */
1165 #define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */
1166 #define CAN_TSR_TERR0_Pos      (3U)
1167 #define CAN_TSR_TERR0_Msk      (0x1UL << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */
1168 #define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */
1169 #define CAN_TSR_ABRQ0_Pos      (7U)
1170 #define CAN_TSR_ABRQ0_Msk      (0x1UL << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */
1171 #define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */
1172 #define CAN_TSR_RQCP1_Pos      (8U)
1173 #define CAN_TSR_RQCP1_Msk      (0x1UL << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */
1174 #define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */
1175 #define CAN_TSR_TXOK1_Pos      (9U)
1176 #define CAN_TSR_TXOK1_Msk      (0x1UL << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */
1177 #define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */
1178 #define CAN_TSR_ALST1_Pos      (10U)
1179 #define CAN_TSR_ALST1_Msk      (0x1UL << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */
1180 #define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */
1181 #define CAN_TSR_TERR1_Pos      (11U)
1182 #define CAN_TSR_TERR1_Msk      (0x1UL << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */
1183 #define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */
1184 #define CAN_TSR_ABRQ1_Pos      (15U)
1185 #define CAN_TSR_ABRQ1_Msk      (0x1UL << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */
1186 #define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */
1187 #define CAN_TSR_RQCP2_Pos      (16U)
1188 #define CAN_TSR_RQCP2_Msk      (0x1UL << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */
1189 #define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */
1190 #define CAN_TSR_TXOK2_Pos      (17U)
1191 #define CAN_TSR_TXOK2_Msk      (0x1UL << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */
1192 #define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */
1193 #define CAN_TSR_ALST2_Pos      (18U)
1194 #define CAN_TSR_ALST2_Msk      (0x1UL << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */
1195 #define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */
1196 #define CAN_TSR_TERR2_Pos      (19U)
1197 #define CAN_TSR_TERR2_Msk      (0x1UL << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */
1198 #define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */
1199 #define CAN_TSR_ABRQ2_Pos      (23U)
1200 #define CAN_TSR_ABRQ2_Msk      (0x1UL << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */
1201 #define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */
1202 #define CAN_TSR_CODE_Pos       (24U)
1203 #define CAN_TSR_CODE_Msk       (0x3UL << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */
1204 #define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */
1205 
1206 #define CAN_TSR_TME_Pos        (26U)
1207 #define CAN_TSR_TME_Msk        (0x7UL << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */
1208 #define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */
1209 #define CAN_TSR_TME0_Pos       (26U)
1210 #define CAN_TSR_TME0_Msk       (0x1UL << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */
1211 #define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */
1212 #define CAN_TSR_TME1_Pos       (27U)
1213 #define CAN_TSR_TME1_Msk       (0x1UL << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */
1214 #define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */
1215 #define CAN_TSR_TME2_Pos       (28U)
1216 #define CAN_TSR_TME2_Msk       (0x1UL << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */
1217 #define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */
1218 
1219 #define CAN_TSR_LOW_Pos        (29U)
1220 #define CAN_TSR_LOW_Msk        (0x7UL << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */
1221 #define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */
1222 #define CAN_TSR_LOW0_Pos       (29U)
1223 #define CAN_TSR_LOW0_Msk       (0x1UL << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */
1224 #define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */
1225 #define CAN_TSR_LOW1_Pos       (30U)
1226 #define CAN_TSR_LOW1_Msk       (0x1UL << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */
1227 #define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */
1228 #define CAN_TSR_LOW2_Pos       (31U)
1229 #define CAN_TSR_LOW2_Msk       (0x1UL << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */
1230 #define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */
1231 
1232 /*******************  Bit definition for CAN_RF0R register  *******************/
1233 #define CAN_RF0R_FMP0_Pos      (0U)
1234 #define CAN_RF0R_FMP0_Msk      (0x3UL << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */
1235 #define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */
1236 #define CAN_RF0R_FULL0_Pos     (3U)
1237 #define CAN_RF0R_FULL0_Msk     (0x1UL << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */
1238 #define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */
1239 #define CAN_RF0R_FOVR0_Pos     (4U)
1240 #define CAN_RF0R_FOVR0_Msk     (0x1UL << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */
1241 #define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */
1242 #define CAN_RF0R_RFOM0_Pos     (5U)
1243 #define CAN_RF0R_RFOM0_Msk     (0x1UL << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */
1244 #define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */
1245 
1246 /*******************  Bit definition for CAN_RF1R register  *******************/
1247 #define CAN_RF1R_FMP1_Pos      (0U)
1248 #define CAN_RF1R_FMP1_Msk      (0x3UL << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */
1249 #define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */
1250 #define CAN_RF1R_FULL1_Pos     (3U)
1251 #define CAN_RF1R_FULL1_Msk     (0x1UL << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */
1252 #define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */
1253 #define CAN_RF1R_FOVR1_Pos     (4U)
1254 #define CAN_RF1R_FOVR1_Msk     (0x1UL << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */
1255 #define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */
1256 #define CAN_RF1R_RFOM1_Pos     (5U)
1257 #define CAN_RF1R_RFOM1_Msk     (0x1UL << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */
1258 #define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */
1259 
1260 /********************  Bit definition for CAN_IER register  *******************/
1261 #define CAN_IER_TMEIE_Pos      (0U)
1262 #define CAN_IER_TMEIE_Msk      (0x1UL << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */
1263 #define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */
1264 #define CAN_IER_FMPIE0_Pos     (1U)
1265 #define CAN_IER_FMPIE0_Msk     (0x1UL << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */
1266 #define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */
1267 #define CAN_IER_FFIE0_Pos      (2U)
1268 #define CAN_IER_FFIE0_Msk      (0x1UL << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */
1269 #define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */
1270 #define CAN_IER_FOVIE0_Pos     (3U)
1271 #define CAN_IER_FOVIE0_Msk     (0x1UL << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */
1272 #define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */
1273 #define CAN_IER_FMPIE1_Pos     (4U)
1274 #define CAN_IER_FMPIE1_Msk     (0x1UL << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */
1275 #define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */
1276 #define CAN_IER_FFIE1_Pos      (5U)
1277 #define CAN_IER_FFIE1_Msk      (0x1UL << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */
1278 #define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */
1279 #define CAN_IER_FOVIE1_Pos     (6U)
1280 #define CAN_IER_FOVIE1_Msk     (0x1UL << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */
1281 #define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */
1282 #define CAN_IER_EWGIE_Pos      (8U)
1283 #define CAN_IER_EWGIE_Msk      (0x1UL << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */
1284 #define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */
1285 #define CAN_IER_EPVIE_Pos      (9U)
1286 #define CAN_IER_EPVIE_Msk      (0x1UL << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */
1287 #define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */
1288 #define CAN_IER_BOFIE_Pos      (10U)
1289 #define CAN_IER_BOFIE_Msk      (0x1UL << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */
1290 #define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */
1291 #define CAN_IER_LECIE_Pos      (11U)
1292 #define CAN_IER_LECIE_Msk      (0x1UL << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */
1293 #define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */
1294 #define CAN_IER_ERRIE_Pos      (15U)
1295 #define CAN_IER_ERRIE_Msk      (0x1UL << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */
1296 #define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */
1297 #define CAN_IER_WKUIE_Pos      (16U)
1298 #define CAN_IER_WKUIE_Msk      (0x1UL << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */
1299 #define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */
1300 #define CAN_IER_SLKIE_Pos      (17U)
1301 #define CAN_IER_SLKIE_Msk      (0x1UL << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */
1302 #define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */
1303 
1304 /********************  Bit definition for CAN_ESR register  *******************/
1305 #define CAN_ESR_EWGF_Pos       (0U)
1306 #define CAN_ESR_EWGF_Msk       (0x1UL << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */
1307 #define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */
1308 #define CAN_ESR_EPVF_Pos       (1U)
1309 #define CAN_ESR_EPVF_Msk       (0x1UL << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */
1310 #define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */
1311 #define CAN_ESR_BOFF_Pos       (2U)
1312 #define CAN_ESR_BOFF_Msk       (0x1UL << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */
1313 #define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */
1314 
1315 #define CAN_ESR_LEC_Pos        (4U)
1316 #define CAN_ESR_LEC_Msk        (0x7UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */
1317 #define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */
1318 #define CAN_ESR_LEC_0          (0x1UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */
1319 #define CAN_ESR_LEC_1          (0x2UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */
1320 #define CAN_ESR_LEC_2          (0x4UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */
1321 
1322 #define CAN_ESR_TEC_Pos        (16U)
1323 #define CAN_ESR_TEC_Msk        (0xFFUL << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */
1324 #define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */
1325 #define CAN_ESR_REC_Pos        (24U)
1326 #define CAN_ESR_REC_Msk        (0xFFUL << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */
1327 #define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */
1328 
1329 /*******************  Bit definition for CAN_BTR register  ********************/
1330 #define CAN_BTR_BRP_Pos        (0U)
1331 #define CAN_BTR_BRP_Msk        (0x3FFUL << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */
1332 #define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */
1333 #define CAN_BTR_TS1_Pos        (16U)
1334 #define CAN_BTR_TS1_Msk        (0xFUL << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */
1335 #define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */
1336 #define CAN_BTR_TS1_0          (0x1UL << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */
1337 #define CAN_BTR_TS1_1          (0x2UL << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */
1338 #define CAN_BTR_TS1_2          (0x4UL << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */
1339 #define CAN_BTR_TS1_3          (0x8UL << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */
1340 #define CAN_BTR_TS2_Pos        (20U)
1341 #define CAN_BTR_TS2_Msk        (0x7UL << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */
1342 #define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */
1343 #define CAN_BTR_TS2_0          (0x1UL << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */
1344 #define CAN_BTR_TS2_1          (0x2UL << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */
1345 #define CAN_BTR_TS2_2          (0x4UL << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */
1346 #define CAN_BTR_SJW_Pos        (24U)
1347 #define CAN_BTR_SJW_Msk        (0x3UL << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */
1348 #define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */
1349 #define CAN_BTR_SJW_0          (0x1UL << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */
1350 #define CAN_BTR_SJW_1          (0x2UL << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */
1351 #define CAN_BTR_LBKM_Pos       (30U)
1352 #define CAN_BTR_LBKM_Msk       (0x1UL << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */
1353 #define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */
1354 #define CAN_BTR_SILM_Pos       (31U)
1355 #define CAN_BTR_SILM_Msk       (0x1UL << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */
1356 #define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */
1357 
1358 /*!<Mailbox registers */
1359 /******************  Bit definition for CAN_TI0R register  ********************/
1360 #define CAN_TI0R_TXRQ_Pos      (0U)
1361 #define CAN_TI0R_TXRQ_Msk      (0x1UL << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */
1362 #define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
1363 #define CAN_TI0R_RTR_Pos       (1U)
1364 #define CAN_TI0R_RTR_Msk       (0x1UL << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */
1365 #define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */
1366 #define CAN_TI0R_IDE_Pos       (2U)
1367 #define CAN_TI0R_IDE_Msk       (0x1UL << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */
1368 #define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */
1369 #define CAN_TI0R_EXID_Pos      (3U)
1370 #define CAN_TI0R_EXID_Msk      (0x3FFFFUL << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
1371 #define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */
1372 #define CAN_TI0R_STID_Pos      (21U)
1373 #define CAN_TI0R_STID_Msk      (0x7FFUL << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */
1374 #define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
1375 
1376 /******************  Bit definition for CAN_TDT0R register  *******************/
1377 #define CAN_TDT0R_DLC_Pos      (0U)
1378 #define CAN_TDT0R_DLC_Msk      (0xFUL << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */
1379 #define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */
1380 #define CAN_TDT0R_TGT_Pos      (8U)
1381 #define CAN_TDT0R_TGT_Msk      (0x1UL << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */
1382 #define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */
1383 #define CAN_TDT0R_TIME_Pos     (16U)
1384 #define CAN_TDT0R_TIME_Msk     (0xFFFFUL << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
1385 #define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */
1386 
1387 /******************  Bit definition for CAN_TDL0R register  *******************/
1388 #define CAN_TDL0R_DATA0_Pos    (0U)
1389 #define CAN_TDL0R_DATA0_Msk    (0xFFUL << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */
1390 #define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */
1391 #define CAN_TDL0R_DATA1_Pos    (8U)
1392 #define CAN_TDL0R_DATA1_Msk    (0xFFUL << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
1393 #define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */
1394 #define CAN_TDL0R_DATA2_Pos    (16U)
1395 #define CAN_TDL0R_DATA2_Msk    (0xFFUL << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
1396 #define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */
1397 #define CAN_TDL0R_DATA3_Pos    (24U)
1398 #define CAN_TDL0R_DATA3_Msk    (0xFFUL << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
1399 #define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */
1400 
1401 /******************  Bit definition for CAN_TDH0R register  *******************/
1402 #define CAN_TDH0R_DATA4_Pos    (0U)
1403 #define CAN_TDH0R_DATA4_Msk    (0xFFUL << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */
1404 #define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */
1405 #define CAN_TDH0R_DATA5_Pos    (8U)
1406 #define CAN_TDH0R_DATA5_Msk    (0xFFUL << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
1407 #define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */
1408 #define CAN_TDH0R_DATA6_Pos    (16U)
1409 #define CAN_TDH0R_DATA6_Msk    (0xFFUL << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
1410 #define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */
1411 #define CAN_TDH0R_DATA7_Pos    (24U)
1412 #define CAN_TDH0R_DATA7_Msk    (0xFFUL << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
1413 #define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */
1414 
1415 /*******************  Bit definition for CAN_TI1R register  *******************/
1416 #define CAN_TI1R_TXRQ_Pos      (0U)
1417 #define CAN_TI1R_TXRQ_Msk      (0x1UL << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */
1418 #define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
1419 #define CAN_TI1R_RTR_Pos       (1U)
1420 #define CAN_TI1R_RTR_Msk       (0x1UL << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */
1421 #define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */
1422 #define CAN_TI1R_IDE_Pos       (2U)
1423 #define CAN_TI1R_IDE_Msk       (0x1UL << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */
1424 #define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */
1425 #define CAN_TI1R_EXID_Pos      (3U)
1426 #define CAN_TI1R_EXID_Msk      (0x3FFFFUL << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
1427 #define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */
1428 #define CAN_TI1R_STID_Pos      (21U)
1429 #define CAN_TI1R_STID_Msk      (0x7FFUL << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */
1430 #define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
1431 
1432 /*******************  Bit definition for CAN_TDT1R register  ******************/
1433 #define CAN_TDT1R_DLC_Pos      (0U)
1434 #define CAN_TDT1R_DLC_Msk      (0xFUL << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */
1435 #define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */
1436 #define CAN_TDT1R_TGT_Pos      (8U)
1437 #define CAN_TDT1R_TGT_Msk      (0x1UL << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */
1438 #define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */
1439 #define CAN_TDT1R_TIME_Pos     (16U)
1440 #define CAN_TDT1R_TIME_Msk     (0xFFFFUL << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
1441 #define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */
1442 
1443 /*******************  Bit definition for CAN_TDL1R register  ******************/
1444 #define CAN_TDL1R_DATA0_Pos    (0U)
1445 #define CAN_TDL1R_DATA0_Msk    (0xFFUL << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */
1446 #define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */
1447 #define CAN_TDL1R_DATA1_Pos    (8U)
1448 #define CAN_TDL1R_DATA1_Msk    (0xFFUL << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
1449 #define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */
1450 #define CAN_TDL1R_DATA2_Pos    (16U)
1451 #define CAN_TDL1R_DATA2_Msk    (0xFFUL << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
1452 #define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */
1453 #define CAN_TDL1R_DATA3_Pos    (24U)
1454 #define CAN_TDL1R_DATA3_Msk    (0xFFUL << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
1455 #define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */
1456 
1457 /*******************  Bit definition for CAN_TDH1R register  ******************/
1458 #define CAN_TDH1R_DATA4_Pos    (0U)
1459 #define CAN_TDH1R_DATA4_Msk    (0xFFUL << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */
1460 #define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */
1461 #define CAN_TDH1R_DATA5_Pos    (8U)
1462 #define CAN_TDH1R_DATA5_Msk    (0xFFUL << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
1463 #define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */
1464 #define CAN_TDH1R_DATA6_Pos    (16U)
1465 #define CAN_TDH1R_DATA6_Msk    (0xFFUL << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
1466 #define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */
1467 #define CAN_TDH1R_DATA7_Pos    (24U)
1468 #define CAN_TDH1R_DATA7_Msk    (0xFFUL << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
1469 #define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */
1470 
1471 /*******************  Bit definition for CAN_TI2R register  *******************/
1472 #define CAN_TI2R_TXRQ_Pos      (0U)
1473 #define CAN_TI2R_TXRQ_Msk      (0x1UL << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */
1474 #define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
1475 #define CAN_TI2R_RTR_Pos       (1U)
1476 #define CAN_TI2R_RTR_Msk       (0x1UL << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */
1477 #define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */
1478 #define CAN_TI2R_IDE_Pos       (2U)
1479 #define CAN_TI2R_IDE_Msk       (0x1UL << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */
1480 #define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */
1481 #define CAN_TI2R_EXID_Pos      (3U)
1482 #define CAN_TI2R_EXID_Msk      (0x3FFFFUL << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */
1483 #define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */
1484 #define CAN_TI2R_STID_Pos      (21U)
1485 #define CAN_TI2R_STID_Msk      (0x7FFUL << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */
1486 #define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
1487 
1488 /*******************  Bit definition for CAN_TDT2R register  ******************/
1489 #define CAN_TDT2R_DLC_Pos      (0U)
1490 #define CAN_TDT2R_DLC_Msk      (0xFUL << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */
1491 #define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */
1492 #define CAN_TDT2R_TGT_Pos      (8U)
1493 #define CAN_TDT2R_TGT_Msk      (0x1UL << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */
1494 #define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */
1495 #define CAN_TDT2R_TIME_Pos     (16U)
1496 #define CAN_TDT2R_TIME_Msk     (0xFFFFUL << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */
1497 #define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */
1498 
1499 /*******************  Bit definition for CAN_TDL2R register  ******************/
1500 #define CAN_TDL2R_DATA0_Pos    (0U)
1501 #define CAN_TDL2R_DATA0_Msk    (0xFFUL << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */
1502 #define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */
1503 #define CAN_TDL2R_DATA1_Pos    (8U)
1504 #define CAN_TDL2R_DATA1_Msk    (0xFFUL << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */
1505 #define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */
1506 #define CAN_TDL2R_DATA2_Pos    (16U)
1507 #define CAN_TDL2R_DATA2_Msk    (0xFFUL << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */
1508 #define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */
1509 #define CAN_TDL2R_DATA3_Pos    (24U)
1510 #define CAN_TDL2R_DATA3_Msk    (0xFFUL << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */
1511 #define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */
1512 
1513 /*******************  Bit definition for CAN_TDH2R register  ******************/
1514 #define CAN_TDH2R_DATA4_Pos    (0U)
1515 #define CAN_TDH2R_DATA4_Msk    (0xFFUL << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */
1516 #define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */
1517 #define CAN_TDH2R_DATA5_Pos    (8U)
1518 #define CAN_TDH2R_DATA5_Msk    (0xFFUL << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */
1519 #define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */
1520 #define CAN_TDH2R_DATA6_Pos    (16U)
1521 #define CAN_TDH2R_DATA6_Msk    (0xFFUL << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */
1522 #define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */
1523 #define CAN_TDH2R_DATA7_Pos    (24U)
1524 #define CAN_TDH2R_DATA7_Msk    (0xFFUL << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */
1525 #define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */
1526 
1527 /*******************  Bit definition for CAN_RI0R register  *******************/
1528 #define CAN_RI0R_RTR_Pos       (1U)
1529 #define CAN_RI0R_RTR_Msk       (0x1UL << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */
1530 #define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */
1531 #define CAN_RI0R_IDE_Pos       (2U)
1532 #define CAN_RI0R_IDE_Msk       (0x1UL << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */
1533 #define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */
1534 #define CAN_RI0R_EXID_Pos      (3U)
1535 #define CAN_RI0R_EXID_Msk      (0x3FFFFUL << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
1536 #define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */
1537 #define CAN_RI0R_STID_Pos      (21U)
1538 #define CAN_RI0R_STID_Msk      (0x7FFUL << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */
1539 #define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
1540 
1541 /*******************  Bit definition for CAN_RDT0R register  ******************/
1542 #define CAN_RDT0R_DLC_Pos      (0U)
1543 #define CAN_RDT0R_DLC_Msk      (0xFUL << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */
1544 #define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */
1545 #define CAN_RDT0R_FMI_Pos      (8U)
1546 #define CAN_RDT0R_FMI_Msk      (0xFFUL << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */
1547 #define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */
1548 #define CAN_RDT0R_TIME_Pos     (16U)
1549 #define CAN_RDT0R_TIME_Msk     (0xFFFFUL << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
1550 #define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */
1551 
1552 /*******************  Bit definition for CAN_RDL0R register  ******************/
1553 #define CAN_RDL0R_DATA0_Pos    (0U)
1554 #define CAN_RDL0R_DATA0_Msk    (0xFFUL << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */
1555 #define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */
1556 #define CAN_RDL0R_DATA1_Pos    (8U)
1557 #define CAN_RDL0R_DATA1_Msk    (0xFFUL << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
1558 #define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */
1559 #define CAN_RDL0R_DATA2_Pos    (16U)
1560 #define CAN_RDL0R_DATA2_Msk    (0xFFUL << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
1561 #define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */
1562 #define CAN_RDL0R_DATA3_Pos    (24U)
1563 #define CAN_RDL0R_DATA3_Msk    (0xFFUL << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
1564 #define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */
1565 
1566 /*******************  Bit definition for CAN_RDH0R register  ******************/
1567 #define CAN_RDH0R_DATA4_Pos    (0U)
1568 #define CAN_RDH0R_DATA4_Msk    (0xFFUL << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */
1569 #define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */
1570 #define CAN_RDH0R_DATA5_Pos    (8U)
1571 #define CAN_RDH0R_DATA5_Msk    (0xFFUL << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
1572 #define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */
1573 #define CAN_RDH0R_DATA6_Pos    (16U)
1574 #define CAN_RDH0R_DATA6_Msk    (0xFFUL << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
1575 #define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */
1576 #define CAN_RDH0R_DATA7_Pos    (24U)
1577 #define CAN_RDH0R_DATA7_Msk    (0xFFUL << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
1578 #define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */
1579 
1580 /*******************  Bit definition for CAN_RI1R register  *******************/
1581 #define CAN_RI1R_RTR_Pos       (1U)
1582 #define CAN_RI1R_RTR_Msk       (0x1UL << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */
1583 #define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */
1584 #define CAN_RI1R_IDE_Pos       (2U)
1585 #define CAN_RI1R_IDE_Msk       (0x1UL << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */
1586 #define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */
1587 #define CAN_RI1R_EXID_Pos      (3U)
1588 #define CAN_RI1R_EXID_Msk      (0x3FFFFUL << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
1589 #define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */
1590 #define CAN_RI1R_STID_Pos      (21U)
1591 #define CAN_RI1R_STID_Msk      (0x7FFUL << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */
1592 #define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
1593 
1594 /*******************  Bit definition for CAN_RDT1R register  ******************/
1595 #define CAN_RDT1R_DLC_Pos      (0U)
1596 #define CAN_RDT1R_DLC_Msk      (0xFUL << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */
1597 #define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */
1598 #define CAN_RDT1R_FMI_Pos      (8U)
1599 #define CAN_RDT1R_FMI_Msk      (0xFFUL << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */
1600 #define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */
1601 #define CAN_RDT1R_TIME_Pos     (16U)
1602 #define CAN_RDT1R_TIME_Msk     (0xFFFFUL << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
1603 #define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */
1604 
1605 /*******************  Bit definition for CAN_RDL1R register  ******************/
1606 #define CAN_RDL1R_DATA0_Pos    (0U)
1607 #define CAN_RDL1R_DATA0_Msk    (0xFFUL << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */
1608 #define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */
1609 #define CAN_RDL1R_DATA1_Pos    (8U)
1610 #define CAN_RDL1R_DATA1_Msk    (0xFFUL << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
1611 #define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */
1612 #define CAN_RDL1R_DATA2_Pos    (16U)
1613 #define CAN_RDL1R_DATA2_Msk    (0xFFUL << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
1614 #define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */
1615 #define CAN_RDL1R_DATA3_Pos    (24U)
1616 #define CAN_RDL1R_DATA3_Msk    (0xFFUL << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
1617 #define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */
1618 
1619 /*******************  Bit definition for CAN_RDH1R register  ******************/
1620 #define CAN_RDH1R_DATA4_Pos    (0U)
1621 #define CAN_RDH1R_DATA4_Msk    (0xFFUL << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */
1622 #define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */
1623 #define CAN_RDH1R_DATA5_Pos    (8U)
1624 #define CAN_RDH1R_DATA5_Msk    (0xFFUL << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
1625 #define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */
1626 #define CAN_RDH1R_DATA6_Pos    (16U)
1627 #define CAN_RDH1R_DATA6_Msk    (0xFFUL << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
1628 #define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */
1629 #define CAN_RDH1R_DATA7_Pos    (24U)
1630 #define CAN_RDH1R_DATA7_Msk    (0xFFUL << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
1631 #define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */
1632 
1633 /*!<CAN filter registers */
1634 /*******************  Bit definition for CAN_FMR register  ********************/
1635 #define CAN_FMR_FINIT_Pos      (0U)
1636 #define CAN_FMR_FINIT_Msk      (0x1UL << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */
1637 #define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */
1638 #define CAN_FMR_CAN2SB_Pos     (8U)
1639 #define CAN_FMR_CAN2SB_Msk     (0x3FUL << CAN_FMR_CAN2SB_Pos)                   /*!< 0x00003F00 */
1640 #define CAN_FMR_CAN2SB         CAN_FMR_CAN2SB_Msk                              /*!<CAN2 start bank */
1641 
1642 /*******************  Bit definition for CAN_FM1R register  *******************/
1643 #define CAN_FM1R_FBM_Pos       (0U)
1644 #define CAN_FM1R_FBM_Msk       (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)                /*!< 0x0FFFFFFF */
1645 #define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */
1646 #define CAN_FM1R_FBM0_Pos      (0U)
1647 #define CAN_FM1R_FBM0_Msk      (0x1UL << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */
1648 #define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */
1649 #define CAN_FM1R_FBM1_Pos      (1U)
1650 #define CAN_FM1R_FBM1_Msk      (0x1UL << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */
1651 #define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */
1652 #define CAN_FM1R_FBM2_Pos      (2U)
1653 #define CAN_FM1R_FBM2_Msk      (0x1UL << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */
1654 #define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */
1655 #define CAN_FM1R_FBM3_Pos      (3U)
1656 #define CAN_FM1R_FBM3_Msk      (0x1UL << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */
1657 #define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */
1658 #define CAN_FM1R_FBM4_Pos      (4U)
1659 #define CAN_FM1R_FBM4_Msk      (0x1UL << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */
1660 #define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */
1661 #define CAN_FM1R_FBM5_Pos      (5U)
1662 #define CAN_FM1R_FBM5_Msk      (0x1UL << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */
1663 #define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */
1664 #define CAN_FM1R_FBM6_Pos      (6U)
1665 #define CAN_FM1R_FBM6_Msk      (0x1UL << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */
1666 #define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */
1667 #define CAN_FM1R_FBM7_Pos      (7U)
1668 #define CAN_FM1R_FBM7_Msk      (0x1UL << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */
1669 #define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */
1670 #define CAN_FM1R_FBM8_Pos      (8U)
1671 #define CAN_FM1R_FBM8_Msk      (0x1UL << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */
1672 #define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */
1673 #define CAN_FM1R_FBM9_Pos      (9U)
1674 #define CAN_FM1R_FBM9_Msk      (0x1UL << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */
1675 #define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */
1676 #define CAN_FM1R_FBM10_Pos     (10U)
1677 #define CAN_FM1R_FBM10_Msk     (0x1UL << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */
1678 #define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */
1679 #define CAN_FM1R_FBM11_Pos     (11U)
1680 #define CAN_FM1R_FBM11_Msk     (0x1UL << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */
1681 #define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */
1682 #define CAN_FM1R_FBM12_Pos     (12U)
1683 #define CAN_FM1R_FBM12_Msk     (0x1UL << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */
1684 #define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */
1685 #define CAN_FM1R_FBM13_Pos     (13U)
1686 #define CAN_FM1R_FBM13_Msk     (0x1UL << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */
1687 #define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */
1688 
1689 /*******************  Bit definition for CAN_FS1R register  *******************/
1690 #define CAN_FS1R_FSC_Pos       (0U)
1691 #define CAN_FS1R_FSC_Msk       (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)                /*!< 0x0FFFFFFF */
1692 #define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */
1693 #define CAN_FS1R_FSC0_Pos      (0U)
1694 #define CAN_FS1R_FSC0_Msk      (0x1UL << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */
1695 #define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */
1696 #define CAN_FS1R_FSC1_Pos      (1U)
1697 #define CAN_FS1R_FSC1_Msk      (0x1UL << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */
1698 #define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */
1699 #define CAN_FS1R_FSC2_Pos      (2U)
1700 #define CAN_FS1R_FSC2_Msk      (0x1UL << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */
1701 #define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */
1702 #define CAN_FS1R_FSC3_Pos      (3U)
1703 #define CAN_FS1R_FSC3_Msk      (0x1UL << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */
1704 #define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */
1705 #define CAN_FS1R_FSC4_Pos      (4U)
1706 #define CAN_FS1R_FSC4_Msk      (0x1UL << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */
1707 #define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */
1708 #define CAN_FS1R_FSC5_Pos      (5U)
1709 #define CAN_FS1R_FSC5_Msk      (0x1UL << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */
1710 #define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */
1711 #define CAN_FS1R_FSC6_Pos      (6U)
1712 #define CAN_FS1R_FSC6_Msk      (0x1UL << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */
1713 #define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */
1714 #define CAN_FS1R_FSC7_Pos      (7U)
1715 #define CAN_FS1R_FSC7_Msk      (0x1UL << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */
1716 #define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */
1717 #define CAN_FS1R_FSC8_Pos      (8U)
1718 #define CAN_FS1R_FSC8_Msk      (0x1UL << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */
1719 #define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */
1720 #define CAN_FS1R_FSC9_Pos      (9U)
1721 #define CAN_FS1R_FSC9_Msk      (0x1UL << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */
1722 #define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */
1723 #define CAN_FS1R_FSC10_Pos     (10U)
1724 #define CAN_FS1R_FSC10_Msk     (0x1UL << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */
1725 #define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */
1726 #define CAN_FS1R_FSC11_Pos     (11U)
1727 #define CAN_FS1R_FSC11_Msk     (0x1UL << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */
1728 #define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */
1729 #define CAN_FS1R_FSC12_Pos     (12U)
1730 #define CAN_FS1R_FSC12_Msk     (0x1UL << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */
1731 #define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */
1732 #define CAN_FS1R_FSC13_Pos     (13U)
1733 #define CAN_FS1R_FSC13_Msk     (0x1UL << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */
1734 #define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */
1735 
1736 /******************  Bit definition for CAN_FFA1R register  *******************/
1737 #define CAN_FFA1R_FFA_Pos      (0U)
1738 #define CAN_FFA1R_FFA_Msk      (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)               /*!< 0x0FFFFFFF */
1739 #define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */
1740 #define CAN_FFA1R_FFA0_Pos     (0U)
1741 #define CAN_FFA1R_FFA0_Msk     (0x1UL << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */
1742 #define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment bit 0 */
1743 #define CAN_FFA1R_FFA1_Pos     (1U)
1744 #define CAN_FFA1R_FFA1_Msk     (0x1UL << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */
1745 #define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment bit 1 */
1746 #define CAN_FFA1R_FFA2_Pos     (2U)
1747 #define CAN_FFA1R_FFA2_Msk     (0x1UL << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */
1748 #define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment bit 2 */
1749 #define CAN_FFA1R_FFA3_Pos     (3U)
1750 #define CAN_FFA1R_FFA3_Msk     (0x1UL << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */
1751 #define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment bit 3 */
1752 #define CAN_FFA1R_FFA4_Pos     (4U)
1753 #define CAN_FFA1R_FFA4_Msk     (0x1UL << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */
1754 #define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment bit 4 */
1755 #define CAN_FFA1R_FFA5_Pos     (5U)
1756 #define CAN_FFA1R_FFA5_Msk     (0x1UL << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */
1757 #define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment bit 5 */
1758 #define CAN_FFA1R_FFA6_Pos     (6U)
1759 #define CAN_FFA1R_FFA6_Msk     (0x1UL << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */
1760 #define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment bit 6 */
1761 #define CAN_FFA1R_FFA7_Pos     (7U)
1762 #define CAN_FFA1R_FFA7_Msk     (0x1UL << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */
1763 #define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment bit 7 */
1764 #define CAN_FFA1R_FFA8_Pos     (8U)
1765 #define CAN_FFA1R_FFA8_Msk     (0x1UL << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */
1766 #define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment bit 8 */
1767 #define CAN_FFA1R_FFA9_Pos     (9U)
1768 #define CAN_FFA1R_FFA9_Msk     (0x1UL << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */
1769 #define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment bit 9 */
1770 #define CAN_FFA1R_FFA10_Pos    (10U)
1771 #define CAN_FFA1R_FFA10_Msk    (0x1UL << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */
1772 #define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment bit 10 */
1773 #define CAN_FFA1R_FFA11_Pos    (11U)
1774 #define CAN_FFA1R_FFA11_Msk    (0x1UL << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */
1775 #define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment bit 11 */
1776 #define CAN_FFA1R_FFA12_Pos    (12U)
1777 #define CAN_FFA1R_FFA12_Msk    (0x1UL << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */
1778 #define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment bit 12 */
1779 #define CAN_FFA1R_FFA13_Pos    (13U)
1780 #define CAN_FFA1R_FFA13_Msk    (0x1UL << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */
1781 #define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment bit 13 */
1782 
1783 /*******************  Bit definition for CAN_FA1R register  *******************/
1784 #define CAN_FA1R_FACT_Pos      (0U)
1785 #define CAN_FA1R_FACT_Msk      (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)               /*!< 0x0FFFFFFF */
1786 #define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */
1787 #define CAN_FA1R_FACT0_Pos     (0U)
1788 #define CAN_FA1R_FACT0_Msk     (0x1UL << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */
1789 #define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter Active bit 0 */
1790 #define CAN_FA1R_FACT1_Pos     (1U)
1791 #define CAN_FA1R_FACT1_Msk     (0x1UL << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */
1792 #define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter Active bit 1 */
1793 #define CAN_FA1R_FACT2_Pos     (2U)
1794 #define CAN_FA1R_FACT2_Msk     (0x1UL << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */
1795 #define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter Active bit 2 */
1796 #define CAN_FA1R_FACT3_Pos     (3U)
1797 #define CAN_FA1R_FACT3_Msk     (0x1UL << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */
1798 #define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter Active bit 3 */
1799 #define CAN_FA1R_FACT4_Pos     (4U)
1800 #define CAN_FA1R_FACT4_Msk     (0x1UL << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */
1801 #define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter Active bit 4 */
1802 #define CAN_FA1R_FACT5_Pos     (5U)
1803 #define CAN_FA1R_FACT5_Msk     (0x1UL << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */
1804 #define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter Active bit 5 */
1805 #define CAN_FA1R_FACT6_Pos     (6U)
1806 #define CAN_FA1R_FACT6_Msk     (0x1UL << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */
1807 #define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter Active bit 6 */
1808 #define CAN_FA1R_FACT7_Pos     (7U)
1809 #define CAN_FA1R_FACT7_Msk     (0x1UL << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */
1810 #define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter Active bit 7 */
1811 #define CAN_FA1R_FACT8_Pos     (8U)
1812 #define CAN_FA1R_FACT8_Msk     (0x1UL << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */
1813 #define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter Active bit 8 */
1814 #define CAN_FA1R_FACT9_Pos     (9U)
1815 #define CAN_FA1R_FACT9_Msk     (0x1UL << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */
1816 #define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter Active bit 9 */
1817 #define CAN_FA1R_FACT10_Pos    (10U)
1818 #define CAN_FA1R_FACT10_Msk    (0x1UL << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */
1819 #define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter Active bit 10 */
1820 #define CAN_FA1R_FACT11_Pos    (11U)
1821 #define CAN_FA1R_FACT11_Msk    (0x1UL << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */
1822 #define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter Active bit 11 */
1823 #define CAN_FA1R_FACT12_Pos    (12U)
1824 #define CAN_FA1R_FACT12_Msk    (0x1UL << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */
1825 #define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter Active bit 12 */
1826 #define CAN_FA1R_FACT13_Pos    (13U)
1827 #define CAN_FA1R_FACT13_Msk    (0x1UL << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */
1828 #define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter Active bit 13 */
1829 
1830 /*******************  Bit definition for CAN_F0R1 register  *******************/
1831 #define CAN_F0R1_FB0_Pos       (0U)
1832 #define CAN_F0R1_FB0_Msk       (0x1UL << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */
1833 #define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */
1834 #define CAN_F0R1_FB1_Pos       (1U)
1835 #define CAN_F0R1_FB1_Msk       (0x1UL << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */
1836 #define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */
1837 #define CAN_F0R1_FB2_Pos       (2U)
1838 #define CAN_F0R1_FB2_Msk       (0x1UL << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */
1839 #define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */
1840 #define CAN_F0R1_FB3_Pos       (3U)
1841 #define CAN_F0R1_FB3_Msk       (0x1UL << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */
1842 #define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */
1843 #define CAN_F0R1_FB4_Pos       (4U)
1844 #define CAN_F0R1_FB4_Msk       (0x1UL << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */
1845 #define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */
1846 #define CAN_F0R1_FB5_Pos       (5U)
1847 #define CAN_F0R1_FB5_Msk       (0x1UL << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */
1848 #define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */
1849 #define CAN_F0R1_FB6_Pos       (6U)
1850 #define CAN_F0R1_FB6_Msk       (0x1UL << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */
1851 #define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */
1852 #define CAN_F0R1_FB7_Pos       (7U)
1853 #define CAN_F0R1_FB7_Msk       (0x1UL << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */
1854 #define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */
1855 #define CAN_F0R1_FB8_Pos       (8U)
1856 #define CAN_F0R1_FB8_Msk       (0x1UL << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */
1857 #define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */
1858 #define CAN_F0R1_FB9_Pos       (9U)
1859 #define CAN_F0R1_FB9_Msk       (0x1UL << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */
1860 #define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */
1861 #define CAN_F0R1_FB10_Pos      (10U)
1862 #define CAN_F0R1_FB10_Msk      (0x1UL << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */
1863 #define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */
1864 #define CAN_F0R1_FB11_Pos      (11U)
1865 #define CAN_F0R1_FB11_Msk      (0x1UL << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */
1866 #define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */
1867 #define CAN_F0R1_FB12_Pos      (12U)
1868 #define CAN_F0R1_FB12_Msk      (0x1UL << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */
1869 #define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */
1870 #define CAN_F0R1_FB13_Pos      (13U)
1871 #define CAN_F0R1_FB13_Msk      (0x1UL << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */
1872 #define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */
1873 #define CAN_F0R1_FB14_Pos      (14U)
1874 #define CAN_F0R1_FB14_Msk      (0x1UL << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */
1875 #define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */
1876 #define CAN_F0R1_FB15_Pos      (15U)
1877 #define CAN_F0R1_FB15_Msk      (0x1UL << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */
1878 #define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */
1879 #define CAN_F0R1_FB16_Pos      (16U)
1880 #define CAN_F0R1_FB16_Msk      (0x1UL << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */
1881 #define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */
1882 #define CAN_F0R1_FB17_Pos      (17U)
1883 #define CAN_F0R1_FB17_Msk      (0x1UL << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */
1884 #define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */
1885 #define CAN_F0R1_FB18_Pos      (18U)
1886 #define CAN_F0R1_FB18_Msk      (0x1UL << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */
1887 #define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */
1888 #define CAN_F0R1_FB19_Pos      (19U)
1889 #define CAN_F0R1_FB19_Msk      (0x1UL << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */
1890 #define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */
1891 #define CAN_F0R1_FB20_Pos      (20U)
1892 #define CAN_F0R1_FB20_Msk      (0x1UL << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */
1893 #define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */
1894 #define CAN_F0R1_FB21_Pos      (21U)
1895 #define CAN_F0R1_FB21_Msk      (0x1UL << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */
1896 #define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */
1897 #define CAN_F0R1_FB22_Pos      (22U)
1898 #define CAN_F0R1_FB22_Msk      (0x1UL << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */
1899 #define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */
1900 #define CAN_F0R1_FB23_Pos      (23U)
1901 #define CAN_F0R1_FB23_Msk      (0x1UL << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */
1902 #define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */
1903 #define CAN_F0R1_FB24_Pos      (24U)
1904 #define CAN_F0R1_FB24_Msk      (0x1UL << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */
1905 #define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */
1906 #define CAN_F0R1_FB25_Pos      (25U)
1907 #define CAN_F0R1_FB25_Msk      (0x1UL << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */
1908 #define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */
1909 #define CAN_F0R1_FB26_Pos      (26U)
1910 #define CAN_F0R1_FB26_Msk      (0x1UL << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */
1911 #define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */
1912 #define CAN_F0R1_FB27_Pos      (27U)
1913 #define CAN_F0R1_FB27_Msk      (0x1UL << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */
1914 #define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */
1915 #define CAN_F0R1_FB28_Pos      (28U)
1916 #define CAN_F0R1_FB28_Msk      (0x1UL << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */
1917 #define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */
1918 #define CAN_F0R1_FB29_Pos      (29U)
1919 #define CAN_F0R1_FB29_Msk      (0x1UL << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */
1920 #define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */
1921 #define CAN_F0R1_FB30_Pos      (30U)
1922 #define CAN_F0R1_FB30_Msk      (0x1UL << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */
1923 #define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */
1924 #define CAN_F0R1_FB31_Pos      (31U)
1925 #define CAN_F0R1_FB31_Msk      (0x1UL << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */
1926 #define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */
1927 
1928 /*******************  Bit definition for CAN_F1R1 register  *******************/
1929 #define CAN_F1R1_FB0_Pos       (0U)
1930 #define CAN_F1R1_FB0_Msk       (0x1UL << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */
1931 #define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */
1932 #define CAN_F1R1_FB1_Pos       (1U)
1933 #define CAN_F1R1_FB1_Msk       (0x1UL << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */
1934 #define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */
1935 #define CAN_F1R1_FB2_Pos       (2U)
1936 #define CAN_F1R1_FB2_Msk       (0x1UL << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */
1937 #define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */
1938 #define CAN_F1R1_FB3_Pos       (3U)
1939 #define CAN_F1R1_FB3_Msk       (0x1UL << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */
1940 #define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */
1941 #define CAN_F1R1_FB4_Pos       (4U)
1942 #define CAN_F1R1_FB4_Msk       (0x1UL << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */
1943 #define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */
1944 #define CAN_F1R1_FB5_Pos       (5U)
1945 #define CAN_F1R1_FB5_Msk       (0x1UL << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */
1946 #define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */
1947 #define CAN_F1R1_FB6_Pos       (6U)
1948 #define CAN_F1R1_FB6_Msk       (0x1UL << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */
1949 #define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */
1950 #define CAN_F1R1_FB7_Pos       (7U)
1951 #define CAN_F1R1_FB7_Msk       (0x1UL << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */
1952 #define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */
1953 #define CAN_F1R1_FB8_Pos       (8U)
1954 #define CAN_F1R1_FB8_Msk       (0x1UL << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */
1955 #define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */
1956 #define CAN_F1R1_FB9_Pos       (9U)
1957 #define CAN_F1R1_FB9_Msk       (0x1UL << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */
1958 #define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */
1959 #define CAN_F1R1_FB10_Pos      (10U)
1960 #define CAN_F1R1_FB10_Msk      (0x1UL << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */
1961 #define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */
1962 #define CAN_F1R1_FB11_Pos      (11U)
1963 #define CAN_F1R1_FB11_Msk      (0x1UL << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */
1964 #define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */
1965 #define CAN_F1R1_FB12_Pos      (12U)
1966 #define CAN_F1R1_FB12_Msk      (0x1UL << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */
1967 #define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */
1968 #define CAN_F1R1_FB13_Pos      (13U)
1969 #define CAN_F1R1_FB13_Msk      (0x1UL << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */
1970 #define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */
1971 #define CAN_F1R1_FB14_Pos      (14U)
1972 #define CAN_F1R1_FB14_Msk      (0x1UL << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */
1973 #define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */
1974 #define CAN_F1R1_FB15_Pos      (15U)
1975 #define CAN_F1R1_FB15_Msk      (0x1UL << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */
1976 #define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */
1977 #define CAN_F1R1_FB16_Pos      (16U)
1978 #define CAN_F1R1_FB16_Msk      (0x1UL << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */
1979 #define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */
1980 #define CAN_F1R1_FB17_Pos      (17U)
1981 #define CAN_F1R1_FB17_Msk      (0x1UL << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */
1982 #define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */
1983 #define CAN_F1R1_FB18_Pos      (18U)
1984 #define CAN_F1R1_FB18_Msk      (0x1UL << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */
1985 #define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */
1986 #define CAN_F1R1_FB19_Pos      (19U)
1987 #define CAN_F1R1_FB19_Msk      (0x1UL << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */
1988 #define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */
1989 #define CAN_F1R1_FB20_Pos      (20U)
1990 #define CAN_F1R1_FB20_Msk      (0x1UL << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */
1991 #define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */
1992 #define CAN_F1R1_FB21_Pos      (21U)
1993 #define CAN_F1R1_FB21_Msk      (0x1UL << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */
1994 #define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */
1995 #define CAN_F1R1_FB22_Pos      (22U)
1996 #define CAN_F1R1_FB22_Msk      (0x1UL << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */
1997 #define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */
1998 #define CAN_F1R1_FB23_Pos      (23U)
1999 #define CAN_F1R1_FB23_Msk      (0x1UL << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */
2000 #define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */
2001 #define CAN_F1R1_FB24_Pos      (24U)
2002 #define CAN_F1R1_FB24_Msk      (0x1UL << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */
2003 #define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */
2004 #define CAN_F1R1_FB25_Pos      (25U)
2005 #define CAN_F1R1_FB25_Msk      (0x1UL << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */
2006 #define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */
2007 #define CAN_F1R1_FB26_Pos      (26U)
2008 #define CAN_F1R1_FB26_Msk      (0x1UL << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */
2009 #define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */
2010 #define CAN_F1R1_FB27_Pos      (27U)
2011 #define CAN_F1R1_FB27_Msk      (0x1UL << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */
2012 #define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */
2013 #define CAN_F1R1_FB28_Pos      (28U)
2014 #define CAN_F1R1_FB28_Msk      (0x1UL << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */
2015 #define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */
2016 #define CAN_F1R1_FB29_Pos      (29U)
2017 #define CAN_F1R1_FB29_Msk      (0x1UL << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */
2018 #define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */
2019 #define CAN_F1R1_FB30_Pos      (30U)
2020 #define CAN_F1R1_FB30_Msk      (0x1UL << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */
2021 #define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */
2022 #define CAN_F1R1_FB31_Pos      (31U)
2023 #define CAN_F1R1_FB31_Msk      (0x1UL << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */
2024 #define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */
2025 
2026 /*******************  Bit definition for CAN_F2R1 register  *******************/
2027 #define CAN_F2R1_FB0_Pos       (0U)
2028 #define CAN_F2R1_FB0_Msk       (0x1UL << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */
2029 #define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */
2030 #define CAN_F2R1_FB1_Pos       (1U)
2031 #define CAN_F2R1_FB1_Msk       (0x1UL << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */
2032 #define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */
2033 #define CAN_F2R1_FB2_Pos       (2U)
2034 #define CAN_F2R1_FB2_Msk       (0x1UL << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */
2035 #define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */
2036 #define CAN_F2R1_FB3_Pos       (3U)
2037 #define CAN_F2R1_FB3_Msk       (0x1UL << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */
2038 #define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */
2039 #define CAN_F2R1_FB4_Pos       (4U)
2040 #define CAN_F2R1_FB4_Msk       (0x1UL << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */
2041 #define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */
2042 #define CAN_F2R1_FB5_Pos       (5U)
2043 #define CAN_F2R1_FB5_Msk       (0x1UL << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */
2044 #define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */
2045 #define CAN_F2R1_FB6_Pos       (6U)
2046 #define CAN_F2R1_FB6_Msk       (0x1UL << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */
2047 #define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */
2048 #define CAN_F2R1_FB7_Pos       (7U)
2049 #define CAN_F2R1_FB7_Msk       (0x1UL << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */
2050 #define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */
2051 #define CAN_F2R1_FB8_Pos       (8U)
2052 #define CAN_F2R1_FB8_Msk       (0x1UL << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */
2053 #define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */
2054 #define CAN_F2R1_FB9_Pos       (9U)
2055 #define CAN_F2R1_FB9_Msk       (0x1UL << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */
2056 #define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */
2057 #define CAN_F2R1_FB10_Pos      (10U)
2058 #define CAN_F2R1_FB10_Msk      (0x1UL << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */
2059 #define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */
2060 #define CAN_F2R1_FB11_Pos      (11U)
2061 #define CAN_F2R1_FB11_Msk      (0x1UL << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */
2062 #define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */
2063 #define CAN_F2R1_FB12_Pos      (12U)
2064 #define CAN_F2R1_FB12_Msk      (0x1UL << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */
2065 #define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */
2066 #define CAN_F2R1_FB13_Pos      (13U)
2067 #define CAN_F2R1_FB13_Msk      (0x1UL << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */
2068 #define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */
2069 #define CAN_F2R1_FB14_Pos      (14U)
2070 #define CAN_F2R1_FB14_Msk      (0x1UL << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */
2071 #define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */
2072 #define CAN_F2R1_FB15_Pos      (15U)
2073 #define CAN_F2R1_FB15_Msk      (0x1UL << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */
2074 #define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */
2075 #define CAN_F2R1_FB16_Pos      (16U)
2076 #define CAN_F2R1_FB16_Msk      (0x1UL << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */
2077 #define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */
2078 #define CAN_F2R1_FB17_Pos      (17U)
2079 #define CAN_F2R1_FB17_Msk      (0x1UL << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */
2080 #define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */
2081 #define CAN_F2R1_FB18_Pos      (18U)
2082 #define CAN_F2R1_FB18_Msk      (0x1UL << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */
2083 #define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */
2084 #define CAN_F2R1_FB19_Pos      (19U)
2085 #define CAN_F2R1_FB19_Msk      (0x1UL << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */
2086 #define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */
2087 #define CAN_F2R1_FB20_Pos      (20U)
2088 #define CAN_F2R1_FB20_Msk      (0x1UL << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */
2089 #define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */
2090 #define CAN_F2R1_FB21_Pos      (21U)
2091 #define CAN_F2R1_FB21_Msk      (0x1UL << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */
2092 #define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */
2093 #define CAN_F2R1_FB22_Pos      (22U)
2094 #define CAN_F2R1_FB22_Msk      (0x1UL << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */
2095 #define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */
2096 #define CAN_F2R1_FB23_Pos      (23U)
2097 #define CAN_F2R1_FB23_Msk      (0x1UL << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */
2098 #define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */
2099 #define CAN_F2R1_FB24_Pos      (24U)
2100 #define CAN_F2R1_FB24_Msk      (0x1UL << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */
2101 #define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */
2102 #define CAN_F2R1_FB25_Pos      (25U)
2103 #define CAN_F2R1_FB25_Msk      (0x1UL << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */
2104 #define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */
2105 #define CAN_F2R1_FB26_Pos      (26U)
2106 #define CAN_F2R1_FB26_Msk      (0x1UL << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */
2107 #define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */
2108 #define CAN_F2R1_FB27_Pos      (27U)
2109 #define CAN_F2R1_FB27_Msk      (0x1UL << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */
2110 #define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */
2111 #define CAN_F2R1_FB28_Pos      (28U)
2112 #define CAN_F2R1_FB28_Msk      (0x1UL << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */
2113 #define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */
2114 #define CAN_F2R1_FB29_Pos      (29U)
2115 #define CAN_F2R1_FB29_Msk      (0x1UL << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */
2116 #define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */
2117 #define CAN_F2R1_FB30_Pos      (30U)
2118 #define CAN_F2R1_FB30_Msk      (0x1UL << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */
2119 #define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */
2120 #define CAN_F2R1_FB31_Pos      (31U)
2121 #define CAN_F2R1_FB31_Msk      (0x1UL << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */
2122 #define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */
2123 
2124 /*******************  Bit definition for CAN_F3R1 register  *******************/
2125 #define CAN_F3R1_FB0_Pos       (0U)
2126 #define CAN_F3R1_FB0_Msk       (0x1UL << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */
2127 #define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */
2128 #define CAN_F3R1_FB1_Pos       (1U)
2129 #define CAN_F3R1_FB1_Msk       (0x1UL << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */
2130 #define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */
2131 #define CAN_F3R1_FB2_Pos       (2U)
2132 #define CAN_F3R1_FB2_Msk       (0x1UL << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */
2133 #define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */
2134 #define CAN_F3R1_FB3_Pos       (3U)
2135 #define CAN_F3R1_FB3_Msk       (0x1UL << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */
2136 #define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */
2137 #define CAN_F3R1_FB4_Pos       (4U)
2138 #define CAN_F3R1_FB4_Msk       (0x1UL << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */
2139 #define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */
2140 #define CAN_F3R1_FB5_Pos       (5U)
2141 #define CAN_F3R1_FB5_Msk       (0x1UL << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */
2142 #define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */
2143 #define CAN_F3R1_FB6_Pos       (6U)
2144 #define CAN_F3R1_FB6_Msk       (0x1UL << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */
2145 #define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */
2146 #define CAN_F3R1_FB7_Pos       (7U)
2147 #define CAN_F3R1_FB7_Msk       (0x1UL << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */
2148 #define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */
2149 #define CAN_F3R1_FB8_Pos       (8U)
2150 #define CAN_F3R1_FB8_Msk       (0x1UL << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */
2151 #define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */
2152 #define CAN_F3R1_FB9_Pos       (9U)
2153 #define CAN_F3R1_FB9_Msk       (0x1UL << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */
2154 #define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */
2155 #define CAN_F3R1_FB10_Pos      (10U)
2156 #define CAN_F3R1_FB10_Msk      (0x1UL << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */
2157 #define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */
2158 #define CAN_F3R1_FB11_Pos      (11U)
2159 #define CAN_F3R1_FB11_Msk      (0x1UL << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */
2160 #define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */
2161 #define CAN_F3R1_FB12_Pos      (12U)
2162 #define CAN_F3R1_FB12_Msk      (0x1UL << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */
2163 #define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */
2164 #define CAN_F3R1_FB13_Pos      (13U)
2165 #define CAN_F3R1_FB13_Msk      (0x1UL << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */
2166 #define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */
2167 #define CAN_F3R1_FB14_Pos      (14U)
2168 #define CAN_F3R1_FB14_Msk      (0x1UL << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */
2169 #define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */
2170 #define CAN_F3R1_FB15_Pos      (15U)
2171 #define CAN_F3R1_FB15_Msk      (0x1UL << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */
2172 #define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */
2173 #define CAN_F3R1_FB16_Pos      (16U)
2174 #define CAN_F3R1_FB16_Msk      (0x1UL << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */
2175 #define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */
2176 #define CAN_F3R1_FB17_Pos      (17U)
2177 #define CAN_F3R1_FB17_Msk      (0x1UL << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */
2178 #define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */
2179 #define CAN_F3R1_FB18_Pos      (18U)
2180 #define CAN_F3R1_FB18_Msk      (0x1UL << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */
2181 #define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */
2182 #define CAN_F3R1_FB19_Pos      (19U)
2183 #define CAN_F3R1_FB19_Msk      (0x1UL << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */
2184 #define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */
2185 #define CAN_F3R1_FB20_Pos      (20U)
2186 #define CAN_F3R1_FB20_Msk      (0x1UL << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */
2187 #define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */
2188 #define CAN_F3R1_FB21_Pos      (21U)
2189 #define CAN_F3R1_FB21_Msk      (0x1UL << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */
2190 #define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */
2191 #define CAN_F3R1_FB22_Pos      (22U)
2192 #define CAN_F3R1_FB22_Msk      (0x1UL << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */
2193 #define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */
2194 #define CAN_F3R1_FB23_Pos      (23U)
2195 #define CAN_F3R1_FB23_Msk      (0x1UL << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */
2196 #define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */
2197 #define CAN_F3R1_FB24_Pos      (24U)
2198 #define CAN_F3R1_FB24_Msk      (0x1UL << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */
2199 #define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */
2200 #define CAN_F3R1_FB25_Pos      (25U)
2201 #define CAN_F3R1_FB25_Msk      (0x1UL << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */
2202 #define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */
2203 #define CAN_F3R1_FB26_Pos      (26U)
2204 #define CAN_F3R1_FB26_Msk      (0x1UL << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */
2205 #define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */
2206 #define CAN_F3R1_FB27_Pos      (27U)
2207 #define CAN_F3R1_FB27_Msk      (0x1UL << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */
2208 #define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */
2209 #define CAN_F3R1_FB28_Pos      (28U)
2210 #define CAN_F3R1_FB28_Msk      (0x1UL << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */
2211 #define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */
2212 #define CAN_F3R1_FB29_Pos      (29U)
2213 #define CAN_F3R1_FB29_Msk      (0x1UL << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */
2214 #define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */
2215 #define CAN_F3R1_FB30_Pos      (30U)
2216 #define CAN_F3R1_FB30_Msk      (0x1UL << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */
2217 #define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */
2218 #define CAN_F3R1_FB31_Pos      (31U)
2219 #define CAN_F3R1_FB31_Msk      (0x1UL << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */
2220 #define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */
2221 
2222 /*******************  Bit definition for CAN_F4R1 register  *******************/
2223 #define CAN_F4R1_FB0_Pos       (0U)
2224 #define CAN_F4R1_FB0_Msk       (0x1UL << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */
2225 #define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */
2226 #define CAN_F4R1_FB1_Pos       (1U)
2227 #define CAN_F4R1_FB1_Msk       (0x1UL << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */
2228 #define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */
2229 #define CAN_F4R1_FB2_Pos       (2U)
2230 #define CAN_F4R1_FB2_Msk       (0x1UL << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */
2231 #define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */
2232 #define CAN_F4R1_FB3_Pos       (3U)
2233 #define CAN_F4R1_FB3_Msk       (0x1UL << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */
2234 #define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */
2235 #define CAN_F4R1_FB4_Pos       (4U)
2236 #define CAN_F4R1_FB4_Msk       (0x1UL << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */
2237 #define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */
2238 #define CAN_F4R1_FB5_Pos       (5U)
2239 #define CAN_F4R1_FB5_Msk       (0x1UL << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */
2240 #define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */
2241 #define CAN_F4R1_FB6_Pos       (6U)
2242 #define CAN_F4R1_FB6_Msk       (0x1UL << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */
2243 #define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */
2244 #define CAN_F4R1_FB7_Pos       (7U)
2245 #define CAN_F4R1_FB7_Msk       (0x1UL << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */
2246 #define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */
2247 #define CAN_F4R1_FB8_Pos       (8U)
2248 #define CAN_F4R1_FB8_Msk       (0x1UL << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */
2249 #define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */
2250 #define CAN_F4R1_FB9_Pos       (9U)
2251 #define CAN_F4R1_FB9_Msk       (0x1UL << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */
2252 #define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */
2253 #define CAN_F4R1_FB10_Pos      (10U)
2254 #define CAN_F4R1_FB10_Msk      (0x1UL << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */
2255 #define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */
2256 #define CAN_F4R1_FB11_Pos      (11U)
2257 #define CAN_F4R1_FB11_Msk      (0x1UL << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */
2258 #define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */
2259 #define CAN_F4R1_FB12_Pos      (12U)
2260 #define CAN_F4R1_FB12_Msk      (0x1UL << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */
2261 #define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */
2262 #define CAN_F4R1_FB13_Pos      (13U)
2263 #define CAN_F4R1_FB13_Msk      (0x1UL << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */
2264 #define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */
2265 #define CAN_F4R1_FB14_Pos      (14U)
2266 #define CAN_F4R1_FB14_Msk      (0x1UL << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */
2267 #define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */
2268 #define CAN_F4R1_FB15_Pos      (15U)
2269 #define CAN_F4R1_FB15_Msk      (0x1UL << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */
2270 #define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */
2271 #define CAN_F4R1_FB16_Pos      (16U)
2272 #define CAN_F4R1_FB16_Msk      (0x1UL << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */
2273 #define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */
2274 #define CAN_F4R1_FB17_Pos      (17U)
2275 #define CAN_F4R1_FB17_Msk      (0x1UL << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */
2276 #define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */
2277 #define CAN_F4R1_FB18_Pos      (18U)
2278 #define CAN_F4R1_FB18_Msk      (0x1UL << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */
2279 #define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */
2280 #define CAN_F4R1_FB19_Pos      (19U)
2281 #define CAN_F4R1_FB19_Msk      (0x1UL << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */
2282 #define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */
2283 #define CAN_F4R1_FB20_Pos      (20U)
2284 #define CAN_F4R1_FB20_Msk      (0x1UL << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */
2285 #define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */
2286 #define CAN_F4R1_FB21_Pos      (21U)
2287 #define CAN_F4R1_FB21_Msk      (0x1UL << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */
2288 #define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */
2289 #define CAN_F4R1_FB22_Pos      (22U)
2290 #define CAN_F4R1_FB22_Msk      (0x1UL << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */
2291 #define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */
2292 #define CAN_F4R1_FB23_Pos      (23U)
2293 #define CAN_F4R1_FB23_Msk      (0x1UL << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */
2294 #define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */
2295 #define CAN_F4R1_FB24_Pos      (24U)
2296 #define CAN_F4R1_FB24_Msk      (0x1UL << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */
2297 #define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */
2298 #define CAN_F4R1_FB25_Pos      (25U)
2299 #define CAN_F4R1_FB25_Msk      (0x1UL << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */
2300 #define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */
2301 #define CAN_F4R1_FB26_Pos      (26U)
2302 #define CAN_F4R1_FB26_Msk      (0x1UL << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */
2303 #define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */
2304 #define CAN_F4R1_FB27_Pos      (27U)
2305 #define CAN_F4R1_FB27_Msk      (0x1UL << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */
2306 #define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */
2307 #define CAN_F4R1_FB28_Pos      (28U)
2308 #define CAN_F4R1_FB28_Msk      (0x1UL << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */
2309 #define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */
2310 #define CAN_F4R1_FB29_Pos      (29U)
2311 #define CAN_F4R1_FB29_Msk      (0x1UL << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */
2312 #define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */
2313 #define CAN_F4R1_FB30_Pos      (30U)
2314 #define CAN_F4R1_FB30_Msk      (0x1UL << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */
2315 #define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */
2316 #define CAN_F4R1_FB31_Pos      (31U)
2317 #define CAN_F4R1_FB31_Msk      (0x1UL << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */
2318 #define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */
2319 
2320 /*******************  Bit definition for CAN_F5R1 register  *******************/
2321 #define CAN_F5R1_FB0_Pos       (0U)
2322 #define CAN_F5R1_FB0_Msk       (0x1UL << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */
2323 #define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */
2324 #define CAN_F5R1_FB1_Pos       (1U)
2325 #define CAN_F5R1_FB1_Msk       (0x1UL << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */
2326 #define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */
2327 #define CAN_F5R1_FB2_Pos       (2U)
2328 #define CAN_F5R1_FB2_Msk       (0x1UL << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */
2329 #define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */
2330 #define CAN_F5R1_FB3_Pos       (3U)
2331 #define CAN_F5R1_FB3_Msk       (0x1UL << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */
2332 #define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */
2333 #define CAN_F5R1_FB4_Pos       (4U)
2334 #define CAN_F5R1_FB4_Msk       (0x1UL << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */
2335 #define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */
2336 #define CAN_F5R1_FB5_Pos       (5U)
2337 #define CAN_F5R1_FB5_Msk       (0x1UL << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */
2338 #define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */
2339 #define CAN_F5R1_FB6_Pos       (6U)
2340 #define CAN_F5R1_FB6_Msk       (0x1UL << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */
2341 #define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */
2342 #define CAN_F5R1_FB7_Pos       (7U)
2343 #define CAN_F5R1_FB7_Msk       (0x1UL << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */
2344 #define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */
2345 #define CAN_F5R1_FB8_Pos       (8U)
2346 #define CAN_F5R1_FB8_Msk       (0x1UL << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */
2347 #define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */
2348 #define CAN_F5R1_FB9_Pos       (9U)
2349 #define CAN_F5R1_FB9_Msk       (0x1UL << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */
2350 #define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */
2351 #define CAN_F5R1_FB10_Pos      (10U)
2352 #define CAN_F5R1_FB10_Msk      (0x1UL << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */
2353 #define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */
2354 #define CAN_F5R1_FB11_Pos      (11U)
2355 #define CAN_F5R1_FB11_Msk      (0x1UL << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */
2356 #define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */
2357 #define CAN_F5R1_FB12_Pos      (12U)
2358 #define CAN_F5R1_FB12_Msk      (0x1UL << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */
2359 #define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */
2360 #define CAN_F5R1_FB13_Pos      (13U)
2361 #define CAN_F5R1_FB13_Msk      (0x1UL << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */
2362 #define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */
2363 #define CAN_F5R1_FB14_Pos      (14U)
2364 #define CAN_F5R1_FB14_Msk      (0x1UL << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */
2365 #define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */
2366 #define CAN_F5R1_FB15_Pos      (15U)
2367 #define CAN_F5R1_FB15_Msk      (0x1UL << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */
2368 #define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */
2369 #define CAN_F5R1_FB16_Pos      (16U)
2370 #define CAN_F5R1_FB16_Msk      (0x1UL << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */
2371 #define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */
2372 #define CAN_F5R1_FB17_Pos      (17U)
2373 #define CAN_F5R1_FB17_Msk      (0x1UL << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */
2374 #define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */
2375 #define CAN_F5R1_FB18_Pos      (18U)
2376 #define CAN_F5R1_FB18_Msk      (0x1UL << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */
2377 #define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */
2378 #define CAN_F5R1_FB19_Pos      (19U)
2379 #define CAN_F5R1_FB19_Msk      (0x1UL << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */
2380 #define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */
2381 #define CAN_F5R1_FB20_Pos      (20U)
2382 #define CAN_F5R1_FB20_Msk      (0x1UL << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */
2383 #define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */
2384 #define CAN_F5R1_FB21_Pos      (21U)
2385 #define CAN_F5R1_FB21_Msk      (0x1UL << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */
2386 #define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */
2387 #define CAN_F5R1_FB22_Pos      (22U)
2388 #define CAN_F5R1_FB22_Msk      (0x1UL << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */
2389 #define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */
2390 #define CAN_F5R1_FB23_Pos      (23U)
2391 #define CAN_F5R1_FB23_Msk      (0x1UL << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */
2392 #define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */
2393 #define CAN_F5R1_FB24_Pos      (24U)
2394 #define CAN_F5R1_FB24_Msk      (0x1UL << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */
2395 #define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */
2396 #define CAN_F5R1_FB25_Pos      (25U)
2397 #define CAN_F5R1_FB25_Msk      (0x1UL << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */
2398 #define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */
2399 #define CAN_F5R1_FB26_Pos      (26U)
2400 #define CAN_F5R1_FB26_Msk      (0x1UL << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */
2401 #define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */
2402 #define CAN_F5R1_FB27_Pos      (27U)
2403 #define CAN_F5R1_FB27_Msk      (0x1UL << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */
2404 #define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */
2405 #define CAN_F5R1_FB28_Pos      (28U)
2406 #define CAN_F5R1_FB28_Msk      (0x1UL << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */
2407 #define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */
2408 #define CAN_F5R1_FB29_Pos      (29U)
2409 #define CAN_F5R1_FB29_Msk      (0x1UL << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */
2410 #define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */
2411 #define CAN_F5R1_FB30_Pos      (30U)
2412 #define CAN_F5R1_FB30_Msk      (0x1UL << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */
2413 #define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */
2414 #define CAN_F5R1_FB31_Pos      (31U)
2415 #define CAN_F5R1_FB31_Msk      (0x1UL << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */
2416 #define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */
2417 
2418 /*******************  Bit definition for CAN_F6R1 register  *******************/
2419 #define CAN_F6R1_FB0_Pos       (0U)
2420 #define CAN_F6R1_FB0_Msk       (0x1UL << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */
2421 #define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */
2422 #define CAN_F6R1_FB1_Pos       (1U)
2423 #define CAN_F6R1_FB1_Msk       (0x1UL << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */
2424 #define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */
2425 #define CAN_F6R1_FB2_Pos       (2U)
2426 #define CAN_F6R1_FB2_Msk       (0x1UL << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */
2427 #define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */
2428 #define CAN_F6R1_FB3_Pos       (3U)
2429 #define CAN_F6R1_FB3_Msk       (0x1UL << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */
2430 #define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */
2431 #define CAN_F6R1_FB4_Pos       (4U)
2432 #define CAN_F6R1_FB4_Msk       (0x1UL << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */
2433 #define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */
2434 #define CAN_F6R1_FB5_Pos       (5U)
2435 #define CAN_F6R1_FB5_Msk       (0x1UL << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */
2436 #define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */
2437 #define CAN_F6R1_FB6_Pos       (6U)
2438 #define CAN_F6R1_FB6_Msk       (0x1UL << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */
2439 #define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */
2440 #define CAN_F6R1_FB7_Pos       (7U)
2441 #define CAN_F6R1_FB7_Msk       (0x1UL << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */
2442 #define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */
2443 #define CAN_F6R1_FB8_Pos       (8U)
2444 #define CAN_F6R1_FB8_Msk       (0x1UL << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */
2445 #define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */
2446 #define CAN_F6R1_FB9_Pos       (9U)
2447 #define CAN_F6R1_FB9_Msk       (0x1UL << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */
2448 #define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */
2449 #define CAN_F6R1_FB10_Pos      (10U)
2450 #define CAN_F6R1_FB10_Msk      (0x1UL << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */
2451 #define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */
2452 #define CAN_F6R1_FB11_Pos      (11U)
2453 #define CAN_F6R1_FB11_Msk      (0x1UL << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */
2454 #define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */
2455 #define CAN_F6R1_FB12_Pos      (12U)
2456 #define CAN_F6R1_FB12_Msk      (0x1UL << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */
2457 #define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */
2458 #define CAN_F6R1_FB13_Pos      (13U)
2459 #define CAN_F6R1_FB13_Msk      (0x1UL << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */
2460 #define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */
2461 #define CAN_F6R1_FB14_Pos      (14U)
2462 #define CAN_F6R1_FB14_Msk      (0x1UL << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */
2463 #define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */
2464 #define CAN_F6R1_FB15_Pos      (15U)
2465 #define CAN_F6R1_FB15_Msk      (0x1UL << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */
2466 #define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */
2467 #define CAN_F6R1_FB16_Pos      (16U)
2468 #define CAN_F6R1_FB16_Msk      (0x1UL << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */
2469 #define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */
2470 #define CAN_F6R1_FB17_Pos      (17U)
2471 #define CAN_F6R1_FB17_Msk      (0x1UL << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */
2472 #define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */
2473 #define CAN_F6R1_FB18_Pos      (18U)
2474 #define CAN_F6R1_FB18_Msk      (0x1UL << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */
2475 #define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */
2476 #define CAN_F6R1_FB19_Pos      (19U)
2477 #define CAN_F6R1_FB19_Msk      (0x1UL << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */
2478 #define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */
2479 #define CAN_F6R1_FB20_Pos      (20U)
2480 #define CAN_F6R1_FB20_Msk      (0x1UL << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */
2481 #define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */
2482 #define CAN_F6R1_FB21_Pos      (21U)
2483 #define CAN_F6R1_FB21_Msk      (0x1UL << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */
2484 #define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */
2485 #define CAN_F6R1_FB22_Pos      (22U)
2486 #define CAN_F6R1_FB22_Msk      (0x1UL << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */
2487 #define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */
2488 #define CAN_F6R1_FB23_Pos      (23U)
2489 #define CAN_F6R1_FB23_Msk      (0x1UL << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */
2490 #define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */
2491 #define CAN_F6R1_FB24_Pos      (24U)
2492 #define CAN_F6R1_FB24_Msk      (0x1UL << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */
2493 #define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */
2494 #define CAN_F6R1_FB25_Pos      (25U)
2495 #define CAN_F6R1_FB25_Msk      (0x1UL << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */
2496 #define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */
2497 #define CAN_F6R1_FB26_Pos      (26U)
2498 #define CAN_F6R1_FB26_Msk      (0x1UL << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */
2499 #define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */
2500 #define CAN_F6R1_FB27_Pos      (27U)
2501 #define CAN_F6R1_FB27_Msk      (0x1UL << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */
2502 #define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */
2503 #define CAN_F6R1_FB28_Pos      (28U)
2504 #define CAN_F6R1_FB28_Msk      (0x1UL << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */
2505 #define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */
2506 #define CAN_F6R1_FB29_Pos      (29U)
2507 #define CAN_F6R1_FB29_Msk      (0x1UL << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */
2508 #define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */
2509 #define CAN_F6R1_FB30_Pos      (30U)
2510 #define CAN_F6R1_FB30_Msk      (0x1UL << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */
2511 #define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */
2512 #define CAN_F6R1_FB31_Pos      (31U)
2513 #define CAN_F6R1_FB31_Msk      (0x1UL << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */
2514 #define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */
2515 
2516 /*******************  Bit definition for CAN_F7R1 register  *******************/
2517 #define CAN_F7R1_FB0_Pos       (0U)
2518 #define CAN_F7R1_FB0_Msk       (0x1UL << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */
2519 #define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */
2520 #define CAN_F7R1_FB1_Pos       (1U)
2521 #define CAN_F7R1_FB1_Msk       (0x1UL << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */
2522 #define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */
2523 #define CAN_F7R1_FB2_Pos       (2U)
2524 #define CAN_F7R1_FB2_Msk       (0x1UL << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */
2525 #define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */
2526 #define CAN_F7R1_FB3_Pos       (3U)
2527 #define CAN_F7R1_FB3_Msk       (0x1UL << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */
2528 #define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */
2529 #define CAN_F7R1_FB4_Pos       (4U)
2530 #define CAN_F7R1_FB4_Msk       (0x1UL << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */
2531 #define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */
2532 #define CAN_F7R1_FB5_Pos       (5U)
2533 #define CAN_F7R1_FB5_Msk       (0x1UL << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */
2534 #define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */
2535 #define CAN_F7R1_FB6_Pos       (6U)
2536 #define CAN_F7R1_FB6_Msk       (0x1UL << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */
2537 #define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */
2538 #define CAN_F7R1_FB7_Pos       (7U)
2539 #define CAN_F7R1_FB7_Msk       (0x1UL << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */
2540 #define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */
2541 #define CAN_F7R1_FB8_Pos       (8U)
2542 #define CAN_F7R1_FB8_Msk       (0x1UL << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */
2543 #define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */
2544 #define CAN_F7R1_FB9_Pos       (9U)
2545 #define CAN_F7R1_FB9_Msk       (0x1UL << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */
2546 #define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */
2547 #define CAN_F7R1_FB10_Pos      (10U)
2548 #define CAN_F7R1_FB10_Msk      (0x1UL << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */
2549 #define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */
2550 #define CAN_F7R1_FB11_Pos      (11U)
2551 #define CAN_F7R1_FB11_Msk      (0x1UL << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */
2552 #define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */
2553 #define CAN_F7R1_FB12_Pos      (12U)
2554 #define CAN_F7R1_FB12_Msk      (0x1UL << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */
2555 #define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */
2556 #define CAN_F7R1_FB13_Pos      (13U)
2557 #define CAN_F7R1_FB13_Msk      (0x1UL << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */
2558 #define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */
2559 #define CAN_F7R1_FB14_Pos      (14U)
2560 #define CAN_F7R1_FB14_Msk      (0x1UL << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */
2561 #define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */
2562 #define CAN_F7R1_FB15_Pos      (15U)
2563 #define CAN_F7R1_FB15_Msk      (0x1UL << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */
2564 #define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */
2565 #define CAN_F7R1_FB16_Pos      (16U)
2566 #define CAN_F7R1_FB16_Msk      (0x1UL << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */
2567 #define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */
2568 #define CAN_F7R1_FB17_Pos      (17U)
2569 #define CAN_F7R1_FB17_Msk      (0x1UL << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */
2570 #define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */
2571 #define CAN_F7R1_FB18_Pos      (18U)
2572 #define CAN_F7R1_FB18_Msk      (0x1UL << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */
2573 #define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */
2574 #define CAN_F7R1_FB19_Pos      (19U)
2575 #define CAN_F7R1_FB19_Msk      (0x1UL << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */
2576 #define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */
2577 #define CAN_F7R1_FB20_Pos      (20U)
2578 #define CAN_F7R1_FB20_Msk      (0x1UL << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */
2579 #define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */
2580 #define CAN_F7R1_FB21_Pos      (21U)
2581 #define CAN_F7R1_FB21_Msk      (0x1UL << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */
2582 #define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */
2583 #define CAN_F7R1_FB22_Pos      (22U)
2584 #define CAN_F7R1_FB22_Msk      (0x1UL << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */
2585 #define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */
2586 #define CAN_F7R1_FB23_Pos      (23U)
2587 #define CAN_F7R1_FB23_Msk      (0x1UL << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */
2588 #define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */
2589 #define CAN_F7R1_FB24_Pos      (24U)
2590 #define CAN_F7R1_FB24_Msk      (0x1UL << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */
2591 #define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */
2592 #define CAN_F7R1_FB25_Pos      (25U)
2593 #define CAN_F7R1_FB25_Msk      (0x1UL << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */
2594 #define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */
2595 #define CAN_F7R1_FB26_Pos      (26U)
2596 #define CAN_F7R1_FB26_Msk      (0x1UL << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */
2597 #define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */
2598 #define CAN_F7R1_FB27_Pos      (27U)
2599 #define CAN_F7R1_FB27_Msk      (0x1UL << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */
2600 #define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */
2601 #define CAN_F7R1_FB28_Pos      (28U)
2602 #define CAN_F7R1_FB28_Msk      (0x1UL << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */
2603 #define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */
2604 #define CAN_F7R1_FB29_Pos      (29U)
2605 #define CAN_F7R1_FB29_Msk      (0x1UL << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */
2606 #define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */
2607 #define CAN_F7R1_FB30_Pos      (30U)
2608 #define CAN_F7R1_FB30_Msk      (0x1UL << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */
2609 #define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */
2610 #define CAN_F7R1_FB31_Pos      (31U)
2611 #define CAN_F7R1_FB31_Msk      (0x1UL << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */
2612 #define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */
2613 
2614 /*******************  Bit definition for CAN_F8R1 register  *******************/
2615 #define CAN_F8R1_FB0_Pos       (0U)
2616 #define CAN_F8R1_FB0_Msk       (0x1UL << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */
2617 #define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */
2618 #define CAN_F8R1_FB1_Pos       (1U)
2619 #define CAN_F8R1_FB1_Msk       (0x1UL << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */
2620 #define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */
2621 #define CAN_F8R1_FB2_Pos       (2U)
2622 #define CAN_F8R1_FB2_Msk       (0x1UL << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */
2623 #define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */
2624 #define CAN_F8R1_FB3_Pos       (3U)
2625 #define CAN_F8R1_FB3_Msk       (0x1UL << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */
2626 #define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */
2627 #define CAN_F8R1_FB4_Pos       (4U)
2628 #define CAN_F8R1_FB4_Msk       (0x1UL << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */
2629 #define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */
2630 #define CAN_F8R1_FB5_Pos       (5U)
2631 #define CAN_F8R1_FB5_Msk       (0x1UL << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */
2632 #define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */
2633 #define CAN_F8R1_FB6_Pos       (6U)
2634 #define CAN_F8R1_FB6_Msk       (0x1UL << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */
2635 #define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */
2636 #define CAN_F8R1_FB7_Pos       (7U)
2637 #define CAN_F8R1_FB7_Msk       (0x1UL << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */
2638 #define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */
2639 #define CAN_F8R1_FB8_Pos       (8U)
2640 #define CAN_F8R1_FB8_Msk       (0x1UL << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */
2641 #define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */
2642 #define CAN_F8R1_FB9_Pos       (9U)
2643 #define CAN_F8R1_FB9_Msk       (0x1UL << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */
2644 #define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */
2645 #define CAN_F8R1_FB10_Pos      (10U)
2646 #define CAN_F8R1_FB10_Msk      (0x1UL << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */
2647 #define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */
2648 #define CAN_F8R1_FB11_Pos      (11U)
2649 #define CAN_F8R1_FB11_Msk      (0x1UL << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */
2650 #define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */
2651 #define CAN_F8R1_FB12_Pos      (12U)
2652 #define CAN_F8R1_FB12_Msk      (0x1UL << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */
2653 #define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */
2654 #define CAN_F8R1_FB13_Pos      (13U)
2655 #define CAN_F8R1_FB13_Msk      (0x1UL << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */
2656 #define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */
2657 #define CAN_F8R1_FB14_Pos      (14U)
2658 #define CAN_F8R1_FB14_Msk      (0x1UL << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */
2659 #define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */
2660 #define CAN_F8R1_FB15_Pos      (15U)
2661 #define CAN_F8R1_FB15_Msk      (0x1UL << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */
2662 #define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */
2663 #define CAN_F8R1_FB16_Pos      (16U)
2664 #define CAN_F8R1_FB16_Msk      (0x1UL << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */
2665 #define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */
2666 #define CAN_F8R1_FB17_Pos      (17U)
2667 #define CAN_F8R1_FB17_Msk      (0x1UL << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */
2668 #define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */
2669 #define CAN_F8R1_FB18_Pos      (18U)
2670 #define CAN_F8R1_FB18_Msk      (0x1UL << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */
2671 #define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */
2672 #define CAN_F8R1_FB19_Pos      (19U)
2673 #define CAN_F8R1_FB19_Msk      (0x1UL << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */
2674 #define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */
2675 #define CAN_F8R1_FB20_Pos      (20U)
2676 #define CAN_F8R1_FB20_Msk      (0x1UL << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */
2677 #define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */
2678 #define CAN_F8R1_FB21_Pos      (21U)
2679 #define CAN_F8R1_FB21_Msk      (0x1UL << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */
2680 #define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */
2681 #define CAN_F8R1_FB22_Pos      (22U)
2682 #define CAN_F8R1_FB22_Msk      (0x1UL << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */
2683 #define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */
2684 #define CAN_F8R1_FB23_Pos      (23U)
2685 #define CAN_F8R1_FB23_Msk      (0x1UL << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */
2686 #define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */
2687 #define CAN_F8R1_FB24_Pos      (24U)
2688 #define CAN_F8R1_FB24_Msk      (0x1UL << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */
2689 #define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */
2690 #define CAN_F8R1_FB25_Pos      (25U)
2691 #define CAN_F8R1_FB25_Msk      (0x1UL << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */
2692 #define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */
2693 #define CAN_F8R1_FB26_Pos      (26U)
2694 #define CAN_F8R1_FB26_Msk      (0x1UL << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */
2695 #define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */
2696 #define CAN_F8R1_FB27_Pos      (27U)
2697 #define CAN_F8R1_FB27_Msk      (0x1UL << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */
2698 #define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */
2699 #define CAN_F8R1_FB28_Pos      (28U)
2700 #define CAN_F8R1_FB28_Msk      (0x1UL << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */
2701 #define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */
2702 #define CAN_F8R1_FB29_Pos      (29U)
2703 #define CAN_F8R1_FB29_Msk      (0x1UL << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */
2704 #define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */
2705 #define CAN_F8R1_FB30_Pos      (30U)
2706 #define CAN_F8R1_FB30_Msk      (0x1UL << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */
2707 #define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */
2708 #define CAN_F8R1_FB31_Pos      (31U)
2709 #define CAN_F8R1_FB31_Msk      (0x1UL << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */
2710 #define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */
2711 
2712 /*******************  Bit definition for CAN_F9R1 register  *******************/
2713 #define CAN_F9R1_FB0_Pos       (0U)
2714 #define CAN_F9R1_FB0_Msk       (0x1UL << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */
2715 #define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */
2716 #define CAN_F9R1_FB1_Pos       (1U)
2717 #define CAN_F9R1_FB1_Msk       (0x1UL << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */
2718 #define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */
2719 #define CAN_F9R1_FB2_Pos       (2U)
2720 #define CAN_F9R1_FB2_Msk       (0x1UL << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */
2721 #define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */
2722 #define CAN_F9R1_FB3_Pos       (3U)
2723 #define CAN_F9R1_FB3_Msk       (0x1UL << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */
2724 #define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */
2725 #define CAN_F9R1_FB4_Pos       (4U)
2726 #define CAN_F9R1_FB4_Msk       (0x1UL << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */
2727 #define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */
2728 #define CAN_F9R1_FB5_Pos       (5U)
2729 #define CAN_F9R1_FB5_Msk       (0x1UL << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */
2730 #define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */
2731 #define CAN_F9R1_FB6_Pos       (6U)
2732 #define CAN_F9R1_FB6_Msk       (0x1UL << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */
2733 #define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */
2734 #define CAN_F9R1_FB7_Pos       (7U)
2735 #define CAN_F9R1_FB7_Msk       (0x1UL << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */
2736 #define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */
2737 #define CAN_F9R1_FB8_Pos       (8U)
2738 #define CAN_F9R1_FB8_Msk       (0x1UL << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */
2739 #define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */
2740 #define CAN_F9R1_FB9_Pos       (9U)
2741 #define CAN_F9R1_FB9_Msk       (0x1UL << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */
2742 #define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */
2743 #define CAN_F9R1_FB10_Pos      (10U)
2744 #define CAN_F9R1_FB10_Msk      (0x1UL << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */
2745 #define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */
2746 #define CAN_F9R1_FB11_Pos      (11U)
2747 #define CAN_F9R1_FB11_Msk      (0x1UL << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */
2748 #define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */
2749 #define CAN_F9R1_FB12_Pos      (12U)
2750 #define CAN_F9R1_FB12_Msk      (0x1UL << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */
2751 #define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */
2752 #define CAN_F9R1_FB13_Pos      (13U)
2753 #define CAN_F9R1_FB13_Msk      (0x1UL << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */
2754 #define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */
2755 #define CAN_F9R1_FB14_Pos      (14U)
2756 #define CAN_F9R1_FB14_Msk      (0x1UL << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */
2757 #define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */
2758 #define CAN_F9R1_FB15_Pos      (15U)
2759 #define CAN_F9R1_FB15_Msk      (0x1UL << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */
2760 #define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */
2761 #define CAN_F9R1_FB16_Pos      (16U)
2762 #define CAN_F9R1_FB16_Msk      (0x1UL << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */
2763 #define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */
2764 #define CAN_F9R1_FB17_Pos      (17U)
2765 #define CAN_F9R1_FB17_Msk      (0x1UL << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */
2766 #define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */
2767 #define CAN_F9R1_FB18_Pos      (18U)
2768 #define CAN_F9R1_FB18_Msk      (0x1UL << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */
2769 #define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */
2770 #define CAN_F9R1_FB19_Pos      (19U)
2771 #define CAN_F9R1_FB19_Msk      (0x1UL << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */
2772 #define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */
2773 #define CAN_F9R1_FB20_Pos      (20U)
2774 #define CAN_F9R1_FB20_Msk      (0x1UL << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */
2775 #define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */
2776 #define CAN_F9R1_FB21_Pos      (21U)
2777 #define CAN_F9R1_FB21_Msk      (0x1UL << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */
2778 #define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */
2779 #define CAN_F9R1_FB22_Pos      (22U)
2780 #define CAN_F9R1_FB22_Msk      (0x1UL << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */
2781 #define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */
2782 #define CAN_F9R1_FB23_Pos      (23U)
2783 #define CAN_F9R1_FB23_Msk      (0x1UL << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */
2784 #define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */
2785 #define CAN_F9R1_FB24_Pos      (24U)
2786 #define CAN_F9R1_FB24_Msk      (0x1UL << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */
2787 #define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */
2788 #define CAN_F9R1_FB25_Pos      (25U)
2789 #define CAN_F9R1_FB25_Msk      (0x1UL << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */
2790 #define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */
2791 #define CAN_F9R1_FB26_Pos      (26U)
2792 #define CAN_F9R1_FB26_Msk      (0x1UL << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */
2793 #define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */
2794 #define CAN_F9R1_FB27_Pos      (27U)
2795 #define CAN_F9R1_FB27_Msk      (0x1UL << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */
2796 #define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */
2797 #define CAN_F9R1_FB28_Pos      (28U)
2798 #define CAN_F9R1_FB28_Msk      (0x1UL << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */
2799 #define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */
2800 #define CAN_F9R1_FB29_Pos      (29U)
2801 #define CAN_F9R1_FB29_Msk      (0x1UL << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */
2802 #define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */
2803 #define CAN_F9R1_FB30_Pos      (30U)
2804 #define CAN_F9R1_FB30_Msk      (0x1UL << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */
2805 #define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */
2806 #define CAN_F9R1_FB31_Pos      (31U)
2807 #define CAN_F9R1_FB31_Msk      (0x1UL << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */
2808 #define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */
2809 
2810 /*******************  Bit definition for CAN_F10R1 register  ******************/
2811 #define CAN_F10R1_FB0_Pos      (0U)
2812 #define CAN_F10R1_FB0_Msk      (0x1UL << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */
2813 #define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */
2814 #define CAN_F10R1_FB1_Pos      (1U)
2815 #define CAN_F10R1_FB1_Msk      (0x1UL << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */
2816 #define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */
2817 #define CAN_F10R1_FB2_Pos      (2U)
2818 #define CAN_F10R1_FB2_Msk      (0x1UL << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */
2819 #define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */
2820 #define CAN_F10R1_FB3_Pos      (3U)
2821 #define CAN_F10R1_FB3_Msk      (0x1UL << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */
2822 #define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */
2823 #define CAN_F10R1_FB4_Pos      (4U)
2824 #define CAN_F10R1_FB4_Msk      (0x1UL << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */
2825 #define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */
2826 #define CAN_F10R1_FB5_Pos      (5U)
2827 #define CAN_F10R1_FB5_Msk      (0x1UL << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */
2828 #define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */
2829 #define CAN_F10R1_FB6_Pos      (6U)
2830 #define CAN_F10R1_FB6_Msk      (0x1UL << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */
2831 #define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */
2832 #define CAN_F10R1_FB7_Pos      (7U)
2833 #define CAN_F10R1_FB7_Msk      (0x1UL << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */
2834 #define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */
2835 #define CAN_F10R1_FB8_Pos      (8U)
2836 #define CAN_F10R1_FB8_Msk      (0x1UL << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */
2837 #define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */
2838 #define CAN_F10R1_FB9_Pos      (9U)
2839 #define CAN_F10R1_FB9_Msk      (0x1UL << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */
2840 #define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */
2841 #define CAN_F10R1_FB10_Pos     (10U)
2842 #define CAN_F10R1_FB10_Msk     (0x1UL << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */
2843 #define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */
2844 #define CAN_F10R1_FB11_Pos     (11U)
2845 #define CAN_F10R1_FB11_Msk     (0x1UL << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */
2846 #define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */
2847 #define CAN_F10R1_FB12_Pos     (12U)
2848 #define CAN_F10R1_FB12_Msk     (0x1UL << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */
2849 #define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */
2850 #define CAN_F10R1_FB13_Pos     (13U)
2851 #define CAN_F10R1_FB13_Msk     (0x1UL << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */
2852 #define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */
2853 #define CAN_F10R1_FB14_Pos     (14U)
2854 #define CAN_F10R1_FB14_Msk     (0x1UL << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */
2855 #define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */
2856 #define CAN_F10R1_FB15_Pos     (15U)
2857 #define CAN_F10R1_FB15_Msk     (0x1UL << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */
2858 #define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */
2859 #define CAN_F10R1_FB16_Pos     (16U)
2860 #define CAN_F10R1_FB16_Msk     (0x1UL << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */
2861 #define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */
2862 #define CAN_F10R1_FB17_Pos     (17U)
2863 #define CAN_F10R1_FB17_Msk     (0x1UL << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */
2864 #define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */
2865 #define CAN_F10R1_FB18_Pos     (18U)
2866 #define CAN_F10R1_FB18_Msk     (0x1UL << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */
2867 #define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */
2868 #define CAN_F10R1_FB19_Pos     (19U)
2869 #define CAN_F10R1_FB19_Msk     (0x1UL << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */
2870 #define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */
2871 #define CAN_F10R1_FB20_Pos     (20U)
2872 #define CAN_F10R1_FB20_Msk     (0x1UL << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */
2873 #define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */
2874 #define CAN_F10R1_FB21_Pos     (21U)
2875 #define CAN_F10R1_FB21_Msk     (0x1UL << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */
2876 #define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */
2877 #define CAN_F10R1_FB22_Pos     (22U)
2878 #define CAN_F10R1_FB22_Msk     (0x1UL << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */
2879 #define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */
2880 #define CAN_F10R1_FB23_Pos     (23U)
2881 #define CAN_F10R1_FB23_Msk     (0x1UL << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */
2882 #define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */
2883 #define CAN_F10R1_FB24_Pos     (24U)
2884 #define CAN_F10R1_FB24_Msk     (0x1UL << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */
2885 #define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */
2886 #define CAN_F10R1_FB25_Pos     (25U)
2887 #define CAN_F10R1_FB25_Msk     (0x1UL << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */
2888 #define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */
2889 #define CAN_F10R1_FB26_Pos     (26U)
2890 #define CAN_F10R1_FB26_Msk     (0x1UL << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */
2891 #define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */
2892 #define CAN_F10R1_FB27_Pos     (27U)
2893 #define CAN_F10R1_FB27_Msk     (0x1UL << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */
2894 #define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */
2895 #define CAN_F10R1_FB28_Pos     (28U)
2896 #define CAN_F10R1_FB28_Msk     (0x1UL << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */
2897 #define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */
2898 #define CAN_F10R1_FB29_Pos     (29U)
2899 #define CAN_F10R1_FB29_Msk     (0x1UL << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */
2900 #define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */
2901 #define CAN_F10R1_FB30_Pos     (30U)
2902 #define CAN_F10R1_FB30_Msk     (0x1UL << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */
2903 #define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */
2904 #define CAN_F10R1_FB31_Pos     (31U)
2905 #define CAN_F10R1_FB31_Msk     (0x1UL << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */
2906 #define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */
2907 
2908 /*******************  Bit definition for CAN_F11R1 register  ******************/
2909 #define CAN_F11R1_FB0_Pos      (0U)
2910 #define CAN_F11R1_FB0_Msk      (0x1UL << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */
2911 #define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */
2912 #define CAN_F11R1_FB1_Pos      (1U)
2913 #define CAN_F11R1_FB1_Msk      (0x1UL << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */
2914 #define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */
2915 #define CAN_F11R1_FB2_Pos      (2U)
2916 #define CAN_F11R1_FB2_Msk      (0x1UL << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */
2917 #define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */
2918 #define CAN_F11R1_FB3_Pos      (3U)
2919 #define CAN_F11R1_FB3_Msk      (0x1UL << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */
2920 #define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */
2921 #define CAN_F11R1_FB4_Pos      (4U)
2922 #define CAN_F11R1_FB4_Msk      (0x1UL << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */
2923 #define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */
2924 #define CAN_F11R1_FB5_Pos      (5U)
2925 #define CAN_F11R1_FB5_Msk      (0x1UL << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */
2926 #define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */
2927 #define CAN_F11R1_FB6_Pos      (6U)
2928 #define CAN_F11R1_FB6_Msk      (0x1UL << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */
2929 #define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */
2930 #define CAN_F11R1_FB7_Pos      (7U)
2931 #define CAN_F11R1_FB7_Msk      (0x1UL << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */
2932 #define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */
2933 #define CAN_F11R1_FB8_Pos      (8U)
2934 #define CAN_F11R1_FB8_Msk      (0x1UL << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */
2935 #define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */
2936 #define CAN_F11R1_FB9_Pos      (9U)
2937 #define CAN_F11R1_FB9_Msk      (0x1UL << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */
2938 #define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */
2939 #define CAN_F11R1_FB10_Pos     (10U)
2940 #define CAN_F11R1_FB10_Msk     (0x1UL << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */
2941 #define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */
2942 #define CAN_F11R1_FB11_Pos     (11U)
2943 #define CAN_F11R1_FB11_Msk     (0x1UL << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */
2944 #define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */
2945 #define CAN_F11R1_FB12_Pos     (12U)
2946 #define CAN_F11R1_FB12_Msk     (0x1UL << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */
2947 #define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */
2948 #define CAN_F11R1_FB13_Pos     (13U)
2949 #define CAN_F11R1_FB13_Msk     (0x1UL << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */
2950 #define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */
2951 #define CAN_F11R1_FB14_Pos     (14U)
2952 #define CAN_F11R1_FB14_Msk     (0x1UL << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */
2953 #define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */
2954 #define CAN_F11R1_FB15_Pos     (15U)
2955 #define CAN_F11R1_FB15_Msk     (0x1UL << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */
2956 #define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */
2957 #define CAN_F11R1_FB16_Pos     (16U)
2958 #define CAN_F11R1_FB16_Msk     (0x1UL << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */
2959 #define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */
2960 #define CAN_F11R1_FB17_Pos     (17U)
2961 #define CAN_F11R1_FB17_Msk     (0x1UL << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */
2962 #define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */
2963 #define CAN_F11R1_FB18_Pos     (18U)
2964 #define CAN_F11R1_FB18_Msk     (0x1UL << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */
2965 #define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */
2966 #define CAN_F11R1_FB19_Pos     (19U)
2967 #define CAN_F11R1_FB19_Msk     (0x1UL << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */
2968 #define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */
2969 #define CAN_F11R1_FB20_Pos     (20U)
2970 #define CAN_F11R1_FB20_Msk     (0x1UL << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */
2971 #define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */
2972 #define CAN_F11R1_FB21_Pos     (21U)
2973 #define CAN_F11R1_FB21_Msk     (0x1UL << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */
2974 #define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */
2975 #define CAN_F11R1_FB22_Pos     (22U)
2976 #define CAN_F11R1_FB22_Msk     (0x1UL << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */
2977 #define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */
2978 #define CAN_F11R1_FB23_Pos     (23U)
2979 #define CAN_F11R1_FB23_Msk     (0x1UL << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */
2980 #define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */
2981 #define CAN_F11R1_FB24_Pos     (24U)
2982 #define CAN_F11R1_FB24_Msk     (0x1UL << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */
2983 #define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */
2984 #define CAN_F11R1_FB25_Pos     (25U)
2985 #define CAN_F11R1_FB25_Msk     (0x1UL << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */
2986 #define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */
2987 #define CAN_F11R1_FB26_Pos     (26U)
2988 #define CAN_F11R1_FB26_Msk     (0x1UL << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */
2989 #define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */
2990 #define CAN_F11R1_FB27_Pos     (27U)
2991 #define CAN_F11R1_FB27_Msk     (0x1UL << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */
2992 #define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */
2993 #define CAN_F11R1_FB28_Pos     (28U)
2994 #define CAN_F11R1_FB28_Msk     (0x1UL << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */
2995 #define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */
2996 #define CAN_F11R1_FB29_Pos     (29U)
2997 #define CAN_F11R1_FB29_Msk     (0x1UL << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */
2998 #define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */
2999 #define CAN_F11R1_FB30_Pos     (30U)
3000 #define CAN_F11R1_FB30_Msk     (0x1UL << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */
3001 #define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */
3002 #define CAN_F11R1_FB31_Pos     (31U)
3003 #define CAN_F11R1_FB31_Msk     (0x1UL << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */
3004 #define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */
3005 
3006 /*******************  Bit definition for CAN_F12R1 register  ******************/
3007 #define CAN_F12R1_FB0_Pos      (0U)
3008 #define CAN_F12R1_FB0_Msk      (0x1UL << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */
3009 #define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */
3010 #define CAN_F12R1_FB1_Pos      (1U)
3011 #define CAN_F12R1_FB1_Msk      (0x1UL << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */
3012 #define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */
3013 #define CAN_F12R1_FB2_Pos      (2U)
3014 #define CAN_F12R1_FB2_Msk      (0x1UL << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */
3015 #define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */
3016 #define CAN_F12R1_FB3_Pos      (3U)
3017 #define CAN_F12R1_FB3_Msk      (0x1UL << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */
3018 #define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */
3019 #define CAN_F12R1_FB4_Pos      (4U)
3020 #define CAN_F12R1_FB4_Msk      (0x1UL << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */
3021 #define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */
3022 #define CAN_F12R1_FB5_Pos      (5U)
3023 #define CAN_F12R1_FB5_Msk      (0x1UL << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */
3024 #define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */
3025 #define CAN_F12R1_FB6_Pos      (6U)
3026 #define CAN_F12R1_FB6_Msk      (0x1UL << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */
3027 #define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */
3028 #define CAN_F12R1_FB7_Pos      (7U)
3029 #define CAN_F12R1_FB7_Msk      (0x1UL << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */
3030 #define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */
3031 #define CAN_F12R1_FB8_Pos      (8U)
3032 #define CAN_F12R1_FB8_Msk      (0x1UL << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */
3033 #define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */
3034 #define CAN_F12R1_FB9_Pos      (9U)
3035 #define CAN_F12R1_FB9_Msk      (0x1UL << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */
3036 #define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */
3037 #define CAN_F12R1_FB10_Pos     (10U)
3038 #define CAN_F12R1_FB10_Msk     (0x1UL << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */
3039 #define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */
3040 #define CAN_F12R1_FB11_Pos     (11U)
3041 #define CAN_F12R1_FB11_Msk     (0x1UL << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */
3042 #define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */
3043 #define CAN_F12R1_FB12_Pos     (12U)
3044 #define CAN_F12R1_FB12_Msk     (0x1UL << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */
3045 #define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */
3046 #define CAN_F12R1_FB13_Pos     (13U)
3047 #define CAN_F12R1_FB13_Msk     (0x1UL << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */
3048 #define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */
3049 #define CAN_F12R1_FB14_Pos     (14U)
3050 #define CAN_F12R1_FB14_Msk     (0x1UL << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */
3051 #define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */
3052 #define CAN_F12R1_FB15_Pos     (15U)
3053 #define CAN_F12R1_FB15_Msk     (0x1UL << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */
3054 #define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */
3055 #define CAN_F12R1_FB16_Pos     (16U)
3056 #define CAN_F12R1_FB16_Msk     (0x1UL << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */
3057 #define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */
3058 #define CAN_F12R1_FB17_Pos     (17U)
3059 #define CAN_F12R1_FB17_Msk     (0x1UL << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */
3060 #define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */
3061 #define CAN_F12R1_FB18_Pos     (18U)
3062 #define CAN_F12R1_FB18_Msk     (0x1UL << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */
3063 #define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */
3064 #define CAN_F12R1_FB19_Pos     (19U)
3065 #define CAN_F12R1_FB19_Msk     (0x1UL << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */
3066 #define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */
3067 #define CAN_F12R1_FB20_Pos     (20U)
3068 #define CAN_F12R1_FB20_Msk     (0x1UL << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */
3069 #define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */
3070 #define CAN_F12R1_FB21_Pos     (21U)
3071 #define CAN_F12R1_FB21_Msk     (0x1UL << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */
3072 #define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */
3073 #define CAN_F12R1_FB22_Pos     (22U)
3074 #define CAN_F12R1_FB22_Msk     (0x1UL << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */
3075 #define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */
3076 #define CAN_F12R1_FB23_Pos     (23U)
3077 #define CAN_F12R1_FB23_Msk     (0x1UL << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */
3078 #define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */
3079 #define CAN_F12R1_FB24_Pos     (24U)
3080 #define CAN_F12R1_FB24_Msk     (0x1UL << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */
3081 #define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */
3082 #define CAN_F12R1_FB25_Pos     (25U)
3083 #define CAN_F12R1_FB25_Msk     (0x1UL << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */
3084 #define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */
3085 #define CAN_F12R1_FB26_Pos     (26U)
3086 #define CAN_F12R1_FB26_Msk     (0x1UL << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */
3087 #define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */
3088 #define CAN_F12R1_FB27_Pos     (27U)
3089 #define CAN_F12R1_FB27_Msk     (0x1UL << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */
3090 #define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */
3091 #define CAN_F12R1_FB28_Pos     (28U)
3092 #define CAN_F12R1_FB28_Msk     (0x1UL << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */
3093 #define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */
3094 #define CAN_F12R1_FB29_Pos     (29U)
3095 #define CAN_F12R1_FB29_Msk     (0x1UL << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */
3096 #define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */
3097 #define CAN_F12R1_FB30_Pos     (30U)
3098 #define CAN_F12R1_FB30_Msk     (0x1UL << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */
3099 #define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */
3100 #define CAN_F12R1_FB31_Pos     (31U)
3101 #define CAN_F12R1_FB31_Msk     (0x1UL << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */
3102 #define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */
3103 
3104 /*******************  Bit definition for CAN_F13R1 register  ******************/
3105 #define CAN_F13R1_FB0_Pos      (0U)
3106 #define CAN_F13R1_FB0_Msk      (0x1UL << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */
3107 #define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */
3108 #define CAN_F13R1_FB1_Pos      (1U)
3109 #define CAN_F13R1_FB1_Msk      (0x1UL << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */
3110 #define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */
3111 #define CAN_F13R1_FB2_Pos      (2U)
3112 #define CAN_F13R1_FB2_Msk      (0x1UL << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */
3113 #define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */
3114 #define CAN_F13R1_FB3_Pos      (3U)
3115 #define CAN_F13R1_FB3_Msk      (0x1UL << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */
3116 #define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */
3117 #define CAN_F13R1_FB4_Pos      (4U)
3118 #define CAN_F13R1_FB4_Msk      (0x1UL << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */
3119 #define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */
3120 #define CAN_F13R1_FB5_Pos      (5U)
3121 #define CAN_F13R1_FB5_Msk      (0x1UL << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */
3122 #define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */
3123 #define CAN_F13R1_FB6_Pos      (6U)
3124 #define CAN_F13R1_FB6_Msk      (0x1UL << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */
3125 #define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */
3126 #define CAN_F13R1_FB7_Pos      (7U)
3127 #define CAN_F13R1_FB7_Msk      (0x1UL << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */
3128 #define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */
3129 #define CAN_F13R1_FB8_Pos      (8U)
3130 #define CAN_F13R1_FB8_Msk      (0x1UL << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */
3131 #define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */
3132 #define CAN_F13R1_FB9_Pos      (9U)
3133 #define CAN_F13R1_FB9_Msk      (0x1UL << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */
3134 #define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */
3135 #define CAN_F13R1_FB10_Pos     (10U)
3136 #define CAN_F13R1_FB10_Msk     (0x1UL << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */
3137 #define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */
3138 #define CAN_F13R1_FB11_Pos     (11U)
3139 #define CAN_F13R1_FB11_Msk     (0x1UL << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */
3140 #define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */
3141 #define CAN_F13R1_FB12_Pos     (12U)
3142 #define CAN_F13R1_FB12_Msk     (0x1UL << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */
3143 #define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */
3144 #define CAN_F13R1_FB13_Pos     (13U)
3145 #define CAN_F13R1_FB13_Msk     (0x1UL << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */
3146 #define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */
3147 #define CAN_F13R1_FB14_Pos     (14U)
3148 #define CAN_F13R1_FB14_Msk     (0x1UL << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */
3149 #define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */
3150 #define CAN_F13R1_FB15_Pos     (15U)
3151 #define CAN_F13R1_FB15_Msk     (0x1UL << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */
3152 #define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */
3153 #define CAN_F13R1_FB16_Pos     (16U)
3154 #define CAN_F13R1_FB16_Msk     (0x1UL << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */
3155 #define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */
3156 #define CAN_F13R1_FB17_Pos     (17U)
3157 #define CAN_F13R1_FB17_Msk     (0x1UL << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */
3158 #define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */
3159 #define CAN_F13R1_FB18_Pos     (18U)
3160 #define CAN_F13R1_FB18_Msk     (0x1UL << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */
3161 #define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */
3162 #define CAN_F13R1_FB19_Pos     (19U)
3163 #define CAN_F13R1_FB19_Msk     (0x1UL << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */
3164 #define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */
3165 #define CAN_F13R1_FB20_Pos     (20U)
3166 #define CAN_F13R1_FB20_Msk     (0x1UL << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */
3167 #define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */
3168 #define CAN_F13R1_FB21_Pos     (21U)
3169 #define CAN_F13R1_FB21_Msk     (0x1UL << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */
3170 #define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */
3171 #define CAN_F13R1_FB22_Pos     (22U)
3172 #define CAN_F13R1_FB22_Msk     (0x1UL << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */
3173 #define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */
3174 #define CAN_F13R1_FB23_Pos     (23U)
3175 #define CAN_F13R1_FB23_Msk     (0x1UL << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */
3176 #define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */
3177 #define CAN_F13R1_FB24_Pos     (24U)
3178 #define CAN_F13R1_FB24_Msk     (0x1UL << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */
3179 #define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */
3180 #define CAN_F13R1_FB25_Pos     (25U)
3181 #define CAN_F13R1_FB25_Msk     (0x1UL << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */
3182 #define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */
3183 #define CAN_F13R1_FB26_Pos     (26U)
3184 #define CAN_F13R1_FB26_Msk     (0x1UL << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */
3185 #define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */
3186 #define CAN_F13R1_FB27_Pos     (27U)
3187 #define CAN_F13R1_FB27_Msk     (0x1UL << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */
3188 #define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */
3189 #define CAN_F13R1_FB28_Pos     (28U)
3190 #define CAN_F13R1_FB28_Msk     (0x1UL << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */
3191 #define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */
3192 #define CAN_F13R1_FB29_Pos     (29U)
3193 #define CAN_F13R1_FB29_Msk     (0x1UL << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */
3194 #define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */
3195 #define CAN_F13R1_FB30_Pos     (30U)
3196 #define CAN_F13R1_FB30_Msk     (0x1UL << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */
3197 #define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */
3198 #define CAN_F13R1_FB31_Pos     (31U)
3199 #define CAN_F13R1_FB31_Msk     (0x1UL << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */
3200 #define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */
3201 
3202 /*******************  Bit definition for CAN_F0R2 register  *******************/
3203 #define CAN_F0R2_FB0_Pos       (0U)
3204 #define CAN_F0R2_FB0_Msk       (0x1UL << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */
3205 #define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */
3206 #define CAN_F0R2_FB1_Pos       (1U)
3207 #define CAN_F0R2_FB1_Msk       (0x1UL << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */
3208 #define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */
3209 #define CAN_F0R2_FB2_Pos       (2U)
3210 #define CAN_F0R2_FB2_Msk       (0x1UL << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */
3211 #define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */
3212 #define CAN_F0R2_FB3_Pos       (3U)
3213 #define CAN_F0R2_FB3_Msk       (0x1UL << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */
3214 #define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */
3215 #define CAN_F0R2_FB4_Pos       (4U)
3216 #define CAN_F0R2_FB4_Msk       (0x1UL << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */
3217 #define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */
3218 #define CAN_F0R2_FB5_Pos       (5U)
3219 #define CAN_F0R2_FB5_Msk       (0x1UL << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */
3220 #define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */
3221 #define CAN_F0R2_FB6_Pos       (6U)
3222 #define CAN_F0R2_FB6_Msk       (0x1UL << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */
3223 #define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */
3224 #define CAN_F0R2_FB7_Pos       (7U)
3225 #define CAN_F0R2_FB7_Msk       (0x1UL << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */
3226 #define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */
3227 #define CAN_F0R2_FB8_Pos       (8U)
3228 #define CAN_F0R2_FB8_Msk       (0x1UL << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */
3229 #define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */
3230 #define CAN_F0R2_FB9_Pos       (9U)
3231 #define CAN_F0R2_FB9_Msk       (0x1UL << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */
3232 #define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */
3233 #define CAN_F0R2_FB10_Pos      (10U)
3234 #define CAN_F0R2_FB10_Msk      (0x1UL << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */
3235 #define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */
3236 #define CAN_F0R2_FB11_Pos      (11U)
3237 #define CAN_F0R2_FB11_Msk      (0x1UL << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */
3238 #define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */
3239 #define CAN_F0R2_FB12_Pos      (12U)
3240 #define CAN_F0R2_FB12_Msk      (0x1UL << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */
3241 #define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */
3242 #define CAN_F0R2_FB13_Pos      (13U)
3243 #define CAN_F0R2_FB13_Msk      (0x1UL << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */
3244 #define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */
3245 #define CAN_F0R2_FB14_Pos      (14U)
3246 #define CAN_F0R2_FB14_Msk      (0x1UL << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */
3247 #define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */
3248 #define CAN_F0R2_FB15_Pos      (15U)
3249 #define CAN_F0R2_FB15_Msk      (0x1UL << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */
3250 #define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */
3251 #define CAN_F0R2_FB16_Pos      (16U)
3252 #define CAN_F0R2_FB16_Msk      (0x1UL << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */
3253 #define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */
3254 #define CAN_F0R2_FB17_Pos      (17U)
3255 #define CAN_F0R2_FB17_Msk      (0x1UL << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */
3256 #define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */
3257 #define CAN_F0R2_FB18_Pos      (18U)
3258 #define CAN_F0R2_FB18_Msk      (0x1UL << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */
3259 #define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */
3260 #define CAN_F0R2_FB19_Pos      (19U)
3261 #define CAN_F0R2_FB19_Msk      (0x1UL << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */
3262 #define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */
3263 #define CAN_F0R2_FB20_Pos      (20U)
3264 #define CAN_F0R2_FB20_Msk      (0x1UL << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */
3265 #define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */
3266 #define CAN_F0R2_FB21_Pos      (21U)
3267 #define CAN_F0R2_FB21_Msk      (0x1UL << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */
3268 #define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */
3269 #define CAN_F0R2_FB22_Pos      (22U)
3270 #define CAN_F0R2_FB22_Msk      (0x1UL << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */
3271 #define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */
3272 #define CAN_F0R2_FB23_Pos      (23U)
3273 #define CAN_F0R2_FB23_Msk      (0x1UL << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */
3274 #define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */
3275 #define CAN_F0R2_FB24_Pos      (24U)
3276 #define CAN_F0R2_FB24_Msk      (0x1UL << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */
3277 #define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */
3278 #define CAN_F0R2_FB25_Pos      (25U)
3279 #define CAN_F0R2_FB25_Msk      (0x1UL << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */
3280 #define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */
3281 #define CAN_F0R2_FB26_Pos      (26U)
3282 #define CAN_F0R2_FB26_Msk      (0x1UL << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */
3283 #define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */
3284 #define CAN_F0R2_FB27_Pos      (27U)
3285 #define CAN_F0R2_FB27_Msk      (0x1UL << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */
3286 #define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */
3287 #define CAN_F0R2_FB28_Pos      (28U)
3288 #define CAN_F0R2_FB28_Msk      (0x1UL << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */
3289 #define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */
3290 #define CAN_F0R2_FB29_Pos      (29U)
3291 #define CAN_F0R2_FB29_Msk      (0x1UL << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */
3292 #define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */
3293 #define CAN_F0R2_FB30_Pos      (30U)
3294 #define CAN_F0R2_FB30_Msk      (0x1UL << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */
3295 #define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */
3296 #define CAN_F0R2_FB31_Pos      (31U)
3297 #define CAN_F0R2_FB31_Msk      (0x1UL << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */
3298 #define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */
3299 
3300 /*******************  Bit definition for CAN_F1R2 register  *******************/
3301 #define CAN_F1R2_FB0_Pos       (0U)
3302 #define CAN_F1R2_FB0_Msk       (0x1UL << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */
3303 #define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */
3304 #define CAN_F1R2_FB1_Pos       (1U)
3305 #define CAN_F1R2_FB1_Msk       (0x1UL << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */
3306 #define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */
3307 #define CAN_F1R2_FB2_Pos       (2U)
3308 #define CAN_F1R2_FB2_Msk       (0x1UL << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */
3309 #define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */
3310 #define CAN_F1R2_FB3_Pos       (3U)
3311 #define CAN_F1R2_FB3_Msk       (0x1UL << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */
3312 #define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */
3313 #define CAN_F1R2_FB4_Pos       (4U)
3314 #define CAN_F1R2_FB4_Msk       (0x1UL << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */
3315 #define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */
3316 #define CAN_F1R2_FB5_Pos       (5U)
3317 #define CAN_F1R2_FB5_Msk       (0x1UL << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */
3318 #define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */
3319 #define CAN_F1R2_FB6_Pos       (6U)
3320 #define CAN_F1R2_FB6_Msk       (0x1UL << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */
3321 #define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */
3322 #define CAN_F1R2_FB7_Pos       (7U)
3323 #define CAN_F1R2_FB7_Msk       (0x1UL << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */
3324 #define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */
3325 #define CAN_F1R2_FB8_Pos       (8U)
3326 #define CAN_F1R2_FB8_Msk       (0x1UL << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */
3327 #define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */
3328 #define CAN_F1R2_FB9_Pos       (9U)
3329 #define CAN_F1R2_FB9_Msk       (0x1UL << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */
3330 #define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */
3331 #define CAN_F1R2_FB10_Pos      (10U)
3332 #define CAN_F1R2_FB10_Msk      (0x1UL << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */
3333 #define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */
3334 #define CAN_F1R2_FB11_Pos      (11U)
3335 #define CAN_F1R2_FB11_Msk      (0x1UL << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */
3336 #define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */
3337 #define CAN_F1R2_FB12_Pos      (12U)
3338 #define CAN_F1R2_FB12_Msk      (0x1UL << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */
3339 #define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */
3340 #define CAN_F1R2_FB13_Pos      (13U)
3341 #define CAN_F1R2_FB13_Msk      (0x1UL << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */
3342 #define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */
3343 #define CAN_F1R2_FB14_Pos      (14U)
3344 #define CAN_F1R2_FB14_Msk      (0x1UL << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */
3345 #define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */
3346 #define CAN_F1R2_FB15_Pos      (15U)
3347 #define CAN_F1R2_FB15_Msk      (0x1UL << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */
3348 #define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */
3349 #define CAN_F1R2_FB16_Pos      (16U)
3350 #define CAN_F1R2_FB16_Msk      (0x1UL << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */
3351 #define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */
3352 #define CAN_F1R2_FB17_Pos      (17U)
3353 #define CAN_F1R2_FB17_Msk      (0x1UL << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */
3354 #define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */
3355 #define CAN_F1R2_FB18_Pos      (18U)
3356 #define CAN_F1R2_FB18_Msk      (0x1UL << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */
3357 #define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */
3358 #define CAN_F1R2_FB19_Pos      (19U)
3359 #define CAN_F1R2_FB19_Msk      (0x1UL << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */
3360 #define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */
3361 #define CAN_F1R2_FB20_Pos      (20U)
3362 #define CAN_F1R2_FB20_Msk      (0x1UL << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */
3363 #define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */
3364 #define CAN_F1R2_FB21_Pos      (21U)
3365 #define CAN_F1R2_FB21_Msk      (0x1UL << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */
3366 #define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */
3367 #define CAN_F1R2_FB22_Pos      (22U)
3368 #define CAN_F1R2_FB22_Msk      (0x1UL << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */
3369 #define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */
3370 #define CAN_F1R2_FB23_Pos      (23U)
3371 #define CAN_F1R2_FB23_Msk      (0x1UL << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */
3372 #define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */
3373 #define CAN_F1R2_FB24_Pos      (24U)
3374 #define CAN_F1R2_FB24_Msk      (0x1UL << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */
3375 #define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */
3376 #define CAN_F1R2_FB25_Pos      (25U)
3377 #define CAN_F1R2_FB25_Msk      (0x1UL << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */
3378 #define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */
3379 #define CAN_F1R2_FB26_Pos      (26U)
3380 #define CAN_F1R2_FB26_Msk      (0x1UL << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */
3381 #define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */
3382 #define CAN_F1R2_FB27_Pos      (27U)
3383 #define CAN_F1R2_FB27_Msk      (0x1UL << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */
3384 #define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */
3385 #define CAN_F1R2_FB28_Pos      (28U)
3386 #define CAN_F1R2_FB28_Msk      (0x1UL << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */
3387 #define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */
3388 #define CAN_F1R2_FB29_Pos      (29U)
3389 #define CAN_F1R2_FB29_Msk      (0x1UL << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */
3390 #define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */
3391 #define CAN_F1R2_FB30_Pos      (30U)
3392 #define CAN_F1R2_FB30_Msk      (0x1UL << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */
3393 #define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */
3394 #define CAN_F1R2_FB31_Pos      (31U)
3395 #define CAN_F1R2_FB31_Msk      (0x1UL << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */
3396 #define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */
3397 
3398 /*******************  Bit definition for CAN_F2R2 register  *******************/
3399 #define CAN_F2R2_FB0_Pos       (0U)
3400 #define CAN_F2R2_FB0_Msk       (0x1UL << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */
3401 #define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */
3402 #define CAN_F2R2_FB1_Pos       (1U)
3403 #define CAN_F2R2_FB1_Msk       (0x1UL << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */
3404 #define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */
3405 #define CAN_F2R2_FB2_Pos       (2U)
3406 #define CAN_F2R2_FB2_Msk       (0x1UL << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */
3407 #define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */
3408 #define CAN_F2R2_FB3_Pos       (3U)
3409 #define CAN_F2R2_FB3_Msk       (0x1UL << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */
3410 #define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */
3411 #define CAN_F2R2_FB4_Pos       (4U)
3412 #define CAN_F2R2_FB4_Msk       (0x1UL << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */
3413 #define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */
3414 #define CAN_F2R2_FB5_Pos       (5U)
3415 #define CAN_F2R2_FB5_Msk       (0x1UL << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */
3416 #define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */
3417 #define CAN_F2R2_FB6_Pos       (6U)
3418 #define CAN_F2R2_FB6_Msk       (0x1UL << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */
3419 #define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */
3420 #define CAN_F2R2_FB7_Pos       (7U)
3421 #define CAN_F2R2_FB7_Msk       (0x1UL << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */
3422 #define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */
3423 #define CAN_F2R2_FB8_Pos       (8U)
3424 #define CAN_F2R2_FB8_Msk       (0x1UL << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */
3425 #define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */
3426 #define CAN_F2R2_FB9_Pos       (9U)
3427 #define CAN_F2R2_FB9_Msk       (0x1UL << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */
3428 #define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */
3429 #define CAN_F2R2_FB10_Pos      (10U)
3430 #define CAN_F2R2_FB10_Msk      (0x1UL << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */
3431 #define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */
3432 #define CAN_F2R2_FB11_Pos      (11U)
3433 #define CAN_F2R2_FB11_Msk      (0x1UL << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */
3434 #define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */
3435 #define CAN_F2R2_FB12_Pos      (12U)
3436 #define CAN_F2R2_FB12_Msk      (0x1UL << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */
3437 #define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */
3438 #define CAN_F2R2_FB13_Pos      (13U)
3439 #define CAN_F2R2_FB13_Msk      (0x1UL << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */
3440 #define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */
3441 #define CAN_F2R2_FB14_Pos      (14U)
3442 #define CAN_F2R2_FB14_Msk      (0x1UL << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */
3443 #define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */
3444 #define CAN_F2R2_FB15_Pos      (15U)
3445 #define CAN_F2R2_FB15_Msk      (0x1UL << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */
3446 #define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */
3447 #define CAN_F2R2_FB16_Pos      (16U)
3448 #define CAN_F2R2_FB16_Msk      (0x1UL << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */
3449 #define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */
3450 #define CAN_F2R2_FB17_Pos      (17U)
3451 #define CAN_F2R2_FB17_Msk      (0x1UL << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */
3452 #define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */
3453 #define CAN_F2R2_FB18_Pos      (18U)
3454 #define CAN_F2R2_FB18_Msk      (0x1UL << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */
3455 #define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */
3456 #define CAN_F2R2_FB19_Pos      (19U)
3457 #define CAN_F2R2_FB19_Msk      (0x1UL << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */
3458 #define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */
3459 #define CAN_F2R2_FB20_Pos      (20U)
3460 #define CAN_F2R2_FB20_Msk      (0x1UL << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */
3461 #define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */
3462 #define CAN_F2R2_FB21_Pos      (21U)
3463 #define CAN_F2R2_FB21_Msk      (0x1UL << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */
3464 #define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */
3465 #define CAN_F2R2_FB22_Pos      (22U)
3466 #define CAN_F2R2_FB22_Msk      (0x1UL << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */
3467 #define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */
3468 #define CAN_F2R2_FB23_Pos      (23U)
3469 #define CAN_F2R2_FB23_Msk      (0x1UL << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */
3470 #define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */
3471 #define CAN_F2R2_FB24_Pos      (24U)
3472 #define CAN_F2R2_FB24_Msk      (0x1UL << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */
3473 #define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */
3474 #define CAN_F2R2_FB25_Pos      (25U)
3475 #define CAN_F2R2_FB25_Msk      (0x1UL << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */
3476 #define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */
3477 #define CAN_F2R2_FB26_Pos      (26U)
3478 #define CAN_F2R2_FB26_Msk      (0x1UL << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */
3479 #define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */
3480 #define CAN_F2R2_FB27_Pos      (27U)
3481 #define CAN_F2R2_FB27_Msk      (0x1UL << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */
3482 #define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */
3483 #define CAN_F2R2_FB28_Pos      (28U)
3484 #define CAN_F2R2_FB28_Msk      (0x1UL << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */
3485 #define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */
3486 #define CAN_F2R2_FB29_Pos      (29U)
3487 #define CAN_F2R2_FB29_Msk      (0x1UL << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */
3488 #define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */
3489 #define CAN_F2R2_FB30_Pos      (30U)
3490 #define CAN_F2R2_FB30_Msk      (0x1UL << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */
3491 #define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */
3492 #define CAN_F2R2_FB31_Pos      (31U)
3493 #define CAN_F2R2_FB31_Msk      (0x1UL << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */
3494 #define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */
3495 
3496 /*******************  Bit definition for CAN_F3R2 register  *******************/
3497 #define CAN_F3R2_FB0_Pos       (0U)
3498 #define CAN_F3R2_FB0_Msk       (0x1UL << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */
3499 #define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */
3500 #define CAN_F3R2_FB1_Pos       (1U)
3501 #define CAN_F3R2_FB1_Msk       (0x1UL << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */
3502 #define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */
3503 #define CAN_F3R2_FB2_Pos       (2U)
3504 #define CAN_F3R2_FB2_Msk       (0x1UL << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */
3505 #define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */
3506 #define CAN_F3R2_FB3_Pos       (3U)
3507 #define CAN_F3R2_FB3_Msk       (0x1UL << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */
3508 #define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */
3509 #define CAN_F3R2_FB4_Pos       (4U)
3510 #define CAN_F3R2_FB4_Msk       (0x1UL << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */
3511 #define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */
3512 #define CAN_F3R2_FB5_Pos       (5U)
3513 #define CAN_F3R2_FB5_Msk       (0x1UL << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */
3514 #define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */
3515 #define CAN_F3R2_FB6_Pos       (6U)
3516 #define CAN_F3R2_FB6_Msk       (0x1UL << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */
3517 #define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */
3518 #define CAN_F3R2_FB7_Pos       (7U)
3519 #define CAN_F3R2_FB7_Msk       (0x1UL << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */
3520 #define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */
3521 #define CAN_F3R2_FB8_Pos       (8U)
3522 #define CAN_F3R2_FB8_Msk       (0x1UL << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */
3523 #define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */
3524 #define CAN_F3R2_FB9_Pos       (9U)
3525 #define CAN_F3R2_FB9_Msk       (0x1UL << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */
3526 #define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */
3527 #define CAN_F3R2_FB10_Pos      (10U)
3528 #define CAN_F3R2_FB10_Msk      (0x1UL << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */
3529 #define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */
3530 #define CAN_F3R2_FB11_Pos      (11U)
3531 #define CAN_F3R2_FB11_Msk      (0x1UL << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */
3532 #define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */
3533 #define CAN_F3R2_FB12_Pos      (12U)
3534 #define CAN_F3R2_FB12_Msk      (0x1UL << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */
3535 #define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */
3536 #define CAN_F3R2_FB13_Pos      (13U)
3537 #define CAN_F3R2_FB13_Msk      (0x1UL << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */
3538 #define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */
3539 #define CAN_F3R2_FB14_Pos      (14U)
3540 #define CAN_F3R2_FB14_Msk      (0x1UL << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */
3541 #define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */
3542 #define CAN_F3R2_FB15_Pos      (15U)
3543 #define CAN_F3R2_FB15_Msk      (0x1UL << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */
3544 #define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */
3545 #define CAN_F3R2_FB16_Pos      (16U)
3546 #define CAN_F3R2_FB16_Msk      (0x1UL << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */
3547 #define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */
3548 #define CAN_F3R2_FB17_Pos      (17U)
3549 #define CAN_F3R2_FB17_Msk      (0x1UL << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */
3550 #define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */
3551 #define CAN_F3R2_FB18_Pos      (18U)
3552 #define CAN_F3R2_FB18_Msk      (0x1UL << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */
3553 #define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */
3554 #define CAN_F3R2_FB19_Pos      (19U)
3555 #define CAN_F3R2_FB19_Msk      (0x1UL << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */
3556 #define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */
3557 #define CAN_F3R2_FB20_Pos      (20U)
3558 #define CAN_F3R2_FB20_Msk      (0x1UL << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */
3559 #define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */
3560 #define CAN_F3R2_FB21_Pos      (21U)
3561 #define CAN_F3R2_FB21_Msk      (0x1UL << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */
3562 #define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */
3563 #define CAN_F3R2_FB22_Pos      (22U)
3564 #define CAN_F3R2_FB22_Msk      (0x1UL << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */
3565 #define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */
3566 #define CAN_F3R2_FB23_Pos      (23U)
3567 #define CAN_F3R2_FB23_Msk      (0x1UL << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */
3568 #define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */
3569 #define CAN_F3R2_FB24_Pos      (24U)
3570 #define CAN_F3R2_FB24_Msk      (0x1UL << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */
3571 #define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */
3572 #define CAN_F3R2_FB25_Pos      (25U)
3573 #define CAN_F3R2_FB25_Msk      (0x1UL << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */
3574 #define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */
3575 #define CAN_F3R2_FB26_Pos      (26U)
3576 #define CAN_F3R2_FB26_Msk      (0x1UL << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */
3577 #define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */
3578 #define CAN_F3R2_FB27_Pos      (27U)
3579 #define CAN_F3R2_FB27_Msk      (0x1UL << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */
3580 #define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */
3581 #define CAN_F3R2_FB28_Pos      (28U)
3582 #define CAN_F3R2_FB28_Msk      (0x1UL << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */
3583 #define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */
3584 #define CAN_F3R2_FB29_Pos      (29U)
3585 #define CAN_F3R2_FB29_Msk      (0x1UL << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */
3586 #define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */
3587 #define CAN_F3R2_FB30_Pos      (30U)
3588 #define CAN_F3R2_FB30_Msk      (0x1UL << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */
3589 #define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */
3590 #define CAN_F3R2_FB31_Pos      (31U)
3591 #define CAN_F3R2_FB31_Msk      (0x1UL << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */
3592 #define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */
3593 
3594 /*******************  Bit definition for CAN_F4R2 register  *******************/
3595 #define CAN_F4R2_FB0_Pos       (0U)
3596 #define CAN_F4R2_FB0_Msk       (0x1UL << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */
3597 #define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */
3598 #define CAN_F4R2_FB1_Pos       (1U)
3599 #define CAN_F4R2_FB1_Msk       (0x1UL << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */
3600 #define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */
3601 #define CAN_F4R2_FB2_Pos       (2U)
3602 #define CAN_F4R2_FB2_Msk       (0x1UL << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */
3603 #define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */
3604 #define CAN_F4R2_FB3_Pos       (3U)
3605 #define CAN_F4R2_FB3_Msk       (0x1UL << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */
3606 #define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */
3607 #define CAN_F4R2_FB4_Pos       (4U)
3608 #define CAN_F4R2_FB4_Msk       (0x1UL << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */
3609 #define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */
3610 #define CAN_F4R2_FB5_Pos       (5U)
3611 #define CAN_F4R2_FB5_Msk       (0x1UL << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */
3612 #define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */
3613 #define CAN_F4R2_FB6_Pos       (6U)
3614 #define CAN_F4R2_FB6_Msk       (0x1UL << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */
3615 #define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */
3616 #define CAN_F4R2_FB7_Pos       (7U)
3617 #define CAN_F4R2_FB7_Msk       (0x1UL << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */
3618 #define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */
3619 #define CAN_F4R2_FB8_Pos       (8U)
3620 #define CAN_F4R2_FB8_Msk       (0x1UL << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */
3621 #define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */
3622 #define CAN_F4R2_FB9_Pos       (9U)
3623 #define CAN_F4R2_FB9_Msk       (0x1UL << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */
3624 #define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */
3625 #define CAN_F4R2_FB10_Pos      (10U)
3626 #define CAN_F4R2_FB10_Msk      (0x1UL << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */
3627 #define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */
3628 #define CAN_F4R2_FB11_Pos      (11U)
3629 #define CAN_F4R2_FB11_Msk      (0x1UL << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */
3630 #define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */
3631 #define CAN_F4R2_FB12_Pos      (12U)
3632 #define CAN_F4R2_FB12_Msk      (0x1UL << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */
3633 #define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */
3634 #define CAN_F4R2_FB13_Pos      (13U)
3635 #define CAN_F4R2_FB13_Msk      (0x1UL << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */
3636 #define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */
3637 #define CAN_F4R2_FB14_Pos      (14U)
3638 #define CAN_F4R2_FB14_Msk      (0x1UL << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */
3639 #define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */
3640 #define CAN_F4R2_FB15_Pos      (15U)
3641 #define CAN_F4R2_FB15_Msk      (0x1UL << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */
3642 #define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */
3643 #define CAN_F4R2_FB16_Pos      (16U)
3644 #define CAN_F4R2_FB16_Msk      (0x1UL << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */
3645 #define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */
3646 #define CAN_F4R2_FB17_Pos      (17U)
3647 #define CAN_F4R2_FB17_Msk      (0x1UL << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */
3648 #define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */
3649 #define CAN_F4R2_FB18_Pos      (18U)
3650 #define CAN_F4R2_FB18_Msk      (0x1UL << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */
3651 #define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */
3652 #define CAN_F4R2_FB19_Pos      (19U)
3653 #define CAN_F4R2_FB19_Msk      (0x1UL << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */
3654 #define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */
3655 #define CAN_F4R2_FB20_Pos      (20U)
3656 #define CAN_F4R2_FB20_Msk      (0x1UL << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */
3657 #define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */
3658 #define CAN_F4R2_FB21_Pos      (21U)
3659 #define CAN_F4R2_FB21_Msk      (0x1UL << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */
3660 #define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */
3661 #define CAN_F4R2_FB22_Pos      (22U)
3662 #define CAN_F4R2_FB22_Msk      (0x1UL << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */
3663 #define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */
3664 #define CAN_F4R2_FB23_Pos      (23U)
3665 #define CAN_F4R2_FB23_Msk      (0x1UL << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */
3666 #define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */
3667 #define CAN_F4R2_FB24_Pos      (24U)
3668 #define CAN_F4R2_FB24_Msk      (0x1UL << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */
3669 #define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */
3670 #define CAN_F4R2_FB25_Pos      (25U)
3671 #define CAN_F4R2_FB25_Msk      (0x1UL << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */
3672 #define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */
3673 #define CAN_F4R2_FB26_Pos      (26U)
3674 #define CAN_F4R2_FB26_Msk      (0x1UL << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */
3675 #define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */
3676 #define CAN_F4R2_FB27_Pos      (27U)
3677 #define CAN_F4R2_FB27_Msk      (0x1UL << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */
3678 #define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */
3679 #define CAN_F4R2_FB28_Pos      (28U)
3680 #define CAN_F4R2_FB28_Msk      (0x1UL << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */
3681 #define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */
3682 #define CAN_F4R2_FB29_Pos      (29U)
3683 #define CAN_F4R2_FB29_Msk      (0x1UL << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */
3684 #define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */
3685 #define CAN_F4R2_FB30_Pos      (30U)
3686 #define CAN_F4R2_FB30_Msk      (0x1UL << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */
3687 #define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */
3688 #define CAN_F4R2_FB31_Pos      (31U)
3689 #define CAN_F4R2_FB31_Msk      (0x1UL << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */
3690 #define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */
3691 
3692 /*******************  Bit definition for CAN_F5R2 register  *******************/
3693 #define CAN_F5R2_FB0_Pos       (0U)
3694 #define CAN_F5R2_FB0_Msk       (0x1UL << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */
3695 #define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */
3696 #define CAN_F5R2_FB1_Pos       (1U)
3697 #define CAN_F5R2_FB1_Msk       (0x1UL << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */
3698 #define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */
3699 #define CAN_F5R2_FB2_Pos       (2U)
3700 #define CAN_F5R2_FB2_Msk       (0x1UL << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */
3701 #define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */
3702 #define CAN_F5R2_FB3_Pos       (3U)
3703 #define CAN_F5R2_FB3_Msk       (0x1UL << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */
3704 #define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */
3705 #define CAN_F5R2_FB4_Pos       (4U)
3706 #define CAN_F5R2_FB4_Msk       (0x1UL << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */
3707 #define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */
3708 #define CAN_F5R2_FB5_Pos       (5U)
3709 #define CAN_F5R2_FB5_Msk       (0x1UL << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */
3710 #define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */
3711 #define CAN_F5R2_FB6_Pos       (6U)
3712 #define CAN_F5R2_FB6_Msk       (0x1UL << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */
3713 #define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */
3714 #define CAN_F5R2_FB7_Pos       (7U)
3715 #define CAN_F5R2_FB7_Msk       (0x1UL << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */
3716 #define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */
3717 #define CAN_F5R2_FB8_Pos       (8U)
3718 #define CAN_F5R2_FB8_Msk       (0x1UL << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */
3719 #define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */
3720 #define CAN_F5R2_FB9_Pos       (9U)
3721 #define CAN_F5R2_FB9_Msk       (0x1UL << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */
3722 #define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */
3723 #define CAN_F5R2_FB10_Pos      (10U)
3724 #define CAN_F5R2_FB10_Msk      (0x1UL << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */
3725 #define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */
3726 #define CAN_F5R2_FB11_Pos      (11U)
3727 #define CAN_F5R2_FB11_Msk      (0x1UL << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */
3728 #define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */
3729 #define CAN_F5R2_FB12_Pos      (12U)
3730 #define CAN_F5R2_FB12_Msk      (0x1UL << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */
3731 #define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */
3732 #define CAN_F5R2_FB13_Pos      (13U)
3733 #define CAN_F5R2_FB13_Msk      (0x1UL << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */
3734 #define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */
3735 #define CAN_F5R2_FB14_Pos      (14U)
3736 #define CAN_F5R2_FB14_Msk      (0x1UL << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */
3737 #define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */
3738 #define CAN_F5R2_FB15_Pos      (15U)
3739 #define CAN_F5R2_FB15_Msk      (0x1UL << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */
3740 #define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */
3741 #define CAN_F5R2_FB16_Pos      (16U)
3742 #define CAN_F5R2_FB16_Msk      (0x1UL << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */
3743 #define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */
3744 #define CAN_F5R2_FB17_Pos      (17U)
3745 #define CAN_F5R2_FB17_Msk      (0x1UL << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */
3746 #define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */
3747 #define CAN_F5R2_FB18_Pos      (18U)
3748 #define CAN_F5R2_FB18_Msk      (0x1UL << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */
3749 #define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */
3750 #define CAN_F5R2_FB19_Pos      (19U)
3751 #define CAN_F5R2_FB19_Msk      (0x1UL << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */
3752 #define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */
3753 #define CAN_F5R2_FB20_Pos      (20U)
3754 #define CAN_F5R2_FB20_Msk      (0x1UL << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */
3755 #define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */
3756 #define CAN_F5R2_FB21_Pos      (21U)
3757 #define CAN_F5R2_FB21_Msk      (0x1UL << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */
3758 #define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */
3759 #define CAN_F5R2_FB22_Pos      (22U)
3760 #define CAN_F5R2_FB22_Msk      (0x1UL << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */
3761 #define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */
3762 #define CAN_F5R2_FB23_Pos      (23U)
3763 #define CAN_F5R2_FB23_Msk      (0x1UL << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */
3764 #define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */
3765 #define CAN_F5R2_FB24_Pos      (24U)
3766 #define CAN_F5R2_FB24_Msk      (0x1UL << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */
3767 #define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */
3768 #define CAN_F5R2_FB25_Pos      (25U)
3769 #define CAN_F5R2_FB25_Msk      (0x1UL << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */
3770 #define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */
3771 #define CAN_F5R2_FB26_Pos      (26U)
3772 #define CAN_F5R2_FB26_Msk      (0x1UL << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */
3773 #define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */
3774 #define CAN_F5R2_FB27_Pos      (27U)
3775 #define CAN_F5R2_FB27_Msk      (0x1UL << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */
3776 #define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */
3777 #define CAN_F5R2_FB28_Pos      (28U)
3778 #define CAN_F5R2_FB28_Msk      (0x1UL << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */
3779 #define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */
3780 #define CAN_F5R2_FB29_Pos      (29U)
3781 #define CAN_F5R2_FB29_Msk      (0x1UL << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */
3782 #define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */
3783 #define CAN_F5R2_FB30_Pos      (30U)
3784 #define CAN_F5R2_FB30_Msk      (0x1UL << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */
3785 #define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */
3786 #define CAN_F5R2_FB31_Pos      (31U)
3787 #define CAN_F5R2_FB31_Msk      (0x1UL << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */
3788 #define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */
3789 
3790 /*******************  Bit definition for CAN_F6R2 register  *******************/
3791 #define CAN_F6R2_FB0_Pos       (0U)
3792 #define CAN_F6R2_FB0_Msk       (0x1UL << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */
3793 #define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */
3794 #define CAN_F6R2_FB1_Pos       (1U)
3795 #define CAN_F6R2_FB1_Msk       (0x1UL << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */
3796 #define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */
3797 #define CAN_F6R2_FB2_Pos       (2U)
3798 #define CAN_F6R2_FB2_Msk       (0x1UL << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */
3799 #define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */
3800 #define CAN_F6R2_FB3_Pos       (3U)
3801 #define CAN_F6R2_FB3_Msk       (0x1UL << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */
3802 #define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */
3803 #define CAN_F6R2_FB4_Pos       (4U)
3804 #define CAN_F6R2_FB4_Msk       (0x1UL << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */
3805 #define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */
3806 #define CAN_F6R2_FB5_Pos       (5U)
3807 #define CAN_F6R2_FB5_Msk       (0x1UL << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */
3808 #define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */
3809 #define CAN_F6R2_FB6_Pos       (6U)
3810 #define CAN_F6R2_FB6_Msk       (0x1UL << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */
3811 #define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */
3812 #define CAN_F6R2_FB7_Pos       (7U)
3813 #define CAN_F6R2_FB7_Msk       (0x1UL << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */
3814 #define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */
3815 #define CAN_F6R2_FB8_Pos       (8U)
3816 #define CAN_F6R2_FB8_Msk       (0x1UL << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */
3817 #define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */
3818 #define CAN_F6R2_FB9_Pos       (9U)
3819 #define CAN_F6R2_FB9_Msk       (0x1UL << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */
3820 #define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */
3821 #define CAN_F6R2_FB10_Pos      (10U)
3822 #define CAN_F6R2_FB10_Msk      (0x1UL << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */
3823 #define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */
3824 #define CAN_F6R2_FB11_Pos      (11U)
3825 #define CAN_F6R2_FB11_Msk      (0x1UL << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */
3826 #define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */
3827 #define CAN_F6R2_FB12_Pos      (12U)
3828 #define CAN_F6R2_FB12_Msk      (0x1UL << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */
3829 #define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */
3830 #define CAN_F6R2_FB13_Pos      (13U)
3831 #define CAN_F6R2_FB13_Msk      (0x1UL << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */
3832 #define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */
3833 #define CAN_F6R2_FB14_Pos      (14U)
3834 #define CAN_F6R2_FB14_Msk      (0x1UL << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */
3835 #define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */
3836 #define CAN_F6R2_FB15_Pos      (15U)
3837 #define CAN_F6R2_FB15_Msk      (0x1UL << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */
3838 #define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */
3839 #define CAN_F6R2_FB16_Pos      (16U)
3840 #define CAN_F6R2_FB16_Msk      (0x1UL << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */
3841 #define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */
3842 #define CAN_F6R2_FB17_Pos      (17U)
3843 #define CAN_F6R2_FB17_Msk      (0x1UL << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */
3844 #define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */
3845 #define CAN_F6R2_FB18_Pos      (18U)
3846 #define CAN_F6R2_FB18_Msk      (0x1UL << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */
3847 #define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */
3848 #define CAN_F6R2_FB19_Pos      (19U)
3849 #define CAN_F6R2_FB19_Msk      (0x1UL << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */
3850 #define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */
3851 #define CAN_F6R2_FB20_Pos      (20U)
3852 #define CAN_F6R2_FB20_Msk      (0x1UL << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */
3853 #define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */
3854 #define CAN_F6R2_FB21_Pos      (21U)
3855 #define CAN_F6R2_FB21_Msk      (0x1UL << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */
3856 #define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */
3857 #define CAN_F6R2_FB22_Pos      (22U)
3858 #define CAN_F6R2_FB22_Msk      (0x1UL << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */
3859 #define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */
3860 #define CAN_F6R2_FB23_Pos      (23U)
3861 #define CAN_F6R2_FB23_Msk      (0x1UL << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */
3862 #define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */
3863 #define CAN_F6R2_FB24_Pos      (24U)
3864 #define CAN_F6R2_FB24_Msk      (0x1UL << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */
3865 #define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */
3866 #define CAN_F6R2_FB25_Pos      (25U)
3867 #define CAN_F6R2_FB25_Msk      (0x1UL << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */
3868 #define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */
3869 #define CAN_F6R2_FB26_Pos      (26U)
3870 #define CAN_F6R2_FB26_Msk      (0x1UL << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */
3871 #define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */
3872 #define CAN_F6R2_FB27_Pos      (27U)
3873 #define CAN_F6R2_FB27_Msk      (0x1UL << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */
3874 #define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */
3875 #define CAN_F6R2_FB28_Pos      (28U)
3876 #define CAN_F6R2_FB28_Msk      (0x1UL << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */
3877 #define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */
3878 #define CAN_F6R2_FB29_Pos      (29U)
3879 #define CAN_F6R2_FB29_Msk      (0x1UL << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */
3880 #define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */
3881 #define CAN_F6R2_FB30_Pos      (30U)
3882 #define CAN_F6R2_FB30_Msk      (0x1UL << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */
3883 #define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */
3884 #define CAN_F6R2_FB31_Pos      (31U)
3885 #define CAN_F6R2_FB31_Msk      (0x1UL << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */
3886 #define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */
3887 
3888 /*******************  Bit definition for CAN_F7R2 register  *******************/
3889 #define CAN_F7R2_FB0_Pos       (0U)
3890 #define CAN_F7R2_FB0_Msk       (0x1UL << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */
3891 #define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */
3892 #define CAN_F7R2_FB1_Pos       (1U)
3893 #define CAN_F7R2_FB1_Msk       (0x1UL << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */
3894 #define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */
3895 #define CAN_F7R2_FB2_Pos       (2U)
3896 #define CAN_F7R2_FB2_Msk       (0x1UL << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */
3897 #define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */
3898 #define CAN_F7R2_FB3_Pos       (3U)
3899 #define CAN_F7R2_FB3_Msk       (0x1UL << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */
3900 #define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */
3901 #define CAN_F7R2_FB4_Pos       (4U)
3902 #define CAN_F7R2_FB4_Msk       (0x1UL << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */
3903 #define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */
3904 #define CAN_F7R2_FB5_Pos       (5U)
3905 #define CAN_F7R2_FB5_Msk       (0x1UL << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */
3906 #define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */
3907 #define CAN_F7R2_FB6_Pos       (6U)
3908 #define CAN_F7R2_FB6_Msk       (0x1UL << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */
3909 #define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */
3910 #define CAN_F7R2_FB7_Pos       (7U)
3911 #define CAN_F7R2_FB7_Msk       (0x1UL << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */
3912 #define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */
3913 #define CAN_F7R2_FB8_Pos       (8U)
3914 #define CAN_F7R2_FB8_Msk       (0x1UL << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */
3915 #define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */
3916 #define CAN_F7R2_FB9_Pos       (9U)
3917 #define CAN_F7R2_FB9_Msk       (0x1UL << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */
3918 #define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */
3919 #define CAN_F7R2_FB10_Pos      (10U)
3920 #define CAN_F7R2_FB10_Msk      (0x1UL << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */
3921 #define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */
3922 #define CAN_F7R2_FB11_Pos      (11U)
3923 #define CAN_F7R2_FB11_Msk      (0x1UL << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */
3924 #define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */
3925 #define CAN_F7R2_FB12_Pos      (12U)
3926 #define CAN_F7R2_FB12_Msk      (0x1UL << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */
3927 #define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */
3928 #define CAN_F7R2_FB13_Pos      (13U)
3929 #define CAN_F7R2_FB13_Msk      (0x1UL << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */
3930 #define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */
3931 #define CAN_F7R2_FB14_Pos      (14U)
3932 #define CAN_F7R2_FB14_Msk      (0x1UL << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */
3933 #define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */
3934 #define CAN_F7R2_FB15_Pos      (15U)
3935 #define CAN_F7R2_FB15_Msk      (0x1UL << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */
3936 #define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */
3937 #define CAN_F7R2_FB16_Pos      (16U)
3938 #define CAN_F7R2_FB16_Msk      (0x1UL << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */
3939 #define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */
3940 #define CAN_F7R2_FB17_Pos      (17U)
3941 #define CAN_F7R2_FB17_Msk      (0x1UL << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */
3942 #define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */
3943 #define CAN_F7R2_FB18_Pos      (18U)
3944 #define CAN_F7R2_FB18_Msk      (0x1UL << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */
3945 #define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */
3946 #define CAN_F7R2_FB19_Pos      (19U)
3947 #define CAN_F7R2_FB19_Msk      (0x1UL << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */
3948 #define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */
3949 #define CAN_F7R2_FB20_Pos      (20U)
3950 #define CAN_F7R2_FB20_Msk      (0x1UL << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */
3951 #define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */
3952 #define CAN_F7R2_FB21_Pos      (21U)
3953 #define CAN_F7R2_FB21_Msk      (0x1UL << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */
3954 #define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */
3955 #define CAN_F7R2_FB22_Pos      (22U)
3956 #define CAN_F7R2_FB22_Msk      (0x1UL << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */
3957 #define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */
3958 #define CAN_F7R2_FB23_Pos      (23U)
3959 #define CAN_F7R2_FB23_Msk      (0x1UL << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */
3960 #define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */
3961 #define CAN_F7R2_FB24_Pos      (24U)
3962 #define CAN_F7R2_FB24_Msk      (0x1UL << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */
3963 #define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */
3964 #define CAN_F7R2_FB25_Pos      (25U)
3965 #define CAN_F7R2_FB25_Msk      (0x1UL << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */
3966 #define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */
3967 #define CAN_F7R2_FB26_Pos      (26U)
3968 #define CAN_F7R2_FB26_Msk      (0x1UL << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */
3969 #define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */
3970 #define CAN_F7R2_FB27_Pos      (27U)
3971 #define CAN_F7R2_FB27_Msk      (0x1UL << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */
3972 #define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */
3973 #define CAN_F7R2_FB28_Pos      (28U)
3974 #define CAN_F7R2_FB28_Msk      (0x1UL << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */
3975 #define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */
3976 #define CAN_F7R2_FB29_Pos      (29U)
3977 #define CAN_F7R2_FB29_Msk      (0x1UL << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */
3978 #define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */
3979 #define CAN_F7R2_FB30_Pos      (30U)
3980 #define CAN_F7R2_FB30_Msk      (0x1UL << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */
3981 #define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */
3982 #define CAN_F7R2_FB31_Pos      (31U)
3983 #define CAN_F7R2_FB31_Msk      (0x1UL << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */
3984 #define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */
3985 
3986 /*******************  Bit definition for CAN_F8R2 register  *******************/
3987 #define CAN_F8R2_FB0_Pos       (0U)
3988 #define CAN_F8R2_FB0_Msk       (0x1UL << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */
3989 #define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */
3990 #define CAN_F8R2_FB1_Pos       (1U)
3991 #define CAN_F8R2_FB1_Msk       (0x1UL << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */
3992 #define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */
3993 #define CAN_F8R2_FB2_Pos       (2U)
3994 #define CAN_F8R2_FB2_Msk       (0x1UL << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */
3995 #define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */
3996 #define CAN_F8R2_FB3_Pos       (3U)
3997 #define CAN_F8R2_FB3_Msk       (0x1UL << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */
3998 #define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */
3999 #define CAN_F8R2_FB4_Pos       (4U)
4000 #define CAN_F8R2_FB4_Msk       (0x1UL << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */
4001 #define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */
4002 #define CAN_F8R2_FB5_Pos       (5U)
4003 #define CAN_F8R2_FB5_Msk       (0x1UL << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */
4004 #define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */
4005 #define CAN_F8R2_FB6_Pos       (6U)
4006 #define CAN_F8R2_FB6_Msk       (0x1UL << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */
4007 #define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */
4008 #define CAN_F8R2_FB7_Pos       (7U)
4009 #define CAN_F8R2_FB7_Msk       (0x1UL << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */
4010 #define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */
4011 #define CAN_F8R2_FB8_Pos       (8U)
4012 #define CAN_F8R2_FB8_Msk       (0x1UL << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */
4013 #define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */
4014 #define CAN_F8R2_FB9_Pos       (9U)
4015 #define CAN_F8R2_FB9_Msk       (0x1UL << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */
4016 #define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */
4017 #define CAN_F8R2_FB10_Pos      (10U)
4018 #define CAN_F8R2_FB10_Msk      (0x1UL << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */
4019 #define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */
4020 #define CAN_F8R2_FB11_Pos      (11U)
4021 #define CAN_F8R2_FB11_Msk      (0x1UL << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */
4022 #define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */
4023 #define CAN_F8R2_FB12_Pos      (12U)
4024 #define CAN_F8R2_FB12_Msk      (0x1UL << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */
4025 #define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */
4026 #define CAN_F8R2_FB13_Pos      (13U)
4027 #define CAN_F8R2_FB13_Msk      (0x1UL << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */
4028 #define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */
4029 #define CAN_F8R2_FB14_Pos      (14U)
4030 #define CAN_F8R2_FB14_Msk      (0x1UL << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */
4031 #define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */
4032 #define CAN_F8R2_FB15_Pos      (15U)
4033 #define CAN_F8R2_FB15_Msk      (0x1UL << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */
4034 #define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */
4035 #define CAN_F8R2_FB16_Pos      (16U)
4036 #define CAN_F8R2_FB16_Msk      (0x1UL << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */
4037 #define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */
4038 #define CAN_F8R2_FB17_Pos      (17U)
4039 #define CAN_F8R2_FB17_Msk      (0x1UL << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */
4040 #define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */
4041 #define CAN_F8R2_FB18_Pos      (18U)
4042 #define CAN_F8R2_FB18_Msk      (0x1UL << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */
4043 #define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */
4044 #define CAN_F8R2_FB19_Pos      (19U)
4045 #define CAN_F8R2_FB19_Msk      (0x1UL << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */
4046 #define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */
4047 #define CAN_F8R2_FB20_Pos      (20U)
4048 #define CAN_F8R2_FB20_Msk      (0x1UL << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */
4049 #define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */
4050 #define CAN_F8R2_FB21_Pos      (21U)
4051 #define CAN_F8R2_FB21_Msk      (0x1UL << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */
4052 #define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */
4053 #define CAN_F8R2_FB22_Pos      (22U)
4054 #define CAN_F8R2_FB22_Msk      (0x1UL << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */
4055 #define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */
4056 #define CAN_F8R2_FB23_Pos      (23U)
4057 #define CAN_F8R2_FB23_Msk      (0x1UL << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */
4058 #define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */
4059 #define CAN_F8R2_FB24_Pos      (24U)
4060 #define CAN_F8R2_FB24_Msk      (0x1UL << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */
4061 #define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */
4062 #define CAN_F8R2_FB25_Pos      (25U)
4063 #define CAN_F8R2_FB25_Msk      (0x1UL << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */
4064 #define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */
4065 #define CAN_F8R2_FB26_Pos      (26U)
4066 #define CAN_F8R2_FB26_Msk      (0x1UL << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */
4067 #define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */
4068 #define CAN_F8R2_FB27_Pos      (27U)
4069 #define CAN_F8R2_FB27_Msk      (0x1UL << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */
4070 #define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */
4071 #define CAN_F8R2_FB28_Pos      (28U)
4072 #define CAN_F8R2_FB28_Msk      (0x1UL << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */
4073 #define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */
4074 #define CAN_F8R2_FB29_Pos      (29U)
4075 #define CAN_F8R2_FB29_Msk      (0x1UL << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */
4076 #define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */
4077 #define CAN_F8R2_FB30_Pos      (30U)
4078 #define CAN_F8R2_FB30_Msk      (0x1UL << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */
4079 #define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */
4080 #define CAN_F8R2_FB31_Pos      (31U)
4081 #define CAN_F8R2_FB31_Msk      (0x1UL << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */
4082 #define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */
4083 
4084 /*******************  Bit definition for CAN_F9R2 register  *******************/
4085 #define CAN_F9R2_FB0_Pos       (0U)
4086 #define CAN_F9R2_FB0_Msk       (0x1UL << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */
4087 #define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */
4088 #define CAN_F9R2_FB1_Pos       (1U)
4089 #define CAN_F9R2_FB1_Msk       (0x1UL << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */
4090 #define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */
4091 #define CAN_F9R2_FB2_Pos       (2U)
4092 #define CAN_F9R2_FB2_Msk       (0x1UL << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */
4093 #define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */
4094 #define CAN_F9R2_FB3_Pos       (3U)
4095 #define CAN_F9R2_FB3_Msk       (0x1UL << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */
4096 #define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */
4097 #define CAN_F9R2_FB4_Pos       (4U)
4098 #define CAN_F9R2_FB4_Msk       (0x1UL << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */
4099 #define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */
4100 #define CAN_F9R2_FB5_Pos       (5U)
4101 #define CAN_F9R2_FB5_Msk       (0x1UL << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */
4102 #define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */
4103 #define CAN_F9R2_FB6_Pos       (6U)
4104 #define CAN_F9R2_FB6_Msk       (0x1UL << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */
4105 #define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */
4106 #define CAN_F9R2_FB7_Pos       (7U)
4107 #define CAN_F9R2_FB7_Msk       (0x1UL << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */
4108 #define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */
4109 #define CAN_F9R2_FB8_Pos       (8U)
4110 #define CAN_F9R2_FB8_Msk       (0x1UL << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */
4111 #define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */
4112 #define CAN_F9R2_FB9_Pos       (9U)
4113 #define CAN_F9R2_FB9_Msk       (0x1UL << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */
4114 #define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */
4115 #define CAN_F9R2_FB10_Pos      (10U)
4116 #define CAN_F9R2_FB10_Msk      (0x1UL << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */
4117 #define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */
4118 #define CAN_F9R2_FB11_Pos      (11U)
4119 #define CAN_F9R2_FB11_Msk      (0x1UL << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */
4120 #define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */
4121 #define CAN_F9R2_FB12_Pos      (12U)
4122 #define CAN_F9R2_FB12_Msk      (0x1UL << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */
4123 #define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */
4124 #define CAN_F9R2_FB13_Pos      (13U)
4125 #define CAN_F9R2_FB13_Msk      (0x1UL << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */
4126 #define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */
4127 #define CAN_F9R2_FB14_Pos      (14U)
4128 #define CAN_F9R2_FB14_Msk      (0x1UL << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */
4129 #define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */
4130 #define CAN_F9R2_FB15_Pos      (15U)
4131 #define CAN_F9R2_FB15_Msk      (0x1UL << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */
4132 #define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */
4133 #define CAN_F9R2_FB16_Pos      (16U)
4134 #define CAN_F9R2_FB16_Msk      (0x1UL << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */
4135 #define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */
4136 #define CAN_F9R2_FB17_Pos      (17U)
4137 #define CAN_F9R2_FB17_Msk      (0x1UL << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */
4138 #define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */
4139 #define CAN_F9R2_FB18_Pos      (18U)
4140 #define CAN_F9R2_FB18_Msk      (0x1UL << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */
4141 #define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */
4142 #define CAN_F9R2_FB19_Pos      (19U)
4143 #define CAN_F9R2_FB19_Msk      (0x1UL << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */
4144 #define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */
4145 #define CAN_F9R2_FB20_Pos      (20U)
4146 #define CAN_F9R2_FB20_Msk      (0x1UL << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */
4147 #define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */
4148 #define CAN_F9R2_FB21_Pos      (21U)
4149 #define CAN_F9R2_FB21_Msk      (0x1UL << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */
4150 #define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */
4151 #define CAN_F9R2_FB22_Pos      (22U)
4152 #define CAN_F9R2_FB22_Msk      (0x1UL << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */
4153 #define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */
4154 #define CAN_F9R2_FB23_Pos      (23U)
4155 #define CAN_F9R2_FB23_Msk      (0x1UL << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */
4156 #define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */
4157 #define CAN_F9R2_FB24_Pos      (24U)
4158 #define CAN_F9R2_FB24_Msk      (0x1UL << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */
4159 #define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */
4160 #define CAN_F9R2_FB25_Pos      (25U)
4161 #define CAN_F9R2_FB25_Msk      (0x1UL << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */
4162 #define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */
4163 #define CAN_F9R2_FB26_Pos      (26U)
4164 #define CAN_F9R2_FB26_Msk      (0x1UL << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */
4165 #define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */
4166 #define CAN_F9R2_FB27_Pos      (27U)
4167 #define CAN_F9R2_FB27_Msk      (0x1UL << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */
4168 #define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */
4169 #define CAN_F9R2_FB28_Pos      (28U)
4170 #define CAN_F9R2_FB28_Msk      (0x1UL << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */
4171 #define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */
4172 #define CAN_F9R2_FB29_Pos      (29U)
4173 #define CAN_F9R2_FB29_Msk      (0x1UL << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */
4174 #define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */
4175 #define CAN_F9R2_FB30_Pos      (30U)
4176 #define CAN_F9R2_FB30_Msk      (0x1UL << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */
4177 #define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */
4178 #define CAN_F9R2_FB31_Pos      (31U)
4179 #define CAN_F9R2_FB31_Msk      (0x1UL << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */
4180 #define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */
4181 
4182 /*******************  Bit definition for CAN_F10R2 register  ******************/
4183 #define CAN_F10R2_FB0_Pos      (0U)
4184 #define CAN_F10R2_FB0_Msk      (0x1UL << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */
4185 #define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */
4186 #define CAN_F10R2_FB1_Pos      (1U)
4187 #define CAN_F10R2_FB1_Msk      (0x1UL << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */
4188 #define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */
4189 #define CAN_F10R2_FB2_Pos      (2U)
4190 #define CAN_F10R2_FB2_Msk      (0x1UL << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */
4191 #define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */
4192 #define CAN_F10R2_FB3_Pos      (3U)
4193 #define CAN_F10R2_FB3_Msk      (0x1UL << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */
4194 #define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */
4195 #define CAN_F10R2_FB4_Pos      (4U)
4196 #define CAN_F10R2_FB4_Msk      (0x1UL << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */
4197 #define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */
4198 #define CAN_F10R2_FB5_Pos      (5U)
4199 #define CAN_F10R2_FB5_Msk      (0x1UL << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */
4200 #define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */
4201 #define CAN_F10R2_FB6_Pos      (6U)
4202 #define CAN_F10R2_FB6_Msk      (0x1UL << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */
4203 #define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */
4204 #define CAN_F10R2_FB7_Pos      (7U)
4205 #define CAN_F10R2_FB7_Msk      (0x1UL << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */
4206 #define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */
4207 #define CAN_F10R2_FB8_Pos      (8U)
4208 #define CAN_F10R2_FB8_Msk      (0x1UL << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */
4209 #define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */
4210 #define CAN_F10R2_FB9_Pos      (9U)
4211 #define CAN_F10R2_FB9_Msk      (0x1UL << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */
4212 #define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */
4213 #define CAN_F10R2_FB10_Pos     (10U)
4214 #define CAN_F10R2_FB10_Msk     (0x1UL << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */
4215 #define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */
4216 #define CAN_F10R2_FB11_Pos     (11U)
4217 #define CAN_F10R2_FB11_Msk     (0x1UL << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */
4218 #define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */
4219 #define CAN_F10R2_FB12_Pos     (12U)
4220 #define CAN_F10R2_FB12_Msk     (0x1UL << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */
4221 #define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */
4222 #define CAN_F10R2_FB13_Pos     (13U)
4223 #define CAN_F10R2_FB13_Msk     (0x1UL << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */
4224 #define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */
4225 #define CAN_F10R2_FB14_Pos     (14U)
4226 #define CAN_F10R2_FB14_Msk     (0x1UL << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */
4227 #define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */
4228 #define CAN_F10R2_FB15_Pos     (15U)
4229 #define CAN_F10R2_FB15_Msk     (0x1UL << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */
4230 #define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */
4231 #define CAN_F10R2_FB16_Pos     (16U)
4232 #define CAN_F10R2_FB16_Msk     (0x1UL << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */
4233 #define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */
4234 #define CAN_F10R2_FB17_Pos     (17U)
4235 #define CAN_F10R2_FB17_Msk     (0x1UL << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */
4236 #define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */
4237 #define CAN_F10R2_FB18_Pos     (18U)
4238 #define CAN_F10R2_FB18_Msk     (0x1UL << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */
4239 #define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */
4240 #define CAN_F10R2_FB19_Pos     (19U)
4241 #define CAN_F10R2_FB19_Msk     (0x1UL << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */
4242 #define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */
4243 #define CAN_F10R2_FB20_Pos     (20U)
4244 #define CAN_F10R2_FB20_Msk     (0x1UL << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */
4245 #define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */
4246 #define CAN_F10R2_FB21_Pos     (21U)
4247 #define CAN_F10R2_FB21_Msk     (0x1UL << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */
4248 #define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */
4249 #define CAN_F10R2_FB22_Pos     (22U)
4250 #define CAN_F10R2_FB22_Msk     (0x1UL << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */
4251 #define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */
4252 #define CAN_F10R2_FB23_Pos     (23U)
4253 #define CAN_F10R2_FB23_Msk     (0x1UL << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */
4254 #define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */
4255 #define CAN_F10R2_FB24_Pos     (24U)
4256 #define CAN_F10R2_FB24_Msk     (0x1UL << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */
4257 #define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */
4258 #define CAN_F10R2_FB25_Pos     (25U)
4259 #define CAN_F10R2_FB25_Msk     (0x1UL << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */
4260 #define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */
4261 #define CAN_F10R2_FB26_Pos     (26U)
4262 #define CAN_F10R2_FB26_Msk     (0x1UL << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */
4263 #define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */
4264 #define CAN_F10R2_FB27_Pos     (27U)
4265 #define CAN_F10R2_FB27_Msk     (0x1UL << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */
4266 #define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */
4267 #define CAN_F10R2_FB28_Pos     (28U)
4268 #define CAN_F10R2_FB28_Msk     (0x1UL << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */
4269 #define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */
4270 #define CAN_F10R2_FB29_Pos     (29U)
4271 #define CAN_F10R2_FB29_Msk     (0x1UL << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */
4272 #define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */
4273 #define CAN_F10R2_FB30_Pos     (30U)
4274 #define CAN_F10R2_FB30_Msk     (0x1UL << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */
4275 #define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */
4276 #define CAN_F10R2_FB31_Pos     (31U)
4277 #define CAN_F10R2_FB31_Msk     (0x1UL << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */
4278 #define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */
4279 
4280 /*******************  Bit definition for CAN_F11R2 register  ******************/
4281 #define CAN_F11R2_FB0_Pos      (0U)
4282 #define CAN_F11R2_FB0_Msk      (0x1UL << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */
4283 #define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */
4284 #define CAN_F11R2_FB1_Pos      (1U)
4285 #define CAN_F11R2_FB1_Msk      (0x1UL << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */
4286 #define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */
4287 #define CAN_F11R2_FB2_Pos      (2U)
4288 #define CAN_F11R2_FB2_Msk      (0x1UL << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */
4289 #define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */
4290 #define CAN_F11R2_FB3_Pos      (3U)
4291 #define CAN_F11R2_FB3_Msk      (0x1UL << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */
4292 #define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */
4293 #define CAN_F11R2_FB4_Pos      (4U)
4294 #define CAN_F11R2_FB4_Msk      (0x1UL << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */
4295 #define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */
4296 #define CAN_F11R2_FB5_Pos      (5U)
4297 #define CAN_F11R2_FB5_Msk      (0x1UL << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */
4298 #define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */
4299 #define CAN_F11R2_FB6_Pos      (6U)
4300 #define CAN_F11R2_FB6_Msk      (0x1UL << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */
4301 #define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */
4302 #define CAN_F11R2_FB7_Pos      (7U)
4303 #define CAN_F11R2_FB7_Msk      (0x1UL << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */
4304 #define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */
4305 #define CAN_F11R2_FB8_Pos      (8U)
4306 #define CAN_F11R2_FB8_Msk      (0x1UL << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */
4307 #define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */
4308 #define CAN_F11R2_FB9_Pos      (9U)
4309 #define CAN_F11R2_FB9_Msk      (0x1UL << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */
4310 #define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */
4311 #define CAN_F11R2_FB10_Pos     (10U)
4312 #define CAN_F11R2_FB10_Msk     (0x1UL << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */
4313 #define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */
4314 #define CAN_F11R2_FB11_Pos     (11U)
4315 #define CAN_F11R2_FB11_Msk     (0x1UL << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */
4316 #define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */
4317 #define CAN_F11R2_FB12_Pos     (12U)
4318 #define CAN_F11R2_FB12_Msk     (0x1UL << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */
4319 #define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */
4320 #define CAN_F11R2_FB13_Pos     (13U)
4321 #define CAN_F11R2_FB13_Msk     (0x1UL << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */
4322 #define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */
4323 #define CAN_F11R2_FB14_Pos     (14U)
4324 #define CAN_F11R2_FB14_Msk     (0x1UL << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */
4325 #define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */
4326 #define CAN_F11R2_FB15_Pos     (15U)
4327 #define CAN_F11R2_FB15_Msk     (0x1UL << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */
4328 #define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */
4329 #define CAN_F11R2_FB16_Pos     (16U)
4330 #define CAN_F11R2_FB16_Msk     (0x1UL << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */
4331 #define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */
4332 #define CAN_F11R2_FB17_Pos     (17U)
4333 #define CAN_F11R2_FB17_Msk     (0x1UL << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */
4334 #define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */
4335 #define CAN_F11R2_FB18_Pos     (18U)
4336 #define CAN_F11R2_FB18_Msk     (0x1UL << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */
4337 #define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */
4338 #define CAN_F11R2_FB19_Pos     (19U)
4339 #define CAN_F11R2_FB19_Msk     (0x1UL << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */
4340 #define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */
4341 #define CAN_F11R2_FB20_Pos     (20U)
4342 #define CAN_F11R2_FB20_Msk     (0x1UL << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */
4343 #define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */
4344 #define CAN_F11R2_FB21_Pos     (21U)
4345 #define CAN_F11R2_FB21_Msk     (0x1UL << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */
4346 #define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */
4347 #define CAN_F11R2_FB22_Pos     (22U)
4348 #define CAN_F11R2_FB22_Msk     (0x1UL << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */
4349 #define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */
4350 #define CAN_F11R2_FB23_Pos     (23U)
4351 #define CAN_F11R2_FB23_Msk     (0x1UL << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */
4352 #define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */
4353 #define CAN_F11R2_FB24_Pos     (24U)
4354 #define CAN_F11R2_FB24_Msk     (0x1UL << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */
4355 #define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */
4356 #define CAN_F11R2_FB25_Pos     (25U)
4357 #define CAN_F11R2_FB25_Msk     (0x1UL << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */
4358 #define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */
4359 #define CAN_F11R2_FB26_Pos     (26U)
4360 #define CAN_F11R2_FB26_Msk     (0x1UL << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */
4361 #define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */
4362 #define CAN_F11R2_FB27_Pos     (27U)
4363 #define CAN_F11R2_FB27_Msk     (0x1UL << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */
4364 #define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */
4365 #define CAN_F11R2_FB28_Pos     (28U)
4366 #define CAN_F11R2_FB28_Msk     (0x1UL << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */
4367 #define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */
4368 #define CAN_F11R2_FB29_Pos     (29U)
4369 #define CAN_F11R2_FB29_Msk     (0x1UL << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */
4370 #define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */
4371 #define CAN_F11R2_FB30_Pos     (30U)
4372 #define CAN_F11R2_FB30_Msk     (0x1UL << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */
4373 #define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */
4374 #define CAN_F11R2_FB31_Pos     (31U)
4375 #define CAN_F11R2_FB31_Msk     (0x1UL << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */
4376 #define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */
4377 
4378 /*******************  Bit definition for CAN_F12R2 register  ******************/
4379 #define CAN_F12R2_FB0_Pos      (0U)
4380 #define CAN_F12R2_FB0_Msk      (0x1UL << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */
4381 #define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */
4382 #define CAN_F12R2_FB1_Pos      (1U)
4383 #define CAN_F12R2_FB1_Msk      (0x1UL << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */
4384 #define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */
4385 #define CAN_F12R2_FB2_Pos      (2U)
4386 #define CAN_F12R2_FB2_Msk      (0x1UL << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */
4387 #define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */
4388 #define CAN_F12R2_FB3_Pos      (3U)
4389 #define CAN_F12R2_FB3_Msk      (0x1UL << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */
4390 #define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */
4391 #define CAN_F12R2_FB4_Pos      (4U)
4392 #define CAN_F12R2_FB4_Msk      (0x1UL << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */
4393 #define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */
4394 #define CAN_F12R2_FB5_Pos      (5U)
4395 #define CAN_F12R2_FB5_Msk      (0x1UL << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */
4396 #define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */
4397 #define CAN_F12R2_FB6_Pos      (6U)
4398 #define CAN_F12R2_FB6_Msk      (0x1UL << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */
4399 #define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */
4400 #define CAN_F12R2_FB7_Pos      (7U)
4401 #define CAN_F12R2_FB7_Msk      (0x1UL << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */
4402 #define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */
4403 #define CAN_F12R2_FB8_Pos      (8U)
4404 #define CAN_F12R2_FB8_Msk      (0x1UL << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */
4405 #define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */
4406 #define CAN_F12R2_FB9_Pos      (9U)
4407 #define CAN_F12R2_FB9_Msk      (0x1UL << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */
4408 #define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */
4409 #define CAN_F12R2_FB10_Pos     (10U)
4410 #define CAN_F12R2_FB10_Msk     (0x1UL << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */
4411 #define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */
4412 #define CAN_F12R2_FB11_Pos     (11U)
4413 #define CAN_F12R2_FB11_Msk     (0x1UL << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */
4414 #define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */
4415 #define CAN_F12R2_FB12_Pos     (12U)
4416 #define CAN_F12R2_FB12_Msk     (0x1UL << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */
4417 #define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */
4418 #define CAN_F12R2_FB13_Pos     (13U)
4419 #define CAN_F12R2_FB13_Msk     (0x1UL << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */
4420 #define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */
4421 #define CAN_F12R2_FB14_Pos     (14U)
4422 #define CAN_F12R2_FB14_Msk     (0x1UL << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */
4423 #define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */
4424 #define CAN_F12R2_FB15_Pos     (15U)
4425 #define CAN_F12R2_FB15_Msk     (0x1UL << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */
4426 #define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */
4427 #define CAN_F12R2_FB16_Pos     (16U)
4428 #define CAN_F12R2_FB16_Msk     (0x1UL << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */
4429 #define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */
4430 #define CAN_F12R2_FB17_Pos     (17U)
4431 #define CAN_F12R2_FB17_Msk     (0x1UL << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */
4432 #define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */
4433 #define CAN_F12R2_FB18_Pos     (18U)
4434 #define CAN_F12R2_FB18_Msk     (0x1UL << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */
4435 #define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */
4436 #define CAN_F12R2_FB19_Pos     (19U)
4437 #define CAN_F12R2_FB19_Msk     (0x1UL << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */
4438 #define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */
4439 #define CAN_F12R2_FB20_Pos     (20U)
4440 #define CAN_F12R2_FB20_Msk     (0x1UL << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */
4441 #define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */
4442 #define CAN_F12R2_FB21_Pos     (21U)
4443 #define CAN_F12R2_FB21_Msk     (0x1UL << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */
4444 #define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */
4445 #define CAN_F12R2_FB22_Pos     (22U)
4446 #define CAN_F12R2_FB22_Msk     (0x1UL << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */
4447 #define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */
4448 #define CAN_F12R2_FB23_Pos     (23U)
4449 #define CAN_F12R2_FB23_Msk     (0x1UL << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */
4450 #define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */
4451 #define CAN_F12R2_FB24_Pos     (24U)
4452 #define CAN_F12R2_FB24_Msk     (0x1UL << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */
4453 #define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */
4454 #define CAN_F12R2_FB25_Pos     (25U)
4455 #define CAN_F12R2_FB25_Msk     (0x1UL << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */
4456 #define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */
4457 #define CAN_F12R2_FB26_Pos     (26U)
4458 #define CAN_F12R2_FB26_Msk     (0x1UL << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */
4459 #define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */
4460 #define CAN_F12R2_FB27_Pos     (27U)
4461 #define CAN_F12R2_FB27_Msk     (0x1UL << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */
4462 #define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */
4463 #define CAN_F12R2_FB28_Pos     (28U)
4464 #define CAN_F12R2_FB28_Msk     (0x1UL << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */
4465 #define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */
4466 #define CAN_F12R2_FB29_Pos     (29U)
4467 #define CAN_F12R2_FB29_Msk     (0x1UL << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */
4468 #define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */
4469 #define CAN_F12R2_FB30_Pos     (30U)
4470 #define CAN_F12R2_FB30_Msk     (0x1UL << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */
4471 #define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */
4472 #define CAN_F12R2_FB31_Pos     (31U)
4473 #define CAN_F12R2_FB31_Msk     (0x1UL << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */
4474 #define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */
4475 
4476 /*******************  Bit definition for CAN_F13R2 register  ******************/
4477 #define CAN_F13R2_FB0_Pos      (0U)
4478 #define CAN_F13R2_FB0_Msk      (0x1UL << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */
4479 #define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */
4480 #define CAN_F13R2_FB1_Pos      (1U)
4481 #define CAN_F13R2_FB1_Msk      (0x1UL << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */
4482 #define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */
4483 #define CAN_F13R2_FB2_Pos      (2U)
4484 #define CAN_F13R2_FB2_Msk      (0x1UL << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */
4485 #define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */
4486 #define CAN_F13R2_FB3_Pos      (3U)
4487 #define CAN_F13R2_FB3_Msk      (0x1UL << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */
4488 #define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */
4489 #define CAN_F13R2_FB4_Pos      (4U)
4490 #define CAN_F13R2_FB4_Msk      (0x1UL << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */
4491 #define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */
4492 #define CAN_F13R2_FB5_Pos      (5U)
4493 #define CAN_F13R2_FB5_Msk      (0x1UL << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */
4494 #define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */
4495 #define CAN_F13R2_FB6_Pos      (6U)
4496 #define CAN_F13R2_FB6_Msk      (0x1UL << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */
4497 #define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */
4498 #define CAN_F13R2_FB7_Pos      (7U)
4499 #define CAN_F13R2_FB7_Msk      (0x1UL << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */
4500 #define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */
4501 #define CAN_F13R2_FB8_Pos      (8U)
4502 #define CAN_F13R2_FB8_Msk      (0x1UL << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */
4503 #define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */
4504 #define CAN_F13R2_FB9_Pos      (9U)
4505 #define CAN_F13R2_FB9_Msk      (0x1UL << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */
4506 #define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */
4507 #define CAN_F13R2_FB10_Pos     (10U)
4508 #define CAN_F13R2_FB10_Msk     (0x1UL << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */
4509 #define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */
4510 #define CAN_F13R2_FB11_Pos     (11U)
4511 #define CAN_F13R2_FB11_Msk     (0x1UL << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */
4512 #define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */
4513 #define CAN_F13R2_FB12_Pos     (12U)
4514 #define CAN_F13R2_FB12_Msk     (0x1UL << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */
4515 #define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */
4516 #define CAN_F13R2_FB13_Pos     (13U)
4517 #define CAN_F13R2_FB13_Msk     (0x1UL << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */
4518 #define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */
4519 #define CAN_F13R2_FB14_Pos     (14U)
4520 #define CAN_F13R2_FB14_Msk     (0x1UL << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */
4521 #define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */
4522 #define CAN_F13R2_FB15_Pos     (15U)
4523 #define CAN_F13R2_FB15_Msk     (0x1UL << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */
4524 #define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */
4525 #define CAN_F13R2_FB16_Pos     (16U)
4526 #define CAN_F13R2_FB16_Msk     (0x1UL << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */
4527 #define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */
4528 #define CAN_F13R2_FB17_Pos     (17U)
4529 #define CAN_F13R2_FB17_Msk     (0x1UL << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */
4530 #define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */
4531 #define CAN_F13R2_FB18_Pos     (18U)
4532 #define CAN_F13R2_FB18_Msk     (0x1UL << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */
4533 #define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */
4534 #define CAN_F13R2_FB19_Pos     (19U)
4535 #define CAN_F13R2_FB19_Msk     (0x1UL << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */
4536 #define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */
4537 #define CAN_F13R2_FB20_Pos     (20U)
4538 #define CAN_F13R2_FB20_Msk     (0x1UL << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */
4539 #define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */
4540 #define CAN_F13R2_FB21_Pos     (21U)
4541 #define CAN_F13R2_FB21_Msk     (0x1UL << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */
4542 #define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */
4543 #define CAN_F13R2_FB22_Pos     (22U)
4544 #define CAN_F13R2_FB22_Msk     (0x1UL << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */
4545 #define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */
4546 #define CAN_F13R2_FB23_Pos     (23U)
4547 #define CAN_F13R2_FB23_Msk     (0x1UL << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */
4548 #define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */
4549 #define CAN_F13R2_FB24_Pos     (24U)
4550 #define CAN_F13R2_FB24_Msk     (0x1UL << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */
4551 #define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */
4552 #define CAN_F13R2_FB25_Pos     (25U)
4553 #define CAN_F13R2_FB25_Msk     (0x1UL << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */
4554 #define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */
4555 #define CAN_F13R2_FB26_Pos     (26U)
4556 #define CAN_F13R2_FB26_Msk     (0x1UL << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */
4557 #define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */
4558 #define CAN_F13R2_FB27_Pos     (27U)
4559 #define CAN_F13R2_FB27_Msk     (0x1UL << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */
4560 #define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */
4561 #define CAN_F13R2_FB28_Pos     (28U)
4562 #define CAN_F13R2_FB28_Msk     (0x1UL << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */
4563 #define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */
4564 #define CAN_F13R2_FB29_Pos     (29U)
4565 #define CAN_F13R2_FB29_Msk     (0x1UL << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */
4566 #define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */
4567 #define CAN_F13R2_FB30_Pos     (30U)
4568 #define CAN_F13R2_FB30_Msk     (0x1UL << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */
4569 #define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */
4570 #define CAN_F13R2_FB31_Pos     (31U)
4571 #define CAN_F13R2_FB31_Msk     (0x1UL << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */
4572 #define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */
4573 
4574 /* CAN filters Legacy aliases */
4575 #define CAN_FM1R_FBM14_Pos     (14U)
4576 #define CAN_FM1R_FBM14_Msk     (0x1UL << CAN_FM1R_FBM14_Pos)                    /*!< 0x00004000 */
4577 #define CAN_FM1R_FBM14         CAN_FM1R_FBM14_Msk                              /*!<Filter Init Mode bit 14 */
4578 #define CAN_FM1R_FBM15_Pos     (15U)
4579 #define CAN_FM1R_FBM15_Msk     (0x1UL << CAN_FM1R_FBM15_Pos)                    /*!< 0x00008000 */
4580 #define CAN_FM1R_FBM15         CAN_FM1R_FBM15_Msk                              /*!<Filter Init Mode bit 15 */
4581 #define CAN_FM1R_FBM16_Pos     (16U)
4582 #define CAN_FM1R_FBM16_Msk     (0x1UL << CAN_FM1R_FBM16_Pos)                    /*!< 0x00010000 */
4583 #define CAN_FM1R_FBM16         CAN_FM1R_FBM16_Msk                              /*!<Filter Init Mode bit 16 */
4584 #define CAN_FM1R_FBM17_Pos     (17U)
4585 #define CAN_FM1R_FBM17_Msk     (0x1UL << CAN_FM1R_FBM17_Pos)                    /*!< 0x00020000 */
4586 #define CAN_FM1R_FBM17         CAN_FM1R_FBM17_Msk                              /*!<Filter Init Mode bit 17 */
4587 #define CAN_FM1R_FBM18_Pos     (18U)
4588 #define CAN_FM1R_FBM18_Msk     (0x1UL << CAN_FM1R_FBM18_Pos)                    /*!< 0x00040000 */
4589 #define CAN_FM1R_FBM18         CAN_FM1R_FBM18_Msk                              /*!<Filter Init Mode bit 18 */
4590 #define CAN_FM1R_FBM19_Pos     (19U)
4591 #define CAN_FM1R_FBM19_Msk     (0x1UL << CAN_FM1R_FBM19_Pos)                    /*!< 0x00080000 */
4592 #define CAN_FM1R_FBM19         CAN_FM1R_FBM19_Msk                              /*!<Filter Init Mode bit 19 */
4593 #define CAN_FM1R_FBM20_Pos     (20U)
4594 #define CAN_FM1R_FBM20_Msk     (0x1UL << CAN_FM1R_FBM20_Pos)                    /*!< 0x00100000 */
4595 #define CAN_FM1R_FBM20         CAN_FM1R_FBM20_Msk                              /*!<Filter Init Mode bit 20 */
4596 #define CAN_FM1R_FBM21_Pos     (21U)
4597 #define CAN_FM1R_FBM21_Msk     (0x1UL << CAN_FM1R_FBM21_Pos)                    /*!< 0x00200000 */
4598 #define CAN_FM1R_FBM21         CAN_FM1R_FBM21_Msk                              /*!<Filter Init Mode bit 21 */
4599 #define CAN_FM1R_FBM22_Pos     (22U)
4600 #define CAN_FM1R_FBM22_Msk     (0x1UL << CAN_FM1R_FBM22_Pos)                    /*!< 0x00400000 */
4601 #define CAN_FM1R_FBM22         CAN_FM1R_FBM22_Msk                              /*!<Filter Init Mode bit 22 */
4602 #define CAN_FM1R_FBM23_Pos     (23U)
4603 #define CAN_FM1R_FBM23_Msk     (0x1UL << CAN_FM1R_FBM23_Pos)                    /*!< 0x00800000 */
4604 #define CAN_FM1R_FBM23         CAN_FM1R_FBM23_Msk                              /*!<Filter Init Mode bit 23 */
4605 #define CAN_FM1R_FBM24_Pos     (24U)
4606 #define CAN_FM1R_FBM24_Msk     (0x1UL << CAN_FM1R_FBM24_Pos)                    /*!< 0x01000000 */
4607 #define CAN_FM1R_FBM24         CAN_FM1R_FBM24_Msk                              /*!<Filter Init Mode bit 24 */
4608 #define CAN_FM1R_FBM25_Pos     (25U)
4609 #define CAN_FM1R_FBM25_Msk     (0x1UL << CAN_FM1R_FBM25_Pos)                    /*!< 0x02000000 */
4610 #define CAN_FM1R_FBM25         CAN_FM1R_FBM25_Msk                              /*!<Filter Init Mode bit 25 */
4611 #define CAN_FM1R_FBM26_Pos     (26U)
4612 #define CAN_FM1R_FBM26_Msk     (0x1UL << CAN_FM1R_FBM26_Pos)                    /*!< 0x04000000 */
4613 #define CAN_FM1R_FBM26         CAN_FM1R_FBM26_Msk                              /*!<Filter Init Mode bit 26 */
4614 #define CAN_FM1R_FBM27_Pos     (27U)
4615 #define CAN_FM1R_FBM27_Msk     (0x1UL << CAN_FM1R_FBM27_Pos)                    /*!< 0x08000000 */
4616 #define CAN_FM1R_FBM27         CAN_FM1R_FBM27_Msk                              /*!<Filter Init Mode bit 27 */
4617 
4618 #define CAN_FS1R_FSC14_Pos     (14U)
4619 #define CAN_FS1R_FSC14_Msk     (0x1UL << CAN_FS1R_FSC14_Pos)                    /*!< 0x00004000 */
4620 #define CAN_FS1R_FSC14         CAN_FS1R_FSC14_Msk                              /*!<Filter Scale Configuration bit 14 */
4621 #define CAN_FS1R_FSC15_Pos     (15U)
4622 #define CAN_FS1R_FSC15_Msk     (0x1UL << CAN_FS1R_FSC15_Pos)                    /*!< 0x00008000 */
4623 #define CAN_FS1R_FSC15         CAN_FS1R_FSC15_Msk                              /*!<Filter Scale Configuration bit 15 */
4624 #define CAN_FS1R_FSC16_Pos     (16U)
4625 #define CAN_FS1R_FSC16_Msk     (0x1UL << CAN_FS1R_FSC16_Pos)                    /*!< 0x00010000 */
4626 #define CAN_FS1R_FSC16         CAN_FS1R_FSC16_Msk                              /*!<Filter Scale Configuration bit 16 */
4627 #define CAN_FS1R_FSC17_Pos     (17U)
4628 #define CAN_FS1R_FSC17_Msk     (0x1UL << CAN_FS1R_FSC17_Pos)                    /*!< 0x00020000 */
4629 #define CAN_FS1R_FSC17         CAN_FS1R_FSC17_Msk                              /*!<Filter Scale Configuration bit 17 */
4630 #define CAN_FS1R_FSC18_Pos     (18U)
4631 #define CAN_FS1R_FSC18_Msk     (0x1UL << CAN_FS1R_FSC18_Pos)                    /*!< 0x00040000 */
4632 #define CAN_FS1R_FSC18         CAN_FS1R_FSC18_Msk                              /*!<Filter Scale Configuration bit 18 */
4633 #define CAN_FS1R_FSC19_Pos     (19U)
4634 #define CAN_FS1R_FSC19_Msk     (0x1UL << CAN_FS1R_FSC19_Pos)                    /*!< 0x00080000 */
4635 #define CAN_FS1R_FSC19         CAN_FS1R_FSC19_Msk                              /*!<Filter Scale Configuration bit 19 */
4636 #define CAN_FS1R_FSC20_Pos     (20U)
4637 #define CAN_FS1R_FSC20_Msk     (0x1UL << CAN_FS1R_FSC20_Pos)                    /*!< 0x00100000 */
4638 #define CAN_FS1R_FSC20         CAN_FS1R_FSC20_Msk                              /*!<Filter Scale Configuration bit 20 */
4639 #define CAN_FS1R_FSC21_Pos     (21U)
4640 #define CAN_FS1R_FSC21_Msk     (0x1UL << CAN_FS1R_FSC21_Pos)                    /*!< 0x00200000 */
4641 #define CAN_FS1R_FSC21         CAN_FS1R_FSC21_Msk                              /*!<Filter Scale Configuration bit 21 */
4642 #define CAN_FS1R_FSC22_Pos     (22U)
4643 #define CAN_FS1R_FSC22_Msk     (0x1UL << CAN_FS1R_FSC22_Pos)                    /*!< 0x00400000 */
4644 #define CAN_FS1R_FSC22         CAN_FS1R_FSC22_Msk                              /*!<Filter Scale Configuration bit 22 */
4645 #define CAN_FS1R_FSC23_Pos     (23U)
4646 #define CAN_FS1R_FSC23_Msk     (0x1UL << CAN_FS1R_FSC23_Pos)                    /*!< 0x00800000 */
4647 #define CAN_FS1R_FSC23         CAN_FS1R_FSC23_Msk                              /*!<Filter Scale Configuration bit 23 */
4648 #define CAN_FS1R_FSC24_Pos     (24U)
4649 #define CAN_FS1R_FSC24_Msk     (0x1UL << CAN_FS1R_FSC24_Pos)                    /*!< 0x01000000 */
4650 #define CAN_FS1R_FSC24         CAN_FS1R_FSC24_Msk                              /*!<Filter Scale Configuration bit 24 */
4651 #define CAN_FS1R_FSC25_Pos     (25U)
4652 #define CAN_FS1R_FSC25_Msk     (0x1UL << CAN_FS1R_FSC25_Pos)                    /*!< 0x02000000 */
4653 #define CAN_FS1R_FSC25         CAN_FS1R_FSC25_Msk                              /*!<Filter Scale Configuration bit 25 */
4654 #define CAN_FS1R_FSC26_Pos     (26U)
4655 #define CAN_FS1R_FSC26_Msk     (0x1UL << CAN_FS1R_FSC26_Pos)                    /*!< 0x04000000 */
4656 #define CAN_FS1R_FSC26         CAN_FS1R_FSC26_Msk                              /*!<Filter Scale Configuration bit 26 */
4657 #define CAN_FS1R_FSC27_Pos     (27U)
4658 #define CAN_FS1R_FSC27_Msk     (0x1UL << CAN_FS1R_FSC27_Pos)                    /*!< 0x08000000 */
4659 #define CAN_FS1R_FSC27         CAN_FS1R_FSC27_Msk                              /*!<Filter Scale Configuration bit 27 */
4660 
4661 #define CAN_FFA1R_FFA14_Pos    (14U)
4662 #define CAN_FFA1R_FFA14_Msk    (0x1UL << CAN_FFA1R_FFA14_Pos)                   /*!< 0x00004000 */
4663 #define CAN_FFA1R_FFA14        CAN_FFA1R_FFA14_Msk                             /*!<Filter FIFO Assignment bit 14 */
4664 #define CAN_FFA1R_FFA15_Pos    (15U)
4665 #define CAN_FFA1R_FFA15_Msk    (0x1UL << CAN_FFA1R_FFA15_Pos)                   /*!< 0x00008000 */
4666 #define CAN_FFA1R_FFA15        CAN_FFA1R_FFA15_Msk                             /*!<Filter FIFO Assignment bit 15 */
4667 #define CAN_FFA1R_FFA16_Pos    (16U)
4668 #define CAN_FFA1R_FFA16_Msk    (0x1UL << CAN_FFA1R_FFA16_Pos)                   /*!< 0x00010000 */
4669 #define CAN_FFA1R_FFA16        CAN_FFA1R_FFA16_Msk                             /*!<Filter FIFO Assignment bit 16 */
4670 #define CAN_FFA1R_FFA17_Pos    (17U)
4671 #define CAN_FFA1R_FFA17_Msk    (0x1UL << CAN_FFA1R_FFA17_Pos)                   /*!< 0x00020000 */
4672 #define CAN_FFA1R_FFA17        CAN_FFA1R_FFA17_Msk                             /*!<Filter FIFO Assignment bit 17 */
4673 #define CAN_FFA1R_FFA18_Pos    (18U)
4674 #define CAN_FFA1R_FFA18_Msk    (0x1UL << CAN_FFA1R_FFA18_Pos)                   /*!< 0x00040000 */
4675 #define CAN_FFA1R_FFA18        CAN_FFA1R_FFA18_Msk                             /*!<Filter FIFO Assignment bit 18 */
4676 #define CAN_FFA1R_FFA19_Pos    (19U)
4677 #define CAN_FFA1R_FFA19_Msk    (0x1UL << CAN_FFA1R_FFA19_Pos)                   /*!< 0x00080000 */
4678 #define CAN_FFA1R_FFA19        CAN_FFA1R_FFA19_Msk                             /*!<Filter FIFO Assignment bit 19 */
4679 #define CAN_FFA1R_FFA20_Pos    (20U)
4680 #define CAN_FFA1R_FFA20_Msk    (0x1UL << CAN_FFA1R_FFA20_Pos)                   /*!< 0x00100000 */
4681 #define CAN_FFA1R_FFA20        CAN_FFA1R_FFA20_Msk                             /*!<Filter FIFO Assignment bit 20 */
4682 #define CAN_FFA1R_FFA21_Pos    (21U)
4683 #define CAN_FFA1R_FFA21_Msk    (0x1UL << CAN_FFA1R_FFA21_Pos)                   /*!< 0x00200000 */
4684 #define CAN_FFA1R_FFA21        CAN_FFA1R_FFA21_Msk                             /*!<Filter FIFO Assignment bit 21 */
4685 #define CAN_FFA1R_FFA22_Pos    (22U)
4686 #define CAN_FFA1R_FFA22_Msk    (0x1UL << CAN_FFA1R_FFA22_Pos)                   /*!< 0x00400000 */
4687 #define CAN_FFA1R_FFA22        CAN_FFA1R_FFA22_Msk                             /*!<Filter FIFO Assignment bit 22 */
4688 #define CAN_FFA1R_FFA23_Pos    (23U)
4689 #define CAN_FFA1R_FFA23_Msk    (0x1UL << CAN_FFA1R_FFA23_Pos)                   /*!< 0x00800000 */
4690 #define CAN_FFA1R_FFA23        CAN_FFA1R_FFA23_Msk                             /*!<Filter FIFO Assignment bit 23 */
4691 #define CAN_FFA1R_FFA24_Pos    (24U)
4692 #define CAN_FFA1R_FFA24_Msk    (0x1UL << CAN_FFA1R_FFA24_Pos)                   /*!< 0x01000000 */
4693 #define CAN_FFA1R_FFA24        CAN_FFA1R_FFA24_Msk                             /*!<Filter FIFO Assignment bit 24 */
4694 #define CAN_FFA1R_FFA25_Pos    (25U)
4695 #define CAN_FFA1R_FFA25_Msk    (0x1UL << CAN_FFA1R_FFA25_Pos)                   /*!< 0x02000000 */
4696 #define CAN_FFA1R_FFA25        CAN_FFA1R_FFA25_Msk                             /*!<Filter FIFO Assignment bit 25 */
4697 #define CAN_FFA1R_FFA26_Pos    (26U)
4698 #define CAN_FFA1R_FFA26_Msk    (0x1UL << CAN_FFA1R_FFA26_Pos)                   /*!< 0x04000000 */
4699 #define CAN_FFA1R_FFA26        CAN_FFA1R_FFA26_Msk                             /*!<Filter FIFO Assignment bit 26 */
4700 #define CAN_FFA1R_FFA27_Pos    (27U)
4701 #define CAN_FFA1R_FFA27_Msk    (0x1UL << CAN_FFA1R_FFA27_Pos)                   /*!< 0x08000000 */
4702 #define CAN_FFA1R_FFA27        CAN_FFA1R_FFA27_Msk                             /*!<Filter FIFO Assignment bit 27 */
4703 
4704 #define CAN_FA1R_FACT14_Pos    (14U)
4705 #define CAN_FA1R_FACT14_Msk    (0x1UL << CAN_FA1R_FACT14_Pos)                   /*!< 0x00004000 */
4706 #define CAN_FA1R_FACT14        CAN_FA1R_FACT14_Msk                             /*!<Filter Active bit 14 */
4707 #define CAN_FA1R_FACT15_Pos    (15U)
4708 #define CAN_FA1R_FACT15_Msk    (0x1UL << CAN_FA1R_FACT15_Pos)                   /*!< 0x00008000 */
4709 #define CAN_FA1R_FACT15        CAN_FA1R_FACT15_Msk                             /*!<Filter Active bit 15 */
4710 #define CAN_FA1R_FACT16_Pos    (16U)
4711 #define CAN_FA1R_FACT16_Msk    (0x1UL << CAN_FA1R_FACT16_Pos)                   /*!< 0x00010000 */
4712 #define CAN_FA1R_FACT16        CAN_FA1R_FACT16_Msk                             /*!<Filter Active bit 16 */
4713 #define CAN_FA1R_FACT17_Pos    (17U)
4714 #define CAN_FA1R_FACT17_Msk    (0x1UL << CAN_FA1R_FACT17_Pos)                   /*!< 0x00020000 */
4715 #define CAN_FA1R_FACT17        CAN_FA1R_FACT17_Msk                             /*!<Filter Active bit 17 */
4716 #define CAN_FA1R_FACT18_Pos    (18U)
4717 #define CAN_FA1R_FACT18_Msk    (0x1UL << CAN_FA1R_FACT18_Pos)                   /*!< 0x00040000 */
4718 #define CAN_FA1R_FACT18        CAN_FA1R_FACT18_Msk                             /*!<Filter Active bit 18 */
4719 #define CAN_FA1R_FACT19_Pos    (19U)
4720 #define CAN_FA1R_FACT19_Msk    (0x1UL << CAN_FA1R_FACT19_Pos)                   /*!< 0x00080000 */
4721 #define CAN_FA1R_FACT19        CAN_FA1R_FACT19_Msk                             /*!<Filter Active bit 19 */
4722 #define CAN_FA1R_FACT20_Pos    (20U)
4723 #define CAN_FA1R_FACT20_Msk    (0x1UL << CAN_FA1R_FACT20_Pos)                   /*!< 0x00100000 */
4724 #define CAN_FA1R_FACT20        CAN_FA1R_FACT20_Msk                             /*!<Filter Active bit 20 */
4725 #define CAN_FA1R_FACT21_Pos    (21U)
4726 #define CAN_FA1R_FACT21_Msk    (0x1UL << CAN_FA1R_FACT21_Pos)                   /*!< 0x00200000 */
4727 #define CAN_FA1R_FACT21        CAN_FA1R_FACT21_Msk                             /*!<Filter Active bit 21 */
4728 #define CAN_FA1R_FACT22_Pos    (22U)
4729 #define CAN_FA1R_FACT22_Msk    (0x1UL << CAN_FA1R_FACT22_Pos)                   /*!< 0x00400000 */
4730 #define CAN_FA1R_FACT22        CAN_FA1R_FACT22_Msk                             /*!<Filter Active bit 22 */
4731 #define CAN_FA1R_FACT23_Pos    (23U)
4732 #define CAN_FA1R_FACT23_Msk    (0x1UL << CAN_FA1R_FACT23_Pos)                   /*!< 0x00800000 */
4733 #define CAN_FA1R_FACT23        CAN_FA1R_FACT23_Msk                             /*!<Filter Active bit 23 */
4734 #define CAN_FA1R_FACT24_Pos    (24U)
4735 #define CAN_FA1R_FACT24_Msk    (0x1UL << CAN_FA1R_FACT24_Pos)                   /*!< 0x01000000 */
4736 #define CAN_FA1R_FACT24        CAN_FA1R_FACT24_Msk                             /*!<Filter Active bit 24 */
4737 #define CAN_FA1R_FACT25_Pos    (25U)
4738 #define CAN_FA1R_FACT25_Msk    (0x1UL << CAN_FA1R_FACT25_Pos)                   /*!< 0x02000000 */
4739 #define CAN_FA1R_FACT25        CAN_FA1R_FACT25_Msk                             /*!<Filter Active bit 25 */
4740 #define CAN_FA1R_FACT26_Pos    (26U)
4741 #define CAN_FA1R_FACT26_Msk    (0x1UL << CAN_FA1R_FACT26_Pos)                   /*!< 0x04000000 */
4742 #define CAN_FA1R_FACT26        CAN_FA1R_FACT26_Msk                             /*!<Filter Active bit 26 */
4743 #define CAN_FA1R_FACT27_Pos    (27U)
4744 #define CAN_FA1R_FACT27_Msk    (0x1UL << CAN_FA1R_FACT27_Pos)                   /*!< 0x08000000 */
4745 #define CAN_FA1R_FACT27        CAN_FA1R_FACT27_Msk                             /*!<Filter Active bit 27 */
4746 
4747 /******************************************************************************/
4748 /*                                                                            */
4749 /*                                 HDMI-CEC (CEC)                             */
4750 /*                                                                            */
4751 /******************************************************************************/
4752 
4753 /*******************  Bit definition for CEC_CR register  *********************/
4754 #define CEC_CR_CECEN_Pos         (0U)
4755 #define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                    /*!< 0x00000001 */
4756 #define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                         */
4757 #define CEC_CR_TXSOM_Pos         (1U)
4758 #define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                    /*!< 0x00000002 */
4759 #define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message            */
4760 #define CEC_CR_TXEOM_Pos         (2U)
4761 #define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                    /*!< 0x00000004 */
4762 #define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message              */
4763 
4764 /*******************  Bit definition for CEC_CFGR register  *******************/
4765 #define CEC_CFGR_SFT_Pos         (0U)
4766 #define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                    /*!< 0x00000007 */
4767 #define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time               */
4768 #define CEC_CFGR_RXTOL_Pos       (3U)
4769 #define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                  /*!< 0x00000008 */
4770 #define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                      */
4771 #define CEC_CFGR_BRESTP_Pos      (4U)
4772 #define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                 /*!< 0x00000010 */
4773 #define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                        */
4774 #define CEC_CFGR_BREGEN_Pos      (5U)
4775 #define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                 /*!< 0x00000020 */
4776 #define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation    */
4777 #define CEC_CFGR_LBPEGEN_Pos     (6U)
4778 #define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)                /*!< 0x00000040 */
4779 #define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error gener.   */
4780 #define CEC_CFGR_BRDNOGEN_Pos    (7U)
4781 #define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)               /*!< 0x00000080 */
4782 #define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No Error generation  */
4783 #define CEC_CFGR_SFTOPT_Pos      (8U)
4784 #define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                 /*!< 0x00000100 */
4785 #define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional      */
4786 #define CEC_CFGR_OAR_Pos         (16U)
4787 #define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                 /*!< 0x7FFF0000 */
4788 #define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                    */
4789 #define CEC_CFGR_LSTN_Pos        (31U)
4790 #define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                   /*!< 0x80000000 */
4791 #define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                    */
4792 
4793 /*******************  Bit definition for CEC_TXDR register  *******************/
4794 #define CEC_TXDR_TXD_Pos         (0U)
4795 #define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                   /*!< 0x000000FF */
4796 #define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                        */
4797 
4798 /*******************  Bit definition for CEC_RXDR register  *******************/
4799 #define CEC_RXDR_RXD_Pos         (0U)
4800 #define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                   /*!< 0x000000FF */
4801 #define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                        */
4802 /* Legacy aliases */
4803 #define CEC_TXDR_RXD_Pos         CEC_RXDR_RXD_Pos
4804 #define CEC_TXDR_RXD_Msk         CEC_RXDR_RXD_Msk
4805 #define CEC_TXDR_RXD             CEC_RXDR_RXD
4806 /*******************  Bit definition for CEC_ISR register  ********************/
4807 #define CEC_ISR_RXBR_Pos         (0U)
4808 #define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                    /*!< 0x00000001 */
4809 #define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                   */
4810 #define CEC_ISR_RXEND_Pos        (1U)
4811 #define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                   /*!< 0x00000002 */
4812 #define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                   */
4813 #define CEC_ISR_RXOVR_Pos        (2U)
4814 #define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                   /*!< 0x00000004 */
4815 #define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                         */
4816 #define CEC_ISR_BRE_Pos          (3U)
4817 #define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                     /*!< 0x00000008 */
4818 #define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                */
4819 #define CEC_ISR_SBPE_Pos         (4U)
4820 #define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                    /*!< 0x00000010 */
4821 #define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error          */
4822 #define CEC_ISR_LBPE_Pos         (5U)
4823 #define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                    /*!< 0x00000020 */
4824 #define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error           */
4825 #define CEC_ISR_RXACKE_Pos       (6U)
4826 #define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                  /*!< 0x00000040 */
4827 #define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge             */
4828 #define CEC_ISR_ARBLST_Pos       (7U)
4829 #define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                  /*!< 0x00000080 */
4830 #define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                   */
4831 #define CEC_ISR_TXBR_Pos         (8U)
4832 #define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                    /*!< 0x00000100 */
4833 #define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                    */
4834 #define CEC_ISR_TXEND_Pos        (9U)
4835 #define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                   /*!< 0x00000200 */
4836 #define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                */
4837 #define CEC_ISR_TXUDR_Pos        (10U)
4838 #define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                   /*!< 0x00000400 */
4839 #define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                 */
4840 #define CEC_ISR_TXERR_Pos        (11U)
4841 #define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                   /*!< 0x00000800 */
4842 #define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                           */
4843 #define CEC_ISR_TXACKE_Pos       (12U)
4844 #define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                  /*!< 0x00001000 */
4845 #define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge             */
4846 
4847 /*******************  Bit definition for CEC_IER register  ********************/
4848 #define CEC_IER_RXBRIE_Pos       (0U)
4849 #define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                  /*!< 0x00000001 */
4850 #define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable         */
4851 #define CEC_IER_RXENDIE_Pos      (1U)
4852 #define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                 /*!< 0x00000002 */
4853 #define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable         */
4854 #define CEC_IER_RXOVRIE_Pos      (2U)
4855 #define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                 /*!< 0x00000004 */
4856 #define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable               */
4857 #define CEC_IER_BREIE_Pos        (3U)
4858 #define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                   /*!< 0x00000008 */
4859 #define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable      */
4860 #define CEC_IER_SBPEIE_Pos       (4U)
4861 #define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                  /*!< 0x00000010 */
4862 #define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable*/
4863 #define CEC_IER_LBPEIE_Pos       (5U)
4864 #define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                  /*!< 0x00000020 */
4865 #define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable */
4866 #define CEC_IER_RXACKEIE_Pos     (6U)
4867 #define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)                /*!< 0x00000040 */
4868 #define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable   */
4869 #define CEC_IER_ARBLSTIE_Pos     (7U)
4870 #define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)                /*!< 0x00000080 */
4871 #define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable         */
4872 #define CEC_IER_TXBRIE_Pos       (8U)
4873 #define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                  /*!< 0x00000100 */
4874 #define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable         */
4875 #define CEC_IER_TXENDIE_Pos      (9U)
4876 #define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                 /*!< 0x00000200 */
4877 #define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable      */
4878 #define CEC_IER_TXUDRIE_Pos      (10U)
4879 #define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                 /*!< 0x00000400 */
4880 #define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable       */
4881 #define CEC_IER_TXERRIE_Pos      (11U)
4882 #define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                 /*!< 0x00000800 */
4883 #define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                 */
4884 #define CEC_IER_TXACKEIE_Pos     (12U)
4885 #define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)                /*!< 0x00001000 */
4886 #define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable   */
4887 
4888 /******************************************************************************/
4889 /*                                                                            */
4890 /*                      Analog Comparators (COMP)                             */
4891 /*                                                                            */
4892 /******************************************************************************/
4893 /***********************  Bit definition for COMP_CSR register  ***************/
4894 /* COMP1 bits definition */
4895 #define COMP_CSR_COMP1EN_Pos          (0U)
4896 #define COMP_CSR_COMP1EN_Msk          (0x1UL << COMP_CSR_COMP1EN_Pos)           /*!< 0x00000001 */
4897 #define COMP_CSR_COMP1EN              COMP_CSR_COMP1EN_Msk                     /*!< COMP1 enable */
4898 #define COMP_CSR_COMP1SW1_Pos         (1U)
4899 #define COMP_CSR_COMP1SW1_Msk         (0x1UL << COMP_CSR_COMP1SW1_Pos)          /*!< 0x00000002 */
4900 #define COMP_CSR_COMP1SW1             COMP_CSR_COMP1SW1_Msk                    /*!< COMP1 SW1 switch control */
4901 #define COMP_CSR_COMP1MODE_Pos        (2U)
4902 #define COMP_CSR_COMP1MODE_Msk        (0x3UL << COMP_CSR_COMP1MODE_Pos)         /*!< 0x0000000C */
4903 #define COMP_CSR_COMP1MODE            COMP_CSR_COMP1MODE_Msk                   /*!< COMP1 power mode */
4904 #define COMP_CSR_COMP1MODE_0          (0x1UL << COMP_CSR_COMP1MODE_Pos)         /*!< 0x00000004 */
4905 #define COMP_CSR_COMP1MODE_1          (0x2UL << COMP_CSR_COMP1MODE_Pos)         /*!< 0x00000008 */
4906 #define COMP_CSR_COMP1INSEL_Pos       (4U)
4907 #define COMP_CSR_COMP1INSEL_Msk       (0x7UL << COMP_CSR_COMP1INSEL_Pos)        /*!< 0x00000070 */
4908 #define COMP_CSR_COMP1INSEL           COMP_CSR_COMP1INSEL_Msk                  /*!< COMP1 inverting input select */
4909 #define COMP_CSR_COMP1INSEL_0         (0x1UL << COMP_CSR_COMP1INSEL_Pos)        /*!< 0x00000010 */
4910 #define COMP_CSR_COMP1INSEL_1         (0x2UL << COMP_CSR_COMP1INSEL_Pos)        /*!< 0x00000020 */
4911 #define COMP_CSR_COMP1INSEL_2         (0x4UL << COMP_CSR_COMP1INSEL_Pos)        /*!< 0x00000040 */
4912 #define COMP_CSR_COMP1OUTSEL_Pos      (8U)
4913 #define COMP_CSR_COMP1OUTSEL_Msk      (0x7UL << COMP_CSR_COMP1OUTSEL_Pos)       /*!< 0x00000700 */
4914 #define COMP_CSR_COMP1OUTSEL          COMP_CSR_COMP1OUTSEL_Msk                 /*!< COMP1 output select */
4915 #define COMP_CSR_COMP1OUTSEL_0        (0x1UL << COMP_CSR_COMP1OUTSEL_Pos)       /*!< 0x00000100 */
4916 #define COMP_CSR_COMP1OUTSEL_1        (0x2UL << COMP_CSR_COMP1OUTSEL_Pos)       /*!< 0x00000200 */
4917 #define COMP_CSR_COMP1OUTSEL_2        (0x4UL << COMP_CSR_COMP1OUTSEL_Pos)       /*!< 0x00000400 */
4918 #define COMP_CSR_COMP1POL_Pos         (11U)
4919 #define COMP_CSR_COMP1POL_Msk         (0x1UL << COMP_CSR_COMP1POL_Pos)          /*!< 0x00000800 */
4920 #define COMP_CSR_COMP1POL             COMP_CSR_COMP1POL_Msk                    /*!< COMP1 output polarity */
4921 #define COMP_CSR_COMP1HYST_Pos        (12U)
4922 #define COMP_CSR_COMP1HYST_Msk        (0x3UL << COMP_CSR_COMP1HYST_Pos)         /*!< 0x00003000 */
4923 #define COMP_CSR_COMP1HYST            COMP_CSR_COMP1HYST_Msk                   /*!< COMP1 hysteresis */
4924 #define COMP_CSR_COMP1HYST_0          (0x1UL << COMP_CSR_COMP1HYST_Pos)         /*!< 0x00001000 */
4925 #define COMP_CSR_COMP1HYST_1          (0x2UL << COMP_CSR_COMP1HYST_Pos)         /*!< 0x00002000 */
4926 #define COMP_CSR_COMP1OUT_Pos         (14U)
4927 #define COMP_CSR_COMP1OUT_Msk         (0x1UL << COMP_CSR_COMP1OUT_Pos)          /*!< 0x00004000 */
4928 #define COMP_CSR_COMP1OUT             COMP_CSR_COMP1OUT_Msk                    /*!< COMP1 output level */
4929 #define COMP_CSR_COMP1LOCK_Pos        (15U)
4930 #define COMP_CSR_COMP1LOCK_Msk        (0x1UL << COMP_CSR_COMP1LOCK_Pos)         /*!< 0x00008000 */
4931 #define COMP_CSR_COMP1LOCK            COMP_CSR_COMP1LOCK_Msk                   /*!< COMP1 lock */
4932 /* COMP2 bits definition */
4933 #define COMP_CSR_COMP2EN_Pos          (16U)
4934 #define COMP_CSR_COMP2EN_Msk          (0x1UL << COMP_CSR_COMP2EN_Pos)           /*!< 0x00010000 */
4935 #define COMP_CSR_COMP2EN              COMP_CSR_COMP2EN_Msk                     /*!< COMP2 enable */
4936 #define COMP_CSR_COMP2MODE_Pos        (18U)
4937 #define COMP_CSR_COMP2MODE_Msk        (0x3UL << COMP_CSR_COMP2MODE_Pos)         /*!< 0x000C0000 */
4938 #define COMP_CSR_COMP2MODE            COMP_CSR_COMP2MODE_Msk                   /*!< COMP2 power mode */
4939 #define COMP_CSR_COMP2MODE_0          (0x1UL << COMP_CSR_COMP2MODE_Pos)         /*!< 0x00040000 */
4940 #define COMP_CSR_COMP2MODE_1          (0x2UL << COMP_CSR_COMP2MODE_Pos)         /*!< 0x00080000 */
4941 #define COMP_CSR_COMP2INSEL_Pos       (20U)
4942 #define COMP_CSR_COMP2INSEL_Msk       (0x7UL << COMP_CSR_COMP2INSEL_Pos)        /*!< 0x00700000 */
4943 #define COMP_CSR_COMP2INSEL           COMP_CSR_COMP2INSEL_Msk                  /*!< COMP2 inverting input select */
4944 #define COMP_CSR_COMP2INSEL_0         (0x1UL << COMP_CSR_COMP2INSEL_Pos)        /*!< 0x00100000 */
4945 #define COMP_CSR_COMP2INSEL_1         (0x2UL << COMP_CSR_COMP2INSEL_Pos)        /*!< 0x00200000 */
4946 #define COMP_CSR_COMP2INSEL_2         (0x4UL << COMP_CSR_COMP2INSEL_Pos)        /*!< 0x00400000 */
4947 #define COMP_CSR_WNDWEN_Pos           (23U)
4948 #define COMP_CSR_WNDWEN_Msk           (0x1UL << COMP_CSR_WNDWEN_Pos)            /*!< 0x00800000 */
4949 #define COMP_CSR_WNDWEN               COMP_CSR_WNDWEN_Msk                      /*!< COMPx window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
4950 #define COMP_CSR_COMP2OUTSEL_Pos      (24U)
4951 #define COMP_CSR_COMP2OUTSEL_Msk      (0x7UL << COMP_CSR_COMP2OUTSEL_Pos)       /*!< 0x07000000 */
4952 #define COMP_CSR_COMP2OUTSEL          COMP_CSR_COMP2OUTSEL_Msk                 /*!< COMP2 output select */
4953 #define COMP_CSR_COMP2OUTSEL_0        (0x1UL << COMP_CSR_COMP2OUTSEL_Pos)       /*!< 0x01000000 */
4954 #define COMP_CSR_COMP2OUTSEL_1        (0x2UL << COMP_CSR_COMP2OUTSEL_Pos)       /*!< 0x02000000 */
4955 #define COMP_CSR_COMP2OUTSEL_2        (0x4UL << COMP_CSR_COMP2OUTSEL_Pos)       /*!< 0x04000000 */
4956 #define COMP_CSR_COMP2POL_Pos         (27U)
4957 #define COMP_CSR_COMP2POL_Msk         (0x1UL << COMP_CSR_COMP2POL_Pos)          /*!< 0x08000000 */
4958 #define COMP_CSR_COMP2POL             COMP_CSR_COMP2POL_Msk                    /*!< COMP2 output polarity */
4959 #define COMP_CSR_COMP2HYST_Pos        (28U)
4960 #define COMP_CSR_COMP2HYST_Msk        (0x3UL << COMP_CSR_COMP2HYST_Pos)         /*!< 0x30000000 */
4961 #define COMP_CSR_COMP2HYST            COMP_CSR_COMP2HYST_Msk                   /*!< COMP2 hysteresis */
4962 #define COMP_CSR_COMP2HYST_0          (0x1UL << COMP_CSR_COMP2HYST_Pos)         /*!< 0x10000000 */
4963 #define COMP_CSR_COMP2HYST_1          (0x2UL << COMP_CSR_COMP2HYST_Pos)         /*!< 0x20000000 */
4964 #define COMP_CSR_COMP2OUT_Pos         (30U)
4965 #define COMP_CSR_COMP2OUT_Msk         (0x1UL << COMP_CSR_COMP2OUT_Pos)          /*!< 0x40000000 */
4966 #define COMP_CSR_COMP2OUT             COMP_CSR_COMP2OUT_Msk                    /*!< COMP2 output level */
4967 #define COMP_CSR_COMP2LOCK_Pos        (31U)
4968 #define COMP_CSR_COMP2LOCK_Msk        (0x1UL << COMP_CSR_COMP2LOCK_Pos)         /*!< 0x80000000 */
4969 #define COMP_CSR_COMP2LOCK            COMP_CSR_COMP2LOCK_Msk                   /*!< COMP2 lock */
4970 /* COMPx bits definition */
4971 #define COMP_CSR_COMPxEN_Pos          (0U)
4972 #define COMP_CSR_COMPxEN_Msk          (0x1UL << COMP_CSR_COMPxEN_Pos)           /*!< 0x00000001 */
4973 #define COMP_CSR_COMPxEN              COMP_CSR_COMPxEN_Msk                     /*!< COMPx enable */
4974 #define COMP_CSR_COMPxMODE_Pos        (2U)
4975 #define COMP_CSR_COMPxMODE_Msk        (0x3UL << COMP_CSR_COMPxMODE_Pos)         /*!< 0x0000000C */
4976 #define COMP_CSR_COMPxMODE            COMP_CSR_COMPxMODE_Msk                   /*!< COMPx power mode */
4977 #define COMP_CSR_COMPxMODE_0          (0x1UL << COMP_CSR_COMPxMODE_Pos)         /*!< 0x00000004 */
4978 #define COMP_CSR_COMPxMODE_1          (0x2UL << COMP_CSR_COMPxMODE_Pos)         /*!< 0x00000008 */
4979 #define COMP_CSR_COMPxINSEL_Pos       (4U)
4980 #define COMP_CSR_COMPxINSEL_Msk       (0x7UL << COMP_CSR_COMPxINSEL_Pos)        /*!< 0x00000070 */
4981 #define COMP_CSR_COMPxINSEL           COMP_CSR_COMPxINSEL_Msk                  /*!< COMPx inverting input select */
4982 #define COMP_CSR_COMPxINSEL_0         (0x1UL << COMP_CSR_COMPxINSEL_Pos)        /*!< 0x00000010 */
4983 #define COMP_CSR_COMPxINSEL_1         (0x2UL << COMP_CSR_COMPxINSEL_Pos)        /*!< 0x00000020 */
4984 #define COMP_CSR_COMPxINSEL_2         (0x4UL << COMP_CSR_COMPxINSEL_Pos)        /*!< 0x00000040 */
4985 #define COMP_CSR_COMPxOUTSEL_Pos      (8U)
4986 #define COMP_CSR_COMPxOUTSEL_Msk      (0x7UL << COMP_CSR_COMPxOUTSEL_Pos)       /*!< 0x00000700 */
4987 #define COMP_CSR_COMPxOUTSEL          COMP_CSR_COMPxOUTSEL_Msk                 /*!< COMPx output select */
4988 #define COMP_CSR_COMPxOUTSEL_0        (0x1UL << COMP_CSR_COMPxOUTSEL_Pos)       /*!< 0x00000100 */
4989 #define COMP_CSR_COMPxOUTSEL_1        (0x2UL << COMP_CSR_COMPxOUTSEL_Pos)       /*!< 0x00000200 */
4990 #define COMP_CSR_COMPxOUTSEL_2        (0x4UL << COMP_CSR_COMPxOUTSEL_Pos)       /*!< 0x00000400 */
4991 #define COMP_CSR_COMPxPOL_Pos         (11U)
4992 #define COMP_CSR_COMPxPOL_Msk         (0x1UL << COMP_CSR_COMPxPOL_Pos)          /*!< 0x00000800 */
4993 #define COMP_CSR_COMPxPOL             COMP_CSR_COMPxPOL_Msk                    /*!< COMPx output polarity */
4994 #define COMP_CSR_COMPxHYST_Pos        (12U)
4995 #define COMP_CSR_COMPxHYST_Msk        (0x3UL << COMP_CSR_COMPxHYST_Pos)         /*!< 0x00003000 */
4996 #define COMP_CSR_COMPxHYST            COMP_CSR_COMPxHYST_Msk                   /*!< COMPx hysteresis */
4997 #define COMP_CSR_COMPxHYST_0          (0x1UL << COMP_CSR_COMPxHYST_Pos)         /*!< 0x00001000 */
4998 #define COMP_CSR_COMPxHYST_1          (0x2UL << COMP_CSR_COMPxHYST_Pos)         /*!< 0x00002000 */
4999 #define COMP_CSR_COMPxOUT_Pos         (14U)
5000 #define COMP_CSR_COMPxOUT_Msk         (0x1UL << COMP_CSR_COMPxOUT_Pos)          /*!< 0x00004000 */
5001 #define COMP_CSR_COMPxOUT             COMP_CSR_COMPxOUT_Msk                    /*!< COMPx output level */
5002 #define COMP_CSR_COMPxLOCK_Pos        (15U)
5003 #define COMP_CSR_COMPxLOCK_Msk        (0x1UL << COMP_CSR_COMPxLOCK_Pos)         /*!< 0x00008000 */
5004 #define COMP_CSR_COMPxLOCK            COMP_CSR_COMPxLOCK_Msk                   /*!< COMPx lock */
5005 
5006 /******************************************************************************/
5007 /*                                                                            */
5008 /*                       CRC calculation unit (CRC)                           */
5009 /*                                                                            */
5010 /******************************************************************************/
5011 
5012 /*
5013 * @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
5014 */
5015 
5016 /* Support of Programmable Polynomial size and value feature */
5017 #define CRC_PROG_POLYNOMIAL_SUPPORT
5018 
5019 /*******************  Bit definition for CRC_DR register  *********************/
5020 #define CRC_DR_DR_Pos            (0U)
5021 #define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
5022 #define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
5023 
5024 /*******************  Bit definition for CRC_IDR register  ********************/
5025 #define CRC_IDR_IDR              ((uint8_t)0xFFU)                              /*!< General-purpose 8-bit data register bits */
5026 
5027 /********************  Bit definition for CRC_CR register  ********************/
5028 #define CRC_CR_RESET_Pos         (0U)
5029 #define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
5030 #define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
5031 #define CRC_CR_POLYSIZE_Pos      (3U)
5032 #define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
5033 #define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
5034 #define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
5035 #define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
5036 #define CRC_CR_REV_IN_Pos        (5U)
5037 #define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
5038 #define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
5039 #define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
5040 #define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
5041 #define CRC_CR_REV_OUT_Pos       (7U)
5042 #define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
5043 #define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
5044 
5045 /*******************  Bit definition for CRC_INIT register  *******************/
5046 #define CRC_INIT_INIT_Pos        (0U)
5047 #define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
5048 #define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
5049 
5050 /*******************  Bit definition for CRC_POL register  ********************/
5051 #define CRC_POL_POL_Pos          (0U)
5052 #define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
5053 #define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial  */
5054 
5055 /******************************************************************************/
5056 /*                                                                            */
5057 /*                          CRS Clock Recovery System                         */
5058 /******************************************************************************/
5059 
5060 /*******************  Bit definition for CRS_CR register  *********************/
5061 #define CRS_CR_SYNCOKIE_Pos       (0U)
5062 #define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)                /*!< 0x00000001 */
5063 #define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /* SYNC event OK interrupt enable        */
5064 #define CRS_CR_SYNCWARNIE_Pos     (1U)
5065 #define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)              /*!< 0x00000002 */
5066 #define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /* SYNC warning interrupt enable         */
5067 #define CRS_CR_ERRIE_Pos          (2U)
5068 #define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                   /*!< 0x00000004 */
5069 #define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /* SYNC error interrupt enable           */
5070 #define CRS_CR_ESYNCIE_Pos        (3U)
5071 #define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                 /*!< 0x00000008 */
5072 #define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /* Expected SYNC(ESYNCF) interrupt Enable*/
5073 #define CRS_CR_CEN_Pos            (5U)
5074 #define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                     /*!< 0x00000020 */
5075 #define CRS_CR_CEN                CRS_CR_CEN_Msk                               /* Frequency error counter enable        */
5076 #define CRS_CR_AUTOTRIMEN_Pos     (6U)
5077 #define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)              /*!< 0x00000040 */
5078 #define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /* Automatic trimming enable             */
5079 #define CRS_CR_SWSYNC_Pos         (7U)
5080 #define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                  /*!< 0x00000080 */
5081 #define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /* A Software SYNC event is generated    */
5082 #define CRS_CR_TRIM_Pos           (8U)
5083 #define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                   /*!< 0x00003F00 */
5084 #define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /* HSI48 oscillator smooth trimming      */
5085 
5086 /*******************  Bit definition for CRS_CFGR register  *********************/
5087 #define CRS_CFGR_RELOAD_Pos       (0U)
5088 #define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)             /*!< 0x0000FFFF */
5089 #define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /* Counter reload value               */
5090 #define CRS_CFGR_FELIM_Pos        (16U)
5091 #define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)                /*!< 0x00FF0000 */
5092 #define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /* Frequency error limit              */
5093 
5094 #define CRS_CFGR_SYNCDIV_Pos      (24U)
5095 #define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x07000000 */
5096 #define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /* SYNC divider                       */
5097 #define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
5098 #define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
5099 #define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
5100 
5101 #define CRS_CFGR_SYNCSRC_Pos      (28U)
5102 #define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x30000000 */
5103 #define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /* SYNC signal source selection       */
5104 #define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
5105 #define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
5106 
5107 #define CRS_CFGR_SYNCPOL_Pos      (31U)
5108 #define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)               /*!< 0x80000000 */
5109 #define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /* SYNC polarity selection            */
5110 
5111 /*******************  Bit definition for CRS_ISR register  *********************/
5112 #define CRS_ISR_SYNCOKF_Pos       (0U)
5113 #define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)                /*!< 0x00000001 */
5114 #define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /* SYNC event OK flag             */
5115 #define CRS_ISR_SYNCWARNF_Pos     (1U)
5116 #define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)              /*!< 0x00000002 */
5117 #define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /* SYNC warning                   */
5118 #define CRS_ISR_ERRF_Pos          (2U)
5119 #define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                   /*!< 0x00000004 */
5120 #define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /* SYNC error flag                */
5121 #define CRS_ISR_ESYNCF_Pos        (3U)
5122 #define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                 /*!< 0x00000008 */
5123 #define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /* Expected SYNC flag             */
5124 #define CRS_ISR_SYNCERR_Pos       (8U)
5125 #define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)                /*!< 0x00000100 */
5126 #define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /* SYNC error                     */
5127 #define CRS_ISR_SYNCMISS_Pos      (9U)
5128 #define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)               /*!< 0x00000200 */
5129 #define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /* SYNC missed                    */
5130 #define CRS_ISR_TRIMOVF_Pos       (10U)
5131 #define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)                /*!< 0x00000400 */
5132 #define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /* Trimming overflow or underflow */
5133 #define CRS_ISR_FEDIR_Pos         (15U)
5134 #define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                  /*!< 0x00008000 */
5135 #define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /* Frequency error direction      */
5136 #define CRS_ISR_FECAP_Pos         (16U)
5137 #define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)               /*!< 0xFFFF0000 */
5138 #define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /* Frequency error capture        */
5139 
5140 /*******************  Bit definition for CRS_ICR register  *********************/
5141 #define CRS_ICR_SYNCOKC_Pos       (0U)
5142 #define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)                /*!< 0x00000001 */
5143 #define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /* SYNC event OK clear flag     */
5144 #define CRS_ICR_SYNCWARNC_Pos     (1U)
5145 #define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)              /*!< 0x00000002 */
5146 #define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /* SYNC warning clear flag      */
5147 #define CRS_ICR_ERRC_Pos          (2U)
5148 #define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                   /*!< 0x00000004 */
5149 #define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /* Error clear flag        */
5150 #define CRS_ICR_ESYNCC_Pos        (3U)
5151 #define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                 /*!< 0x00000008 */
5152 #define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /* Expected SYNC clear flag     */
5153 
5154 /******************************************************************************/
5155 /*                                                                            */
5156 /*                 Digital to Analog Converter (DAC)                          */
5157 /*                                                                            */
5158 /******************************************************************************/
5159 
5160 /*
5161  * @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
5162  */
5163 #define DAC_CHANNEL2_SUPPORT                       /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
5164 
5165 /********************  Bit definition for DAC_CR register  ********************/
5166 #define DAC_CR_EN1_Pos              (0U)
5167 #define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
5168 #define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!< DAC channel1 enable */
5169 #define DAC_CR_BOFF1_Pos            (1U)
5170 #define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
5171 #define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!< DAC channel1 output buffer disable */
5172 #define DAC_CR_TEN1_Pos             (2U)
5173 #define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
5174 #define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!< DAC channel1 Trigger enable */
5175 
5176 #define DAC_CR_TSEL1_Pos            (3U)
5177 #define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
5178 #define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
5179 #define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
5180 #define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
5181 #define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
5182 
5183 #define DAC_CR_WAVE1_Pos            (6U)
5184 #define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
5185 #define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5186 #define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
5187 #define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
5188 
5189 #define DAC_CR_MAMP1_Pos            (8U)
5190 #define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
5191 #define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)  */
5192 #define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
5193 #define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
5194 #define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
5195 #define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
5196 
5197 #define DAC_CR_DMAEN1_Pos           (12U)
5198 #define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
5199 #define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!< DAC channel1 DMA enable */
5200 #define DAC_CR_DMAUDRIE1_Pos        (13U)
5201 #define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
5202 #define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!< DAC channel1 DMA Underrun Interrupt enable */
5203 
5204 #define DAC_CR_EN2_Pos              (16U)
5205 #define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
5206 #define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!< DAC channel2 enable */
5207 #define DAC_CR_BOFF2_Pos            (17U)
5208 #define DAC_CR_BOFF2_Msk            (0x1UL << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */
5209 #define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!< DAC channel2 output buffer disable */
5210 #define DAC_CR_TEN2_Pos             (18U)
5211 #define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
5212 #define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!< DAC channel2 Trigger enable */
5213 
5214 #define DAC_CR_TSEL2_Pos            (19U)
5215 #define DAC_CR_TSEL2_Msk            (0x7UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
5216 #define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
5217 #define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
5218 #define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
5219 #define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
5220 
5221 #define DAC_CR_WAVE2_Pos            (22U)
5222 #define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
5223 #define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5224 #define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
5225 #define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
5226 
5227 #define DAC_CR_MAMP2_Pos            (24U)
5228 #define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
5229 #define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5230 #define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
5231 #define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
5232 #define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
5233 #define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
5234 
5235 #define DAC_CR_DMAEN2_Pos           (28U)
5236 #define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
5237 #define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!< DAC channel2 DMA enabled */
5238 #define DAC_CR_DMAUDRIE2_Pos        (29U)
5239 #define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
5240 #define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!< DAC channel2 DMA Underrun Interrupt enable */
5241 
5242 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
5243 #define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
5244 #define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
5245 #define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!< DAC channel1 software trigger */
5246 #define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
5247 #define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
5248 #define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!< DAC channel2 software trigger */
5249 
5250 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
5251 #define DAC_DHR12R1_DACC1DHR_Pos    (0U)
5252 #define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
5253 #define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Right aligned data */
5254 
5255 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
5256 #define DAC_DHR12L1_DACC1DHR_Pos    (4U)
5257 #define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
5258 #define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Left aligned data */
5259 
5260 /******************  Bit definition for DAC_DHR8R1 register  ******************/
5261 #define DAC_DHR8R1_DACC1DHR_Pos     (0U)
5262 #define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
5263 #define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!< DAC channel1 8-bit Right aligned data */
5264 
5265 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
5266 #define DAC_DHR12R2_DACC2DHR_Pos    (0U)
5267 #define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
5268 #define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Right aligned data */
5269 
5270 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
5271 #define DAC_DHR12L2_DACC2DHR_Pos    (4U)
5272 #define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
5273 #define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Left aligned data */
5274 
5275 /******************  Bit definition for DAC_DHR8R2 register  ******************/
5276 #define DAC_DHR8R2_DACC2DHR_Pos     (0U)
5277 #define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
5278 #define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!< DAC channel2 8-bit Right aligned data */
5279 
5280 /*****************  Bit definition for DAC_DHR12RD register  ******************/
5281 #define DAC_DHR12RD_DACC1DHR_Pos    (0U)
5282 #define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
5283 #define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Right aligned data */
5284 #define DAC_DHR12RD_DACC2DHR_Pos    (16U)
5285 #define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
5286 #define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Right aligned data  */
5287 
5288 /*****************  Bit definition for DAC_DHR12LD register  ******************/
5289 #define DAC_DHR12LD_DACC1DHR_Pos    (4U)
5290 #define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
5291 #define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Left aligned data */
5292 #define DAC_DHR12LD_DACC2DHR_Pos    (20U)
5293 #define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
5294 #define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Left aligned data  */
5295 
5296 /******************  Bit definition for DAC_DHR8RD register  ******************/
5297 #define DAC_DHR8RD_DACC1DHR_Pos     (0U)
5298 #define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
5299 #define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!< DAC channel1 8-bit Right aligned data */
5300 #define DAC_DHR8RD_DACC2DHR_Pos     (8U)
5301 #define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
5302 #define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!< DAC channel2 8-bit Right aligned data */
5303 
5304 /*******************  Bit definition for DAC_DOR1 register  *******************/
5305 #define DAC_DOR1_DACC1DOR_Pos       (0U)
5306 #define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
5307 #define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!< DAC channel1 data output */
5308 
5309 /*******************  Bit definition for DAC_DOR2 register  *******************/
5310 #define DAC_DOR2_DACC2DOR_Pos       (0U)
5311 #define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
5312 #define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!< DAC channel2 data output */
5313 
5314 /********************  Bit definition for DAC_SR register  ********************/
5315 #define DAC_SR_DMAUDR1_Pos          (13U)
5316 #define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
5317 #define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!< DAC channel1 DMA underrun flag */
5318 #define DAC_SR_DMAUDR2_Pos          (29U)
5319 #define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
5320 #define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!< DAC channel2 DMA underrun flag  */
5321 
5322 /******************************************************************************/
5323 /*                                                                            */
5324 /*                           Debug MCU (DBGMCU)                               */
5325 /*                                                                            */
5326 /******************************************************************************/
5327 
5328 /****************  Bit definition for DBGMCU_IDCODE register  *****************/
5329 #define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)
5330 #define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
5331 #define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk  /*!< Device Identifier */
5332 
5333 #define DBGMCU_IDCODE_REV_ID_Pos                     (16U)
5334 #define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
5335 #define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk  /*!< REV_ID[15:0] bits (Revision Identifier) */
5336 #define DBGMCU_IDCODE_REV_ID_0                       (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
5337 #define DBGMCU_IDCODE_REV_ID_1                       (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
5338 #define DBGMCU_IDCODE_REV_ID_2                       (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
5339 #define DBGMCU_IDCODE_REV_ID_3                       (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
5340 #define DBGMCU_IDCODE_REV_ID_4                       (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
5341 #define DBGMCU_IDCODE_REV_ID_5                       (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
5342 #define DBGMCU_IDCODE_REV_ID_6                       (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
5343 #define DBGMCU_IDCODE_REV_ID_7                       (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
5344 #define DBGMCU_IDCODE_REV_ID_8                       (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
5345 #define DBGMCU_IDCODE_REV_ID_9                       (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
5346 #define DBGMCU_IDCODE_REV_ID_10                      (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
5347 #define DBGMCU_IDCODE_REV_ID_11                      (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
5348 #define DBGMCU_IDCODE_REV_ID_12                      (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
5349 #define DBGMCU_IDCODE_REV_ID_13                      (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
5350 #define DBGMCU_IDCODE_REV_ID_14                      (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
5351 #define DBGMCU_IDCODE_REV_ID_15                      (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
5352 
5353 /******************  Bit definition for DBGMCU_CR register  *******************/
5354 #define DBGMCU_CR_DBG_STOP_Pos                       (1U)
5355 #define DBGMCU_CR_DBG_STOP_Msk                       (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
5356 #define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk    /*!< Debug Stop Mode */
5357 #define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)
5358 #define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
5359 #define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
5360 
5361 /******************  Bit definition for DBGMCU_APB1_FZ register  **************/
5362 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)
5363 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
5364 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
5365 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)
5366 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
5367 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
5368 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)
5369 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
5370 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
5371 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos             (5U)
5372 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
5373 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP                 DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted  */
5374 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos            (8U)
5375 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
5376 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP                DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk /*!< TIM14 counter stopped when core is halted */
5377 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)
5378 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
5379 #define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
5380 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)
5381 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
5382 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
5383 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)
5384 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
5385 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
5386 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)
5387 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
5388 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
5389 #define DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos              (25U)
5390 #define DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk              (0x1UL << DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
5391 #define DBGMCU_APB1_FZ_DBG_CAN_STOP                  DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk /*!< CAN debug stopped when Core is halted  */
5392 
5393 /******************  Bit definition for DBGMCU_APB2_FZ register  **************/
5394 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (11U)
5395 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
5396 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */
5397 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos            (16U)
5398 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
5399 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP                DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk /*!< TIM15 counter stopped when core is halted  */
5400 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos            (17U)
5401 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
5402 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP                DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk /*!< TIM16 counter stopped when core is halted */
5403 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos            (18U)
5404 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
5405 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP                DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk /*!< TIM17 counter stopped when core is halted */
5406 
5407 /******************************************************************************/
5408 /*                                                                            */
5409 /*                           DMA Controller (DMA)                             */
5410 /*                                                                            */
5411 /******************************************************************************/
5412 /*******************  Bit definition for DMA_ISR register  ********************/
5413 #define DMA_ISR_GIF1_Pos       (0U)
5414 #define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
5415 #define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag    */
5416 #define DMA_ISR_TCIF1_Pos      (1U)
5417 #define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
5418 #define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag   */
5419 #define DMA_ISR_HTIF1_Pos      (2U)
5420 #define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
5421 #define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag       */
5422 #define DMA_ISR_TEIF1_Pos      (3U)
5423 #define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
5424 #define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag      */
5425 #define DMA_ISR_GIF2_Pos       (4U)
5426 #define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
5427 #define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag    */
5428 #define DMA_ISR_TCIF2_Pos      (5U)
5429 #define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
5430 #define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag   */
5431 #define DMA_ISR_HTIF2_Pos      (6U)
5432 #define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
5433 #define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag       */
5434 #define DMA_ISR_TEIF2_Pos      (7U)
5435 #define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
5436 #define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag      */
5437 #define DMA_ISR_GIF3_Pos       (8U)
5438 #define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
5439 #define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag    */
5440 #define DMA_ISR_TCIF3_Pos      (9U)
5441 #define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
5442 #define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag   */
5443 #define DMA_ISR_HTIF3_Pos      (10U)
5444 #define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
5445 #define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag       */
5446 #define DMA_ISR_TEIF3_Pos      (11U)
5447 #define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
5448 #define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag      */
5449 #define DMA_ISR_GIF4_Pos       (12U)
5450 #define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
5451 #define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag    */
5452 #define DMA_ISR_TCIF4_Pos      (13U)
5453 #define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
5454 #define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag   */
5455 #define DMA_ISR_HTIF4_Pos      (14U)
5456 #define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
5457 #define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag       */
5458 #define DMA_ISR_TEIF4_Pos      (15U)
5459 #define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
5460 #define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag      */
5461 #define DMA_ISR_GIF5_Pos       (16U)
5462 #define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
5463 #define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag    */
5464 #define DMA_ISR_TCIF5_Pos      (17U)
5465 #define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
5466 #define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag   */
5467 #define DMA_ISR_HTIF5_Pos      (18U)
5468 #define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
5469 #define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag       */
5470 #define DMA_ISR_TEIF5_Pos      (19U)
5471 #define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
5472 #define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag      */
5473 #define DMA_ISR_GIF6_Pos       (20U)
5474 #define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
5475 #define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag    */
5476 #define DMA_ISR_TCIF6_Pos      (21U)
5477 #define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
5478 #define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag   */
5479 #define DMA_ISR_HTIF6_Pos      (22U)
5480 #define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
5481 #define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag       */
5482 #define DMA_ISR_TEIF6_Pos      (23U)
5483 #define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
5484 #define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag      */
5485 #define DMA_ISR_GIF7_Pos       (24U)
5486 #define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
5487 #define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag    */
5488 #define DMA_ISR_TCIF7_Pos      (25U)
5489 #define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
5490 #define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag   */
5491 #define DMA_ISR_HTIF7_Pos      (26U)
5492 #define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
5493 #define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag       */
5494 #define DMA_ISR_TEIF7_Pos      (27U)
5495 #define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
5496 #define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag      */
5497 
5498 /*******************  Bit definition for DMA_IFCR register  *******************/
5499 #define DMA_IFCR_CGIF1_Pos     (0U)
5500 #define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
5501 #define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear    */
5502 #define DMA_IFCR_CTCIF1_Pos    (1U)
5503 #define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
5504 #define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear   */
5505 #define DMA_IFCR_CHTIF1_Pos    (2U)
5506 #define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
5507 #define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear       */
5508 #define DMA_IFCR_CTEIF1_Pos    (3U)
5509 #define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
5510 #define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear      */
5511 #define DMA_IFCR_CGIF2_Pos     (4U)
5512 #define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
5513 #define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear    */
5514 #define DMA_IFCR_CTCIF2_Pos    (5U)
5515 #define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
5516 #define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear   */
5517 #define DMA_IFCR_CHTIF2_Pos    (6U)
5518 #define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
5519 #define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear       */
5520 #define DMA_IFCR_CTEIF2_Pos    (7U)
5521 #define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
5522 #define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear      */
5523 #define DMA_IFCR_CGIF3_Pos     (8U)
5524 #define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
5525 #define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear    */
5526 #define DMA_IFCR_CTCIF3_Pos    (9U)
5527 #define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
5528 #define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear   */
5529 #define DMA_IFCR_CHTIF3_Pos    (10U)
5530 #define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
5531 #define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear       */
5532 #define DMA_IFCR_CTEIF3_Pos    (11U)
5533 #define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
5534 #define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear      */
5535 #define DMA_IFCR_CGIF4_Pos     (12U)
5536 #define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
5537 #define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear    */
5538 #define DMA_IFCR_CTCIF4_Pos    (13U)
5539 #define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
5540 #define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear   */
5541 #define DMA_IFCR_CHTIF4_Pos    (14U)
5542 #define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
5543 #define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear       */
5544 #define DMA_IFCR_CTEIF4_Pos    (15U)
5545 #define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
5546 #define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear      */
5547 #define DMA_IFCR_CGIF5_Pos     (16U)
5548 #define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
5549 #define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear    */
5550 #define DMA_IFCR_CTCIF5_Pos    (17U)
5551 #define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
5552 #define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear   */
5553 #define DMA_IFCR_CHTIF5_Pos    (18U)
5554 #define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
5555 #define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear       */
5556 #define DMA_IFCR_CTEIF5_Pos    (19U)
5557 #define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
5558 #define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear      */
5559 #define DMA_IFCR_CGIF6_Pos     (20U)
5560 #define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
5561 #define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear    */
5562 #define DMA_IFCR_CTCIF6_Pos    (21U)
5563 #define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
5564 #define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear   */
5565 #define DMA_IFCR_CHTIF6_Pos    (22U)
5566 #define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
5567 #define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear       */
5568 #define DMA_IFCR_CTEIF6_Pos    (23U)
5569 #define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
5570 #define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear      */
5571 #define DMA_IFCR_CGIF7_Pos     (24U)
5572 #define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
5573 #define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear    */
5574 #define DMA_IFCR_CTCIF7_Pos    (25U)
5575 #define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
5576 #define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear   */
5577 #define DMA_IFCR_CHTIF7_Pos    (26U)
5578 #define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
5579 #define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear       */
5580 #define DMA_IFCR_CTEIF7_Pos    (27U)
5581 #define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
5582 #define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear      */
5583 
5584 /*******************  Bit definition for DMA_CCR register  ********************/
5585 #define DMA_CCR_EN_Pos         (0U)
5586 #define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
5587 #define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
5588 #define DMA_CCR_TCIE_Pos       (1U)
5589 #define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
5590 #define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
5591 #define DMA_CCR_HTIE_Pos       (2U)
5592 #define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
5593 #define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
5594 #define DMA_CCR_TEIE_Pos       (3U)
5595 #define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
5596 #define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
5597 #define DMA_CCR_DIR_Pos        (4U)
5598 #define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
5599 #define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
5600 #define DMA_CCR_CIRC_Pos       (5U)
5601 #define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
5602 #define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
5603 #define DMA_CCR_PINC_Pos       (6U)
5604 #define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
5605 #define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
5606 #define DMA_CCR_MINC_Pos       (7U)
5607 #define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
5608 #define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
5609 
5610 #define DMA_CCR_PSIZE_Pos      (8U)
5611 #define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
5612 #define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
5613 #define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
5614 #define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
5615 
5616 #define DMA_CCR_MSIZE_Pos      (10U)
5617 #define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
5618 #define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
5619 #define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
5620 #define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
5621 
5622 #define DMA_CCR_PL_Pos         (12U)
5623 #define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
5624 #define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
5625 #define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
5626 #define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
5627 
5628 #define DMA_CCR_MEM2MEM_Pos    (14U)
5629 #define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
5630 #define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
5631 
5632 /******************  Bit definition for DMA_CNDTR register  *******************/
5633 #define DMA_CNDTR_NDT_Pos      (0U)
5634 #define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
5635 #define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
5636 
5637 /******************  Bit definition for DMA_CPAR register  ********************/
5638 #define DMA_CPAR_PA_Pos        (0U)
5639 #define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
5640 #define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
5641 
5642 /******************  Bit definition for DMA_CMAR register  ********************/
5643 #define DMA_CMAR_MA_Pos        (0U)
5644 #define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
5645 #define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
5646 
5647 /******************  Bit definition for DMA1_CSELR register  ********************/
5648 #define DMA_CSELR_C1S_Pos      (0U)
5649 #define DMA_CSELR_C1S_Msk      (0xFUL << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
5650 #define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */
5651 #define DMA_CSELR_C2S_Pos      (4U)
5652 #define DMA_CSELR_C2S_Msk      (0xFUL << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
5653 #define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */
5654 #define DMA_CSELR_C3S_Pos      (8U)
5655 #define DMA_CSELR_C3S_Msk      (0xFUL << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
5656 #define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */
5657 #define DMA_CSELR_C4S_Pos      (12U)
5658 #define DMA_CSELR_C4S_Msk      (0xFUL << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
5659 #define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */
5660 #define DMA_CSELR_C5S_Pos      (16U)
5661 #define DMA_CSELR_C5S_Msk      (0xFUL << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
5662 #define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */
5663 #define DMA_CSELR_C6S_Pos      (20U)
5664 #define DMA_CSELR_C6S_Msk      (0xFUL << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
5665 #define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */
5666 #define DMA_CSELR_C7S_Pos      (24U)
5667 #define DMA_CSELR_C7S_Msk      (0xFUL << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
5668 #define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
5669 
5670 #define DMA1_CSELR_DEFAULT              (0x00000000U)                          /*!< Default remap position for DMA1 */
5671 #define DMA1_CSELR_CH1_ADC_Pos          (0U)
5672 #define DMA1_CSELR_CH1_ADC_Msk          (0x1UL << DMA1_CSELR_CH1_ADC_Pos)       /*!< 0x00000001 */
5673 #define DMA1_CSELR_CH1_ADC              DMA1_CSELR_CH1_ADC_Msk                 /*!< Remap ADC on DMA1 Channel 1*/
5674 #define DMA1_CSELR_CH1_TIM17_CH1_Pos    (0U)
5675 #define DMA1_CSELR_CH1_TIM17_CH1_Msk    (0x7UL << DMA1_CSELR_CH1_TIM17_CH1_Pos) /*!< 0x00000007 */
5676 #define DMA1_CSELR_CH1_TIM17_CH1        DMA1_CSELR_CH1_TIM17_CH1_Msk           /*!< Remap TIM17 channel 1 on DMA1 channel 1 */
5677 #define DMA1_CSELR_CH1_TIM17_UP_Pos     (0U)
5678 #define DMA1_CSELR_CH1_TIM17_UP_Msk     (0x7UL << DMA1_CSELR_CH1_TIM17_UP_Pos)  /*!< 0x00000007 */
5679 #define DMA1_CSELR_CH1_TIM17_UP         DMA1_CSELR_CH1_TIM17_UP_Msk            /*!< Remap TIM17 up on DMA1 channel 1 */
5680 #define DMA1_CSELR_CH1_USART1_RX_Pos    (3U)
5681 #define DMA1_CSELR_CH1_USART1_RX_Msk    (0x1UL << DMA1_CSELR_CH1_USART1_RX_Pos) /*!< 0x00000008 */
5682 #define DMA1_CSELR_CH1_USART1_RX        DMA1_CSELR_CH1_USART1_RX_Msk           /*!< Remap USART1 Rx on DMA1 channel 1 */
5683 #define DMA1_CSELR_CH1_USART2_RX_Pos    (0U)
5684 #define DMA1_CSELR_CH1_USART2_RX_Msk    (0x9UL << DMA1_CSELR_CH1_USART2_RX_Pos) /*!< 0x00000009 */
5685 #define DMA1_CSELR_CH1_USART2_RX        DMA1_CSELR_CH1_USART2_RX_Msk           /*!< Remap USART2 Rx on DMA1 channel 1 */
5686 #define DMA1_CSELR_CH1_USART3_RX_Pos    (1U)
5687 #define DMA1_CSELR_CH1_USART3_RX_Msk    (0x5UL << DMA1_CSELR_CH1_USART3_RX_Pos) /*!< 0x0000000A */
5688 #define DMA1_CSELR_CH1_USART3_RX        DMA1_CSELR_CH1_USART3_RX_Msk           /*!< Remap USART3 Rx on DMA1 channel 1 */
5689 #define DMA1_CSELR_CH1_USART4_RX_Pos    (0U)
5690 #define DMA1_CSELR_CH1_USART4_RX_Msk    (0xBUL << DMA1_CSELR_CH1_USART4_RX_Pos) /*!< 0x0000000B */
5691 #define DMA1_CSELR_CH1_USART4_RX        DMA1_CSELR_CH1_USART4_RX_Msk           /*!< Remap USART4 Rx on DMA1 channel 1 */
5692 #define DMA1_CSELR_CH1_USART5_RX_Pos    (2U)
5693 #define DMA1_CSELR_CH1_USART5_RX_Msk    (0x3UL << DMA1_CSELR_CH1_USART5_RX_Pos) /*!< 0x0000000C */
5694 #define DMA1_CSELR_CH1_USART5_RX        DMA1_CSELR_CH1_USART5_RX_Msk           /*!< Remap USART5 Rx on DMA1 channel 1 */
5695 #define DMA1_CSELR_CH1_USART6_RX_Pos    (0U)
5696 #define DMA1_CSELR_CH1_USART6_RX_Msk    (0xDUL << DMA1_CSELR_CH1_USART6_RX_Pos) /*!< 0x0000000D */
5697 #define DMA1_CSELR_CH1_USART6_RX        DMA1_CSELR_CH1_USART6_RX_Msk           /*!< Remap USART6 Rx on DMA1 channel 1 */
5698 #define DMA1_CSELR_CH1_USART7_RX_Pos    (1U)
5699 #define DMA1_CSELR_CH1_USART7_RX_Msk    (0x7UL << DMA1_CSELR_CH1_USART7_RX_Pos) /*!< 0x0000000E */
5700 #define DMA1_CSELR_CH1_USART7_RX        DMA1_CSELR_CH1_USART7_RX_Msk           /*!< Remap USART7 Rx on DMA1 channel 1 */
5701 #define DMA1_CSELR_CH1_USART8_RX_Pos    (0U)
5702 #define DMA1_CSELR_CH1_USART8_RX_Msk    (0xFUL << DMA1_CSELR_CH1_USART8_RX_Pos) /*!< 0x0000000F */
5703 #define DMA1_CSELR_CH1_USART8_RX        DMA1_CSELR_CH1_USART8_RX_Msk           /*!< Remap USART8 Rx on DMA1 channel 1 */
5704 #define DMA1_CSELR_CH2_ADC_Pos          (4U)
5705 #define DMA1_CSELR_CH2_ADC_Msk          (0x1UL << DMA1_CSELR_CH2_ADC_Pos)       /*!< 0x00000010 */
5706 #define DMA1_CSELR_CH2_ADC              DMA1_CSELR_CH2_ADC_Msk                 /*!< Remap ADC on DMA1 channel 2 */
5707 #define DMA1_CSELR_CH2_I2C1_TX_Pos      (5U)
5708 #define DMA1_CSELR_CH2_I2C1_TX_Msk      (0x1UL << DMA1_CSELR_CH2_I2C1_TX_Pos)   /*!< 0x00000020 */
5709 #define DMA1_CSELR_CH2_I2C1_TX          DMA1_CSELR_CH2_I2C1_TX_Msk             /*!< Remap I2C1 Tx on DMA1 channel 2 */
5710 #define DMA1_CSELR_CH2_SPI1_RX_Pos      (4U)
5711 #define DMA1_CSELR_CH2_SPI1_RX_Msk      (0x3UL << DMA1_CSELR_CH2_SPI1_RX_Pos)   /*!< 0x00000030 */
5712 #define DMA1_CSELR_CH2_SPI1_RX          DMA1_CSELR_CH2_SPI1_RX_Msk             /*!< Remap SPI1 Rx on DMA1 channel 2 */
5713 #define DMA1_CSELR_CH2_TIM1_CH1_Pos     (6U)
5714 #define DMA1_CSELR_CH2_TIM1_CH1_Msk     (0x1UL << DMA1_CSELR_CH2_TIM1_CH1_Pos)  /*!< 0x00000040 */
5715 #define DMA1_CSELR_CH2_TIM1_CH1         DMA1_CSELR_CH2_TIM1_CH1_Msk            /*!< Remap TIM1 channel 1 on DMA1 channel 2 */
5716 #define DMA1_CSELR_CH2_TIM17_CH1_Pos    (4U)
5717 #define DMA1_CSELR_CH2_TIM17_CH1_Msk    (0x7UL << DMA1_CSELR_CH2_TIM17_CH1_Pos) /*!< 0x00000070 */
5718 #define DMA1_CSELR_CH2_TIM17_CH1        DMA1_CSELR_CH2_TIM17_CH1_Msk           /*!< Remap TIM17 channel 1 on DMA1 channel 2 */
5719 #define DMA1_CSELR_CH2_TIM17_UP_Pos     (4U)
5720 #define DMA1_CSELR_CH2_TIM17_UP_Msk     (0x7UL << DMA1_CSELR_CH2_TIM17_UP_Pos)  /*!< 0x00000070 */
5721 #define DMA1_CSELR_CH2_TIM17_UP         DMA1_CSELR_CH2_TIM17_UP_Msk            /*!< Remap TIM17 up on DMA1 channel 2 */
5722 #define DMA1_CSELR_CH2_USART1_TX_Pos    (7U)
5723 #define DMA1_CSELR_CH2_USART1_TX_Msk    (0x1UL << DMA1_CSELR_CH2_USART1_TX_Pos) /*!< 0x00000080 */
5724 #define DMA1_CSELR_CH2_USART1_TX        DMA1_CSELR_CH2_USART1_TX_Msk           /*!< Remap USART1 Tx on DMA1 channel 2 */
5725 #define DMA1_CSELR_CH2_USART2_TX_Pos    (4U)
5726 #define DMA1_CSELR_CH2_USART2_TX_Msk    (0x9UL << DMA1_CSELR_CH2_USART2_TX_Pos) /*!< 0x00000090 */
5727 #define DMA1_CSELR_CH2_USART2_TX        DMA1_CSELR_CH2_USART2_TX_Msk           /*!< Remap USART2 Tx on DMA1 channel 2 */
5728 #define DMA1_CSELR_CH2_USART3_TX_Pos    (5U)
5729 #define DMA1_CSELR_CH2_USART3_TX_Msk    (0x5UL << DMA1_CSELR_CH2_USART3_TX_Pos) /*!< 0x000000A0 */
5730 #define DMA1_CSELR_CH2_USART3_TX        DMA1_CSELR_CH2_USART3_TX_Msk           /*!< Remap USART3 Tx on DMA1 channel 2 */
5731 #define DMA1_CSELR_CH2_USART4_TX_Pos    (4U)
5732 #define DMA1_CSELR_CH2_USART4_TX_Msk    (0xBUL << DMA1_CSELR_CH2_USART4_TX_Pos) /*!< 0x000000B0 */
5733 #define DMA1_CSELR_CH2_USART4_TX        DMA1_CSELR_CH2_USART4_TX_Msk           /*!< Remap USART4 Tx on DMA1 channel 2 */
5734 #define DMA1_CSELR_CH2_USART5_TX_Pos    (6U)
5735 #define DMA1_CSELR_CH2_USART5_TX_Msk    (0x3UL << DMA1_CSELR_CH2_USART5_TX_Pos) /*!< 0x000000C0 */
5736 #define DMA1_CSELR_CH2_USART5_TX        DMA1_CSELR_CH2_USART5_TX_Msk           /*!< Remap USART5 Tx on DMA1 channel 2 */
5737 #define DMA1_CSELR_CH2_USART6_TX_Pos    (4U)
5738 #define DMA1_CSELR_CH2_USART6_TX_Msk    (0xDUL << DMA1_CSELR_CH2_USART6_TX_Pos) /*!< 0x000000D0 */
5739 #define DMA1_CSELR_CH2_USART6_TX        DMA1_CSELR_CH2_USART6_TX_Msk           /*!< Remap USART6 Tx on DMA1 channel 2 */
5740 #define DMA1_CSELR_CH2_USART7_TX_Pos    (5U)
5741 #define DMA1_CSELR_CH2_USART7_TX_Msk    (0x7UL << DMA1_CSELR_CH2_USART7_TX_Pos) /*!< 0x000000E0 */
5742 #define DMA1_CSELR_CH2_USART7_TX        DMA1_CSELR_CH2_USART7_TX_Msk           /*!< Remap USART7 Tx on DMA1 channel 2 */
5743 #define DMA1_CSELR_CH2_USART8_TX_Pos    (4U)
5744 #define DMA1_CSELR_CH2_USART8_TX_Msk    (0xFUL << DMA1_CSELR_CH2_USART8_TX_Pos) /*!< 0x000000F0 */
5745 #define DMA1_CSELR_CH2_USART8_TX        DMA1_CSELR_CH2_USART8_TX_Msk           /*!< Remap USART8 Tx on DMA1 channel 2 */
5746 #define DMA1_CSELR_CH3_TIM6_UP_Pos      (8U)
5747 #define DMA1_CSELR_CH3_TIM6_UP_Msk      (0x1UL << DMA1_CSELR_CH3_TIM6_UP_Pos)   /*!< 0x00000100 */
5748 #define DMA1_CSELR_CH3_TIM6_UP          DMA1_CSELR_CH3_TIM6_UP_Msk             /*!< Remap TIM6 up on DMA1 channel 3 */
5749 #define DMA1_CSELR_CH3_DAC_CH1_Pos      (8U)
5750 #define DMA1_CSELR_CH3_DAC_CH1_Msk      (0x1UL << DMA1_CSELR_CH3_DAC_CH1_Pos)   /*!< 0x00000100 */
5751 #define DMA1_CSELR_CH3_DAC_CH1          DMA1_CSELR_CH3_DAC_CH1_Msk             /*!< Remap DAC Channel 1on DMA1 channel 3 */
5752 #define DMA1_CSELR_CH3_I2C1_RX_Pos      (9U)
5753 #define DMA1_CSELR_CH3_I2C1_RX_Msk      (0x1UL << DMA1_CSELR_CH3_I2C1_RX_Pos)   /*!< 0x00000200 */
5754 #define DMA1_CSELR_CH3_I2C1_RX          DMA1_CSELR_CH3_I2C1_RX_Msk             /*!< Remap I2C1 Rx on DMA1 channel 3 */
5755 #define DMA1_CSELR_CH3_SPI1_TX_Pos      (8U)
5756 #define DMA1_CSELR_CH3_SPI1_TX_Msk      (0x3UL << DMA1_CSELR_CH3_SPI1_TX_Pos)   /*!< 0x00000300 */
5757 #define DMA1_CSELR_CH3_SPI1_TX          DMA1_CSELR_CH3_SPI1_TX_Msk             /*!< Remap SPI1 Tx on DMA1 channel 3 */
5758 #define DMA1_CSELR_CH3_TIM1_CH2_Pos     (10U)
5759 #define DMA1_CSELR_CH3_TIM1_CH2_Msk     (0x1UL << DMA1_CSELR_CH3_TIM1_CH2_Pos)  /*!< 0x00000400 */
5760 #define DMA1_CSELR_CH3_TIM1_CH2         DMA1_CSELR_CH3_TIM1_CH2_Msk            /*!< Remap TIM1 channel 2 on DMA1 channel 3 */
5761 #define DMA1_CSELR_CH3_TIM2_CH2_Pos     (8U)
5762 #define DMA1_CSELR_CH3_TIM2_CH2_Msk     (0x5UL << DMA1_CSELR_CH3_TIM2_CH2_Pos)  /*!< 0x00000500 */
5763 #define DMA1_CSELR_CH3_TIM2_CH2         DMA1_CSELR_CH3_TIM2_CH2_Msk            /*!< Remap TIM2 channel 2 on DMA1 channel 3 */
5764 #define DMA1_CSELR_CH3_TIM16_CH1_Pos    (8U)
5765 #define DMA1_CSELR_CH3_TIM16_CH1_Msk    (0x7UL << DMA1_CSELR_CH3_TIM16_CH1_Pos) /*!< 0x00000700 */
5766 #define DMA1_CSELR_CH3_TIM16_CH1        DMA1_CSELR_CH3_TIM16_CH1_Msk           /*!< Remap TIM16 channel 1 on DMA1 channel 3 */
5767 #define DMA1_CSELR_CH3_TIM16_UP_Pos     (8U)
5768 #define DMA1_CSELR_CH3_TIM16_UP_Msk     (0x7UL << DMA1_CSELR_CH3_TIM16_UP_Pos)  /*!< 0x00000700 */
5769 #define DMA1_CSELR_CH3_TIM16_UP         DMA1_CSELR_CH3_TIM16_UP_Msk            /*!< Remap TIM16 up on DMA1 channel 3 */
5770 #define DMA1_CSELR_CH3_USART1_RX_Pos    (11U)
5771 #define DMA1_CSELR_CH3_USART1_RX_Msk    (0x1UL << DMA1_CSELR_CH3_USART1_RX_Pos) /*!< 0x00000800 */
5772 #define DMA1_CSELR_CH3_USART1_RX        DMA1_CSELR_CH3_USART1_RX_Msk           /*!< Remap USART1 Rx on DMA1 channel 3 */
5773 #define DMA1_CSELR_CH3_USART2_RX_Pos    (8U)
5774 #define DMA1_CSELR_CH3_USART2_RX_Msk    (0x9UL << DMA1_CSELR_CH3_USART2_RX_Pos) /*!< 0x00000900 */
5775 #define DMA1_CSELR_CH3_USART2_RX        DMA1_CSELR_CH3_USART2_RX_Msk           /*!< Remap USART2 Rx on DMA1 channel 3 */
5776 #define DMA1_CSELR_CH3_USART3_RX_Pos    (9U)
5777 #define DMA1_CSELR_CH3_USART3_RX_Msk    (0x5UL << DMA1_CSELR_CH3_USART3_RX_Pos) /*!< 0x00000A00 */
5778 #define DMA1_CSELR_CH3_USART3_RX        DMA1_CSELR_CH3_USART3_RX_Msk           /*!< Remap USART3 Rx on DMA1 channel 3 */
5779 #define DMA1_CSELR_CH3_USART4_RX_Pos    (8U)
5780 #define DMA1_CSELR_CH3_USART4_RX_Msk    (0xBUL << DMA1_CSELR_CH3_USART4_RX_Pos) /*!< 0x00000B00 */
5781 #define DMA1_CSELR_CH3_USART4_RX        DMA1_CSELR_CH3_USART4_RX_Msk           /*!< Remap USART4 Rx on DMA1 channel 3 */
5782 #define DMA1_CSELR_CH3_USART5_RX_Pos    (10U)
5783 #define DMA1_CSELR_CH3_USART5_RX_Msk    (0x3UL << DMA1_CSELR_CH3_USART5_RX_Pos) /*!< 0x00000C00 */
5784 #define DMA1_CSELR_CH3_USART5_RX        DMA1_CSELR_CH3_USART5_RX_Msk           /*!< Remap USART5 Rx on DMA1 channel 3 */
5785 #define DMA1_CSELR_CH3_USART6_RX_Pos    (8U)
5786 #define DMA1_CSELR_CH3_USART6_RX_Msk    (0xDUL << DMA1_CSELR_CH3_USART6_RX_Pos) /*!< 0x00000D00 */
5787 #define DMA1_CSELR_CH3_USART6_RX        DMA1_CSELR_CH3_USART6_RX_Msk           /*!< Remap USART6 Rx on DMA1 channel 3 */
5788 #define DMA1_CSELR_CH3_USART7_RX_Pos    (9U)
5789 #define DMA1_CSELR_CH3_USART7_RX_Msk    (0x7UL << DMA1_CSELR_CH3_USART7_RX_Pos) /*!< 0x00000E00 */
5790 #define DMA1_CSELR_CH3_USART7_RX        DMA1_CSELR_CH3_USART7_RX_Msk           /*!< Remap USART7 Rx on DMA1 channel 3 */
5791 #define DMA1_CSELR_CH3_USART8_RX_Pos    (8U)
5792 #define DMA1_CSELR_CH3_USART8_RX_Msk    (0xFUL << DMA1_CSELR_CH3_USART8_RX_Pos) /*!< 0x00000F00 */
5793 #define DMA1_CSELR_CH3_USART8_RX        DMA1_CSELR_CH3_USART8_RX_Msk           /*!< Remap USART8 Rx on DMA1 channel 3 */
5794 #define DMA1_CSELR_CH4_TIM7_UP_Pos      (12U)
5795 #define DMA1_CSELR_CH4_TIM7_UP_Msk      (0x1UL << DMA1_CSELR_CH4_TIM7_UP_Pos)   /*!< 0x00001000 */
5796 #define DMA1_CSELR_CH4_TIM7_UP          DMA1_CSELR_CH4_TIM7_UP_Msk             /*!< Remap TIM7 up on DMA1 channel 4 */
5797 #define DMA1_CSELR_CH4_DAC_CH2_Pos      (12U)
5798 #define DMA1_CSELR_CH4_DAC_CH2_Msk      (0x1UL << DMA1_CSELR_CH4_DAC_CH2_Pos)   /*!< 0x00001000 */
5799 #define DMA1_CSELR_CH4_DAC_CH2          DMA1_CSELR_CH4_DAC_CH2_Msk             /*!< Remap DAC Channel 2 on DMA1 channel 4 */
5800 #define DMA1_CSELR_CH4_I2C2_TX_Pos      (13U)
5801 #define DMA1_CSELR_CH4_I2C2_TX_Msk      (0x1UL << DMA1_CSELR_CH4_I2C2_TX_Pos)   /*!< 0x00002000 */
5802 #define DMA1_CSELR_CH4_I2C2_TX          DMA1_CSELR_CH4_I2C2_TX_Msk             /*!< Remap I2C2 Tx on DMA1 channel 4 */
5803 #define DMA1_CSELR_CH4_SPI2_RX_Pos      (12U)
5804 #define DMA1_CSELR_CH4_SPI2_RX_Msk      (0x3UL << DMA1_CSELR_CH4_SPI2_RX_Pos)   /*!< 0x00003000 */
5805 #define DMA1_CSELR_CH4_SPI2_RX          DMA1_CSELR_CH4_SPI2_RX_Msk             /*!< Remap SPI2 Rx on DMA1 channel 4 */
5806 #define DMA1_CSELR_CH4_TIM2_CH4_Pos     (12U)
5807 #define DMA1_CSELR_CH4_TIM2_CH4_Msk     (0x5UL << DMA1_CSELR_CH4_TIM2_CH4_Pos)  /*!< 0x00005000 */
5808 #define DMA1_CSELR_CH4_TIM2_CH4         DMA1_CSELR_CH4_TIM2_CH4_Msk            /*!< Remap TIM2 channel 4 on DMA1 channel 4 */
5809 #define DMA1_CSELR_CH4_TIM3_CH1_Pos     (13U)
5810 #define DMA1_CSELR_CH4_TIM3_CH1_Msk     (0x3UL << DMA1_CSELR_CH4_TIM3_CH1_Pos)  /*!< 0x00006000 */
5811 #define DMA1_CSELR_CH4_TIM3_CH1         DMA1_CSELR_CH4_TIM3_CH1_Msk            /*!< Remap TIM3 channel 1 on DMA1 channel 4 */
5812 #define DMA1_CSELR_CH4_TIM3_TRIG_Pos    (13U)
5813 #define DMA1_CSELR_CH4_TIM3_TRIG_Msk    (0x3UL << DMA1_CSELR_CH4_TIM3_TRIG_Pos) /*!< 0x00006000 */
5814 #define DMA1_CSELR_CH4_TIM3_TRIG        DMA1_CSELR_CH4_TIM3_TRIG_Msk           /*!< Remap TIM3 Trig on DMA1 channel 4 */
5815 #define DMA1_CSELR_CH4_TIM16_CH1_Pos    (12U)
5816 #define DMA1_CSELR_CH4_TIM16_CH1_Msk    (0x7UL << DMA1_CSELR_CH4_TIM16_CH1_Pos) /*!< 0x00007000 */
5817 #define DMA1_CSELR_CH4_TIM16_CH1        DMA1_CSELR_CH4_TIM16_CH1_Msk           /*!< Remap TIM16 channel 1 on DMA1 channel 4 */
5818 #define DMA1_CSELR_CH4_TIM16_UP_Pos     (12U)
5819 #define DMA1_CSELR_CH4_TIM16_UP_Msk     (0x7UL << DMA1_CSELR_CH4_TIM16_UP_Pos)  /*!< 0x00007000 */
5820 #define DMA1_CSELR_CH4_TIM16_UP         DMA1_CSELR_CH4_TIM16_UP_Msk            /*!< Remap TIM16 up on DMA1 channel 4 */
5821 #define DMA1_CSELR_CH4_USART1_TX_Pos    (15U)
5822 #define DMA1_CSELR_CH4_USART1_TX_Msk    (0x1UL << DMA1_CSELR_CH4_USART1_TX_Pos) /*!< 0x00008000 */
5823 #define DMA1_CSELR_CH4_USART1_TX        DMA1_CSELR_CH4_USART1_TX_Msk           /*!< Remap USART1 Tx on DMA1 channel 4 */
5824 #define DMA1_CSELR_CH4_USART2_TX_Pos    (12U)
5825 #define DMA1_CSELR_CH4_USART2_TX_Msk    (0x9UL << DMA1_CSELR_CH4_USART2_TX_Pos) /*!< 0x00009000 */
5826 #define DMA1_CSELR_CH4_USART2_TX        DMA1_CSELR_CH4_USART2_TX_Msk           /*!< Remap USART2 Tx on DMA1 channel 4 */
5827 #define DMA1_CSELR_CH4_USART3_TX_Pos    (13U)
5828 #define DMA1_CSELR_CH4_USART3_TX_Msk    (0x5UL << DMA1_CSELR_CH4_USART3_TX_Pos) /*!< 0x0000A000 */
5829 #define DMA1_CSELR_CH4_USART3_TX        DMA1_CSELR_CH4_USART3_TX_Msk           /*!< Remap USART3 Tx on DMA1 channel 4 */
5830 #define DMA1_CSELR_CH4_USART4_TX_Pos    (12U)
5831 #define DMA1_CSELR_CH4_USART4_TX_Msk    (0xBUL << DMA1_CSELR_CH4_USART4_TX_Pos) /*!< 0x0000B000 */
5832 #define DMA1_CSELR_CH4_USART4_TX        DMA1_CSELR_CH4_USART4_TX_Msk           /*!< Remap USART4 Tx on DMA1 channel 4 */
5833 #define DMA1_CSELR_CH4_USART5_TX_Pos    (14U)
5834 #define DMA1_CSELR_CH4_USART5_TX_Msk    (0x3UL << DMA1_CSELR_CH4_USART5_TX_Pos) /*!< 0x0000C000 */
5835 #define DMA1_CSELR_CH4_USART5_TX        DMA1_CSELR_CH4_USART5_TX_Msk           /*!< Remap USART5 Tx on DMA1 channel 4 */
5836 #define DMA1_CSELR_CH4_USART6_TX_Pos    (12U)
5837 #define DMA1_CSELR_CH4_USART6_TX_Msk    (0xDUL << DMA1_CSELR_CH4_USART6_TX_Pos) /*!< 0x0000D000 */
5838 #define DMA1_CSELR_CH4_USART6_TX        DMA1_CSELR_CH4_USART6_TX_Msk           /*!< Remap USART6 Tx on DMA1 channel 4 */
5839 #define DMA1_CSELR_CH4_USART7_TX_Pos    (13U)
5840 #define DMA1_CSELR_CH4_USART7_TX_Msk    (0x7UL << DMA1_CSELR_CH4_USART7_TX_Pos) /*!< 0x0000E000 */
5841 #define DMA1_CSELR_CH4_USART7_TX        DMA1_CSELR_CH4_USART7_TX_Msk           /*!< Remap USART7 Tx on DMA1 channel 4 */
5842 #define DMA1_CSELR_CH4_USART8_TX_Pos    (12U)
5843 #define DMA1_CSELR_CH4_USART8_TX_Msk    (0xFUL << DMA1_CSELR_CH4_USART8_TX_Pos) /*!< 0x0000F000 */
5844 #define DMA1_CSELR_CH4_USART8_TX        DMA1_CSELR_CH4_USART8_TX_Msk           /*!< Remap USART8 Tx on DMA1 channel 4 */
5845 #define DMA1_CSELR_CH5_I2C2_RX_Pos      (17U)
5846 #define DMA1_CSELR_CH5_I2C2_RX_Msk      (0x1UL << DMA1_CSELR_CH5_I2C2_RX_Pos)   /*!< 0x00020000 */
5847 #define DMA1_CSELR_CH5_I2C2_RX          DMA1_CSELR_CH5_I2C2_RX_Msk             /*!< Remap I2C2 Rx on DMA1 channel 5 */
5848 #define DMA1_CSELR_CH5_SPI2_TX_Pos      (16U)
5849 #define DMA1_CSELR_CH5_SPI2_TX_Msk      (0x3UL << DMA1_CSELR_CH5_SPI2_TX_Pos)   /*!< 0x00030000 */
5850 #define DMA1_CSELR_CH5_SPI2_TX          DMA1_CSELR_CH5_SPI2_TX_Msk             /*!< Remap SPI1 Tx on DMA1 channel 5 */
5851 #define DMA1_CSELR_CH5_TIM1_CH3_Pos     (18U)
5852 #define DMA1_CSELR_CH5_TIM1_CH3_Msk     (0x1UL << DMA1_CSELR_CH5_TIM1_CH3_Pos)  /*!< 0x00040000 */
5853 #define DMA1_CSELR_CH5_TIM1_CH3         DMA1_CSELR_CH5_TIM1_CH3_Msk            /*!< Remap TIM1 channel 3 on DMA1 channel 5 */
5854 #define DMA1_CSELR_CH5_USART1_RX_Pos    (19U)
5855 #define DMA1_CSELR_CH5_USART1_RX_Msk    (0x1UL << DMA1_CSELR_CH5_USART1_RX_Pos) /*!< 0x00080000 */
5856 #define DMA1_CSELR_CH5_USART1_RX        DMA1_CSELR_CH5_USART1_RX_Msk           /*!< Remap USART1 Rx on DMA1 channel 5 */
5857 #define DMA1_CSELR_CH5_USART2_RX_Pos    (16U)
5858 #define DMA1_CSELR_CH5_USART2_RX_Msk    (0x9UL << DMA1_CSELR_CH5_USART2_RX_Pos) /*!< 0x00090000 */
5859 #define DMA1_CSELR_CH5_USART2_RX        DMA1_CSELR_CH5_USART2_RX_Msk           /*!< Remap USART2 Rx on DMA1 channel 5 */
5860 #define DMA1_CSELR_CH5_USART3_RX_Pos    (17U)
5861 #define DMA1_CSELR_CH5_USART3_RX_Msk    (0x5UL << DMA1_CSELR_CH5_USART3_RX_Pos) /*!< 0x000A0000 */
5862 #define DMA1_CSELR_CH5_USART3_RX        DMA1_CSELR_CH5_USART3_RX_Msk           /*!< Remap USART3 Rx on DMA1 channel 5 */
5863 #define DMA1_CSELR_CH5_USART4_RX_Pos    (16U)
5864 #define DMA1_CSELR_CH5_USART4_RX_Msk    (0xBUL << DMA1_CSELR_CH5_USART4_RX_Pos) /*!< 0x000B0000 */
5865 #define DMA1_CSELR_CH5_USART4_RX        DMA1_CSELR_CH5_USART4_RX_Msk           /*!< Remap USART4 Rx on DMA1 channel 5 */
5866 #define DMA1_CSELR_CH5_USART5_RX_Pos    (18U)
5867 #define DMA1_CSELR_CH5_USART5_RX_Msk    (0x3UL << DMA1_CSELR_CH5_USART5_RX_Pos) /*!< 0x000C0000 */
5868 #define DMA1_CSELR_CH5_USART5_RX        DMA1_CSELR_CH5_USART5_RX_Msk           /*!< Remap USART5 Rx on DMA1 channel 5 */
5869 #define DMA1_CSELR_CH5_USART6_RX_Pos    (16U)
5870 #define DMA1_CSELR_CH5_USART6_RX_Msk    (0xDUL << DMA1_CSELR_CH5_USART6_RX_Pos) /*!< 0x000D0000 */
5871 #define DMA1_CSELR_CH5_USART6_RX        DMA1_CSELR_CH5_USART6_RX_Msk           /*!< Remap USART6 Rx on DMA1 channel 5 */
5872 #define DMA1_CSELR_CH5_USART7_RX_Pos    (17U)
5873 #define DMA1_CSELR_CH5_USART7_RX_Msk    (0x7UL << DMA1_CSELR_CH5_USART7_RX_Pos) /*!< 0x000E0000 */
5874 #define DMA1_CSELR_CH5_USART7_RX        DMA1_CSELR_CH5_USART7_RX_Msk           /*!< Remap USART7 Rx on DMA1 channel 5 */
5875 #define DMA1_CSELR_CH5_USART8_RX_Pos    (16U)
5876 #define DMA1_CSELR_CH5_USART8_RX_Msk    (0xFUL << DMA1_CSELR_CH5_USART8_RX_Pos) /*!< 0x000F0000 */
5877 #define DMA1_CSELR_CH5_USART8_RX        DMA1_CSELR_CH5_USART8_RX_Msk           /*!< Remap USART8 Rx on DMA1 channel 5 */
5878 #define DMA1_CSELR_CH6_I2C1_TX_Pos      (21U)
5879 #define DMA1_CSELR_CH6_I2C1_TX_Msk      (0x1UL << DMA1_CSELR_CH6_I2C1_TX_Pos)   /*!< 0x00200000 */
5880 #define DMA1_CSELR_CH6_I2C1_TX          DMA1_CSELR_CH6_I2C1_TX_Msk             /*!< Remap I2C1 Tx on DMA1 channel 6 */
5881 #define DMA1_CSELR_CH6_SPI2_RX_Pos      (20U)
5882 #define DMA1_CSELR_CH6_SPI2_RX_Msk      (0x3UL << DMA1_CSELR_CH6_SPI2_RX_Pos)   /*!< 0x00300000 */
5883 #define DMA1_CSELR_CH6_SPI2_RX          DMA1_CSELR_CH6_SPI2_RX_Msk             /*!< Remap SPI2 Rx on DMA1 channel 6 */
5884 #define DMA1_CSELR_CH6_TIM1_CH1_Pos     (22U)
5885 #define DMA1_CSELR_CH6_TIM1_CH1_Msk     (0x1UL << DMA1_CSELR_CH6_TIM1_CH1_Pos)  /*!< 0x00400000 */
5886 #define DMA1_CSELR_CH6_TIM1_CH1         DMA1_CSELR_CH6_TIM1_CH1_Msk            /*!< Remap TIM1 channel 1 on DMA1 channel 6 */
5887 #define DMA1_CSELR_CH6_TIM1_CH2_Pos     (22U)
5888 #define DMA1_CSELR_CH6_TIM1_CH2_Msk     (0x1UL << DMA1_CSELR_CH6_TIM1_CH2_Pos)  /*!< 0x00400000 */
5889 #define DMA1_CSELR_CH6_TIM1_CH2         DMA1_CSELR_CH6_TIM1_CH2_Msk            /*!< Remap TIM1 channel 2 on DMA1 channel 6 */
5890 #define DMA1_CSELR_CH6_TIM1_CH3_Pos     (22U)
5891 #define DMA1_CSELR_CH6_TIM1_CH3_Msk     (0x1UL << DMA1_CSELR_CH6_TIM1_CH3_Pos)  /*!< 0x00400000 */
5892 #define DMA1_CSELR_CH6_TIM1_CH3         DMA1_CSELR_CH6_TIM1_CH3_Msk            /*!< Remap TIM1 channel 3 on DMA1 channel 6 */
5893 #define DMA1_CSELR_CH6_TIM3_CH1_Pos     (21U)
5894 #define DMA1_CSELR_CH6_TIM3_CH1_Msk     (0x3UL << DMA1_CSELR_CH6_TIM3_CH1_Pos)  /*!< 0x00600000 */
5895 #define DMA1_CSELR_CH6_TIM3_CH1         DMA1_CSELR_CH6_TIM3_CH1_Msk            /*!< Remap TIM3 channel 1 on DMA1 channel 6 */
5896 #define DMA1_CSELR_CH6_TIM3_TRIG_Pos    (21U)
5897 #define DMA1_CSELR_CH6_TIM3_TRIG_Msk    (0x3UL << DMA1_CSELR_CH6_TIM3_TRIG_Pos) /*!< 0x00600000 */
5898 #define DMA1_CSELR_CH6_TIM3_TRIG        DMA1_CSELR_CH6_TIM3_TRIG_Msk           /*!< Remap TIM3 Trig on DMA1 channel 6 */
5899 #define DMA1_CSELR_CH6_TIM16_CH1_Pos    (20U)
5900 #define DMA1_CSELR_CH6_TIM16_CH1_Msk    (0x7UL << DMA1_CSELR_CH6_TIM16_CH1_Pos) /*!< 0x00700000 */
5901 #define DMA1_CSELR_CH6_TIM16_CH1        DMA1_CSELR_CH6_TIM16_CH1_Msk           /*!< Remap TIM16 channel 1 on DMA1 channel 6 */
5902 #define DMA1_CSELR_CH6_TIM16_UP_Pos     (20U)
5903 #define DMA1_CSELR_CH6_TIM16_UP_Msk     (0x7UL << DMA1_CSELR_CH6_TIM16_UP_Pos)  /*!< 0x00700000 */
5904 #define DMA1_CSELR_CH6_TIM16_UP         DMA1_CSELR_CH6_TIM16_UP_Msk            /*!< Remap TIM16 up on DMA1 channel 6 */
5905 #define DMA1_CSELR_CH6_USART1_RX_Pos    (23U)
5906 #define DMA1_CSELR_CH6_USART1_RX_Msk    (0x1UL << DMA1_CSELR_CH6_USART1_RX_Pos) /*!< 0x00800000 */
5907 #define DMA1_CSELR_CH6_USART1_RX        DMA1_CSELR_CH6_USART1_RX_Msk           /*!< Remap USART1 Rx on DMA1 channel 6 */
5908 #define DMA1_CSELR_CH6_USART2_RX_Pos    (20U)
5909 #define DMA1_CSELR_CH6_USART2_RX_Msk    (0x9UL << DMA1_CSELR_CH6_USART2_RX_Pos) /*!< 0x00900000 */
5910 #define DMA1_CSELR_CH6_USART2_RX        DMA1_CSELR_CH6_USART2_RX_Msk           /*!< Remap USART2 Rx on DMA1 channel 6 */
5911 #define DMA1_CSELR_CH6_USART3_RX_Pos    (21U)
5912 #define DMA1_CSELR_CH6_USART3_RX_Msk    (0x5UL << DMA1_CSELR_CH6_USART3_RX_Pos) /*!< 0x00A00000 */
5913 #define DMA1_CSELR_CH6_USART3_RX        DMA1_CSELR_CH6_USART3_RX_Msk           /*!< Remap USART3 Rx on DMA1 channel 6 */
5914 #define DMA1_CSELR_CH6_USART4_RX_Pos    (20U)
5915 #define DMA1_CSELR_CH6_USART4_RX_Msk    (0xBUL << DMA1_CSELR_CH6_USART4_RX_Pos) /*!< 0x00B00000 */
5916 #define DMA1_CSELR_CH6_USART4_RX        DMA1_CSELR_CH6_USART4_RX_Msk           /*!< Remap USART4 Rx on DMA1 channel 6 */
5917 #define DMA1_CSELR_CH6_USART5_RX_Pos    (22U)
5918 #define DMA1_CSELR_CH6_USART5_RX_Msk    (0x3UL << DMA1_CSELR_CH6_USART5_RX_Pos) /*!< 0x00C00000 */
5919 #define DMA1_CSELR_CH6_USART5_RX        DMA1_CSELR_CH6_USART5_RX_Msk           /*!< Remap USART5 Rx on DMA1 channel 6 */
5920 #define DMA1_CSELR_CH6_USART6_RX_Pos    (20U)
5921 #define DMA1_CSELR_CH6_USART6_RX_Msk    (0xDUL << DMA1_CSELR_CH6_USART6_RX_Pos) /*!< 0x00D00000 */
5922 #define DMA1_CSELR_CH6_USART6_RX        DMA1_CSELR_CH6_USART6_RX_Msk           /*!< Remap USART6 Rx on DMA1 channel 6 */
5923 #define DMA1_CSELR_CH6_USART7_RX_Pos    (21U)
5924 #define DMA1_CSELR_CH6_USART7_RX_Msk    (0x7UL << DMA1_CSELR_CH6_USART7_RX_Pos) /*!< 0x00E00000 */
5925 #define DMA1_CSELR_CH6_USART7_RX        DMA1_CSELR_CH6_USART7_RX_Msk           /*!< Remap USART7 Rx on DMA1 channel 6 */
5926 #define DMA1_CSELR_CH6_USART8_RX_Pos    (20U)
5927 #define DMA1_CSELR_CH6_USART8_RX_Msk    (0xFUL << DMA1_CSELR_CH6_USART8_RX_Pos) /*!< 0x00F00000 */
5928 #define DMA1_CSELR_CH6_USART8_RX        DMA1_CSELR_CH6_USART8_RX_Msk           /*!< Remap USART8 Rx on DMA1 channel 6 */
5929 #define DMA1_CSELR_CH7_I2C1_RX_Pos      (25U)
5930 #define DMA1_CSELR_CH7_I2C1_RX_Msk      (0x1UL << DMA1_CSELR_CH7_I2C1_RX_Pos)   /*!< 0x02000000 */
5931 #define DMA1_CSELR_CH7_I2C1_RX          DMA1_CSELR_CH7_I2C1_RX_Msk             /*!< Remap I2C1 Rx on DMA1 channel 7 */
5932 #define DMA1_CSELR_CH7_SPI2_TX_Pos      (24U)
5933 #define DMA1_CSELR_CH7_SPI2_TX_Msk      (0x3UL << DMA1_CSELR_CH7_SPI2_TX_Pos)   /*!< 0x03000000 */
5934 #define DMA1_CSELR_CH7_SPI2_TX          DMA1_CSELR_CH7_SPI2_TX_Msk             /*!< Remap SPI2 Tx on DMA1 channel 7 */
5935 #define DMA1_CSELR_CH7_TIM2_CH2_Pos     (24U)
5936 #define DMA1_CSELR_CH7_TIM2_CH2_Msk     (0x5UL << DMA1_CSELR_CH7_TIM2_CH2_Pos)  /*!< 0x05000000 */
5937 #define DMA1_CSELR_CH7_TIM2_CH2         DMA1_CSELR_CH7_TIM2_CH2_Msk            /*!< Remap TIM2 channel 2 on DMA1 channel 7 */
5938 #define DMA1_CSELR_CH7_TIM2_CH4_Pos     (24U)
5939 #define DMA1_CSELR_CH7_TIM2_CH4_Msk     (0x5UL << DMA1_CSELR_CH7_TIM2_CH4_Pos)  /*!< 0x05000000 */
5940 #define DMA1_CSELR_CH7_TIM2_CH4         DMA1_CSELR_CH7_TIM2_CH4_Msk            /*!< Remap TIM2 channel 4 on DMA1 channel 7 */
5941 #define DMA1_CSELR_CH7_TIM17_CH1_Pos    (24U)
5942 #define DMA1_CSELR_CH7_TIM17_CH1_Msk    (0x7UL << DMA1_CSELR_CH7_TIM17_CH1_Pos) /*!< 0x07000000 */
5943 #define DMA1_CSELR_CH7_TIM17_CH1        DMA1_CSELR_CH7_TIM17_CH1_Msk           /*!< Remap TIM17 channel 1 on DMA1 channel 7 */
5944 #define DMA1_CSELR_CH7_TIM17_UP_Pos     (24U)
5945 #define DMA1_CSELR_CH7_TIM17_UP_Msk     (0x7UL << DMA1_CSELR_CH7_TIM17_UP_Pos)  /*!< 0x07000000 */
5946 #define DMA1_CSELR_CH7_TIM17_UP         DMA1_CSELR_CH7_TIM17_UP_Msk            /*!< Remap TIM17 up on DMA1 channel 7 */
5947 #define DMA1_CSELR_CH7_USART1_TX_Pos    (27U)
5948 #define DMA1_CSELR_CH7_USART1_TX_Msk    (0x1UL << DMA1_CSELR_CH7_USART1_TX_Pos) /*!< 0x08000000 */
5949 #define DMA1_CSELR_CH7_USART1_TX        DMA1_CSELR_CH7_USART1_TX_Msk           /*!< Remap USART1 Tx on DMA1 channel 7 */
5950 #define DMA1_CSELR_CH7_USART2_TX_Pos    (24U)
5951 #define DMA1_CSELR_CH7_USART2_TX_Msk    (0x9UL << DMA1_CSELR_CH7_USART2_TX_Pos) /*!< 0x09000000 */
5952 #define DMA1_CSELR_CH7_USART2_TX        DMA1_CSELR_CH7_USART2_TX_Msk           /*!< Remap USART2 Tx on DMA1 channel 7 */
5953 #define DMA1_CSELR_CH7_USART3_TX_Pos    (25U)
5954 #define DMA1_CSELR_CH7_USART3_TX_Msk    (0x5UL << DMA1_CSELR_CH7_USART3_TX_Pos) /*!< 0x0A000000 */
5955 #define DMA1_CSELR_CH7_USART3_TX        DMA1_CSELR_CH7_USART3_TX_Msk           /*!< Remap USART3 Tx on DMA1 channel 7 */
5956 #define DMA1_CSELR_CH7_USART4_TX_Pos    (24U)
5957 #define DMA1_CSELR_CH7_USART4_TX_Msk    (0xBUL << DMA1_CSELR_CH7_USART4_TX_Pos) /*!< 0x0B000000 */
5958 #define DMA1_CSELR_CH7_USART4_TX        DMA1_CSELR_CH7_USART4_TX_Msk           /*!< Remap USART4 Tx on DMA1 channel 7 */
5959 #define DMA1_CSELR_CH7_USART5_TX_Pos    (26U)
5960 #define DMA1_CSELR_CH7_USART5_TX_Msk    (0x3UL << DMA1_CSELR_CH7_USART5_TX_Pos) /*!< 0x0C000000 */
5961 #define DMA1_CSELR_CH7_USART5_TX        DMA1_CSELR_CH7_USART5_TX_Msk           /*!< Remap USART5 Tx on DMA1 channel 7 */
5962 #define DMA1_CSELR_CH7_USART6_TX_Pos    (24U)
5963 #define DMA1_CSELR_CH7_USART6_TX_Msk    (0xDUL << DMA1_CSELR_CH7_USART6_TX_Pos) /*!< 0x0D000000 */
5964 #define DMA1_CSELR_CH7_USART6_TX        DMA1_CSELR_CH7_USART6_TX_Msk           /*!< Remap USART6 Tx on DMA1 channel 7 */
5965 #define DMA1_CSELR_CH7_USART7_TX_Pos    (25U)
5966 #define DMA1_CSELR_CH7_USART7_TX_Msk    (0x7UL << DMA1_CSELR_CH7_USART7_TX_Pos) /*!< 0x0E000000 */
5967 #define DMA1_CSELR_CH7_USART7_TX        DMA1_CSELR_CH7_USART7_TX_Msk           /*!< Remap USART7 Tx on DMA1 channel 7 */
5968 #define DMA1_CSELR_CH7_USART8_TX_Pos    (24U)
5969 #define DMA1_CSELR_CH7_USART8_TX_Msk    (0xFUL << DMA1_CSELR_CH7_USART8_TX_Pos) /*!< 0x0F000000 */
5970 #define DMA1_CSELR_CH7_USART8_TX        DMA1_CSELR_CH7_USART8_TX_Msk           /*!< Remap USART8 Tx on DMA1 channel 7 */
5971 
5972 /******************  Bit definition for DMA2_CSELR register  ********************/
5973 #define DMA2_CSELR_DEFAULT              (0x00000000U)                          /*!< Default remap position for DMA2 */
5974 #define DMA2_CSELR_CH1_I2C2_TX_Pos      (1U)
5975 #define DMA2_CSELR_CH1_I2C2_TX_Msk      (0x1UL << DMA2_CSELR_CH1_I2C2_TX_Pos)   /*!< 0x00000002 */
5976 #define DMA2_CSELR_CH1_I2C2_TX          DMA2_CSELR_CH1_I2C2_TX_Msk             /*!< Remap I2C2 TX on DMA2 channel 1 */
5977 #define DMA2_CSELR_CH1_USART1_TX_Pos    (3U)
5978 #define DMA2_CSELR_CH1_USART1_TX_Msk    (0x1UL << DMA2_CSELR_CH1_USART1_TX_Pos) /*!< 0x00000008 */
5979 #define DMA2_CSELR_CH1_USART1_TX        DMA2_CSELR_CH1_USART1_TX_Msk           /*!< Remap USART1 Tx on DMA2 channel 1 */
5980 #define DMA2_CSELR_CH1_USART2_TX_Pos    (0U)
5981 #define DMA2_CSELR_CH1_USART2_TX_Msk    (0x9UL << DMA2_CSELR_CH1_USART2_TX_Pos) /*!< 0x00000009 */
5982 #define DMA2_CSELR_CH1_USART2_TX        DMA2_CSELR_CH1_USART2_TX_Msk           /*!< Remap USART2 Tx on DMA2 channel 1 */
5983 #define DMA2_CSELR_CH1_USART3_TX_Pos    (1U)
5984 #define DMA2_CSELR_CH1_USART3_TX_Msk    (0x5UL << DMA2_CSELR_CH1_USART3_TX_Pos) /*!< 0x0000000A */
5985 #define DMA2_CSELR_CH1_USART3_TX        DMA2_CSELR_CH1_USART3_TX_Msk           /*!< Remap USART3 Tx on DMA2 channel 1 */
5986 #define DMA2_CSELR_CH1_USART4_TX_Pos    (0U)
5987 #define DMA2_CSELR_CH1_USART4_TX_Msk    (0xBUL << DMA2_CSELR_CH1_USART4_TX_Pos) /*!< 0x0000000B */
5988 #define DMA2_CSELR_CH1_USART4_TX        DMA2_CSELR_CH1_USART4_TX_Msk           /*!< Remap USART4 Tx on DMA2 channel 1 */
5989 #define DMA2_CSELR_CH1_USART5_TX_Pos    (2U)
5990 #define DMA2_CSELR_CH1_USART5_TX_Msk    (0x3UL << DMA2_CSELR_CH1_USART5_TX_Pos) /*!< 0x0000000C */
5991 #define DMA2_CSELR_CH1_USART5_TX        DMA2_CSELR_CH1_USART5_TX_Msk           /*!< Remap USART5 Tx on DMA2 channel 1 */
5992 #define DMA2_CSELR_CH1_USART6_TX_Pos    (0U)
5993 #define DMA2_CSELR_CH1_USART6_TX_Msk    (0xDUL << DMA2_CSELR_CH1_USART6_TX_Pos) /*!< 0x0000000D */
5994 #define DMA2_CSELR_CH1_USART6_TX        DMA2_CSELR_CH1_USART6_TX_Msk           /*!< Remap USART6 Tx on DMA2 channel 1 */
5995 #define DMA2_CSELR_CH1_USART7_TX_Pos    (1U)
5996 #define DMA2_CSELR_CH1_USART7_TX_Msk    (0x7UL << DMA2_CSELR_CH1_USART7_TX_Pos) /*!< 0x0000000E */
5997 #define DMA2_CSELR_CH1_USART7_TX        DMA2_CSELR_CH1_USART7_TX_Msk           /*!< Remap USART7 Tx on DMA2 channel 1 */
5998 #define DMA2_CSELR_CH1_USART8_TX_Pos    (0U)
5999 #define DMA2_CSELR_CH1_USART8_TX_Msk    (0xFUL << DMA2_CSELR_CH1_USART8_TX_Pos) /*!< 0x0000000F */
6000 #define DMA2_CSELR_CH1_USART8_TX        DMA2_CSELR_CH1_USART8_TX_Msk           /*!< Remap USART8 Tx on DMA2 channel 1 */
6001 #define DMA2_CSELR_CH2_I2C2_RX_Pos      (5U)
6002 #define DMA2_CSELR_CH2_I2C2_RX_Msk      (0x1UL << DMA2_CSELR_CH2_I2C2_RX_Pos)   /*!< 0x00000020 */
6003 #define DMA2_CSELR_CH2_I2C2_RX          DMA2_CSELR_CH2_I2C2_RX_Msk             /*!< Remap I2C2 Rx on DMA2 channel 2 */
6004 #define DMA2_CSELR_CH2_USART1_RX_Pos    (7U)
6005 #define DMA2_CSELR_CH2_USART1_RX_Msk    (0x1UL << DMA2_CSELR_CH2_USART1_RX_Pos) /*!< 0x00000080 */
6006 #define DMA2_CSELR_CH2_USART1_RX        DMA2_CSELR_CH2_USART1_RX_Msk           /*!< Remap USART1 Rx on DMA2 channel 2 */
6007 #define DMA2_CSELR_CH2_USART2_RX_Pos    (4U)
6008 #define DMA2_CSELR_CH2_USART2_RX_Msk    (0x9UL << DMA2_CSELR_CH2_USART2_RX_Pos) /*!< 0x00000090 */
6009 #define DMA2_CSELR_CH2_USART2_RX        DMA2_CSELR_CH2_USART2_RX_Msk           /*!< Remap USART2 Rx on DMA2 channel 2 */
6010 #define DMA2_CSELR_CH2_USART3_RX_Pos    (5U)
6011 #define DMA2_CSELR_CH2_USART3_RX_Msk    (0x5UL << DMA2_CSELR_CH2_USART3_RX_Pos) /*!< 0x000000A0 */
6012 #define DMA2_CSELR_CH2_USART3_RX        DMA2_CSELR_CH2_USART3_RX_Msk           /*!< Remap USART3 Rx on DMA2 channel 2 */
6013 #define DMA2_CSELR_CH2_USART4_RX_Pos    (4U)
6014 #define DMA2_CSELR_CH2_USART4_RX_Msk    (0xBUL << DMA2_CSELR_CH2_USART4_RX_Pos) /*!< 0x000000B0 */
6015 #define DMA2_CSELR_CH2_USART4_RX        DMA2_CSELR_CH2_USART4_RX_Msk           /*!< Remap USART4 Rx on DMA2 channel 2 */
6016 #define DMA2_CSELR_CH2_USART5_RX_Pos    (6U)
6017 #define DMA2_CSELR_CH2_USART5_RX_Msk    (0x3UL << DMA2_CSELR_CH2_USART5_RX_Pos) /*!< 0x000000C0 */
6018 #define DMA2_CSELR_CH2_USART5_RX        DMA2_CSELR_CH2_USART5_RX_Msk           /*!< Remap USART5 Rx on DMA2 channel 2 */
6019 #define DMA2_CSELR_CH2_USART6_RX_Pos    (4U)
6020 #define DMA2_CSELR_CH2_USART6_RX_Msk    (0xDUL << DMA2_CSELR_CH2_USART6_RX_Pos) /*!< 0x000000D0 */
6021 #define DMA2_CSELR_CH2_USART6_RX        DMA2_CSELR_CH2_USART6_RX_Msk           /*!< Remap USART6 Rx on DMA2 channel 2 */
6022 #define DMA2_CSELR_CH2_USART7_RX_Pos    (5U)
6023 #define DMA2_CSELR_CH2_USART7_RX_Msk    (0x7UL << DMA2_CSELR_CH2_USART7_RX_Pos) /*!< 0x000000E0 */
6024 #define DMA2_CSELR_CH2_USART7_RX        DMA2_CSELR_CH2_USART7_RX_Msk           /*!< Remap USART7 Rx on DMA2 channel 2 */
6025 #define DMA2_CSELR_CH2_USART8_RX_Pos    (4U)
6026 #define DMA2_CSELR_CH2_USART8_RX_Msk    (0xFUL << DMA2_CSELR_CH2_USART8_RX_Pos) /*!< 0x000000F0 */
6027 #define DMA2_CSELR_CH2_USART8_RX        DMA2_CSELR_CH2_USART8_RX_Msk           /*!< Remap USART8 Rx on DMA2 channel 2 */
6028 #define DMA2_CSELR_CH3_TIM6_UP_Pos      (8U)
6029 #define DMA2_CSELR_CH3_TIM6_UP_Msk      (0x1UL << DMA2_CSELR_CH3_TIM6_UP_Pos)   /*!< 0x00000100 */
6030 #define DMA2_CSELR_CH3_TIM6_UP          DMA2_CSELR_CH3_TIM6_UP_Msk             /*!< Remap TIM6 up on DMA2 channel 3 */
6031 #define DMA2_CSELR_CH3_DAC_CH1_Pos      (8U)
6032 #define DMA2_CSELR_CH3_DAC_CH1_Msk      (0x1UL << DMA2_CSELR_CH3_DAC_CH1_Pos)   /*!< 0x00000100 */
6033 #define DMA2_CSELR_CH3_DAC_CH1          DMA2_CSELR_CH3_DAC_CH1_Msk             /*!< Remap DAC channel 1 on DMA2 channel 3 */
6034 #define DMA2_CSELR_CH3_SPI1_RX_Pos      (8U)
6035 #define DMA2_CSELR_CH3_SPI1_RX_Msk      (0x3UL << DMA2_CSELR_CH3_SPI1_RX_Pos)   /*!< 0x00000300 */
6036 #define DMA2_CSELR_CH3_SPI1_RX          DMA2_CSELR_CH3_SPI1_RX_Msk             /*!< Remap SPI1 Rx on DMA2 channel 3 */
6037 #define DMA2_CSELR_CH3_USART1_RX_Pos    (11U)
6038 #define DMA2_CSELR_CH3_USART1_RX_Msk    (0x1UL << DMA2_CSELR_CH3_USART1_RX_Pos) /*!< 0x00000800 */
6039 #define DMA2_CSELR_CH3_USART1_RX        DMA2_CSELR_CH3_USART1_RX_Msk           /*!< Remap USART1 Rx on DMA2 channel 3 */
6040 #define DMA2_CSELR_CH3_USART2_RX_Pos    (8U)
6041 #define DMA2_CSELR_CH3_USART2_RX_Msk    (0x9UL << DMA2_CSELR_CH3_USART2_RX_Pos) /*!< 0x00000900 */
6042 #define DMA2_CSELR_CH3_USART2_RX        DMA2_CSELR_CH3_USART2_RX_Msk           /*!< Remap USART2 Rx on DMA2 channel 3 */
6043 #define DMA2_CSELR_CH3_USART3_RX_Pos    (9U)
6044 #define DMA2_CSELR_CH3_USART3_RX_Msk    (0x5UL << DMA2_CSELR_CH3_USART3_RX_Pos) /*!< 0x00000A00 */
6045 #define DMA2_CSELR_CH3_USART3_RX        DMA2_CSELR_CH3_USART3_RX_Msk           /*!< Remap USART3 Rx on DMA2 channel 3 */
6046 #define DMA2_CSELR_CH3_USART4_RX_Pos    (8U)
6047 #define DMA2_CSELR_CH3_USART4_RX_Msk    (0xBUL << DMA2_CSELR_CH3_USART4_RX_Pos) /*!< 0x00000B00 */
6048 #define DMA2_CSELR_CH3_USART4_RX        DMA2_CSELR_CH3_USART4_RX_Msk           /*!< Remap USART4 Rx on DMA2 channel 3 */
6049 #define DMA2_CSELR_CH3_USART5_RX_Pos    (10U)
6050 #define DMA2_CSELR_CH3_USART5_RX_Msk    (0x3UL << DMA2_CSELR_CH3_USART5_RX_Pos) /*!< 0x00000C00 */
6051 #define DMA2_CSELR_CH3_USART5_RX        DMA2_CSELR_CH3_USART5_RX_Msk           /*!< Remap USART5 Rx on DMA2 channel 3 */
6052 #define DMA2_CSELR_CH3_USART6_RX_Pos    (8U)
6053 #define DMA2_CSELR_CH3_USART6_RX_Msk    (0xDUL << DMA2_CSELR_CH3_USART6_RX_Pos) /*!< 0x00000D00 */
6054 #define DMA2_CSELR_CH3_USART6_RX        DMA2_CSELR_CH3_USART6_RX_Msk           /*!< Remap USART6 Rx on DMA2 channel 3 */
6055 #define DMA2_CSELR_CH3_USART7_RX_Pos    (9U)
6056 #define DMA2_CSELR_CH3_USART7_RX_Msk    (0x7UL << DMA2_CSELR_CH3_USART7_RX_Pos) /*!< 0x00000E00 */
6057 #define DMA2_CSELR_CH3_USART7_RX        DMA2_CSELR_CH3_USART7_RX_Msk           /*!< Remap USART7 Rx on DMA2 channel 3 */
6058 #define DMA2_CSELR_CH3_USART8_RX_Pos    (8U)
6059 #define DMA2_CSELR_CH3_USART8_RX_Msk    (0xFUL << DMA2_CSELR_CH3_USART8_RX_Pos) /*!< 0x00000F00 */
6060 #define DMA2_CSELR_CH3_USART8_RX        DMA2_CSELR_CH3_USART8_RX_Msk           /*!< Remap USART8 Rx on DMA2 channel 3 */
6061 #define DMA2_CSELR_CH4_TIM7_UP_Pos      (12U)
6062 #define DMA2_CSELR_CH4_TIM7_UP_Msk      (0x1UL << DMA2_CSELR_CH4_TIM7_UP_Pos)   /*!< 0x00001000 */
6063 #define DMA2_CSELR_CH4_TIM7_UP          DMA2_CSELR_CH4_TIM7_UP_Msk             /*!< Remap TIM7 up on DMA2 channel 4 */
6064 #define DMA2_CSELR_CH4_DAC_CH2_Pos      (12U)
6065 #define DMA2_CSELR_CH4_DAC_CH2_Msk      (0x1UL << DMA2_CSELR_CH4_DAC_CH2_Pos)   /*!< 0x00001000 */
6066 #define DMA2_CSELR_CH4_DAC_CH2          DMA2_CSELR_CH4_DAC_CH2_Msk             /*!< Remap DAC channel 2 on DMA2 channel 4 */
6067 #define DMA2_CSELR_CH4_SPI1_TX_Pos      (12U)
6068 #define DMA2_CSELR_CH4_SPI1_TX_Msk      (0x3UL << DMA2_CSELR_CH4_SPI1_TX_Pos)   /*!< 0x00003000 */
6069 #define DMA2_CSELR_CH4_SPI1_TX          DMA2_CSELR_CH4_SPI1_TX_Msk             /*!< Remap SPI1 Tx on DMA2 channel 4 */
6070 #define DMA2_CSELR_CH4_USART1_TX_Pos    (15U)
6071 #define DMA2_CSELR_CH4_USART1_TX_Msk    (0x1UL << DMA2_CSELR_CH4_USART1_TX_Pos) /*!< 0x00008000 */
6072 #define DMA2_CSELR_CH4_USART1_TX        DMA2_CSELR_CH4_USART1_TX_Msk           /*!< Remap USART1 Tx on DMA2 channel 4 */
6073 #define DMA2_CSELR_CH4_USART2_TX_Pos    (12U)
6074 #define DMA2_CSELR_CH4_USART2_TX_Msk    (0x9UL << DMA2_CSELR_CH4_USART2_TX_Pos) /*!< 0x00009000 */
6075 #define DMA2_CSELR_CH4_USART2_TX        DMA2_CSELR_CH4_USART2_TX_Msk           /*!< Remap USART2 Tx on DMA2 channel 4 */
6076 #define DMA2_CSELR_CH4_USART3_TX_Pos    (13U)
6077 #define DMA2_CSELR_CH4_USART3_TX_Msk    (0x5UL << DMA2_CSELR_CH4_USART3_TX_Pos) /*!< 0x0000A000 */
6078 #define DMA2_CSELR_CH4_USART3_TX        DMA2_CSELR_CH4_USART3_TX_Msk           /*!< Remap USART3 Tx on DMA2 channel 4 */
6079 #define DMA2_CSELR_CH4_USART4_TX_Pos    (12U)
6080 #define DMA2_CSELR_CH4_USART4_TX_Msk    (0xBUL << DMA2_CSELR_CH4_USART4_TX_Pos) /*!< 0x0000B000 */
6081 #define DMA2_CSELR_CH4_USART4_TX        DMA2_CSELR_CH4_USART4_TX_Msk           /*!< Remap USART4 Tx on DMA2 channel 4 */
6082 #define DMA2_CSELR_CH4_USART5_TX_Pos    (14U)
6083 #define DMA2_CSELR_CH4_USART5_TX_Msk    (0x3UL << DMA2_CSELR_CH4_USART5_TX_Pos) /*!< 0x0000C000 */
6084 #define DMA2_CSELR_CH4_USART5_TX        DMA2_CSELR_CH4_USART5_TX_Msk           /*!< Remap USART5 Tx on DMA2 channel 4 */
6085 #define DMA2_CSELR_CH4_USART6_TX_Pos    (12U)
6086 #define DMA2_CSELR_CH4_USART6_TX_Msk    (0xDUL << DMA2_CSELR_CH4_USART6_TX_Pos) /*!< 0x0000D000 */
6087 #define DMA2_CSELR_CH4_USART6_TX        DMA2_CSELR_CH4_USART6_TX_Msk           /*!< Remap USART6 Tx on DMA2 channel 4 */
6088 #define DMA2_CSELR_CH4_USART7_TX_Pos    (13U)
6089 #define DMA2_CSELR_CH4_USART7_TX_Msk    (0x7UL << DMA2_CSELR_CH4_USART7_TX_Pos) /*!< 0x0000E000 */
6090 #define DMA2_CSELR_CH4_USART7_TX        DMA2_CSELR_CH4_USART7_TX_Msk           /*!< Remap USART7 Tx on DMA2 channel 4 */
6091 #define DMA2_CSELR_CH4_USART8_TX_Pos    (12U)
6092 #define DMA2_CSELR_CH4_USART8_TX_Msk    (0xFUL << DMA2_CSELR_CH4_USART8_TX_Pos) /*!< 0x0000F000 */
6093 #define DMA2_CSELR_CH4_USART8_TX        DMA2_CSELR_CH4_USART8_TX_Msk           /*!< Remap USART8 Tx on DMA2 channel 4 */
6094 #define DMA2_CSELR_CH5_ADC_Pos          (16U)
6095 #define DMA2_CSELR_CH5_ADC_Msk          (0x1UL << DMA2_CSELR_CH5_ADC_Pos)       /*!< 0x00010000 */
6096 #define DMA2_CSELR_CH5_ADC              DMA2_CSELR_CH5_ADC_Msk                 /*!< Remap ADC on DMA2 channel 5 */
6097 #define DMA2_CSELR_CH5_USART1_TX_Pos    (19U)
6098 #define DMA2_CSELR_CH5_USART1_TX_Msk    (0x1UL << DMA2_CSELR_CH5_USART1_TX_Pos) /*!< 0x00080000 */
6099 #define DMA2_CSELR_CH5_USART1_TX        DMA2_CSELR_CH5_USART1_TX_Msk           /*!< Remap USART1 Tx on DMA2 channel 5 */
6100 #define DMA2_CSELR_CH5_USART2_TX_Pos    (16U)
6101 #define DMA2_CSELR_CH5_USART2_TX_Msk    (0x9UL << DMA2_CSELR_CH5_USART2_TX_Pos) /*!< 0x00090000 */
6102 #define DMA2_CSELR_CH5_USART2_TX        DMA2_CSELR_CH5_USART2_TX_Msk           /*!< Remap USART2 Tx on DMA2 channel 5 */
6103 #define DMA2_CSELR_CH5_USART3_TX_Pos    (17U)
6104 #define DMA2_CSELR_CH5_USART3_TX_Msk    (0x5UL << DMA2_CSELR_CH5_USART3_TX_Pos) /*!< 0x000A0000 */
6105 #define DMA2_CSELR_CH5_USART3_TX        DMA2_CSELR_CH5_USART3_TX_Msk           /*!< Remap USART3 Tx on DMA2 channel 5 */
6106 #define DMA2_CSELR_CH5_USART4_TX_Pos    (16U)
6107 #define DMA2_CSELR_CH5_USART4_TX_Msk    (0xBUL << DMA2_CSELR_CH5_USART4_TX_Pos) /*!< 0x000B0000 */
6108 #define DMA2_CSELR_CH5_USART4_TX        DMA2_CSELR_CH5_USART4_TX_Msk           /*!< Remap USART4 Tx on DMA2 channel 5 */
6109 #define DMA2_CSELR_CH5_USART5_TX_Pos    (18U)
6110 #define DMA2_CSELR_CH5_USART5_TX_Msk    (0x3UL << DMA2_CSELR_CH5_USART5_TX_Pos) /*!< 0x000C0000 */
6111 #define DMA2_CSELR_CH5_USART5_TX        DMA2_CSELR_CH5_USART5_TX_Msk           /*!< Remap USART5 Tx on DMA2 channel 5 */
6112 #define DMA2_CSELR_CH5_USART6_TX_Pos    (16U)
6113 #define DMA2_CSELR_CH5_USART6_TX_Msk    (0xDUL << DMA2_CSELR_CH5_USART6_TX_Pos) /*!< 0x000D0000 */
6114 #define DMA2_CSELR_CH5_USART6_TX        DMA2_CSELR_CH5_USART6_TX_Msk           /*!< Remap USART6 Tx on DMA2 channel 5 */
6115 #define DMA2_CSELR_CH5_USART7_TX_Pos    (17U)
6116 #define DMA2_CSELR_CH5_USART7_TX_Msk    (0x7UL << DMA2_CSELR_CH5_USART7_TX_Pos) /*!< 0x000E0000 */
6117 #define DMA2_CSELR_CH5_USART7_TX        DMA2_CSELR_CH5_USART7_TX_Msk           /*!< Remap USART7 Tx on DMA2 channel 5 */
6118 #define DMA2_CSELR_CH5_USART8_TX_Pos    (16U)
6119 #define DMA2_CSELR_CH5_USART8_TX_Msk    (0xFUL << DMA2_CSELR_CH5_USART8_TX_Pos) /*!< 0x000F0000 */
6120 #define DMA2_CSELR_CH5_USART8_TX        DMA2_CSELR_CH5_USART8_TX_Msk           /*!< Remap USART8 Tx on DMA2 channel 5 */
6121 
6122 /******************************************************************************/
6123 /*                                                                            */
6124 /*                 External Interrupt/Event Controller (EXTI)                 */
6125 /*                                                                            */
6126 /******************************************************************************/
6127 /*******************  Bit definition for EXTI_IMR register  *******************/
6128 #define EXTI_IMR_MR0_Pos          (0U)
6129 #define EXTI_IMR_MR0_Msk          (0x1UL << EXTI_IMR_MR0_Pos)                   /*!< 0x00000001 */
6130 #define EXTI_IMR_MR0              EXTI_IMR_MR0_Msk                             /*!< Interrupt Mask on line 0  */
6131 #define EXTI_IMR_MR1_Pos          (1U)
6132 #define EXTI_IMR_MR1_Msk          (0x1UL << EXTI_IMR_MR1_Pos)                   /*!< 0x00000002 */
6133 #define EXTI_IMR_MR1              EXTI_IMR_MR1_Msk                             /*!< Interrupt Mask on line 1  */
6134 #define EXTI_IMR_MR2_Pos          (2U)
6135 #define EXTI_IMR_MR2_Msk          (0x1UL << EXTI_IMR_MR2_Pos)                   /*!< 0x00000004 */
6136 #define EXTI_IMR_MR2              EXTI_IMR_MR2_Msk                             /*!< Interrupt Mask on line 2  */
6137 #define EXTI_IMR_MR3_Pos          (3U)
6138 #define EXTI_IMR_MR3_Msk          (0x1UL << EXTI_IMR_MR3_Pos)                   /*!< 0x00000008 */
6139 #define EXTI_IMR_MR3              EXTI_IMR_MR3_Msk                             /*!< Interrupt Mask on line 3  */
6140 #define EXTI_IMR_MR4_Pos          (4U)
6141 #define EXTI_IMR_MR4_Msk          (0x1UL << EXTI_IMR_MR4_Pos)                   /*!< 0x00000010 */
6142 #define EXTI_IMR_MR4              EXTI_IMR_MR4_Msk                             /*!< Interrupt Mask on line 4  */
6143 #define EXTI_IMR_MR5_Pos          (5U)
6144 #define EXTI_IMR_MR5_Msk          (0x1UL << EXTI_IMR_MR5_Pos)                   /*!< 0x00000020 */
6145 #define EXTI_IMR_MR5              EXTI_IMR_MR5_Msk                             /*!< Interrupt Mask on line 5  */
6146 #define EXTI_IMR_MR6_Pos          (6U)
6147 #define EXTI_IMR_MR6_Msk          (0x1UL << EXTI_IMR_MR6_Pos)                   /*!< 0x00000040 */
6148 #define EXTI_IMR_MR6              EXTI_IMR_MR6_Msk                             /*!< Interrupt Mask on line 6  */
6149 #define EXTI_IMR_MR7_Pos          (7U)
6150 #define EXTI_IMR_MR7_Msk          (0x1UL << EXTI_IMR_MR7_Pos)                   /*!< 0x00000080 */
6151 #define EXTI_IMR_MR7              EXTI_IMR_MR7_Msk                             /*!< Interrupt Mask on line 7  */
6152 #define EXTI_IMR_MR8_Pos          (8U)
6153 #define EXTI_IMR_MR8_Msk          (0x1UL << EXTI_IMR_MR8_Pos)                   /*!< 0x00000100 */
6154 #define EXTI_IMR_MR8              EXTI_IMR_MR8_Msk                             /*!< Interrupt Mask on line 8  */
6155 #define EXTI_IMR_MR9_Pos          (9U)
6156 #define EXTI_IMR_MR9_Msk          (0x1UL << EXTI_IMR_MR9_Pos)                   /*!< 0x00000200 */
6157 #define EXTI_IMR_MR9              EXTI_IMR_MR9_Msk                             /*!< Interrupt Mask on line 9  */
6158 #define EXTI_IMR_MR10_Pos         (10U)
6159 #define EXTI_IMR_MR10_Msk         (0x1UL << EXTI_IMR_MR10_Pos)                  /*!< 0x00000400 */
6160 #define EXTI_IMR_MR10             EXTI_IMR_MR10_Msk                            /*!< Interrupt Mask on line 10 */
6161 #define EXTI_IMR_MR11_Pos         (11U)
6162 #define EXTI_IMR_MR11_Msk         (0x1UL << EXTI_IMR_MR11_Pos)                  /*!< 0x00000800 */
6163 #define EXTI_IMR_MR11             EXTI_IMR_MR11_Msk                            /*!< Interrupt Mask on line 11 */
6164 #define EXTI_IMR_MR12_Pos         (12U)
6165 #define EXTI_IMR_MR12_Msk         (0x1UL << EXTI_IMR_MR12_Pos)                  /*!< 0x00001000 */
6166 #define EXTI_IMR_MR12             EXTI_IMR_MR12_Msk                            /*!< Interrupt Mask on line 12 */
6167 #define EXTI_IMR_MR13_Pos         (13U)
6168 #define EXTI_IMR_MR13_Msk         (0x1UL << EXTI_IMR_MR13_Pos)                  /*!< 0x00002000 */
6169 #define EXTI_IMR_MR13             EXTI_IMR_MR13_Msk                            /*!< Interrupt Mask on line 13 */
6170 #define EXTI_IMR_MR14_Pos         (14U)
6171 #define EXTI_IMR_MR14_Msk         (0x1UL << EXTI_IMR_MR14_Pos)                  /*!< 0x00004000 */
6172 #define EXTI_IMR_MR14             EXTI_IMR_MR14_Msk                            /*!< Interrupt Mask on line 14 */
6173 #define EXTI_IMR_MR15_Pos         (15U)
6174 #define EXTI_IMR_MR15_Msk         (0x1UL << EXTI_IMR_MR15_Pos)                  /*!< 0x00008000 */
6175 #define EXTI_IMR_MR15             EXTI_IMR_MR15_Msk                            /*!< Interrupt Mask on line 15 */
6176 #define EXTI_IMR_MR16_Pos         (16U)
6177 #define EXTI_IMR_MR16_Msk         (0x1UL << EXTI_IMR_MR16_Pos)                  /*!< 0x00010000 */
6178 #define EXTI_IMR_MR16             EXTI_IMR_MR16_Msk                            /*!< Interrupt Mask on line 16 */
6179 #define EXTI_IMR_MR17_Pos         (17U)
6180 #define EXTI_IMR_MR17_Msk         (0x1UL << EXTI_IMR_MR17_Pos)                  /*!< 0x00020000 */
6181 #define EXTI_IMR_MR17             EXTI_IMR_MR17_Msk                            /*!< Interrupt Mask on line 17 */
6182 #define EXTI_IMR_MR19_Pos         (19U)
6183 #define EXTI_IMR_MR19_Msk         (0x1UL << EXTI_IMR_MR19_Pos)                  /*!< 0x00080000 */
6184 #define EXTI_IMR_MR19             EXTI_IMR_MR19_Msk                            /*!< Interrupt Mask on line 19 */
6185 #define EXTI_IMR_MR20_Pos         (20U)
6186 #define EXTI_IMR_MR20_Msk         (0x1UL << EXTI_IMR_MR20_Pos)                  /*!< 0x00100000 */
6187 #define EXTI_IMR_MR20             EXTI_IMR_MR20_Msk                            /*!< Interrupt Mask on line 20 */
6188 #define EXTI_IMR_MR21_Pos         (21U)
6189 #define EXTI_IMR_MR21_Msk         (0x1UL << EXTI_IMR_MR21_Pos)                  /*!< 0x00200000 */
6190 #define EXTI_IMR_MR21             EXTI_IMR_MR21_Msk                            /*!< Interrupt Mask on line 21 */
6191 #define EXTI_IMR_MR22_Pos         (22U)
6192 #define EXTI_IMR_MR22_Msk         (0x1UL << EXTI_IMR_MR22_Pos)                  /*!< 0x00400000 */
6193 #define EXTI_IMR_MR22             EXTI_IMR_MR22_Msk                            /*!< Interrupt Mask on line 22 */
6194 #define EXTI_IMR_MR23_Pos         (23U)
6195 #define EXTI_IMR_MR23_Msk         (0x1UL << EXTI_IMR_MR23_Pos)                  /*!< 0x00800000 */
6196 #define EXTI_IMR_MR23             EXTI_IMR_MR23_Msk                            /*!< Interrupt Mask on line 23 */
6197 #define EXTI_IMR_MR25_Pos         (25U)
6198 #define EXTI_IMR_MR25_Msk         (0x1UL << EXTI_IMR_MR25_Pos)                  /*!< 0x02000000 */
6199 #define EXTI_IMR_MR25             EXTI_IMR_MR25_Msk                            /*!< Interrupt Mask on line 25 */
6200 #define EXTI_IMR_MR26_Pos         (26U)
6201 #define EXTI_IMR_MR26_Msk         (0x1UL << EXTI_IMR_MR26_Pos)                  /*!< 0x04000000 */
6202 #define EXTI_IMR_MR26             EXTI_IMR_MR26_Msk                            /*!< Interrupt Mask on line 26 */
6203 #define EXTI_IMR_MR27_Pos         (27U)
6204 #define EXTI_IMR_MR27_Msk         (0x1UL << EXTI_IMR_MR27_Pos)                  /*!< 0x08000000 */
6205 #define EXTI_IMR_MR27             EXTI_IMR_MR27_Msk                            /*!< Interrupt Mask on line 27 */
6206 #define EXTI_IMR_MR28_Pos         (28U)
6207 #define EXTI_IMR_MR28_Msk         (0x1UL << EXTI_IMR_MR28_Pos)                  /*!< 0x10000000 */
6208 #define EXTI_IMR_MR28             EXTI_IMR_MR28_Msk                            /*!< Interrupt Mask on line 28 */
6209 #define EXTI_IMR_MR31_Pos         (31U)
6210 #define EXTI_IMR_MR31_Msk         (0x1UL << EXTI_IMR_MR31_Pos)                  /*!< 0x80000000 */
6211 #define EXTI_IMR_MR31             EXTI_IMR_MR31_Msk                            /*!< Interrupt Mask on line 31 */
6212 
6213 /* References Defines */
6214 #define  EXTI_IMR_IM0 EXTI_IMR_MR0
6215 #define  EXTI_IMR_IM1 EXTI_IMR_MR1
6216 #define  EXTI_IMR_IM2 EXTI_IMR_MR2
6217 #define  EXTI_IMR_IM3 EXTI_IMR_MR3
6218 #define  EXTI_IMR_IM4 EXTI_IMR_MR4
6219 #define  EXTI_IMR_IM5 EXTI_IMR_MR5
6220 #define  EXTI_IMR_IM6 EXTI_IMR_MR6
6221 #define  EXTI_IMR_IM7 EXTI_IMR_MR7
6222 #define  EXTI_IMR_IM8 EXTI_IMR_MR8
6223 #define  EXTI_IMR_IM9 EXTI_IMR_MR9
6224 #define  EXTI_IMR_IM10 EXTI_IMR_MR10
6225 #define  EXTI_IMR_IM11 EXTI_IMR_MR11
6226 #define  EXTI_IMR_IM12 EXTI_IMR_MR12
6227 #define  EXTI_IMR_IM13 EXTI_IMR_MR13
6228 #define  EXTI_IMR_IM14 EXTI_IMR_MR14
6229 #define  EXTI_IMR_IM15 EXTI_IMR_MR15
6230 #define  EXTI_IMR_IM16 EXTI_IMR_MR16
6231 #define  EXTI_IMR_IM17 EXTI_IMR_MR17
6232 #define  EXTI_IMR_IM19 EXTI_IMR_MR19
6233 #define  EXTI_IMR_IM20 EXTI_IMR_MR20
6234 #define  EXTI_IMR_IM21 EXTI_IMR_MR21
6235 #define  EXTI_IMR_IM22 EXTI_IMR_MR22
6236 #define  EXTI_IMR_IM23 EXTI_IMR_MR23
6237 #define  EXTI_IMR_IM25 EXTI_IMR_MR25
6238 #define  EXTI_IMR_IM26 EXTI_IMR_MR26
6239 #define  EXTI_IMR_IM27 EXTI_IMR_MR27
6240 #define  EXTI_IMR_IM28 EXTI_IMR_MR28
6241 #define  EXTI_IMR_IM31 EXTI_IMR_MR31
6242 
6243 #define EXTI_IMR_IM_Pos           (0U)
6244 #define EXTI_IMR_IM_Msk           (0x9EFFFFFFUL << EXTI_IMR_IM_Pos)             /*!< 0x9EFFFFFF */
6245 #define EXTI_IMR_IM               EXTI_IMR_IM_Msk                              /*!< Interrupt Mask All */
6246 
6247 
6248 /******************  Bit definition for EXTI_EMR register  ********************/
6249 #define EXTI_EMR_MR0_Pos          (0U)
6250 #define EXTI_EMR_MR0_Msk          (0x1UL << EXTI_EMR_MR0_Pos)                   /*!< 0x00000001 */
6251 #define EXTI_EMR_MR0              EXTI_EMR_MR0_Msk                             /*!< Event Mask on line 0  */
6252 #define EXTI_EMR_MR1_Pos          (1U)
6253 #define EXTI_EMR_MR1_Msk          (0x1UL << EXTI_EMR_MR1_Pos)                   /*!< 0x00000002 */
6254 #define EXTI_EMR_MR1              EXTI_EMR_MR1_Msk                             /*!< Event Mask on line 1  */
6255 #define EXTI_EMR_MR2_Pos          (2U)
6256 #define EXTI_EMR_MR2_Msk          (0x1UL << EXTI_EMR_MR2_Pos)                   /*!< 0x00000004 */
6257 #define EXTI_EMR_MR2              EXTI_EMR_MR2_Msk                             /*!< Event Mask on line 2  */
6258 #define EXTI_EMR_MR3_Pos          (3U)
6259 #define EXTI_EMR_MR3_Msk          (0x1UL << EXTI_EMR_MR3_Pos)                   /*!< 0x00000008 */
6260 #define EXTI_EMR_MR3              EXTI_EMR_MR3_Msk                             /*!< Event Mask on line 3  */
6261 #define EXTI_EMR_MR4_Pos          (4U)
6262 #define EXTI_EMR_MR4_Msk          (0x1UL << EXTI_EMR_MR4_Pos)                   /*!< 0x00000010 */
6263 #define EXTI_EMR_MR4              EXTI_EMR_MR4_Msk                             /*!< Event Mask on line 4  */
6264 #define EXTI_EMR_MR5_Pos          (5U)
6265 #define EXTI_EMR_MR5_Msk          (0x1UL << EXTI_EMR_MR5_Pos)                   /*!< 0x00000020 */
6266 #define EXTI_EMR_MR5              EXTI_EMR_MR5_Msk                             /*!< Event Mask on line 5  */
6267 #define EXTI_EMR_MR6_Pos          (6U)
6268 #define EXTI_EMR_MR6_Msk          (0x1UL << EXTI_EMR_MR6_Pos)                   /*!< 0x00000040 */
6269 #define EXTI_EMR_MR6              EXTI_EMR_MR6_Msk                             /*!< Event Mask on line 6  */
6270 #define EXTI_EMR_MR7_Pos          (7U)
6271 #define EXTI_EMR_MR7_Msk          (0x1UL << EXTI_EMR_MR7_Pos)                   /*!< 0x00000080 */
6272 #define EXTI_EMR_MR7              EXTI_EMR_MR7_Msk                             /*!< Event Mask on line 7  */
6273 #define EXTI_EMR_MR8_Pos          (8U)
6274 #define EXTI_EMR_MR8_Msk          (0x1UL << EXTI_EMR_MR8_Pos)                   /*!< 0x00000100 */
6275 #define EXTI_EMR_MR8              EXTI_EMR_MR8_Msk                             /*!< Event Mask on line 8  */
6276 #define EXTI_EMR_MR9_Pos          (9U)
6277 #define EXTI_EMR_MR9_Msk          (0x1UL << EXTI_EMR_MR9_Pos)                   /*!< 0x00000200 */
6278 #define EXTI_EMR_MR9              EXTI_EMR_MR9_Msk                             /*!< Event Mask on line 9  */
6279 #define EXTI_EMR_MR10_Pos         (10U)
6280 #define EXTI_EMR_MR10_Msk         (0x1UL << EXTI_EMR_MR10_Pos)                  /*!< 0x00000400 */
6281 #define EXTI_EMR_MR10             EXTI_EMR_MR10_Msk                            /*!< Event Mask on line 10 */
6282 #define EXTI_EMR_MR11_Pos         (11U)
6283 #define EXTI_EMR_MR11_Msk         (0x1UL << EXTI_EMR_MR11_Pos)                  /*!< 0x00000800 */
6284 #define EXTI_EMR_MR11             EXTI_EMR_MR11_Msk                            /*!< Event Mask on line 11 */
6285 #define EXTI_EMR_MR12_Pos         (12U)
6286 #define EXTI_EMR_MR12_Msk         (0x1UL << EXTI_EMR_MR12_Pos)                  /*!< 0x00001000 */
6287 #define EXTI_EMR_MR12             EXTI_EMR_MR12_Msk                            /*!< Event Mask on line 12 */
6288 #define EXTI_EMR_MR13_Pos         (13U)
6289 #define EXTI_EMR_MR13_Msk         (0x1UL << EXTI_EMR_MR13_Pos)                  /*!< 0x00002000 */
6290 #define EXTI_EMR_MR13             EXTI_EMR_MR13_Msk                            /*!< Event Mask on line 13 */
6291 #define EXTI_EMR_MR14_Pos         (14U)
6292 #define EXTI_EMR_MR14_Msk         (0x1UL << EXTI_EMR_MR14_Pos)                  /*!< 0x00004000 */
6293 #define EXTI_EMR_MR14             EXTI_EMR_MR14_Msk                            /*!< Event Mask on line 14 */
6294 #define EXTI_EMR_MR15_Pos         (15U)
6295 #define EXTI_EMR_MR15_Msk         (0x1UL << EXTI_EMR_MR15_Pos)                  /*!< 0x00008000 */
6296 #define EXTI_EMR_MR15             EXTI_EMR_MR15_Msk                            /*!< Event Mask on line 15 */
6297 #define EXTI_EMR_MR16_Pos         (16U)
6298 #define EXTI_EMR_MR16_Msk         (0x1UL << EXTI_EMR_MR16_Pos)                  /*!< 0x00010000 */
6299 #define EXTI_EMR_MR16             EXTI_EMR_MR16_Msk                            /*!< Event Mask on line 16 */
6300 #define EXTI_EMR_MR17_Pos         (17U)
6301 #define EXTI_EMR_MR17_Msk         (0x1UL << EXTI_EMR_MR17_Pos)                  /*!< 0x00020000 */
6302 #define EXTI_EMR_MR17             EXTI_EMR_MR17_Msk                            /*!< Event Mask on line 17 */
6303 #define EXTI_EMR_MR19_Pos         (19U)
6304 #define EXTI_EMR_MR19_Msk         (0x1UL << EXTI_EMR_MR19_Pos)                  /*!< 0x00080000 */
6305 #define EXTI_EMR_MR19             EXTI_EMR_MR19_Msk                            /*!< Event Mask on line 19 */
6306 #define EXTI_EMR_MR20_Pos         (20U)
6307 #define EXTI_EMR_MR20_Msk         (0x1UL << EXTI_EMR_MR20_Pos)                  /*!< 0x00100000 */
6308 #define EXTI_EMR_MR20             EXTI_EMR_MR20_Msk                            /*!< Event Mask on line 20 */
6309 #define EXTI_EMR_MR21_Pos         (21U)
6310 #define EXTI_EMR_MR21_Msk         (0x1UL << EXTI_EMR_MR21_Pos)                  /*!< 0x00200000 */
6311 #define EXTI_EMR_MR21             EXTI_EMR_MR21_Msk                            /*!< Event Mask on line 21 */
6312 #define EXTI_EMR_MR22_Pos         (22U)
6313 #define EXTI_EMR_MR22_Msk         (0x1UL << EXTI_EMR_MR22_Pos)                  /*!< 0x00400000 */
6314 #define EXTI_EMR_MR22             EXTI_EMR_MR22_Msk                            /*!< Event Mask on line 22 */
6315 #define EXTI_EMR_MR23_Pos         (23U)
6316 #define EXTI_EMR_MR23_Msk         (0x1UL << EXTI_EMR_MR23_Pos)                  /*!< 0x00800000 */
6317 #define EXTI_EMR_MR23             EXTI_EMR_MR23_Msk                            /*!< Event Mask on line 23 */
6318 #define EXTI_EMR_MR25_Pos         (25U)
6319 #define EXTI_EMR_MR25_Msk         (0x1UL << EXTI_EMR_MR25_Pos)                  /*!< 0x02000000 */
6320 #define EXTI_EMR_MR25             EXTI_EMR_MR25_Msk                            /*!< Event Mask on line 25 */
6321 #define EXTI_EMR_MR26_Pos         (26U)
6322 #define EXTI_EMR_MR26_Msk         (0x1UL << EXTI_EMR_MR26_Pos)                  /*!< 0x04000000 */
6323 #define EXTI_EMR_MR26             EXTI_EMR_MR26_Msk                            /*!< Event Mask on line 26 */
6324 #define EXTI_EMR_MR27_Pos         (27U)
6325 #define EXTI_EMR_MR27_Msk         (0x1UL << EXTI_EMR_MR27_Pos)                  /*!< 0x08000000 */
6326 #define EXTI_EMR_MR27             EXTI_EMR_MR27_Msk                            /*!< Event Mask on line 27 */
6327 #define EXTI_EMR_MR28_Pos         (28U)
6328 #define EXTI_EMR_MR28_Msk         (0x1UL << EXTI_EMR_MR28_Pos)                  /*!< 0x10000000 */
6329 #define EXTI_EMR_MR28             EXTI_EMR_MR28_Msk                            /*!< Event Mask on line 28 */
6330 #define EXTI_EMR_MR31_Pos         (31U)
6331 #define EXTI_EMR_MR31_Msk         (0x1UL << EXTI_EMR_MR31_Pos)                  /*!< 0x80000000 */
6332 #define EXTI_EMR_MR31             EXTI_EMR_MR31_Msk                            /*!< Event Mask on line 31 */
6333 
6334 /* References Defines */
6335 #define  EXTI_EMR_EM0 EXTI_EMR_MR0
6336 #define  EXTI_EMR_EM1 EXTI_EMR_MR1
6337 #define  EXTI_EMR_EM2 EXTI_EMR_MR2
6338 #define  EXTI_EMR_EM3 EXTI_EMR_MR3
6339 #define  EXTI_EMR_EM4 EXTI_EMR_MR4
6340 #define  EXTI_EMR_EM5 EXTI_EMR_MR5
6341 #define  EXTI_EMR_EM6 EXTI_EMR_MR6
6342 #define  EXTI_EMR_EM7 EXTI_EMR_MR7
6343 #define  EXTI_EMR_EM8 EXTI_EMR_MR8
6344 #define  EXTI_EMR_EM9 EXTI_EMR_MR9
6345 #define  EXTI_EMR_EM10 EXTI_EMR_MR10
6346 #define  EXTI_EMR_EM11 EXTI_EMR_MR11
6347 #define  EXTI_EMR_EM12 EXTI_EMR_MR12
6348 #define  EXTI_EMR_EM13 EXTI_EMR_MR13
6349 #define  EXTI_EMR_EM14 EXTI_EMR_MR14
6350 #define  EXTI_EMR_EM15 EXTI_EMR_MR15
6351 #define  EXTI_EMR_EM16 EXTI_EMR_MR16
6352 #define  EXTI_EMR_EM17 EXTI_EMR_MR17
6353 #define  EXTI_EMR_EM19 EXTI_EMR_MR19
6354 #define  EXTI_EMR_EM20 EXTI_EMR_MR20
6355 #define  EXTI_EMR_EM21 EXTI_EMR_MR21
6356 #define  EXTI_EMR_EM22 EXTI_EMR_MR22
6357 #define  EXTI_EMR_EM23 EXTI_EMR_MR23
6358 #define  EXTI_EMR_EM25 EXTI_EMR_MR25
6359 #define  EXTI_EMR_EM26 EXTI_EMR_MR26
6360 #define  EXTI_EMR_EM27 EXTI_EMR_MR27
6361 #define  EXTI_EMR_EM28 EXTI_EMR_MR28
6362 #define  EXTI_EMR_EM31 EXTI_EMR_MR31
6363 
6364 /*******************  Bit definition for EXTI_RTSR register  ******************/
6365 #define EXTI_RTSR_TR0_Pos         (0U)
6366 #define EXTI_RTSR_TR0_Msk         (0x1UL << EXTI_RTSR_TR0_Pos)                  /*!< 0x00000001 */
6367 #define EXTI_RTSR_TR0             EXTI_RTSR_TR0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
6368 #define EXTI_RTSR_TR1_Pos         (1U)
6369 #define EXTI_RTSR_TR1_Msk         (0x1UL << EXTI_RTSR_TR1_Pos)                  /*!< 0x00000002 */
6370 #define EXTI_RTSR_TR1             EXTI_RTSR_TR1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
6371 #define EXTI_RTSR_TR2_Pos         (2U)
6372 #define EXTI_RTSR_TR2_Msk         (0x1UL << EXTI_RTSR_TR2_Pos)                  /*!< 0x00000004 */
6373 #define EXTI_RTSR_TR2             EXTI_RTSR_TR2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
6374 #define EXTI_RTSR_TR3_Pos         (3U)
6375 #define EXTI_RTSR_TR3_Msk         (0x1UL << EXTI_RTSR_TR3_Pos)                  /*!< 0x00000008 */
6376 #define EXTI_RTSR_TR3             EXTI_RTSR_TR3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
6377 #define EXTI_RTSR_TR4_Pos         (4U)
6378 #define EXTI_RTSR_TR4_Msk         (0x1UL << EXTI_RTSR_TR4_Pos)                  /*!< 0x00000010 */
6379 #define EXTI_RTSR_TR4             EXTI_RTSR_TR4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
6380 #define EXTI_RTSR_TR5_Pos         (5U)
6381 #define EXTI_RTSR_TR5_Msk         (0x1UL << EXTI_RTSR_TR5_Pos)                  /*!< 0x00000020 */
6382 #define EXTI_RTSR_TR5             EXTI_RTSR_TR5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
6383 #define EXTI_RTSR_TR6_Pos         (6U)
6384 #define EXTI_RTSR_TR6_Msk         (0x1UL << EXTI_RTSR_TR6_Pos)                  /*!< 0x00000040 */
6385 #define EXTI_RTSR_TR6             EXTI_RTSR_TR6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
6386 #define EXTI_RTSR_TR7_Pos         (7U)
6387 #define EXTI_RTSR_TR7_Msk         (0x1UL << EXTI_RTSR_TR7_Pos)                  /*!< 0x00000080 */
6388 #define EXTI_RTSR_TR7             EXTI_RTSR_TR7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
6389 #define EXTI_RTSR_TR8_Pos         (8U)
6390 #define EXTI_RTSR_TR8_Msk         (0x1UL << EXTI_RTSR_TR8_Pos)                  /*!< 0x00000100 */
6391 #define EXTI_RTSR_TR8             EXTI_RTSR_TR8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
6392 #define EXTI_RTSR_TR9_Pos         (9U)
6393 #define EXTI_RTSR_TR9_Msk         (0x1UL << EXTI_RTSR_TR9_Pos)                  /*!< 0x00000200 */
6394 #define EXTI_RTSR_TR9             EXTI_RTSR_TR9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
6395 #define EXTI_RTSR_TR10_Pos        (10U)
6396 #define EXTI_RTSR_TR10_Msk        (0x1UL << EXTI_RTSR_TR10_Pos)                 /*!< 0x00000400 */
6397 #define EXTI_RTSR_TR10            EXTI_RTSR_TR10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
6398 #define EXTI_RTSR_TR11_Pos        (11U)
6399 #define EXTI_RTSR_TR11_Msk        (0x1UL << EXTI_RTSR_TR11_Pos)                 /*!< 0x00000800 */
6400 #define EXTI_RTSR_TR11            EXTI_RTSR_TR11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
6401 #define EXTI_RTSR_TR12_Pos        (12U)
6402 #define EXTI_RTSR_TR12_Msk        (0x1UL << EXTI_RTSR_TR12_Pos)                 /*!< 0x00001000 */
6403 #define EXTI_RTSR_TR12            EXTI_RTSR_TR12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
6404 #define EXTI_RTSR_TR13_Pos        (13U)
6405 #define EXTI_RTSR_TR13_Msk        (0x1UL << EXTI_RTSR_TR13_Pos)                 /*!< 0x00002000 */
6406 #define EXTI_RTSR_TR13            EXTI_RTSR_TR13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
6407 #define EXTI_RTSR_TR14_Pos        (14U)
6408 #define EXTI_RTSR_TR14_Msk        (0x1UL << EXTI_RTSR_TR14_Pos)                 /*!< 0x00004000 */
6409 #define EXTI_RTSR_TR14            EXTI_RTSR_TR14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
6410 #define EXTI_RTSR_TR15_Pos        (15U)
6411 #define EXTI_RTSR_TR15_Msk        (0x1UL << EXTI_RTSR_TR15_Pos)                 /*!< 0x00008000 */
6412 #define EXTI_RTSR_TR15            EXTI_RTSR_TR15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
6413 #define EXTI_RTSR_TR16_Pos        (16U)
6414 #define EXTI_RTSR_TR16_Msk        (0x1UL << EXTI_RTSR_TR16_Pos)                 /*!< 0x00010000 */
6415 #define EXTI_RTSR_TR16            EXTI_RTSR_TR16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
6416 #define EXTI_RTSR_TR17_Pos        (17U)
6417 #define EXTI_RTSR_TR17_Msk        (0x1UL << EXTI_RTSR_TR17_Pos)                 /*!< 0x00020000 */
6418 #define EXTI_RTSR_TR17            EXTI_RTSR_TR17_Msk                           /*!< Rising trigger event configuration bit of line 17 */
6419 #define EXTI_RTSR_TR19_Pos        (19U)
6420 #define EXTI_RTSR_TR19_Msk        (0x1UL << EXTI_RTSR_TR19_Pos)                 /*!< 0x00080000 */
6421 #define EXTI_RTSR_TR19            EXTI_RTSR_TR19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
6422 #define EXTI_RTSR_TR20_Pos        (20U)
6423 #define EXTI_RTSR_TR20_Msk        (0x1UL << EXTI_RTSR_TR20_Pos)                 /*!< 0x00100000 */
6424 #define EXTI_RTSR_TR20            EXTI_RTSR_TR20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
6425 #define EXTI_RTSR_TR21_Pos        (21U)
6426 #define EXTI_RTSR_TR21_Msk        (0x1UL << EXTI_RTSR_TR21_Pos)                 /*!< 0x00200000 */
6427 #define EXTI_RTSR_TR21            EXTI_RTSR_TR21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
6428 #define EXTI_RTSR_TR22_Pos        (22U)
6429 #define EXTI_RTSR_TR22_Msk        (0x1UL << EXTI_RTSR_TR22_Pos)                 /*!< 0x00400000 */
6430 #define EXTI_RTSR_TR22            EXTI_RTSR_TR22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
6431 #define EXTI_RTSR_TR31_Pos        (31U)
6432 #define EXTI_RTSR_TR31_Msk        (0x1UL << EXTI_RTSR_TR31_Pos)                 /*!< 0x80000000 */
6433 #define EXTI_RTSR_TR31            EXTI_RTSR_TR31_Msk                           /*!< Rising trigger event configuration bit of line 31 */
6434 
6435 /* References Defines */
6436 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0
6437 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1
6438 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2
6439 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3
6440 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4
6441 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5
6442 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6
6443 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7
6444 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8
6445 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9
6446 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10
6447 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11
6448 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12
6449 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13
6450 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14
6451 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15
6452 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
6453 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17
6454 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19
6455 #define EXTI_RTSR_RT20 EXTI_RTSR_TR20
6456 #define EXTI_RTSR_RT21 EXTI_RTSR_TR21
6457 #define EXTI_RTSR_RT22 EXTI_RTSR_TR22
6458 #define  EXTI_RTSR_RT31 EXTI_RTSR_TR31
6459 
6460 /*******************  Bit definition for EXTI_FTSR register *******************/
6461 #define EXTI_FTSR_TR0_Pos         (0U)
6462 #define EXTI_FTSR_TR0_Msk         (0x1UL << EXTI_FTSR_TR0_Pos)                  /*!< 0x00000001 */
6463 #define EXTI_FTSR_TR0             EXTI_FTSR_TR0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
6464 #define EXTI_FTSR_TR1_Pos         (1U)
6465 #define EXTI_FTSR_TR1_Msk         (0x1UL << EXTI_FTSR_TR1_Pos)                  /*!< 0x00000002 */
6466 #define EXTI_FTSR_TR1             EXTI_FTSR_TR1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
6467 #define EXTI_FTSR_TR2_Pos         (2U)
6468 #define EXTI_FTSR_TR2_Msk         (0x1UL << EXTI_FTSR_TR2_Pos)                  /*!< 0x00000004 */
6469 #define EXTI_FTSR_TR2             EXTI_FTSR_TR2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
6470 #define EXTI_FTSR_TR3_Pos         (3U)
6471 #define EXTI_FTSR_TR3_Msk         (0x1UL << EXTI_FTSR_TR3_Pos)                  /*!< 0x00000008 */
6472 #define EXTI_FTSR_TR3             EXTI_FTSR_TR3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
6473 #define EXTI_FTSR_TR4_Pos         (4U)
6474 #define EXTI_FTSR_TR4_Msk         (0x1UL << EXTI_FTSR_TR4_Pos)                  /*!< 0x00000010 */
6475 #define EXTI_FTSR_TR4             EXTI_FTSR_TR4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
6476 #define EXTI_FTSR_TR5_Pos         (5U)
6477 #define EXTI_FTSR_TR5_Msk         (0x1UL << EXTI_FTSR_TR5_Pos)                  /*!< 0x00000020 */
6478 #define EXTI_FTSR_TR5             EXTI_FTSR_TR5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
6479 #define EXTI_FTSR_TR6_Pos         (6U)
6480 #define EXTI_FTSR_TR6_Msk         (0x1UL << EXTI_FTSR_TR6_Pos)                  /*!< 0x00000040 */
6481 #define EXTI_FTSR_TR6             EXTI_FTSR_TR6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
6482 #define EXTI_FTSR_TR7_Pos         (7U)
6483 #define EXTI_FTSR_TR7_Msk         (0x1UL << EXTI_FTSR_TR7_Pos)                  /*!< 0x00000080 */
6484 #define EXTI_FTSR_TR7             EXTI_FTSR_TR7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
6485 #define EXTI_FTSR_TR8_Pos         (8U)
6486 #define EXTI_FTSR_TR8_Msk         (0x1UL << EXTI_FTSR_TR8_Pos)                  /*!< 0x00000100 */
6487 #define EXTI_FTSR_TR8             EXTI_FTSR_TR8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
6488 #define EXTI_FTSR_TR9_Pos         (9U)
6489 #define EXTI_FTSR_TR9_Msk         (0x1UL << EXTI_FTSR_TR9_Pos)                  /*!< 0x00000200 */
6490 #define EXTI_FTSR_TR9             EXTI_FTSR_TR9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
6491 #define EXTI_FTSR_TR10_Pos        (10U)
6492 #define EXTI_FTSR_TR10_Msk        (0x1UL << EXTI_FTSR_TR10_Pos)                 /*!< 0x00000400 */
6493 #define EXTI_FTSR_TR10            EXTI_FTSR_TR10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
6494 #define EXTI_FTSR_TR11_Pos        (11U)
6495 #define EXTI_FTSR_TR11_Msk        (0x1UL << EXTI_FTSR_TR11_Pos)                 /*!< 0x00000800 */
6496 #define EXTI_FTSR_TR11            EXTI_FTSR_TR11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
6497 #define EXTI_FTSR_TR12_Pos        (12U)
6498 #define EXTI_FTSR_TR12_Msk        (0x1UL << EXTI_FTSR_TR12_Pos)                 /*!< 0x00001000 */
6499 #define EXTI_FTSR_TR12            EXTI_FTSR_TR12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
6500 #define EXTI_FTSR_TR13_Pos        (13U)
6501 #define EXTI_FTSR_TR13_Msk        (0x1UL << EXTI_FTSR_TR13_Pos)                 /*!< 0x00002000 */
6502 #define EXTI_FTSR_TR13            EXTI_FTSR_TR13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
6503 #define EXTI_FTSR_TR14_Pos        (14U)
6504 #define EXTI_FTSR_TR14_Msk        (0x1UL << EXTI_FTSR_TR14_Pos)                 /*!< 0x00004000 */
6505 #define EXTI_FTSR_TR14            EXTI_FTSR_TR14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
6506 #define EXTI_FTSR_TR15_Pos        (15U)
6507 #define EXTI_FTSR_TR15_Msk        (0x1UL << EXTI_FTSR_TR15_Pos)                 /*!< 0x00008000 */
6508 #define EXTI_FTSR_TR15            EXTI_FTSR_TR15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
6509 #define EXTI_FTSR_TR16_Pos        (16U)
6510 #define EXTI_FTSR_TR16_Msk        (0x1UL << EXTI_FTSR_TR16_Pos)                 /*!< 0x00010000 */
6511 #define EXTI_FTSR_TR16            EXTI_FTSR_TR16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
6512 #define EXTI_FTSR_TR17_Pos        (17U)
6513 #define EXTI_FTSR_TR17_Msk        (0x1UL << EXTI_FTSR_TR17_Pos)                 /*!< 0x00020000 */
6514 #define EXTI_FTSR_TR17            EXTI_FTSR_TR17_Msk                           /*!< Falling trigger event configuration bit of line 17 */
6515 #define EXTI_FTSR_TR19_Pos        (19U)
6516 #define EXTI_FTSR_TR19_Msk        (0x1UL << EXTI_FTSR_TR19_Pos)                 /*!< 0x00080000 */
6517 #define EXTI_FTSR_TR19            EXTI_FTSR_TR19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
6518 #define EXTI_FTSR_TR20_Pos        (20U)
6519 #define EXTI_FTSR_TR20_Msk        (0x1UL << EXTI_FTSR_TR20_Pos)                 /*!< 0x00100000 */
6520 #define EXTI_FTSR_TR20            EXTI_FTSR_TR20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
6521 #define EXTI_FTSR_TR21_Pos        (21U)
6522 #define EXTI_FTSR_TR21_Msk        (0x1UL << EXTI_FTSR_TR21_Pos)                 /*!< 0x00200000 */
6523 #define EXTI_FTSR_TR21            EXTI_FTSR_TR21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
6524 #define EXTI_FTSR_TR22_Pos        (22U)
6525 #define EXTI_FTSR_TR22_Msk        (0x1UL << EXTI_FTSR_TR22_Pos)                 /*!< 0x00400000 */
6526 #define EXTI_FTSR_TR22            EXTI_FTSR_TR22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
6527 #define EXTI_FTSR_TR31_Pos        (31U)
6528 #define EXTI_FTSR_TR31_Msk        (0x1UL << EXTI_FTSR_TR31_Pos)                 /*!< 0x80000000 */
6529 #define EXTI_FTSR_TR31            EXTI_FTSR_TR31_Msk                           /*!< Falling trigger event configuration bit of line 31 */
6530 
6531 /* References Defines */
6532 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0
6533 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1
6534 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2
6535 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3
6536 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4
6537 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5
6538 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6
6539 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7
6540 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8
6541 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9
6542 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10
6543 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11
6544 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12
6545 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13
6546 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14
6547 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15
6548 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
6549 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17
6550 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19
6551 #define EXTI_FTSR_FT20 EXTI_FTSR_TR20
6552 #define EXTI_FTSR_FT21 EXTI_FTSR_TR21
6553 #define EXTI_FTSR_FT22 EXTI_FTSR_TR22
6554 #define EXTI_FTSR_FT31 EXTI_FTSR_TR31
6555 
6556 /******************* Bit definition for EXTI_SWIER register *******************/
6557 #define EXTI_SWIER_SWIER0_Pos     (0U)
6558 #define EXTI_SWIER_SWIER0_Msk     (0x1UL << EXTI_SWIER_SWIER0_Pos)              /*!< 0x00000001 */
6559 #define EXTI_SWIER_SWIER0         EXTI_SWIER_SWIER0_Msk                        /*!< Software Interrupt on line 0  */
6560 #define EXTI_SWIER_SWIER1_Pos     (1U)
6561 #define EXTI_SWIER_SWIER1_Msk     (0x1UL << EXTI_SWIER_SWIER1_Pos)              /*!< 0x00000002 */
6562 #define EXTI_SWIER_SWIER1         EXTI_SWIER_SWIER1_Msk                        /*!< Software Interrupt on line 1  */
6563 #define EXTI_SWIER_SWIER2_Pos     (2U)
6564 #define EXTI_SWIER_SWIER2_Msk     (0x1UL << EXTI_SWIER_SWIER2_Pos)              /*!< 0x00000004 */
6565 #define EXTI_SWIER_SWIER2         EXTI_SWIER_SWIER2_Msk                        /*!< Software Interrupt on line 2  */
6566 #define EXTI_SWIER_SWIER3_Pos     (3U)
6567 #define EXTI_SWIER_SWIER3_Msk     (0x1UL << EXTI_SWIER_SWIER3_Pos)              /*!< 0x00000008 */
6568 #define EXTI_SWIER_SWIER3         EXTI_SWIER_SWIER3_Msk                        /*!< Software Interrupt on line 3  */
6569 #define EXTI_SWIER_SWIER4_Pos     (4U)
6570 #define EXTI_SWIER_SWIER4_Msk     (0x1UL << EXTI_SWIER_SWIER4_Pos)              /*!< 0x00000010 */
6571 #define EXTI_SWIER_SWIER4         EXTI_SWIER_SWIER4_Msk                        /*!< Software Interrupt on line 4  */
6572 #define EXTI_SWIER_SWIER5_Pos     (5U)
6573 #define EXTI_SWIER_SWIER5_Msk     (0x1UL << EXTI_SWIER_SWIER5_Pos)              /*!< 0x00000020 */
6574 #define EXTI_SWIER_SWIER5         EXTI_SWIER_SWIER5_Msk                        /*!< Software Interrupt on line 5  */
6575 #define EXTI_SWIER_SWIER6_Pos     (6U)
6576 #define EXTI_SWIER_SWIER6_Msk     (0x1UL << EXTI_SWIER_SWIER6_Pos)              /*!< 0x00000040 */
6577 #define EXTI_SWIER_SWIER6         EXTI_SWIER_SWIER6_Msk                        /*!< Software Interrupt on line 6  */
6578 #define EXTI_SWIER_SWIER7_Pos     (7U)
6579 #define EXTI_SWIER_SWIER7_Msk     (0x1UL << EXTI_SWIER_SWIER7_Pos)              /*!< 0x00000080 */
6580 #define EXTI_SWIER_SWIER7         EXTI_SWIER_SWIER7_Msk                        /*!< Software Interrupt on line 7  */
6581 #define EXTI_SWIER_SWIER8_Pos     (8U)
6582 #define EXTI_SWIER_SWIER8_Msk     (0x1UL << EXTI_SWIER_SWIER8_Pos)              /*!< 0x00000100 */
6583 #define EXTI_SWIER_SWIER8         EXTI_SWIER_SWIER8_Msk                        /*!< Software Interrupt on line 8  */
6584 #define EXTI_SWIER_SWIER9_Pos     (9U)
6585 #define EXTI_SWIER_SWIER9_Msk     (0x1UL << EXTI_SWIER_SWIER9_Pos)              /*!< 0x00000200 */
6586 #define EXTI_SWIER_SWIER9         EXTI_SWIER_SWIER9_Msk                        /*!< Software Interrupt on line 9  */
6587 #define EXTI_SWIER_SWIER10_Pos    (10U)
6588 #define EXTI_SWIER_SWIER10_Msk    (0x1UL << EXTI_SWIER_SWIER10_Pos)             /*!< 0x00000400 */
6589 #define EXTI_SWIER_SWIER10        EXTI_SWIER_SWIER10_Msk                       /*!< Software Interrupt on line 10 */
6590 #define EXTI_SWIER_SWIER11_Pos    (11U)
6591 #define EXTI_SWIER_SWIER11_Msk    (0x1UL << EXTI_SWIER_SWIER11_Pos)             /*!< 0x00000800 */
6592 #define EXTI_SWIER_SWIER11        EXTI_SWIER_SWIER11_Msk                       /*!< Software Interrupt on line 11 */
6593 #define EXTI_SWIER_SWIER12_Pos    (12U)
6594 #define EXTI_SWIER_SWIER12_Msk    (0x1UL << EXTI_SWIER_SWIER12_Pos)             /*!< 0x00001000 */
6595 #define EXTI_SWIER_SWIER12        EXTI_SWIER_SWIER12_Msk                       /*!< Software Interrupt on line 12 */
6596 #define EXTI_SWIER_SWIER13_Pos    (13U)
6597 #define EXTI_SWIER_SWIER13_Msk    (0x1UL << EXTI_SWIER_SWIER13_Pos)             /*!< 0x00002000 */
6598 #define EXTI_SWIER_SWIER13        EXTI_SWIER_SWIER13_Msk                       /*!< Software Interrupt on line 13 */
6599 #define EXTI_SWIER_SWIER14_Pos    (14U)
6600 #define EXTI_SWIER_SWIER14_Msk    (0x1UL << EXTI_SWIER_SWIER14_Pos)             /*!< 0x00004000 */
6601 #define EXTI_SWIER_SWIER14        EXTI_SWIER_SWIER14_Msk                       /*!< Software Interrupt on line 14 */
6602 #define EXTI_SWIER_SWIER15_Pos    (15U)
6603 #define EXTI_SWIER_SWIER15_Msk    (0x1UL << EXTI_SWIER_SWIER15_Pos)             /*!< 0x00008000 */
6604 #define EXTI_SWIER_SWIER15        EXTI_SWIER_SWIER15_Msk                       /*!< Software Interrupt on line 15 */
6605 #define EXTI_SWIER_SWIER16_Pos    (16U)
6606 #define EXTI_SWIER_SWIER16_Msk    (0x1UL << EXTI_SWIER_SWIER16_Pos)             /*!< 0x00010000 */
6607 #define EXTI_SWIER_SWIER16        EXTI_SWIER_SWIER16_Msk                       /*!< Software Interrupt on line 16 */
6608 #define EXTI_SWIER_SWIER17_Pos    (17U)
6609 #define EXTI_SWIER_SWIER17_Msk    (0x1UL << EXTI_SWIER_SWIER17_Pos)             /*!< 0x00020000 */
6610 #define EXTI_SWIER_SWIER17        EXTI_SWIER_SWIER17_Msk                       /*!< Software Interrupt on line 17 */
6611 #define EXTI_SWIER_SWIER19_Pos    (19U)
6612 #define EXTI_SWIER_SWIER19_Msk    (0x1UL << EXTI_SWIER_SWIER19_Pos)             /*!< 0x00080000 */
6613 #define EXTI_SWIER_SWIER19        EXTI_SWIER_SWIER19_Msk                       /*!< Software Interrupt on line 19 */
6614 #define EXTI_SWIER_SWIER20_Pos    (20U)
6615 #define EXTI_SWIER_SWIER20_Msk    (0x1UL << EXTI_SWIER_SWIER20_Pos)             /*!< 0x00100000 */
6616 #define EXTI_SWIER_SWIER20        EXTI_SWIER_SWIER20_Msk                       /*!< Software Interrupt on line 20 */
6617 #define EXTI_SWIER_SWIER21_Pos    (21U)
6618 #define EXTI_SWIER_SWIER21_Msk    (0x1UL << EXTI_SWIER_SWIER21_Pos)             /*!< 0x00200000 */
6619 #define EXTI_SWIER_SWIER21        EXTI_SWIER_SWIER21_Msk                       /*!< Software Interrupt on line 21 */
6620 #define EXTI_SWIER_SWIER22_Pos    (22U)
6621 #define EXTI_SWIER_SWIER22_Msk    (0x1UL << EXTI_SWIER_SWIER22_Pos)             /*!< 0x00400000 */
6622 #define EXTI_SWIER_SWIER22        EXTI_SWIER_SWIER22_Msk                       /*!< Software Interrupt on line 22 */
6623 #define EXTI_SWIER_SWIER31_Pos    (31U)
6624 #define EXTI_SWIER_SWIER31_Msk    (0x1UL << EXTI_SWIER_SWIER31_Pos)             /*!< 0x80000000 */
6625 #define EXTI_SWIER_SWIER31        EXTI_SWIER_SWIER31_Msk                       /*!< Software Interrupt on line 31 */
6626 
6627 /* References Defines */
6628 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
6629 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
6630 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
6631 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
6632 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
6633 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
6634 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
6635 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
6636 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
6637 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
6638 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
6639 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
6640 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
6641 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
6642 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
6643 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
6644 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
6645 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
6646 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
6647 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
6648 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
6649 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
6650 #define  EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
6651 
6652 /******************  Bit definition for EXTI_PR register  *********************/
6653 #define EXTI_PR_PR0_Pos           (0U)
6654 #define EXTI_PR_PR0_Msk           (0x1UL << EXTI_PR_PR0_Pos)                    /*!< 0x00000001 */
6655 #define EXTI_PR_PR0               EXTI_PR_PR0_Msk                              /*!< Pending bit 0  */
6656 #define EXTI_PR_PR1_Pos           (1U)
6657 #define EXTI_PR_PR1_Msk           (0x1UL << EXTI_PR_PR1_Pos)                    /*!< 0x00000002 */
6658 #define EXTI_PR_PR1               EXTI_PR_PR1_Msk                              /*!< Pending bit 1  */
6659 #define EXTI_PR_PR2_Pos           (2U)
6660 #define EXTI_PR_PR2_Msk           (0x1UL << EXTI_PR_PR2_Pos)                    /*!< 0x00000004 */
6661 #define EXTI_PR_PR2               EXTI_PR_PR2_Msk                              /*!< Pending bit 2  */
6662 #define EXTI_PR_PR3_Pos           (3U)
6663 #define EXTI_PR_PR3_Msk           (0x1UL << EXTI_PR_PR3_Pos)                    /*!< 0x00000008 */
6664 #define EXTI_PR_PR3               EXTI_PR_PR3_Msk                              /*!< Pending bit 3  */
6665 #define EXTI_PR_PR4_Pos           (4U)
6666 #define EXTI_PR_PR4_Msk           (0x1UL << EXTI_PR_PR4_Pos)                    /*!< 0x00000010 */
6667 #define EXTI_PR_PR4               EXTI_PR_PR4_Msk                              /*!< Pending bit 4  */
6668 #define EXTI_PR_PR5_Pos           (5U)
6669 #define EXTI_PR_PR5_Msk           (0x1UL << EXTI_PR_PR5_Pos)                    /*!< 0x00000020 */
6670 #define EXTI_PR_PR5               EXTI_PR_PR5_Msk                              /*!< Pending bit 5  */
6671 #define EXTI_PR_PR6_Pos           (6U)
6672 #define EXTI_PR_PR6_Msk           (0x1UL << EXTI_PR_PR6_Pos)                    /*!< 0x00000040 */
6673 #define EXTI_PR_PR6               EXTI_PR_PR6_Msk                              /*!< Pending bit 6  */
6674 #define EXTI_PR_PR7_Pos           (7U)
6675 #define EXTI_PR_PR7_Msk           (0x1UL << EXTI_PR_PR7_Pos)                    /*!< 0x00000080 */
6676 #define EXTI_PR_PR7               EXTI_PR_PR7_Msk                              /*!< Pending bit 7  */
6677 #define EXTI_PR_PR8_Pos           (8U)
6678 #define EXTI_PR_PR8_Msk           (0x1UL << EXTI_PR_PR8_Pos)                    /*!< 0x00000100 */
6679 #define EXTI_PR_PR8               EXTI_PR_PR8_Msk                              /*!< Pending bit 8  */
6680 #define EXTI_PR_PR9_Pos           (9U)
6681 #define EXTI_PR_PR9_Msk           (0x1UL << EXTI_PR_PR9_Pos)                    /*!< 0x00000200 */
6682 #define EXTI_PR_PR9               EXTI_PR_PR9_Msk                              /*!< Pending bit 9  */
6683 #define EXTI_PR_PR10_Pos          (10U)
6684 #define EXTI_PR_PR10_Msk          (0x1UL << EXTI_PR_PR10_Pos)                   /*!< 0x00000400 */
6685 #define EXTI_PR_PR10              EXTI_PR_PR10_Msk                             /*!< Pending bit 10 */
6686 #define EXTI_PR_PR11_Pos          (11U)
6687 #define EXTI_PR_PR11_Msk          (0x1UL << EXTI_PR_PR11_Pos)                   /*!< 0x00000800 */
6688 #define EXTI_PR_PR11              EXTI_PR_PR11_Msk                             /*!< Pending bit 11 */
6689 #define EXTI_PR_PR12_Pos          (12U)
6690 #define EXTI_PR_PR12_Msk          (0x1UL << EXTI_PR_PR12_Pos)                   /*!< 0x00001000 */
6691 #define EXTI_PR_PR12              EXTI_PR_PR12_Msk                             /*!< Pending bit 12 */
6692 #define EXTI_PR_PR13_Pos          (13U)
6693 #define EXTI_PR_PR13_Msk          (0x1UL << EXTI_PR_PR13_Pos)                   /*!< 0x00002000 */
6694 #define EXTI_PR_PR13              EXTI_PR_PR13_Msk                             /*!< Pending bit 13 */
6695 #define EXTI_PR_PR14_Pos          (14U)
6696 #define EXTI_PR_PR14_Msk          (0x1UL << EXTI_PR_PR14_Pos)                   /*!< 0x00004000 */
6697 #define EXTI_PR_PR14              EXTI_PR_PR14_Msk                             /*!< Pending bit 14 */
6698 #define EXTI_PR_PR15_Pos          (15U)
6699 #define EXTI_PR_PR15_Msk          (0x1UL << EXTI_PR_PR15_Pos)                   /*!< 0x00008000 */
6700 #define EXTI_PR_PR15              EXTI_PR_PR15_Msk                             /*!< Pending bit 15 */
6701 #define EXTI_PR_PR16_Pos          (16U)
6702 #define EXTI_PR_PR16_Msk          (0x1UL << EXTI_PR_PR16_Pos)                   /*!< 0x00010000 */
6703 #define EXTI_PR_PR16              EXTI_PR_PR16_Msk                             /*!< Pending bit 16 */
6704 #define EXTI_PR_PR17_Pos          (17U)
6705 #define EXTI_PR_PR17_Msk          (0x1UL << EXTI_PR_PR17_Pos)                   /*!< 0x00020000 */
6706 #define EXTI_PR_PR17              EXTI_PR_PR17_Msk                             /*!< Pending bit 17 */
6707 #define EXTI_PR_PR19_Pos          (19U)
6708 #define EXTI_PR_PR19_Msk          (0x1UL << EXTI_PR_PR19_Pos)                   /*!< 0x00080000 */
6709 #define EXTI_PR_PR19              EXTI_PR_PR19_Msk                             /*!< Pending bit 19 */
6710 #define EXTI_PR_PR20_Pos          (20U)
6711 #define EXTI_PR_PR20_Msk          (0x1UL << EXTI_PR_PR20_Pos)                   /*!< 0x00100000 */
6712 #define EXTI_PR_PR20              EXTI_PR_PR20_Msk                             /*!< Pending bit 20 */
6713 #define EXTI_PR_PR21_Pos          (21U)
6714 #define EXTI_PR_PR21_Msk          (0x1UL << EXTI_PR_PR21_Pos)                   /*!< 0x00200000 */
6715 #define EXTI_PR_PR21              EXTI_PR_PR21_Msk                             /*!< Pending bit 21 */
6716 #define EXTI_PR_PR22_Pos          (22U)
6717 #define EXTI_PR_PR22_Msk          (0x1UL << EXTI_PR_PR22_Pos)                   /*!< 0x00400000 */
6718 #define EXTI_PR_PR22              EXTI_PR_PR22_Msk                             /*!< Pending bit 22 */
6719 #define EXTI_PR_PR31_Pos          (31U)
6720 #define EXTI_PR_PR31_Msk          (0x1UL << EXTI_PR_PR31_Pos)                   /*!< 0x80000000 */
6721 #define EXTI_PR_PR31              EXTI_PR_PR31_Msk                             /*!< Pending bit 31 */
6722 
6723 /* References Defines */
6724 #define EXTI_PR_PIF0 EXTI_PR_PR0
6725 #define EXTI_PR_PIF1 EXTI_PR_PR1
6726 #define EXTI_PR_PIF2 EXTI_PR_PR2
6727 #define EXTI_PR_PIF3 EXTI_PR_PR3
6728 #define EXTI_PR_PIF4 EXTI_PR_PR4
6729 #define EXTI_PR_PIF5 EXTI_PR_PR5
6730 #define EXTI_PR_PIF6 EXTI_PR_PR6
6731 #define EXTI_PR_PIF7 EXTI_PR_PR7
6732 #define EXTI_PR_PIF8 EXTI_PR_PR8
6733 #define EXTI_PR_PIF9 EXTI_PR_PR9
6734 #define EXTI_PR_PIF10 EXTI_PR_PR10
6735 #define EXTI_PR_PIF11 EXTI_PR_PR11
6736 #define EXTI_PR_PIF12 EXTI_PR_PR12
6737 #define EXTI_PR_PIF13 EXTI_PR_PR13
6738 #define EXTI_PR_PIF14 EXTI_PR_PR14
6739 #define EXTI_PR_PIF15 EXTI_PR_PR15
6740 #define EXTI_PR_PIF16 EXTI_PR_PR16
6741 #define EXTI_PR_PIF17 EXTI_PR_PR17
6742 #define EXTI_PR_PIF19 EXTI_PR_PR19
6743 #define EXTI_PR_PIF20 EXTI_PR_PR20
6744 #define EXTI_PR_PIF21 EXTI_PR_PR21
6745 #define EXTI_PR_PIF22 EXTI_PR_PR22
6746 #define EXTI_PR_PIF31 EXTI_PR_PR31
6747 
6748 /******************************************************************************/
6749 /*                                                                            */
6750 /*                      FLASH and Option Bytes Registers                      */
6751 /*                                                                            */
6752 /******************************************************************************/
6753 
6754 /*******************  Bit definition for FLASH_ACR register  ******************/
6755 #define FLASH_ACR_LATENCY_Pos             (0U)
6756 #define FLASH_ACR_LATENCY_Msk             (0x1UL << FLASH_ACR_LATENCY_Pos)      /*!< 0x00000001 */
6757 #define FLASH_ACR_LATENCY                 FLASH_ACR_LATENCY_Msk                /*!< LATENCY bit (Latency) */
6758 
6759 #define FLASH_ACR_PRFTBE_Pos              (4U)
6760 #define FLASH_ACR_PRFTBE_Msk              (0x1UL << FLASH_ACR_PRFTBE_Pos)       /*!< 0x00000010 */
6761 #define FLASH_ACR_PRFTBE                  FLASH_ACR_PRFTBE_Msk                 /*!< Prefetch Buffer Enable */
6762 #define FLASH_ACR_PRFTBS_Pos              (5U)
6763 #define FLASH_ACR_PRFTBS_Msk              (0x1UL << FLASH_ACR_PRFTBS_Pos)       /*!< 0x00000020 */
6764 #define FLASH_ACR_PRFTBS                  FLASH_ACR_PRFTBS_Msk                 /*!< Prefetch Buffer Status */
6765 
6766 /******************  Bit definition for FLASH_KEYR register  ******************/
6767 #define FLASH_KEYR_FKEYR_Pos              (0U)
6768 #define FLASH_KEYR_FKEYR_Msk              (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
6769 #define FLASH_KEYR_FKEYR                  FLASH_KEYR_FKEYR_Msk                 /*!< FPEC Key */
6770 
6771 /*****************  Bit definition for FLASH_OPTKEYR register  ****************/
6772 #define FLASH_OPTKEYR_OPTKEYR_Pos         (0U)
6773 #define FLASH_OPTKEYR_OPTKEYR_Msk         (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
6774 #define FLASH_OPTKEYR_OPTKEYR             FLASH_OPTKEYR_OPTKEYR_Msk            /*!< Option Byte Key */
6775 
6776 /******************  FLASH Keys  **********************************************/
6777 #define FLASH_KEY1_Pos                    (0U)
6778 #define FLASH_KEY1_Msk                    (0x45670123UL << FLASH_KEY1_Pos)      /*!< 0x45670123 */
6779 #define FLASH_KEY1                        FLASH_KEY1_Msk                       /*!< Flash program erase key1 */
6780 #define FLASH_KEY2_Pos                    (0U)
6781 #define FLASH_KEY2_Msk                    (0xCDEF89ABUL << FLASH_KEY2_Pos)      /*!< 0xCDEF89AB */
6782 #define FLASH_KEY2                        FLASH_KEY2_Msk                       /*!< Flash program erase key2: used with FLASH_PEKEY1
6783                                                                                 to unlock the write access to the FPEC. */
6784 
6785 #define FLASH_OPTKEY1_Pos                 (0U)
6786 #define FLASH_OPTKEY1_Msk                 (0x45670123UL << FLASH_OPTKEY1_Pos)   /*!< 0x45670123 */
6787 #define FLASH_OPTKEY1                     FLASH_OPTKEY1_Msk                    /*!< Flash option key1 */
6788 #define FLASH_OPTKEY2_Pos                 (0U)
6789 #define FLASH_OPTKEY2_Msk                 (0xCDEF89ABUL << FLASH_OPTKEY2_Pos)   /*!< 0xCDEF89AB */
6790 #define FLASH_OPTKEY2                     FLASH_OPTKEY2_Msk                    /*!< Flash option key2: used with FLASH_OPTKEY1 to
6791                                                                                 unlock the write access to the option byte block */
6792 
6793 /******************  Bit definition for FLASH_SR register  *******************/
6794 #define FLASH_SR_BSY_Pos                  (0U)
6795 #define FLASH_SR_BSY_Msk                  (0x1UL << FLASH_SR_BSY_Pos)           /*!< 0x00000001 */
6796 #define FLASH_SR_BSY                      FLASH_SR_BSY_Msk                     /*!< Busy */
6797 #define FLASH_SR_PGERR_Pos                (2U)
6798 #define FLASH_SR_PGERR_Msk                (0x1UL << FLASH_SR_PGERR_Pos)         /*!< 0x00000004 */
6799 #define FLASH_SR_PGERR                    FLASH_SR_PGERR_Msk                   /*!< Programming Error */
6800 #define FLASH_SR_WRPRTERR_Pos             (4U)
6801 #define FLASH_SR_WRPRTERR_Msk             (0x1UL << FLASH_SR_WRPRTERR_Pos)      /*!< 0x00000010 */
6802 #define FLASH_SR_WRPRTERR                 FLASH_SR_WRPRTERR_Msk                /*!< Write Protection Error */
6803 #define FLASH_SR_EOP_Pos                  (5U)
6804 #define FLASH_SR_EOP_Msk                  (0x1UL << FLASH_SR_EOP_Pos)           /*!< 0x00000020 */
6805 #define FLASH_SR_EOP                      FLASH_SR_EOP_Msk                     /*!< End of operation */
6806 #define  FLASH_SR_WRPERR                     FLASH_SR_WRPRTERR             /*!< Legacy of Write Protection Error */
6807 
6808 /*******************  Bit definition for FLASH_CR register  *******************/
6809 #define FLASH_CR_PG_Pos                   (0U)
6810 #define FLASH_CR_PG_Msk                   (0x1UL << FLASH_CR_PG_Pos)            /*!< 0x00000001 */
6811 #define FLASH_CR_PG                       FLASH_CR_PG_Msk                      /*!< Programming */
6812 #define FLASH_CR_PER_Pos                  (1U)
6813 #define FLASH_CR_PER_Msk                  (0x1UL << FLASH_CR_PER_Pos)           /*!< 0x00000002 */
6814 #define FLASH_CR_PER                      FLASH_CR_PER_Msk                     /*!< Page Erase */
6815 #define FLASH_CR_MER_Pos                  (2U)
6816 #define FLASH_CR_MER_Msk                  (0x1UL << FLASH_CR_MER_Pos)           /*!< 0x00000004 */
6817 #define FLASH_CR_MER                      FLASH_CR_MER_Msk                     /*!< Mass Erase */
6818 #define FLASH_CR_OPTPG_Pos                (4U)
6819 #define FLASH_CR_OPTPG_Msk                (0x1UL << FLASH_CR_OPTPG_Pos)         /*!< 0x00000010 */
6820 #define FLASH_CR_OPTPG                    FLASH_CR_OPTPG_Msk                   /*!< Option Byte Programming */
6821 #define FLASH_CR_OPTER_Pos                (5U)
6822 #define FLASH_CR_OPTER_Msk                (0x1UL << FLASH_CR_OPTER_Pos)         /*!< 0x00000020 */
6823 #define FLASH_CR_OPTER                    FLASH_CR_OPTER_Msk                   /*!< Option Byte Erase */
6824 #define FLASH_CR_STRT_Pos                 (6U)
6825 #define FLASH_CR_STRT_Msk                 (0x1UL << FLASH_CR_STRT_Pos)          /*!< 0x00000040 */
6826 #define FLASH_CR_STRT                     FLASH_CR_STRT_Msk                    /*!< Start */
6827 #define FLASH_CR_LOCK_Pos                 (7U)
6828 #define FLASH_CR_LOCK_Msk                 (0x1UL << FLASH_CR_LOCK_Pos)          /*!< 0x00000080 */
6829 #define FLASH_CR_LOCK                     FLASH_CR_LOCK_Msk                    /*!< Lock */
6830 #define FLASH_CR_OPTWRE_Pos               (9U)
6831 #define FLASH_CR_OPTWRE_Msk               (0x1UL << FLASH_CR_OPTWRE_Pos)        /*!< 0x00000200 */
6832 #define FLASH_CR_OPTWRE                   FLASH_CR_OPTWRE_Msk                  /*!< Option Bytes Write Enable */
6833 #define FLASH_CR_ERRIE_Pos                (10U)
6834 #define FLASH_CR_ERRIE_Msk                (0x1UL << FLASH_CR_ERRIE_Pos)         /*!< 0x00000400 */
6835 #define FLASH_CR_ERRIE                    FLASH_CR_ERRIE_Msk                   /*!< Error Interrupt Enable */
6836 #define FLASH_CR_EOPIE_Pos                (12U)
6837 #define FLASH_CR_EOPIE_Msk                (0x1UL << FLASH_CR_EOPIE_Pos)         /*!< 0x00001000 */
6838 #define FLASH_CR_EOPIE                    FLASH_CR_EOPIE_Msk                   /*!< End of operation interrupt enable */
6839 #define FLASH_CR_OBL_LAUNCH_Pos           (13U)
6840 #define FLASH_CR_OBL_LAUNCH_Msk           (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)    /*!< 0x00002000 */
6841 #define FLASH_CR_OBL_LAUNCH               FLASH_CR_OBL_LAUNCH_Msk              /*!< Option Bytes Loader Launch */
6842 
6843 /*******************  Bit definition for FLASH_AR register  *******************/
6844 #define FLASH_AR_FAR_Pos                  (0U)
6845 #define FLASH_AR_FAR_Msk                  (0xFFFFFFFFUL << FLASH_AR_FAR_Pos)    /*!< 0xFFFFFFFF */
6846 #define FLASH_AR_FAR                      FLASH_AR_FAR_Msk                     /*!< Flash Address */
6847 
6848 /******************  Bit definition for FLASH_OBR register  *******************/
6849 #define FLASH_OBR_OPTERR_Pos              (0U)
6850 #define FLASH_OBR_OPTERR_Msk              (0x1UL << FLASH_OBR_OPTERR_Pos)       /*!< 0x00000001 */
6851 #define FLASH_OBR_OPTERR                  FLASH_OBR_OPTERR_Msk                 /*!< Option Byte Error */
6852 #define FLASH_OBR_RDPRT1_Pos              (1U)
6853 #define FLASH_OBR_RDPRT1_Msk              (0x1UL << FLASH_OBR_RDPRT1_Pos)       /*!< 0x00000002 */
6854 #define FLASH_OBR_RDPRT1                  FLASH_OBR_RDPRT1_Msk                 /*!< Read protection Level 1 */
6855 #define FLASH_OBR_RDPRT2_Pos              (2U)
6856 #define FLASH_OBR_RDPRT2_Msk              (0x1UL << FLASH_OBR_RDPRT2_Pos)       /*!< 0x00000004 */
6857 #define FLASH_OBR_RDPRT2                  FLASH_OBR_RDPRT2_Msk                 /*!< Read protection Level 2 */
6858 
6859 #define FLASH_OBR_USER_Pos                (8U)
6860 #define FLASH_OBR_USER_Msk                (0xFFUL << FLASH_OBR_USER_Pos)        /*!< 0x0000FF00 */
6861 #define FLASH_OBR_USER                    FLASH_OBR_USER_Msk                   /*!< User Option Bytes */
6862 #define FLASH_OBR_IWDG_SW_Pos             (8U)
6863 #define FLASH_OBR_IWDG_SW_Msk             (0x1UL << FLASH_OBR_IWDG_SW_Pos)      /*!< 0x00000100 */
6864 #define FLASH_OBR_IWDG_SW                 FLASH_OBR_IWDG_SW_Msk                /*!< IWDG SW */
6865 #define FLASH_OBR_nRST_STOP_Pos           (9U)
6866 #define FLASH_OBR_nRST_STOP_Msk           (0x1UL << FLASH_OBR_nRST_STOP_Pos)    /*!< 0x00000200 */
6867 #define FLASH_OBR_nRST_STOP               FLASH_OBR_nRST_STOP_Msk              /*!< nRST_STOP */
6868 #define FLASH_OBR_nRST_STDBY_Pos          (10U)
6869 #define FLASH_OBR_nRST_STDBY_Msk          (0x1UL << FLASH_OBR_nRST_STDBY_Pos)   /*!< 0x00000400 */
6870 #define FLASH_OBR_nRST_STDBY              FLASH_OBR_nRST_STDBY_Msk             /*!< nRST_STDBY */
6871 #define FLASH_OBR_nBOOT0_Pos              (11U)
6872 #define FLASH_OBR_nBOOT0_Msk              (0x1UL << FLASH_OBR_nBOOT0_Pos)       /*!< 0x00000800 */
6873 #define FLASH_OBR_nBOOT0                  FLASH_OBR_nBOOT0_Msk                 /*!< nBOOT0 */
6874 #define FLASH_OBR_nBOOT1_Pos              (12U)
6875 #define FLASH_OBR_nBOOT1_Msk              (0x1UL << FLASH_OBR_nBOOT1_Pos)       /*!< 0x00001000 */
6876 #define FLASH_OBR_nBOOT1                  FLASH_OBR_nBOOT1_Msk                 /*!< nBOOT1 */
6877 #define FLASH_OBR_VDDA_MONITOR_Pos        (13U)
6878 #define FLASH_OBR_VDDA_MONITOR_Msk        (0x1UL << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */
6879 #define FLASH_OBR_VDDA_MONITOR            FLASH_OBR_VDDA_MONITOR_Msk           /*!< VDDA power supply supervisor */
6880 #define FLASH_OBR_RAM_PARITY_CHECK_Pos    (14U)
6881 #define FLASH_OBR_RAM_PARITY_CHECK_Msk    (0x1UL << FLASH_OBR_RAM_PARITY_CHECK_Pos) /*!< 0x00004000 */
6882 #define FLASH_OBR_RAM_PARITY_CHECK        FLASH_OBR_RAM_PARITY_CHECK_Msk       /*!< RAM parity check */
6883 #define FLASH_OBR_BOOT_SEL_Pos            (15U)
6884 #define FLASH_OBR_BOOT_SEL_Msk            (0x1UL << FLASH_OBR_BOOT_SEL_Pos)     /*!< 0x00008000 */
6885 #define FLASH_OBR_BOOT_SEL                FLASH_OBR_BOOT_SEL_Msk               /*!< BOOT selection */
6886 #define FLASH_OBR_DATA0_Pos               (16U)
6887 #define FLASH_OBR_DATA0_Msk               (0xFFUL << FLASH_OBR_DATA0_Pos)       /*!< 0x00FF0000 */
6888 #define FLASH_OBR_DATA0                   FLASH_OBR_DATA0_Msk                  /*!< Data0 */
6889 #define FLASH_OBR_DATA1_Pos               (24U)
6890 #define FLASH_OBR_DATA1_Msk               (0xFFUL << FLASH_OBR_DATA1_Pos)       /*!< 0xFF000000 */
6891 #define FLASH_OBR_DATA1                   FLASH_OBR_DATA1_Msk                  /*!< Data1 */
6892 
6893 /* Old BOOT1 bit definition, maintained for legacy purpose */
6894 #define FLASH_OBR_BOOT1                      FLASH_OBR_nBOOT1
6895 
6896 /* Old OBR_VDDA bit definition, maintained for legacy purpose */
6897 #define FLASH_OBR_VDDA_ANALOG                FLASH_OBR_VDDA_MONITOR
6898 
6899 /******************  Bit definition for FLASH_WRPR register  ******************/
6900 #define FLASH_WRPR_WRP_Pos                (0U)
6901 #define FLASH_WRPR_WRP_Msk                (0xFFFFUL << FLASH_WRPR_WRP_Pos)      /*!< 0x0000FFFF */
6902 #define FLASH_WRPR_WRP                    FLASH_WRPR_WRP_Msk                   /*!< Write Protect */
6903 
6904 /*----------------------------------------------------------------------------*/
6905 
6906 /******************  Bit definition for OB_RDP register  **********************/
6907 #define OB_RDP_RDP_Pos       (0U)
6908 #define OB_RDP_RDP_Msk       (0xFFUL << OB_RDP_RDP_Pos)                         /*!< 0x000000FF */
6909 #define OB_RDP_RDP           OB_RDP_RDP_Msk                                    /*!< Read protection option byte */
6910 #define OB_RDP_nRDP_Pos      (8U)
6911 #define OB_RDP_nRDP_Msk      (0xFFUL << OB_RDP_nRDP_Pos)                        /*!< 0x0000FF00 */
6912 #define OB_RDP_nRDP          OB_RDP_nRDP_Msk                                   /*!< Read protection complemented option byte */
6913 
6914 /******************  Bit definition for OB_USER register  *********************/
6915 #define OB_USER_USER_Pos     (16U)
6916 #define OB_USER_USER_Msk     (0xFFUL << OB_USER_USER_Pos)                       /*!< 0x00FF0000 */
6917 #define OB_USER_USER         OB_USER_USER_Msk                                  /*!< User option byte */
6918 #define OB_USER_nUSER_Pos    (24U)
6919 #define OB_USER_nUSER_Msk    (0xFFUL << OB_USER_nUSER_Pos)                      /*!< 0xFF000000 */
6920 #define OB_USER_nUSER        OB_USER_nUSER_Msk                                 /*!< User complemented option byte */
6921 
6922 /******************  Bit definition for OB_WRP0 register  *********************/
6923 #define OB_WRP0_WRP0_Pos     (0U)
6924 #define OB_WRP0_WRP0_Msk     (0xFFUL << OB_WRP0_WRP0_Pos)                       /*!< 0x000000FF */
6925 #define OB_WRP0_WRP0         OB_WRP0_WRP0_Msk                                  /*!< Flash memory write protection option bytes */
6926 #define OB_WRP0_nWRP0_Pos    (8U)
6927 #define OB_WRP0_nWRP0_Msk    (0xFFUL << OB_WRP0_nWRP0_Pos)                      /*!< 0x0000FF00 */
6928 #define OB_WRP0_nWRP0        OB_WRP0_nWRP0_Msk                                 /*!< Flash memory write protection complemented option bytes */
6929 
6930 /******************  Bit definition for OB_WRP1 register  *********************/
6931 #define OB_WRP1_WRP1_Pos     (16U)
6932 #define OB_WRP1_WRP1_Msk     (0xFFUL << OB_WRP1_WRP1_Pos)                       /*!< 0x00FF0000 */
6933 #define OB_WRP1_WRP1         OB_WRP1_WRP1_Msk                                  /*!< Flash memory write protection option bytes */
6934 #define OB_WRP1_nWRP1_Pos    (24U)
6935 #define OB_WRP1_nWRP1_Msk    (0xFFUL << OB_WRP1_nWRP1_Pos)                      /*!< 0xFF000000 */
6936 #define OB_WRP1_nWRP1        OB_WRP1_nWRP1_Msk                                 /*!< Flash memory write protection complemented option bytes */
6937 
6938 /******************  Bit definition for OB_WRP2 register  *********************/
6939 #define OB_WRP2_WRP2_Pos     (0U)
6940 #define OB_WRP2_WRP2_Msk     (0xFFUL << OB_WRP2_WRP2_Pos)                       /*!< 0x000000FF */
6941 #define OB_WRP2_WRP2         OB_WRP2_WRP2_Msk                                  /*!< Flash memory write protection option bytes */
6942 #define OB_WRP2_nWRP2_Pos    (8U)
6943 #define OB_WRP2_nWRP2_Msk    (0xFFUL << OB_WRP2_nWRP2_Pos)                      /*!< 0x0000FF00 */
6944 #define OB_WRP2_nWRP2        OB_WRP2_nWRP2_Msk                                 /*!< Flash memory write protection complemented option bytes */
6945 
6946 /******************  Bit definition for OB_WRP3 register  *********************/
6947 #define OB_WRP3_WRP3_Pos     (16U)
6948 #define OB_WRP3_WRP3_Msk     (0xFFUL << OB_WRP3_WRP3_Pos)                       /*!< 0x00FF0000 */
6949 #define OB_WRP3_WRP3         OB_WRP3_WRP3_Msk                                  /*!< Flash memory write protection option bytes */
6950 #define OB_WRP3_nWRP3_Pos    (24U)
6951 #define OB_WRP3_nWRP3_Msk    (0xFFUL << OB_WRP3_nWRP3_Pos)                      /*!< 0xFF000000 */
6952 #define OB_WRP3_nWRP3        OB_WRP3_nWRP3_Msk                                 /*!< Flash memory write protection complemented option bytes */
6953 
6954 /******************************************************************************/
6955 /*                                                                            */
6956 /*                       General Purpose IOs (GPIO)                           */
6957 /*                                                                            */
6958 /******************************************************************************/
6959 /*******************  Bit definition for GPIO_MODER register  *****************/
6960 #define GPIO_MODER_MODER0_Pos           (0U)
6961 #define GPIO_MODER_MODER0_Msk           (0x3UL << GPIO_MODER_MODER0_Pos)        /*!< 0x00000003 */
6962 #define GPIO_MODER_MODER0               GPIO_MODER_MODER0_Msk
6963 #define GPIO_MODER_MODER0_0             (0x1UL << GPIO_MODER_MODER0_Pos)        /*!< 0x00000001 */
6964 #define GPIO_MODER_MODER0_1             (0x2UL << GPIO_MODER_MODER0_Pos)        /*!< 0x00000002 */
6965 #define GPIO_MODER_MODER1_Pos           (2U)
6966 #define GPIO_MODER_MODER1_Msk           (0x3UL << GPIO_MODER_MODER1_Pos)        /*!< 0x0000000C */
6967 #define GPIO_MODER_MODER1               GPIO_MODER_MODER1_Msk
6968 #define GPIO_MODER_MODER1_0             (0x1UL << GPIO_MODER_MODER1_Pos)        /*!< 0x00000004 */
6969 #define GPIO_MODER_MODER1_1             (0x2UL << GPIO_MODER_MODER1_Pos)        /*!< 0x00000008 */
6970 #define GPIO_MODER_MODER2_Pos           (4U)
6971 #define GPIO_MODER_MODER2_Msk           (0x3UL << GPIO_MODER_MODER2_Pos)        /*!< 0x00000030 */
6972 #define GPIO_MODER_MODER2               GPIO_MODER_MODER2_Msk
6973 #define GPIO_MODER_MODER2_0             (0x1UL << GPIO_MODER_MODER2_Pos)        /*!< 0x00000010 */
6974 #define GPIO_MODER_MODER2_1             (0x2UL << GPIO_MODER_MODER2_Pos)        /*!< 0x00000020 */
6975 #define GPIO_MODER_MODER3_Pos           (6U)
6976 #define GPIO_MODER_MODER3_Msk           (0x3UL << GPIO_MODER_MODER3_Pos)        /*!< 0x000000C0 */
6977 #define GPIO_MODER_MODER3               GPIO_MODER_MODER3_Msk
6978 #define GPIO_MODER_MODER3_0             (0x1UL << GPIO_MODER_MODER3_Pos)        /*!< 0x00000040 */
6979 #define GPIO_MODER_MODER3_1             (0x2UL << GPIO_MODER_MODER3_Pos)        /*!< 0x00000080 */
6980 #define GPIO_MODER_MODER4_Pos           (8U)
6981 #define GPIO_MODER_MODER4_Msk           (0x3UL << GPIO_MODER_MODER4_Pos)        /*!< 0x00000300 */
6982 #define GPIO_MODER_MODER4               GPIO_MODER_MODER4_Msk
6983 #define GPIO_MODER_MODER4_0             (0x1UL << GPIO_MODER_MODER4_Pos)        /*!< 0x00000100 */
6984 #define GPIO_MODER_MODER4_1             (0x2UL << GPIO_MODER_MODER4_Pos)        /*!< 0x00000200 */
6985 #define GPIO_MODER_MODER5_Pos           (10U)
6986 #define GPIO_MODER_MODER5_Msk           (0x3UL << GPIO_MODER_MODER5_Pos)        /*!< 0x00000C00 */
6987 #define GPIO_MODER_MODER5               GPIO_MODER_MODER5_Msk
6988 #define GPIO_MODER_MODER5_0             (0x1UL << GPIO_MODER_MODER5_Pos)        /*!< 0x00000400 */
6989 #define GPIO_MODER_MODER5_1             (0x2UL << GPIO_MODER_MODER5_Pos)        /*!< 0x00000800 */
6990 #define GPIO_MODER_MODER6_Pos           (12U)
6991 #define GPIO_MODER_MODER6_Msk           (0x3UL << GPIO_MODER_MODER6_Pos)        /*!< 0x00003000 */
6992 #define GPIO_MODER_MODER6               GPIO_MODER_MODER6_Msk
6993 #define GPIO_MODER_MODER6_0             (0x1UL << GPIO_MODER_MODER6_Pos)        /*!< 0x00001000 */
6994 #define GPIO_MODER_MODER6_1             (0x2UL << GPIO_MODER_MODER6_Pos)        /*!< 0x00002000 */
6995 #define GPIO_MODER_MODER7_Pos           (14U)
6996 #define GPIO_MODER_MODER7_Msk           (0x3UL << GPIO_MODER_MODER7_Pos)        /*!< 0x0000C000 */
6997 #define GPIO_MODER_MODER7               GPIO_MODER_MODER7_Msk
6998 #define GPIO_MODER_MODER7_0             (0x1UL << GPIO_MODER_MODER7_Pos)        /*!< 0x00004000 */
6999 #define GPIO_MODER_MODER7_1             (0x2UL << GPIO_MODER_MODER7_Pos)        /*!< 0x00008000 */
7000 #define GPIO_MODER_MODER8_Pos           (16U)
7001 #define GPIO_MODER_MODER8_Msk           (0x3UL << GPIO_MODER_MODER8_Pos)        /*!< 0x00030000 */
7002 #define GPIO_MODER_MODER8               GPIO_MODER_MODER8_Msk
7003 #define GPIO_MODER_MODER8_0             (0x1UL << GPIO_MODER_MODER8_Pos)        /*!< 0x00010000 */
7004 #define GPIO_MODER_MODER8_1             (0x2UL << GPIO_MODER_MODER8_Pos)        /*!< 0x00020000 */
7005 #define GPIO_MODER_MODER9_Pos           (18U)
7006 #define GPIO_MODER_MODER9_Msk           (0x3UL << GPIO_MODER_MODER9_Pos)        /*!< 0x000C0000 */
7007 #define GPIO_MODER_MODER9               GPIO_MODER_MODER9_Msk
7008 #define GPIO_MODER_MODER9_0             (0x1UL << GPIO_MODER_MODER9_Pos)        /*!< 0x00040000 */
7009 #define GPIO_MODER_MODER9_1             (0x2UL << GPIO_MODER_MODER9_Pos)        /*!< 0x00080000 */
7010 #define GPIO_MODER_MODER10_Pos          (20U)
7011 #define GPIO_MODER_MODER10_Msk          (0x3UL << GPIO_MODER_MODER10_Pos)       /*!< 0x00300000 */
7012 #define GPIO_MODER_MODER10              GPIO_MODER_MODER10_Msk
7013 #define GPIO_MODER_MODER10_0            (0x1UL << GPIO_MODER_MODER10_Pos)       /*!< 0x00100000 */
7014 #define GPIO_MODER_MODER10_1            (0x2UL << GPIO_MODER_MODER10_Pos)       /*!< 0x00200000 */
7015 #define GPIO_MODER_MODER11_Pos          (22U)
7016 #define GPIO_MODER_MODER11_Msk          (0x3UL << GPIO_MODER_MODER11_Pos)       /*!< 0x00C00000 */
7017 #define GPIO_MODER_MODER11              GPIO_MODER_MODER11_Msk
7018 #define GPIO_MODER_MODER11_0            (0x1UL << GPIO_MODER_MODER11_Pos)       /*!< 0x00400000 */
7019 #define GPIO_MODER_MODER11_1            (0x2UL << GPIO_MODER_MODER11_Pos)       /*!< 0x00800000 */
7020 #define GPIO_MODER_MODER12_Pos          (24U)
7021 #define GPIO_MODER_MODER12_Msk          (0x3UL << GPIO_MODER_MODER12_Pos)       /*!< 0x03000000 */
7022 #define GPIO_MODER_MODER12              GPIO_MODER_MODER12_Msk
7023 #define GPIO_MODER_MODER12_0            (0x1UL << GPIO_MODER_MODER12_Pos)       /*!< 0x01000000 */
7024 #define GPIO_MODER_MODER12_1            (0x2UL << GPIO_MODER_MODER12_Pos)       /*!< 0x02000000 */
7025 #define GPIO_MODER_MODER13_Pos          (26U)
7026 #define GPIO_MODER_MODER13_Msk          (0x3UL << GPIO_MODER_MODER13_Pos)       /*!< 0x0C000000 */
7027 #define GPIO_MODER_MODER13              GPIO_MODER_MODER13_Msk
7028 #define GPIO_MODER_MODER13_0            (0x1UL << GPIO_MODER_MODER13_Pos)       /*!< 0x04000000 */
7029 #define GPIO_MODER_MODER13_1            (0x2UL << GPIO_MODER_MODER13_Pos)       /*!< 0x08000000 */
7030 #define GPIO_MODER_MODER14_Pos          (28U)
7031 #define GPIO_MODER_MODER14_Msk          (0x3UL << GPIO_MODER_MODER14_Pos)       /*!< 0x30000000 */
7032 #define GPIO_MODER_MODER14              GPIO_MODER_MODER14_Msk
7033 #define GPIO_MODER_MODER14_0            (0x1UL << GPIO_MODER_MODER14_Pos)       /*!< 0x10000000 */
7034 #define GPIO_MODER_MODER14_1            (0x2UL << GPIO_MODER_MODER14_Pos)       /*!< 0x20000000 */
7035 #define GPIO_MODER_MODER15_Pos          (30U)
7036 #define GPIO_MODER_MODER15_Msk          (0x3UL << GPIO_MODER_MODER15_Pos)       /*!< 0xC0000000 */
7037 #define GPIO_MODER_MODER15              GPIO_MODER_MODER15_Msk
7038 #define GPIO_MODER_MODER15_0            (0x1UL << GPIO_MODER_MODER15_Pos)       /*!< 0x40000000 */
7039 #define GPIO_MODER_MODER15_1            (0x2UL << GPIO_MODER_MODER15_Pos)       /*!< 0x80000000 */
7040 
7041 /******************  Bit definition for GPIO_OTYPER register  *****************/
7042 #define GPIO_OTYPER_OT_0                (0x00000001U)
7043 #define GPIO_OTYPER_OT_1                (0x00000002U)
7044 #define GPIO_OTYPER_OT_2                (0x00000004U)
7045 #define GPIO_OTYPER_OT_3                (0x00000008U)
7046 #define GPIO_OTYPER_OT_4                (0x00000010U)
7047 #define GPIO_OTYPER_OT_5                (0x00000020U)
7048 #define GPIO_OTYPER_OT_6                (0x00000040U)
7049 #define GPIO_OTYPER_OT_7                (0x00000080U)
7050 #define GPIO_OTYPER_OT_8                (0x00000100U)
7051 #define GPIO_OTYPER_OT_9                (0x00000200U)
7052 #define GPIO_OTYPER_OT_10               (0x00000400U)
7053 #define GPIO_OTYPER_OT_11               (0x00000800U)
7054 #define GPIO_OTYPER_OT_12               (0x00001000U)
7055 #define GPIO_OTYPER_OT_13               (0x00002000U)
7056 #define GPIO_OTYPER_OT_14               (0x00004000U)
7057 #define GPIO_OTYPER_OT_15               (0x00008000U)
7058 
7059 /****************  Bit definition for GPIO_OSPEEDR register  ******************/
7060 #define GPIO_OSPEEDR_OSPEEDR0_Pos       (0U)
7061 #define GPIO_OSPEEDR_OSPEEDR0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR0_Pos)    /*!< 0x00000003 */
7062 #define GPIO_OSPEEDR_OSPEEDR0           GPIO_OSPEEDR_OSPEEDR0_Msk
7063 #define GPIO_OSPEEDR_OSPEEDR0_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR0_Pos)    /*!< 0x00000001 */
7064 #define GPIO_OSPEEDR_OSPEEDR0_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR0_Pos)    /*!< 0x00000002 */
7065 #define GPIO_OSPEEDR_OSPEEDR1_Pos       (2U)
7066 #define GPIO_OSPEEDR_OSPEEDR1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR1_Pos)    /*!< 0x0000000C */
7067 #define GPIO_OSPEEDR_OSPEEDR1           GPIO_OSPEEDR_OSPEEDR1_Msk
7068 #define GPIO_OSPEEDR_OSPEEDR1_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR1_Pos)    /*!< 0x00000004 */
7069 #define GPIO_OSPEEDR_OSPEEDR1_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR1_Pos)    /*!< 0x00000008 */
7070 #define GPIO_OSPEEDR_OSPEEDR2_Pos       (4U)
7071 #define GPIO_OSPEEDR_OSPEEDR2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR2_Pos)    /*!< 0x00000030 */
7072 #define GPIO_OSPEEDR_OSPEEDR2           GPIO_OSPEEDR_OSPEEDR2_Msk
7073 #define GPIO_OSPEEDR_OSPEEDR2_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR2_Pos)    /*!< 0x00000010 */
7074 #define GPIO_OSPEEDR_OSPEEDR2_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR2_Pos)    /*!< 0x00000020 */
7075 #define GPIO_OSPEEDR_OSPEEDR3_Pos       (6U)
7076 #define GPIO_OSPEEDR_OSPEEDR3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR3_Pos)    /*!< 0x000000C0 */
7077 #define GPIO_OSPEEDR_OSPEEDR3           GPIO_OSPEEDR_OSPEEDR3_Msk
7078 #define GPIO_OSPEEDR_OSPEEDR3_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR3_Pos)    /*!< 0x00000040 */
7079 #define GPIO_OSPEEDR_OSPEEDR3_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR3_Pos)    /*!< 0x00000080 */
7080 #define GPIO_OSPEEDR_OSPEEDR4_Pos       (8U)
7081 #define GPIO_OSPEEDR_OSPEEDR4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR4_Pos)    /*!< 0x00000300 */
7082 #define GPIO_OSPEEDR_OSPEEDR4           GPIO_OSPEEDR_OSPEEDR4_Msk
7083 #define GPIO_OSPEEDR_OSPEEDR4_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR4_Pos)    /*!< 0x00000100 */
7084 #define GPIO_OSPEEDR_OSPEEDR4_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR4_Pos)    /*!< 0x00000200 */
7085 #define GPIO_OSPEEDR_OSPEEDR5_Pos       (10U)
7086 #define GPIO_OSPEEDR_OSPEEDR5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR5_Pos)    /*!< 0x00000C00 */
7087 #define GPIO_OSPEEDR_OSPEEDR5           GPIO_OSPEEDR_OSPEEDR5_Msk
7088 #define GPIO_OSPEEDR_OSPEEDR5_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR5_Pos)    /*!< 0x00000400 */
7089 #define GPIO_OSPEEDR_OSPEEDR5_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR5_Pos)    /*!< 0x00000800 */
7090 #define GPIO_OSPEEDR_OSPEEDR6_Pos       (12U)
7091 #define GPIO_OSPEEDR_OSPEEDR6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR6_Pos)    /*!< 0x00003000 */
7092 #define GPIO_OSPEEDR_OSPEEDR6           GPIO_OSPEEDR_OSPEEDR6_Msk
7093 #define GPIO_OSPEEDR_OSPEEDR6_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR6_Pos)    /*!< 0x00001000 */
7094 #define GPIO_OSPEEDR_OSPEEDR6_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR6_Pos)    /*!< 0x00002000 */
7095 #define GPIO_OSPEEDR_OSPEEDR7_Pos       (14U)
7096 #define GPIO_OSPEEDR_OSPEEDR7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR7_Pos)    /*!< 0x0000C000 */
7097 #define GPIO_OSPEEDR_OSPEEDR7           GPIO_OSPEEDR_OSPEEDR7_Msk
7098 #define GPIO_OSPEEDR_OSPEEDR7_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR7_Pos)    /*!< 0x00004000 */
7099 #define GPIO_OSPEEDR_OSPEEDR7_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR7_Pos)    /*!< 0x00008000 */
7100 #define GPIO_OSPEEDR_OSPEEDR8_Pos       (16U)
7101 #define GPIO_OSPEEDR_OSPEEDR8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR8_Pos)    /*!< 0x00030000 */
7102 #define GPIO_OSPEEDR_OSPEEDR8           GPIO_OSPEEDR_OSPEEDR8_Msk
7103 #define GPIO_OSPEEDR_OSPEEDR8_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR8_Pos)    /*!< 0x00010000 */
7104 #define GPIO_OSPEEDR_OSPEEDR8_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR8_Pos)    /*!< 0x00020000 */
7105 #define GPIO_OSPEEDR_OSPEEDR9_Pos       (18U)
7106 #define GPIO_OSPEEDR_OSPEEDR9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR9_Pos)    /*!< 0x000C0000 */
7107 #define GPIO_OSPEEDR_OSPEEDR9           GPIO_OSPEEDR_OSPEEDR9_Msk
7108 #define GPIO_OSPEEDR_OSPEEDR9_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR9_Pos)    /*!< 0x00040000 */
7109 #define GPIO_OSPEEDR_OSPEEDR9_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR9_Pos)    /*!< 0x00080000 */
7110 #define GPIO_OSPEEDR_OSPEEDR10_Pos      (20U)
7111 #define GPIO_OSPEEDR_OSPEEDR10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEEDR10_Pos)   /*!< 0x00300000 */
7112 #define GPIO_OSPEEDR_OSPEEDR10          GPIO_OSPEEDR_OSPEEDR10_Msk
7113 #define GPIO_OSPEEDR_OSPEEDR10_0        (0x1UL << GPIO_OSPEEDR_OSPEEDR10_Pos)   /*!< 0x00100000 */
7114 #define GPIO_OSPEEDR_OSPEEDR10_1        (0x2UL << GPIO_OSPEEDR_OSPEEDR10_Pos)   /*!< 0x00200000 */
7115 #define GPIO_OSPEEDR_OSPEEDR11_Pos      (22U)
7116 #define GPIO_OSPEEDR_OSPEEDR11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEEDR11_Pos)   /*!< 0x00C00000 */
7117 #define GPIO_OSPEEDR_OSPEEDR11          GPIO_OSPEEDR_OSPEEDR11_Msk
7118 #define GPIO_OSPEEDR_OSPEEDR11_0        (0x1UL << GPIO_OSPEEDR_OSPEEDR11_Pos)   /*!< 0x00400000 */
7119 #define GPIO_OSPEEDR_OSPEEDR11_1        (0x2UL << GPIO_OSPEEDR_OSPEEDR11_Pos)   /*!< 0x00800000 */
7120 #define GPIO_OSPEEDR_OSPEEDR12_Pos      (24U)
7121 #define GPIO_OSPEEDR_OSPEEDR12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEEDR12_Pos)   /*!< 0x03000000 */
7122 #define GPIO_OSPEEDR_OSPEEDR12          GPIO_OSPEEDR_OSPEEDR12_Msk
7123 #define GPIO_OSPEEDR_OSPEEDR12_0        (0x1UL << GPIO_OSPEEDR_OSPEEDR12_Pos)   /*!< 0x01000000 */
7124 #define GPIO_OSPEEDR_OSPEEDR12_1        (0x2UL << GPIO_OSPEEDR_OSPEEDR12_Pos)   /*!< 0x02000000 */
7125 #define GPIO_OSPEEDR_OSPEEDR13_Pos      (26U)
7126 #define GPIO_OSPEEDR_OSPEEDR13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEEDR13_Pos)   /*!< 0x0C000000 */
7127 #define GPIO_OSPEEDR_OSPEEDR13          GPIO_OSPEEDR_OSPEEDR13_Msk
7128 #define GPIO_OSPEEDR_OSPEEDR13_0        (0x1UL << GPIO_OSPEEDR_OSPEEDR13_Pos)   /*!< 0x04000000 */
7129 #define GPIO_OSPEEDR_OSPEEDR13_1        (0x2UL << GPIO_OSPEEDR_OSPEEDR13_Pos)   /*!< 0x08000000 */
7130 #define GPIO_OSPEEDR_OSPEEDR14_Pos      (28U)
7131 #define GPIO_OSPEEDR_OSPEEDR14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEEDR14_Pos)   /*!< 0x30000000 */
7132 #define GPIO_OSPEEDR_OSPEEDR14          GPIO_OSPEEDR_OSPEEDR14_Msk
7133 #define GPIO_OSPEEDR_OSPEEDR14_0        (0x1UL << GPIO_OSPEEDR_OSPEEDR14_Pos)   /*!< 0x10000000 */
7134 #define GPIO_OSPEEDR_OSPEEDR14_1        (0x2UL << GPIO_OSPEEDR_OSPEEDR14_Pos)   /*!< 0x20000000 */
7135 #define GPIO_OSPEEDR_OSPEEDR15_Pos      (30U)
7136 #define GPIO_OSPEEDR_OSPEEDR15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEEDR15_Pos)   /*!< 0xC0000000 */
7137 #define GPIO_OSPEEDR_OSPEEDR15          GPIO_OSPEEDR_OSPEEDR15_Msk
7138 #define GPIO_OSPEEDR_OSPEEDR15_0        (0x1UL << GPIO_OSPEEDR_OSPEEDR15_Pos)   /*!< 0x40000000 */
7139 #define GPIO_OSPEEDR_OSPEEDR15_1        (0x2UL << GPIO_OSPEEDR_OSPEEDR15_Pos)   /*!< 0x80000000 */
7140 
7141 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
7142 #define GPIO_OSPEEDER_OSPEEDR0     GPIO_OSPEEDR_OSPEEDR0
7143 #define GPIO_OSPEEDER_OSPEEDR0_0   GPIO_OSPEEDR_OSPEEDR0_0
7144 #define GPIO_OSPEEDER_OSPEEDR0_1   GPIO_OSPEEDR_OSPEEDR0_1
7145 #define GPIO_OSPEEDER_OSPEEDR1     GPIO_OSPEEDR_OSPEEDR1
7146 #define GPIO_OSPEEDER_OSPEEDR1_0   GPIO_OSPEEDR_OSPEEDR1_0
7147 #define GPIO_OSPEEDER_OSPEEDR1_1   GPIO_OSPEEDR_OSPEEDR1_1
7148 #define GPIO_OSPEEDER_OSPEEDR2     GPIO_OSPEEDR_OSPEEDR2
7149 #define GPIO_OSPEEDER_OSPEEDR2_0   GPIO_OSPEEDR_OSPEEDR2_0
7150 #define GPIO_OSPEEDER_OSPEEDR2_1   GPIO_OSPEEDR_OSPEEDR2_1
7151 #define GPIO_OSPEEDER_OSPEEDR3     GPIO_OSPEEDR_OSPEEDR3
7152 #define GPIO_OSPEEDER_OSPEEDR3_0   GPIO_OSPEEDR_OSPEEDR3_0
7153 #define GPIO_OSPEEDER_OSPEEDR3_1   GPIO_OSPEEDR_OSPEEDR3_1
7154 #define GPIO_OSPEEDER_OSPEEDR4     GPIO_OSPEEDR_OSPEEDR4
7155 #define GPIO_OSPEEDER_OSPEEDR4_0   GPIO_OSPEEDR_OSPEEDR4_0
7156 #define GPIO_OSPEEDER_OSPEEDR4_1   GPIO_OSPEEDR_OSPEEDR4_1
7157 #define GPIO_OSPEEDER_OSPEEDR5     GPIO_OSPEEDR_OSPEEDR5
7158 #define GPIO_OSPEEDER_OSPEEDR5_0   GPIO_OSPEEDR_OSPEEDR5_0
7159 #define GPIO_OSPEEDER_OSPEEDR5_1   GPIO_OSPEEDR_OSPEEDR5_1
7160 #define GPIO_OSPEEDER_OSPEEDR6     GPIO_OSPEEDR_OSPEEDR6
7161 #define GPIO_OSPEEDER_OSPEEDR6_0   GPIO_OSPEEDR_OSPEEDR6_0
7162 #define GPIO_OSPEEDER_OSPEEDR6_1   GPIO_OSPEEDR_OSPEEDR6_1
7163 #define GPIO_OSPEEDER_OSPEEDR7     GPIO_OSPEEDR_OSPEEDR7
7164 #define GPIO_OSPEEDER_OSPEEDR7_0   GPIO_OSPEEDR_OSPEEDR7_0
7165 #define GPIO_OSPEEDER_OSPEEDR7_1   GPIO_OSPEEDR_OSPEEDR7_1
7166 #define GPIO_OSPEEDER_OSPEEDR8     GPIO_OSPEEDR_OSPEEDR8
7167 #define GPIO_OSPEEDER_OSPEEDR8_0   GPIO_OSPEEDR_OSPEEDR8_0
7168 #define GPIO_OSPEEDER_OSPEEDR8_1   GPIO_OSPEEDR_OSPEEDR8_1
7169 #define GPIO_OSPEEDER_OSPEEDR9     GPIO_OSPEEDR_OSPEEDR9
7170 #define GPIO_OSPEEDER_OSPEEDR9_0   GPIO_OSPEEDR_OSPEEDR9_0
7171 #define GPIO_OSPEEDER_OSPEEDR9_1   GPIO_OSPEEDR_OSPEEDR9_1
7172 #define GPIO_OSPEEDER_OSPEEDR10    GPIO_OSPEEDR_OSPEEDR10
7173 #define GPIO_OSPEEDER_OSPEEDR10_0  GPIO_OSPEEDR_OSPEEDR10_0
7174 #define GPIO_OSPEEDER_OSPEEDR10_1  GPIO_OSPEEDR_OSPEEDR10_1
7175 #define GPIO_OSPEEDER_OSPEEDR11    GPIO_OSPEEDR_OSPEEDR11
7176 #define GPIO_OSPEEDER_OSPEEDR11_0  GPIO_OSPEEDR_OSPEEDR11_0
7177 #define GPIO_OSPEEDER_OSPEEDR11_1  GPIO_OSPEEDR_OSPEEDR11_1
7178 #define GPIO_OSPEEDER_OSPEEDR12    GPIO_OSPEEDR_OSPEEDR12
7179 #define GPIO_OSPEEDER_OSPEEDR12_0  GPIO_OSPEEDR_OSPEEDR12_0
7180 #define GPIO_OSPEEDER_OSPEEDR12_1  GPIO_OSPEEDR_OSPEEDR12_1
7181 #define GPIO_OSPEEDER_OSPEEDR13    GPIO_OSPEEDR_OSPEEDR13
7182 #define GPIO_OSPEEDER_OSPEEDR13_0  GPIO_OSPEEDR_OSPEEDR13_0
7183 #define GPIO_OSPEEDER_OSPEEDR13_1  GPIO_OSPEEDR_OSPEEDR13_1
7184 #define GPIO_OSPEEDER_OSPEEDR14    GPIO_OSPEEDR_OSPEEDR14
7185 #define GPIO_OSPEEDER_OSPEEDR14_0  GPIO_OSPEEDR_OSPEEDR14_0
7186 #define GPIO_OSPEEDER_OSPEEDR14_1  GPIO_OSPEEDR_OSPEEDR14_1
7187 #define GPIO_OSPEEDER_OSPEEDR15    GPIO_OSPEEDR_OSPEEDR15
7188 #define GPIO_OSPEEDER_OSPEEDR15_0  GPIO_OSPEEDR_OSPEEDR15_0
7189 #define GPIO_OSPEEDER_OSPEEDR15_1  GPIO_OSPEEDR_OSPEEDR15_1
7190 
7191 /*******************  Bit definition for GPIO_PUPDR register ******************/
7192 #define GPIO_PUPDR_PUPDR0_Pos           (0U)
7193 #define GPIO_PUPDR_PUPDR0_Msk           (0x3UL << GPIO_PUPDR_PUPDR0_Pos)        /*!< 0x00000003 */
7194 #define GPIO_PUPDR_PUPDR0               GPIO_PUPDR_PUPDR0_Msk
7195 #define GPIO_PUPDR_PUPDR0_0             (0x1UL << GPIO_PUPDR_PUPDR0_Pos)        /*!< 0x00000001 */
7196 #define GPIO_PUPDR_PUPDR0_1             (0x2UL << GPIO_PUPDR_PUPDR0_Pos)        /*!< 0x00000002 */
7197 #define GPIO_PUPDR_PUPDR1_Pos           (2U)
7198 #define GPIO_PUPDR_PUPDR1_Msk           (0x3UL << GPIO_PUPDR_PUPDR1_Pos)        /*!< 0x0000000C */
7199 #define GPIO_PUPDR_PUPDR1               GPIO_PUPDR_PUPDR1_Msk
7200 #define GPIO_PUPDR_PUPDR1_0             (0x1UL << GPIO_PUPDR_PUPDR1_Pos)        /*!< 0x00000004 */
7201 #define GPIO_PUPDR_PUPDR1_1             (0x2UL << GPIO_PUPDR_PUPDR1_Pos)        /*!< 0x00000008 */
7202 #define GPIO_PUPDR_PUPDR2_Pos           (4U)
7203 #define GPIO_PUPDR_PUPDR2_Msk           (0x3UL << GPIO_PUPDR_PUPDR2_Pos)        /*!< 0x00000030 */
7204 #define GPIO_PUPDR_PUPDR2               GPIO_PUPDR_PUPDR2_Msk
7205 #define GPIO_PUPDR_PUPDR2_0             (0x1UL << GPIO_PUPDR_PUPDR2_Pos)        /*!< 0x00000010 */
7206 #define GPIO_PUPDR_PUPDR2_1             (0x2UL << GPIO_PUPDR_PUPDR2_Pos)        /*!< 0x00000020 */
7207 #define GPIO_PUPDR_PUPDR3_Pos           (6U)
7208 #define GPIO_PUPDR_PUPDR3_Msk           (0x3UL << GPIO_PUPDR_PUPDR3_Pos)        /*!< 0x000000C0 */
7209 #define GPIO_PUPDR_PUPDR3               GPIO_PUPDR_PUPDR3_Msk
7210 #define GPIO_PUPDR_PUPDR3_0             (0x1UL << GPIO_PUPDR_PUPDR3_Pos)        /*!< 0x00000040 */
7211 #define GPIO_PUPDR_PUPDR3_1             (0x2UL << GPIO_PUPDR_PUPDR3_Pos)        /*!< 0x00000080 */
7212 #define GPIO_PUPDR_PUPDR4_Pos           (8U)
7213 #define GPIO_PUPDR_PUPDR4_Msk           (0x3UL << GPIO_PUPDR_PUPDR4_Pos)        /*!< 0x00000300 */
7214 #define GPIO_PUPDR_PUPDR4               GPIO_PUPDR_PUPDR4_Msk
7215 #define GPIO_PUPDR_PUPDR4_0             (0x1UL << GPIO_PUPDR_PUPDR4_Pos)        /*!< 0x00000100 */
7216 #define GPIO_PUPDR_PUPDR4_1             (0x2UL << GPIO_PUPDR_PUPDR4_Pos)        /*!< 0x00000200 */
7217 #define GPIO_PUPDR_PUPDR5_Pos           (10U)
7218 #define GPIO_PUPDR_PUPDR5_Msk           (0x3UL << GPIO_PUPDR_PUPDR5_Pos)        /*!< 0x00000C00 */
7219 #define GPIO_PUPDR_PUPDR5               GPIO_PUPDR_PUPDR5_Msk
7220 #define GPIO_PUPDR_PUPDR5_0             (0x1UL << GPIO_PUPDR_PUPDR5_Pos)        /*!< 0x00000400 */
7221 #define GPIO_PUPDR_PUPDR5_1             (0x2UL << GPIO_PUPDR_PUPDR5_Pos)        /*!< 0x00000800 */
7222 #define GPIO_PUPDR_PUPDR6_Pos           (12U)
7223 #define GPIO_PUPDR_PUPDR6_Msk           (0x3UL << GPIO_PUPDR_PUPDR6_Pos)        /*!< 0x00003000 */
7224 #define GPIO_PUPDR_PUPDR6               GPIO_PUPDR_PUPDR6_Msk
7225 #define GPIO_PUPDR_PUPDR6_0             (0x1UL << GPIO_PUPDR_PUPDR6_Pos)        /*!< 0x00001000 */
7226 #define GPIO_PUPDR_PUPDR6_1             (0x2UL << GPIO_PUPDR_PUPDR6_Pos)        /*!< 0x00002000 */
7227 #define GPIO_PUPDR_PUPDR7_Pos           (14U)
7228 #define GPIO_PUPDR_PUPDR7_Msk           (0x3UL << GPIO_PUPDR_PUPDR7_Pos)        /*!< 0x0000C000 */
7229 #define GPIO_PUPDR_PUPDR7               GPIO_PUPDR_PUPDR7_Msk
7230 #define GPIO_PUPDR_PUPDR7_0             (0x1UL << GPIO_PUPDR_PUPDR7_Pos)        /*!< 0x00004000 */
7231 #define GPIO_PUPDR_PUPDR7_1             (0x2UL << GPIO_PUPDR_PUPDR7_Pos)        /*!< 0x00008000 */
7232 #define GPIO_PUPDR_PUPDR8_Pos           (16U)
7233 #define GPIO_PUPDR_PUPDR8_Msk           (0x3UL << GPIO_PUPDR_PUPDR8_Pos)        /*!< 0x00030000 */
7234 #define GPIO_PUPDR_PUPDR8               GPIO_PUPDR_PUPDR8_Msk
7235 #define GPIO_PUPDR_PUPDR8_0             (0x1UL << GPIO_PUPDR_PUPDR8_Pos)        /*!< 0x00010000 */
7236 #define GPIO_PUPDR_PUPDR8_1             (0x2UL << GPIO_PUPDR_PUPDR8_Pos)        /*!< 0x00020000 */
7237 #define GPIO_PUPDR_PUPDR9_Pos           (18U)
7238 #define GPIO_PUPDR_PUPDR9_Msk           (0x3UL << GPIO_PUPDR_PUPDR9_Pos)        /*!< 0x000C0000 */
7239 #define GPIO_PUPDR_PUPDR9               GPIO_PUPDR_PUPDR9_Msk
7240 #define GPIO_PUPDR_PUPDR9_0             (0x1UL << GPIO_PUPDR_PUPDR9_Pos)        /*!< 0x00040000 */
7241 #define GPIO_PUPDR_PUPDR9_1             (0x2UL << GPIO_PUPDR_PUPDR9_Pos)        /*!< 0x00080000 */
7242 #define GPIO_PUPDR_PUPDR10_Pos          (20U)
7243 #define GPIO_PUPDR_PUPDR10_Msk          (0x3UL << GPIO_PUPDR_PUPDR10_Pos)       /*!< 0x00300000 */
7244 #define GPIO_PUPDR_PUPDR10              GPIO_PUPDR_PUPDR10_Msk
7245 #define GPIO_PUPDR_PUPDR10_0            (0x1UL << GPIO_PUPDR_PUPDR10_Pos)       /*!< 0x00100000 */
7246 #define GPIO_PUPDR_PUPDR10_1            (0x2UL << GPIO_PUPDR_PUPDR10_Pos)       /*!< 0x00200000 */
7247 #define GPIO_PUPDR_PUPDR11_Pos          (22U)
7248 #define GPIO_PUPDR_PUPDR11_Msk          (0x3UL << GPIO_PUPDR_PUPDR11_Pos)       /*!< 0x00C00000 */
7249 #define GPIO_PUPDR_PUPDR11              GPIO_PUPDR_PUPDR11_Msk
7250 #define GPIO_PUPDR_PUPDR11_0            (0x1UL << GPIO_PUPDR_PUPDR11_Pos)       /*!< 0x00400000 */
7251 #define GPIO_PUPDR_PUPDR11_1            (0x2UL << GPIO_PUPDR_PUPDR11_Pos)       /*!< 0x00800000 */
7252 #define GPIO_PUPDR_PUPDR12_Pos          (24U)
7253 #define GPIO_PUPDR_PUPDR12_Msk          (0x3UL << GPIO_PUPDR_PUPDR12_Pos)       /*!< 0x03000000 */
7254 #define GPIO_PUPDR_PUPDR12              GPIO_PUPDR_PUPDR12_Msk
7255 #define GPIO_PUPDR_PUPDR12_0            (0x1UL << GPIO_PUPDR_PUPDR12_Pos)       /*!< 0x01000000 */
7256 #define GPIO_PUPDR_PUPDR12_1            (0x2UL << GPIO_PUPDR_PUPDR12_Pos)       /*!< 0x02000000 */
7257 #define GPIO_PUPDR_PUPDR13_Pos          (26U)
7258 #define GPIO_PUPDR_PUPDR13_Msk          (0x3UL << GPIO_PUPDR_PUPDR13_Pos)       /*!< 0x0C000000 */
7259 #define GPIO_PUPDR_PUPDR13              GPIO_PUPDR_PUPDR13_Msk
7260 #define GPIO_PUPDR_PUPDR13_0            (0x1UL << GPIO_PUPDR_PUPDR13_Pos)       /*!< 0x04000000 */
7261 #define GPIO_PUPDR_PUPDR13_1            (0x2UL << GPIO_PUPDR_PUPDR13_Pos)       /*!< 0x08000000 */
7262 #define GPIO_PUPDR_PUPDR14_Pos          (28U)
7263 #define GPIO_PUPDR_PUPDR14_Msk          (0x3UL << GPIO_PUPDR_PUPDR14_Pos)       /*!< 0x30000000 */
7264 #define GPIO_PUPDR_PUPDR14              GPIO_PUPDR_PUPDR14_Msk
7265 #define GPIO_PUPDR_PUPDR14_0            (0x1UL << GPIO_PUPDR_PUPDR14_Pos)       /*!< 0x10000000 */
7266 #define GPIO_PUPDR_PUPDR14_1            (0x2UL << GPIO_PUPDR_PUPDR14_Pos)       /*!< 0x20000000 */
7267 #define GPIO_PUPDR_PUPDR15_Pos          (30U)
7268 #define GPIO_PUPDR_PUPDR15_Msk          (0x3UL << GPIO_PUPDR_PUPDR15_Pos)       /*!< 0xC0000000 */
7269 #define GPIO_PUPDR_PUPDR15              GPIO_PUPDR_PUPDR15_Msk
7270 #define GPIO_PUPDR_PUPDR15_0            (0x1UL << GPIO_PUPDR_PUPDR15_Pos)       /*!< 0x40000000 */
7271 #define GPIO_PUPDR_PUPDR15_1            (0x2UL << GPIO_PUPDR_PUPDR15_Pos)       /*!< 0x80000000 */
7272 
7273 /*******************  Bit definition for GPIO_IDR register  *******************/
7274 #define GPIO_IDR_0                      (0x00000001U)
7275 #define GPIO_IDR_1                      (0x00000002U)
7276 #define GPIO_IDR_2                      (0x00000004U)
7277 #define GPIO_IDR_3                      (0x00000008U)
7278 #define GPIO_IDR_4                      (0x00000010U)
7279 #define GPIO_IDR_5                      (0x00000020U)
7280 #define GPIO_IDR_6                      (0x00000040U)
7281 #define GPIO_IDR_7                      (0x00000080U)
7282 #define GPIO_IDR_8                      (0x00000100U)
7283 #define GPIO_IDR_9                      (0x00000200U)
7284 #define GPIO_IDR_10                     (0x00000400U)
7285 #define GPIO_IDR_11                     (0x00000800U)
7286 #define GPIO_IDR_12                     (0x00001000U)
7287 #define GPIO_IDR_13                     (0x00002000U)
7288 #define GPIO_IDR_14                     (0x00004000U)
7289 #define GPIO_IDR_15                     (0x00008000U)
7290 
7291 /******************  Bit definition for GPIO_ODR register  ********************/
7292 #define GPIO_ODR_0                      (0x00000001U)
7293 #define GPIO_ODR_1                      (0x00000002U)
7294 #define GPIO_ODR_2                      (0x00000004U)
7295 #define GPIO_ODR_3                      (0x00000008U)
7296 #define GPIO_ODR_4                      (0x00000010U)
7297 #define GPIO_ODR_5                      (0x00000020U)
7298 #define GPIO_ODR_6                      (0x00000040U)
7299 #define GPIO_ODR_7                      (0x00000080U)
7300 #define GPIO_ODR_8                      (0x00000100U)
7301 #define GPIO_ODR_9                      (0x00000200U)
7302 #define GPIO_ODR_10                     (0x00000400U)
7303 #define GPIO_ODR_11                     (0x00000800U)
7304 #define GPIO_ODR_12                     (0x00001000U)
7305 #define GPIO_ODR_13                     (0x00002000U)
7306 #define GPIO_ODR_14                     (0x00004000U)
7307 #define GPIO_ODR_15                     (0x00008000U)
7308 
7309 /****************** Bit definition for GPIO_BSRR register  ********************/
7310 #define GPIO_BSRR_BS_0                  (0x00000001U)
7311 #define GPIO_BSRR_BS_1                  (0x00000002U)
7312 #define GPIO_BSRR_BS_2                  (0x00000004U)
7313 #define GPIO_BSRR_BS_3                  (0x00000008U)
7314 #define GPIO_BSRR_BS_4                  (0x00000010U)
7315 #define GPIO_BSRR_BS_5                  (0x00000020U)
7316 #define GPIO_BSRR_BS_6                  (0x00000040U)
7317 #define GPIO_BSRR_BS_7                  (0x00000080U)
7318 #define GPIO_BSRR_BS_8                  (0x00000100U)
7319 #define GPIO_BSRR_BS_9                  (0x00000200U)
7320 #define GPIO_BSRR_BS_10                 (0x00000400U)
7321 #define GPIO_BSRR_BS_11                 (0x00000800U)
7322 #define GPIO_BSRR_BS_12                 (0x00001000U)
7323 #define GPIO_BSRR_BS_13                 (0x00002000U)
7324 #define GPIO_BSRR_BS_14                 (0x00004000U)
7325 #define GPIO_BSRR_BS_15                 (0x00008000U)
7326 #define GPIO_BSRR_BR_0                  (0x00010000U)
7327 #define GPIO_BSRR_BR_1                  (0x00020000U)
7328 #define GPIO_BSRR_BR_2                  (0x00040000U)
7329 #define GPIO_BSRR_BR_3                  (0x00080000U)
7330 #define GPIO_BSRR_BR_4                  (0x00100000U)
7331 #define GPIO_BSRR_BR_5                  (0x00200000U)
7332 #define GPIO_BSRR_BR_6                  (0x00400000U)
7333 #define GPIO_BSRR_BR_7                  (0x00800000U)
7334 #define GPIO_BSRR_BR_8                  (0x01000000U)
7335 #define GPIO_BSRR_BR_9                  (0x02000000U)
7336 #define GPIO_BSRR_BR_10                 (0x04000000U)
7337 #define GPIO_BSRR_BR_11                 (0x08000000U)
7338 #define GPIO_BSRR_BR_12                 (0x10000000U)
7339 #define GPIO_BSRR_BR_13                 (0x20000000U)
7340 #define GPIO_BSRR_BR_14                 (0x40000000U)
7341 #define GPIO_BSRR_BR_15                 (0x80000000U)
7342 
7343 /****************** Bit definition for GPIO_LCKR register  ********************/
7344 #define GPIO_LCKR_LCK0_Pos              (0U)
7345 #define GPIO_LCKR_LCK0_Msk              (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
7346 #define GPIO_LCKR_LCK0                  GPIO_LCKR_LCK0_Msk
7347 #define GPIO_LCKR_LCK1_Pos              (1U)
7348 #define GPIO_LCKR_LCK1_Msk              (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
7349 #define GPIO_LCKR_LCK1                  GPIO_LCKR_LCK1_Msk
7350 #define GPIO_LCKR_LCK2_Pos              (2U)
7351 #define GPIO_LCKR_LCK2_Msk              (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
7352 #define GPIO_LCKR_LCK2                  GPIO_LCKR_LCK2_Msk
7353 #define GPIO_LCKR_LCK3_Pos              (3U)
7354 #define GPIO_LCKR_LCK3_Msk              (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
7355 #define GPIO_LCKR_LCK3                  GPIO_LCKR_LCK3_Msk
7356 #define GPIO_LCKR_LCK4_Pos              (4U)
7357 #define GPIO_LCKR_LCK4_Msk              (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
7358 #define GPIO_LCKR_LCK4                  GPIO_LCKR_LCK4_Msk
7359 #define GPIO_LCKR_LCK5_Pos              (5U)
7360 #define GPIO_LCKR_LCK5_Msk              (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
7361 #define GPIO_LCKR_LCK5                  GPIO_LCKR_LCK5_Msk
7362 #define GPIO_LCKR_LCK6_Pos              (6U)
7363 #define GPIO_LCKR_LCK6_Msk              (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
7364 #define GPIO_LCKR_LCK6                  GPIO_LCKR_LCK6_Msk
7365 #define GPIO_LCKR_LCK7_Pos              (7U)
7366 #define GPIO_LCKR_LCK7_Msk              (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
7367 #define GPIO_LCKR_LCK7                  GPIO_LCKR_LCK7_Msk
7368 #define GPIO_LCKR_LCK8_Pos              (8U)
7369 #define GPIO_LCKR_LCK8_Msk              (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
7370 #define GPIO_LCKR_LCK8                  GPIO_LCKR_LCK8_Msk
7371 #define GPIO_LCKR_LCK9_Pos              (9U)
7372 #define GPIO_LCKR_LCK9_Msk              (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
7373 #define GPIO_LCKR_LCK9                  GPIO_LCKR_LCK9_Msk
7374 #define GPIO_LCKR_LCK10_Pos             (10U)
7375 #define GPIO_LCKR_LCK10_Msk             (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
7376 #define GPIO_LCKR_LCK10                 GPIO_LCKR_LCK10_Msk
7377 #define GPIO_LCKR_LCK11_Pos             (11U)
7378 #define GPIO_LCKR_LCK11_Msk             (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
7379 #define GPIO_LCKR_LCK11                 GPIO_LCKR_LCK11_Msk
7380 #define GPIO_LCKR_LCK12_Pos             (12U)
7381 #define GPIO_LCKR_LCK12_Msk             (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
7382 #define GPIO_LCKR_LCK12                 GPIO_LCKR_LCK12_Msk
7383 #define GPIO_LCKR_LCK13_Pos             (13U)
7384 #define GPIO_LCKR_LCK13_Msk             (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
7385 #define GPIO_LCKR_LCK13                 GPIO_LCKR_LCK13_Msk
7386 #define GPIO_LCKR_LCK14_Pos             (14U)
7387 #define GPIO_LCKR_LCK14_Msk             (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
7388 #define GPIO_LCKR_LCK14                 GPIO_LCKR_LCK14_Msk
7389 #define GPIO_LCKR_LCK15_Pos             (15U)
7390 #define GPIO_LCKR_LCK15_Msk             (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
7391 #define GPIO_LCKR_LCK15                 GPIO_LCKR_LCK15_Msk
7392 #define GPIO_LCKR_LCKK_Pos              (16U)
7393 #define GPIO_LCKR_LCKK_Msk              (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
7394 #define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk
7395 
7396 /****************** Bit definition for GPIO_AFRL register  ********************/
7397 #define GPIO_AFRL_AFSEL0_Pos            (0U)
7398 #define GPIO_AFRL_AFSEL0_Msk            (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
7399 #define GPIO_AFRL_AFSEL0                GPIO_AFRL_AFSEL0_Msk
7400 #define GPIO_AFRL_AFSEL1_Pos            (4U)
7401 #define GPIO_AFRL_AFSEL1_Msk            (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
7402 #define GPIO_AFRL_AFSEL1                GPIO_AFRL_AFSEL1_Msk
7403 #define GPIO_AFRL_AFSEL2_Pos            (8U)
7404 #define GPIO_AFRL_AFSEL2_Msk            (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
7405 #define GPIO_AFRL_AFSEL2                GPIO_AFRL_AFSEL2_Msk
7406 #define GPIO_AFRL_AFSEL3_Pos            (12U)
7407 #define GPIO_AFRL_AFSEL3_Msk            (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
7408 #define GPIO_AFRL_AFSEL3                GPIO_AFRL_AFSEL3_Msk
7409 #define GPIO_AFRL_AFSEL4_Pos            (16U)
7410 #define GPIO_AFRL_AFSEL4_Msk            (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
7411 #define GPIO_AFRL_AFSEL4                GPIO_AFRL_AFSEL4_Msk
7412 #define GPIO_AFRL_AFSEL5_Pos            (20U)
7413 #define GPIO_AFRL_AFSEL5_Msk            (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
7414 #define GPIO_AFRL_AFSEL5                GPIO_AFRL_AFSEL5_Msk
7415 #define GPIO_AFRL_AFSEL6_Pos            (24U)
7416 #define GPIO_AFRL_AFSEL6_Msk            (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
7417 #define GPIO_AFRL_AFSEL6                GPIO_AFRL_AFSEL6_Msk
7418 #define GPIO_AFRL_AFSEL7_Pos            (28U)
7419 #define GPIO_AFRL_AFSEL7_Msk            (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
7420 #define GPIO_AFRL_AFSEL7                GPIO_AFRL_AFSEL7_Msk
7421 
7422 /* Legacy aliases */
7423 #define GPIO_AFRL_AFRL0_Pos             GPIO_AFRL_AFSEL0_Pos
7424 #define GPIO_AFRL_AFRL0_Msk             GPIO_AFRL_AFSEL0_Msk
7425 #define GPIO_AFRL_AFRL0                 GPIO_AFRL_AFSEL0
7426 #define GPIO_AFRL_AFRL1_Pos             GPIO_AFRL_AFSEL1_Pos
7427 #define GPIO_AFRL_AFRL1_Msk             GPIO_AFRL_AFSEL1_Msk
7428 #define GPIO_AFRL_AFRL1                 GPIO_AFRL_AFSEL1
7429 #define GPIO_AFRL_AFRL2_Pos             GPIO_AFRL_AFSEL2_Pos
7430 #define GPIO_AFRL_AFRL2_Msk             GPIO_AFRL_AFSEL2_Msk
7431 #define GPIO_AFRL_AFRL2                 GPIO_AFRL_AFSEL2
7432 #define GPIO_AFRL_AFRL3_Pos             GPIO_AFRL_AFSEL3_Pos
7433 #define GPIO_AFRL_AFRL3_Msk             GPIO_AFRL_AFSEL3_Msk
7434 #define GPIO_AFRL_AFRL3                 GPIO_AFRL_AFSEL3
7435 #define GPIO_AFRL_AFRL4_Pos             GPIO_AFRL_AFSEL4_Pos
7436 #define GPIO_AFRL_AFRL4_Msk             GPIO_AFRL_AFSEL4_Msk
7437 #define GPIO_AFRL_AFRL4                 GPIO_AFRL_AFSEL4
7438 #define GPIO_AFRL_AFRL5_Pos             GPIO_AFRL_AFSEL5_Pos
7439 #define GPIO_AFRL_AFRL5_Msk             GPIO_AFRL_AFSEL5_Msk
7440 #define GPIO_AFRL_AFRL5                 GPIO_AFRL_AFSEL5
7441 #define GPIO_AFRL_AFRL6_Pos             GPIO_AFRL_AFSEL6_Pos
7442 #define GPIO_AFRL_AFRL6_Msk             GPIO_AFRL_AFSEL6_Msk
7443 #define GPIO_AFRL_AFRL6                 GPIO_AFRL_AFSEL6
7444 #define GPIO_AFRL_AFRL7_Pos             GPIO_AFRL_AFSEL7_Pos
7445 #define GPIO_AFRL_AFRL7_Msk             GPIO_AFRL_AFSEL7_Msk
7446 #define GPIO_AFRL_AFRL7                 GPIO_AFRL_AFSEL7
7447 
7448 /****************** Bit definition for GPIO_AFRH register  ********************/
7449 #define GPIO_AFRH_AFSEL8_Pos            (0U)
7450 #define GPIO_AFRH_AFSEL8_Msk            (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
7451 #define GPIO_AFRH_AFSEL8                GPIO_AFRH_AFSEL8_Msk
7452 #define GPIO_AFRH_AFSEL9_Pos            (4U)
7453 #define GPIO_AFRH_AFSEL9_Msk            (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
7454 #define GPIO_AFRH_AFSEL9                GPIO_AFRH_AFSEL9_Msk
7455 #define GPIO_AFRH_AFSEL10_Pos           (8U)
7456 #define GPIO_AFRH_AFSEL10_Msk           (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
7457 #define GPIO_AFRH_AFSEL10               GPIO_AFRH_AFSEL10_Msk
7458 #define GPIO_AFRH_AFSEL11_Pos           (12U)
7459 #define GPIO_AFRH_AFSEL11_Msk           (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
7460 #define GPIO_AFRH_AFSEL11               GPIO_AFRH_AFSEL11_Msk
7461 #define GPIO_AFRH_AFSEL12_Pos           (16U)
7462 #define GPIO_AFRH_AFSEL12_Msk           (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
7463 #define GPIO_AFRH_AFSEL12               GPIO_AFRH_AFSEL12_Msk
7464 #define GPIO_AFRH_AFSEL13_Pos           (20U)
7465 #define GPIO_AFRH_AFSEL13_Msk           (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
7466 #define GPIO_AFRH_AFSEL13               GPIO_AFRH_AFSEL13_Msk
7467 #define GPIO_AFRH_AFSEL14_Pos           (24U)
7468 #define GPIO_AFRH_AFSEL14_Msk           (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
7469 #define GPIO_AFRH_AFSEL14               GPIO_AFRH_AFSEL14_Msk
7470 #define GPIO_AFRH_AFSEL15_Pos           (28U)
7471 #define GPIO_AFRH_AFSEL15_Msk           (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
7472 #define GPIO_AFRH_AFSEL15               GPIO_AFRH_AFSEL15_Msk
7473 
7474 /* Legacy aliases */
7475 #define GPIO_AFRH_AFRH0_Pos             GPIO_AFRH_AFSEL8_Pos
7476 #define GPIO_AFRH_AFRH0_Msk             GPIO_AFRH_AFSEL8_Msk
7477 #define GPIO_AFRH_AFRH0                 GPIO_AFRH_AFSEL8
7478 #define GPIO_AFRH_AFRH1_Pos             GPIO_AFRH_AFSEL9_Pos
7479 #define GPIO_AFRH_AFRH1_Msk             GPIO_AFRH_AFSEL9_Msk
7480 #define GPIO_AFRH_AFRH1                 GPIO_AFRH_AFSEL9
7481 #define GPIO_AFRH_AFRH2_Pos             GPIO_AFRH_AFSEL10_Pos
7482 #define GPIO_AFRH_AFRH2_Msk             GPIO_AFRH_AFSEL10_Msk
7483 #define GPIO_AFRH_AFRH2                 GPIO_AFRH_AFSEL10
7484 #define GPIO_AFRH_AFRH3_Pos             GPIO_AFRH_AFSEL11_Pos
7485 #define GPIO_AFRH_AFRH3_Msk             GPIO_AFRH_AFSEL11_Msk
7486 #define GPIO_AFRH_AFRH3                 GPIO_AFRH_AFSEL11
7487 #define GPIO_AFRH_AFRH4_Pos             GPIO_AFRH_AFSEL12_Pos
7488 #define GPIO_AFRH_AFRH4_Msk             GPIO_AFRH_AFSEL12_Msk
7489 #define GPIO_AFRH_AFRH4                 GPIO_AFRH_AFSEL12
7490 #define GPIO_AFRH_AFRH5_Pos             GPIO_AFRH_AFSEL13_Pos
7491 #define GPIO_AFRH_AFRH5_Msk             GPIO_AFRH_AFSEL13_Msk
7492 #define GPIO_AFRH_AFRH5                 GPIO_AFRH_AFSEL13
7493 #define GPIO_AFRH_AFRH6_Pos             GPIO_AFRH_AFSEL14_Pos
7494 #define GPIO_AFRH_AFRH6_Msk             GPIO_AFRH_AFSEL14_Msk
7495 #define GPIO_AFRH_AFRH6                 GPIO_AFRH_AFSEL14
7496 #define GPIO_AFRH_AFRH7_Pos             GPIO_AFRH_AFSEL15_Pos
7497 #define GPIO_AFRH_AFRH7_Msk             GPIO_AFRH_AFSEL15_Msk
7498 #define GPIO_AFRH_AFRH7                 GPIO_AFRH_AFSEL15
7499 
7500 /****************** Bit definition for GPIO_BRR register  *********************/
7501 #define GPIO_BRR_BR_0                   (0x00000001U)
7502 #define GPIO_BRR_BR_1                   (0x00000002U)
7503 #define GPIO_BRR_BR_2                   (0x00000004U)
7504 #define GPIO_BRR_BR_3                   (0x00000008U)
7505 #define GPIO_BRR_BR_4                   (0x00000010U)
7506 #define GPIO_BRR_BR_5                   (0x00000020U)
7507 #define GPIO_BRR_BR_6                   (0x00000040U)
7508 #define GPIO_BRR_BR_7                   (0x00000080U)
7509 #define GPIO_BRR_BR_8                   (0x00000100U)
7510 #define GPIO_BRR_BR_9                   (0x00000200U)
7511 #define GPIO_BRR_BR_10                  (0x00000400U)
7512 #define GPIO_BRR_BR_11                  (0x00000800U)
7513 #define GPIO_BRR_BR_12                  (0x00001000U)
7514 #define GPIO_BRR_BR_13                  (0x00002000U)
7515 #define GPIO_BRR_BR_14                  (0x00004000U)
7516 #define GPIO_BRR_BR_15                  (0x00008000U)
7517 
7518 /******************************************************************************/
7519 /*                                                                            */
7520 /*                   Inter-integrated Circuit Interface (I2C)                 */
7521 /*                                                                            */
7522 /******************************************************************************/
7523 
7524 /*******************  Bit definition for I2C_CR1 register  *******************/
7525 #define I2C_CR1_PE_Pos               (0U)
7526 #define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
7527 #define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
7528 #define I2C_CR1_TXIE_Pos             (1U)
7529 #define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
7530 #define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
7531 #define I2C_CR1_RXIE_Pos             (2U)
7532 #define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
7533 #define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
7534 #define I2C_CR1_ADDRIE_Pos           (3U)
7535 #define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
7536 #define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
7537 #define I2C_CR1_NACKIE_Pos           (4U)
7538 #define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
7539 #define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
7540 #define I2C_CR1_STOPIE_Pos           (5U)
7541 #define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
7542 #define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
7543 #define I2C_CR1_TCIE_Pos             (6U)
7544 #define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
7545 #define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
7546 #define I2C_CR1_ERRIE_Pos            (7U)
7547 #define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
7548 #define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
7549 #define I2C_CR1_DNF_Pos              (8U)
7550 #define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
7551 #define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
7552 #define I2C_CR1_ANFOFF_Pos           (12U)
7553 #define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
7554 #define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
7555 #define I2C_CR1_SWRST_Pos            (13U)
7556 #define I2C_CR1_SWRST_Msk            (0x1UL << I2C_CR1_SWRST_Pos)               /*!< 0x00002000 */
7557 #define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset */
7558 #define I2C_CR1_TXDMAEN_Pos          (14U)
7559 #define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
7560 #define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
7561 #define I2C_CR1_RXDMAEN_Pos          (15U)
7562 #define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
7563 #define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
7564 #define I2C_CR1_SBC_Pos              (16U)
7565 #define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
7566 #define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
7567 #define I2C_CR1_NOSTRETCH_Pos        (17U)
7568 #define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
7569 #define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
7570 #define I2C_CR1_WUPEN_Pos            (18U)
7571 #define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
7572 #define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
7573 #define I2C_CR1_GCEN_Pos             (19U)
7574 #define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
7575 #define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
7576 #define I2C_CR1_SMBHEN_Pos           (20U)
7577 #define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
7578 #define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
7579 #define I2C_CR1_SMBDEN_Pos           (21U)
7580 #define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
7581 #define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
7582 #define I2C_CR1_ALERTEN_Pos          (22U)
7583 #define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
7584 #define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
7585 #define I2C_CR1_PECEN_Pos            (23U)
7586 #define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
7587 #define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
7588 
7589 /******************  Bit definition for I2C_CR2 register  ********************/
7590 #define I2C_CR2_SADD_Pos             (0U)
7591 #define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
7592 #define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
7593 #define I2C_CR2_RD_WRN_Pos           (10U)
7594 #define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
7595 #define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
7596 #define I2C_CR2_ADD10_Pos            (11U)
7597 #define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
7598 #define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
7599 #define I2C_CR2_HEAD10R_Pos          (12U)
7600 #define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
7601 #define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
7602 #define I2C_CR2_START_Pos            (13U)
7603 #define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)               /*!< 0x00002000 */
7604 #define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
7605 #define I2C_CR2_STOP_Pos             (14U)
7606 #define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
7607 #define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
7608 #define I2C_CR2_NACK_Pos             (15U)
7609 #define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
7610 #define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
7611 #define I2C_CR2_NBYTES_Pos           (16U)
7612 #define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
7613 #define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
7614 #define I2C_CR2_RELOAD_Pos           (24U)
7615 #define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
7616 #define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
7617 #define I2C_CR2_AUTOEND_Pos          (25U)
7618 #define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
7619 #define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
7620 #define I2C_CR2_PECBYTE_Pos          (26U)
7621 #define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
7622 #define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
7623 
7624 /*******************  Bit definition for I2C_OAR1 register  ******************/
7625 #define I2C_OAR1_OA1_Pos             (0U)
7626 #define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
7627 #define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
7628 #define I2C_OAR1_OA1MODE_Pos         (10U)
7629 #define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
7630 #define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
7631 #define I2C_OAR1_OA1EN_Pos           (15U)
7632 #define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
7633 #define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
7634 
7635 /*******************  Bit definition for I2C_OAR2 register  ******************/
7636 #define I2C_OAR2_OA2_Pos             (1U)
7637 #define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
7638 #define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */
7639 #define I2C_OAR2_OA2MSK_Pos          (8U)
7640 #define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
7641 #define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */
7642 #define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
7643 #define I2C_OAR2_OA2MASK01_Pos       (8U)
7644 #define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
7645 #define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
7646 #define I2C_OAR2_OA2MASK02_Pos       (9U)
7647 #define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
7648 #define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
7649 #define I2C_OAR2_OA2MASK03_Pos       (8U)
7650 #define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
7651 #define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
7652 #define I2C_OAR2_OA2MASK04_Pos       (10U)
7653 #define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
7654 #define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
7655 #define I2C_OAR2_OA2MASK05_Pos       (8U)
7656 #define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
7657 #define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
7658 #define I2C_OAR2_OA2MASK06_Pos       (9U)
7659 #define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
7660 #define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
7661 #define I2C_OAR2_OA2MASK07_Pos       (8U)
7662 #define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
7663 #define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
7664 #define I2C_OAR2_OA2EN_Pos           (15U)
7665 #define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
7666 #define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */
7667 
7668 /*******************  Bit definition for I2C_TIMINGR register ****************/
7669 #define I2C_TIMINGR_SCLL_Pos         (0U)
7670 #define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
7671 #define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
7672 #define I2C_TIMINGR_SCLH_Pos         (8U)
7673 #define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
7674 #define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
7675 #define I2C_TIMINGR_SDADEL_Pos       (16U)
7676 #define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
7677 #define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
7678 #define I2C_TIMINGR_SCLDEL_Pos       (20U)
7679 #define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
7680 #define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
7681 #define I2C_TIMINGR_PRESC_Pos        (28U)
7682 #define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
7683 #define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
7684 
7685 /******************* Bit definition for I2C_TIMEOUTR register ****************/
7686 #define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
7687 #define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
7688 #define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
7689 #define I2C_TIMEOUTR_TIDLE_Pos       (12U)
7690 #define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
7691 #define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
7692 #define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
7693 #define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
7694 #define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
7695 #define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
7696 #define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
7697 #define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
7698 #define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
7699 #define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
7700 #define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
7701 
7702 /******************  Bit definition for I2C_ISR register  ********************/
7703 #define I2C_ISR_TXE_Pos              (0U)
7704 #define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
7705 #define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
7706 #define I2C_ISR_TXIS_Pos             (1U)
7707 #define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
7708 #define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
7709 #define I2C_ISR_RXNE_Pos             (2U)
7710 #define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
7711 #define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
7712 #define I2C_ISR_ADDR_Pos             (3U)
7713 #define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
7714 #define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
7715 #define I2C_ISR_NACKF_Pos            (4U)
7716 #define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
7717 #define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
7718 #define I2C_ISR_STOPF_Pos            (5U)
7719 #define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
7720 #define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
7721 #define I2C_ISR_TC_Pos               (6U)
7722 #define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
7723 #define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
7724 #define I2C_ISR_TCR_Pos              (7U)
7725 #define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
7726 #define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
7727 #define I2C_ISR_BERR_Pos             (8U)
7728 #define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
7729 #define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
7730 #define I2C_ISR_ARLO_Pos             (9U)
7731 #define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
7732 #define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
7733 #define I2C_ISR_OVR_Pos              (10U)
7734 #define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
7735 #define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
7736 #define I2C_ISR_PECERR_Pos           (11U)
7737 #define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
7738 #define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
7739 #define I2C_ISR_TIMEOUT_Pos          (12U)
7740 #define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
7741 #define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
7742 #define I2C_ISR_ALERT_Pos            (13U)
7743 #define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
7744 #define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
7745 #define I2C_ISR_BUSY_Pos             (15U)
7746 #define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
7747 #define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
7748 #define I2C_ISR_DIR_Pos              (16U)
7749 #define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
7750 #define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
7751 #define I2C_ISR_ADDCODE_Pos          (17U)
7752 #define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
7753 #define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
7754 
7755 /******************  Bit definition for I2C_ICR register  ********************/
7756 #define I2C_ICR_ADDRCF_Pos           (3U)
7757 #define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
7758 #define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
7759 #define I2C_ICR_NACKCF_Pos           (4U)
7760 #define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
7761 #define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
7762 #define I2C_ICR_STOPCF_Pos           (5U)
7763 #define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
7764 #define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
7765 #define I2C_ICR_BERRCF_Pos           (8U)
7766 #define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
7767 #define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
7768 #define I2C_ICR_ARLOCF_Pos           (9U)
7769 #define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
7770 #define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
7771 #define I2C_ICR_OVRCF_Pos            (10U)
7772 #define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
7773 #define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
7774 #define I2C_ICR_PECCF_Pos            (11U)
7775 #define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
7776 #define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
7777 #define I2C_ICR_TIMOUTCF_Pos         (12U)
7778 #define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
7779 #define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
7780 #define I2C_ICR_ALERTCF_Pos          (13U)
7781 #define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
7782 #define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
7783 
7784 /******************  Bit definition for I2C_PECR register  *******************/
7785 #define I2C_PECR_PEC_Pos             (0U)
7786 #define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
7787 #define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
7788 
7789 /******************  Bit definition for I2C_RXDR register  *********************/
7790 #define I2C_RXDR_RXDATA_Pos          (0U)
7791 #define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
7792 #define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
7793 
7794 /******************  Bit definition for I2C_TXDR register  *******************/
7795 #define I2C_TXDR_TXDATA_Pos          (0U)
7796 #define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
7797 #define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
7798 
7799 /*****************************************************************************/
7800 /*                                                                           */
7801 /*                        Independent WATCHDOG (IWDG)                        */
7802 /*                                                                           */
7803 /*****************************************************************************/
7804 /*******************  Bit definition for IWDG_KR register  *******************/
7805 #define IWDG_KR_KEY_Pos      (0U)
7806 #define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
7807 #define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
7808 
7809 /*******************  Bit definition for IWDG_PR register  *******************/
7810 #define IWDG_PR_PR_Pos       (0U)
7811 #define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
7812 #define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
7813 #define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x01 */
7814 #define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x02 */
7815 #define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x04 */
7816 
7817 /*******************  Bit definition for IWDG_RLR register  ******************/
7818 #define IWDG_RLR_RL_Pos      (0U)
7819 #define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
7820 #define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
7821 
7822 /*******************  Bit definition for IWDG_SR register  *******************/
7823 #define IWDG_SR_PVU_Pos      (0U)
7824 #define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
7825 #define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
7826 #define IWDG_SR_RVU_Pos      (1U)
7827 #define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
7828 #define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
7829 #define IWDG_SR_WVU_Pos      (2U)
7830 #define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
7831 #define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
7832 
7833 /*******************  Bit definition for IWDG_KR register  *******************/
7834 #define IWDG_WINR_WIN_Pos    (0U)
7835 #define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
7836 #define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
7837 
7838 /*****************************************************************************/
7839 /*                                                                           */
7840 /*                          Power Control (PWR)                              */
7841 /*                                                                           */
7842 /*****************************************************************************/
7843 
7844 #define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
7845 
7846 
7847 /********************  Bit definition for PWR_CR register  *******************/
7848 #define PWR_CR_LPDS_Pos            (0U)
7849 #define PWR_CR_LPDS_Msk            (0x1UL << PWR_CR_LPDS_Pos)                   /*!< 0x00000001 */
7850 #define PWR_CR_LPDS                PWR_CR_LPDS_Msk                             /*!< Low-power Deepsleep */
7851 #define PWR_CR_PDDS_Pos            (1U)
7852 #define PWR_CR_PDDS_Msk            (0x1UL << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
7853 #define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
7854 #define PWR_CR_CWUF_Pos            (2U)
7855 #define PWR_CR_CWUF_Msk            (0x1UL << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
7856 #define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
7857 #define PWR_CR_CSBF_Pos            (3U)
7858 #define PWR_CR_CSBF_Msk            (0x1UL << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
7859 #define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
7860 #define PWR_CR_PVDE_Pos            (4U)
7861 #define PWR_CR_PVDE_Msk            (0x1UL << PWR_CR_PVDE_Pos)                   /*!< 0x00000010 */
7862 #define PWR_CR_PVDE                PWR_CR_PVDE_Msk                             /*!< Power Voltage Detector Enable */
7863 
7864 #define PWR_CR_PLS_Pos             (5U)
7865 #define PWR_CR_PLS_Msk             (0x7UL << PWR_CR_PLS_Pos)                    /*!< 0x000000E0 */
7866 #define PWR_CR_PLS                 PWR_CR_PLS_Msk                              /*!< PLS[2:0] bits (PVD Level Selection) */
7867 #define PWR_CR_PLS_0               (0x1UL << PWR_CR_PLS_Pos)                    /*!< 0x00000020 */
7868 #define PWR_CR_PLS_1               (0x2UL << PWR_CR_PLS_Pos)                    /*!< 0x00000040 */
7869 #define PWR_CR_PLS_2               (0x4UL << PWR_CR_PLS_Pos)                    /*!< 0x00000080 */
7870 
7871 /*!< PVD level configuration */
7872 #define PWR_CR_PLS_LEV0            (0x00000000U)                               /*!< PVD level 0 */
7873 #define PWR_CR_PLS_LEV1            (0x00000020U)                               /*!< PVD level 1 */
7874 #define PWR_CR_PLS_LEV2            (0x00000040U)                               /*!< PVD level 2 */
7875 #define PWR_CR_PLS_LEV3            (0x00000060U)                               /*!< PVD level 3 */
7876 #define PWR_CR_PLS_LEV4            (0x00000080U)                               /*!< PVD level 4 */
7877 #define PWR_CR_PLS_LEV5            (0x000000A0U)                               /*!< PVD level 5 */
7878 #define PWR_CR_PLS_LEV6            (0x000000C0U)                               /*!< PVD level 6 */
7879 #define PWR_CR_PLS_LEV7            (0x000000E0U)                               /*!< PVD level 7 */
7880 
7881 #define PWR_CR_DBP_Pos             (8U)
7882 #define PWR_CR_DBP_Msk             (0x1UL << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
7883 #define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
7884 
7885 /*******************  Bit definition for PWR_CSR register  *******************/
7886 #define PWR_CSR_WUF_Pos            (0U)
7887 #define PWR_CSR_WUF_Msk            (0x1UL << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
7888 #define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
7889 #define PWR_CSR_SBF_Pos            (1U)
7890 #define PWR_CSR_SBF_Msk            (0x1UL << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
7891 #define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
7892 #define PWR_CSR_PVDO_Pos           (2U)
7893 #define PWR_CSR_PVDO_Msk           (0x1UL << PWR_CSR_PVDO_Pos)                  /*!< 0x00000004 */
7894 #define PWR_CSR_PVDO               PWR_CSR_PVDO_Msk                            /*!< PVD Output */
7895 #define PWR_CSR_VREFINTRDYF_Pos    (3U)
7896 #define PWR_CSR_VREFINTRDYF_Msk    (0x1UL << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
7897 #define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
7898 
7899 #define PWR_CSR_EWUP1_Pos          (8U)
7900 #define PWR_CSR_EWUP1_Msk          (0x1UL << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
7901 #define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
7902 #define PWR_CSR_EWUP2_Pos          (9U)
7903 #define PWR_CSR_EWUP2_Msk          (0x1UL << PWR_CSR_EWUP2_Pos)                 /*!< 0x00000200 */
7904 #define PWR_CSR_EWUP2              PWR_CSR_EWUP2_Msk                           /*!< Enable WKUP pin 2 */
7905 #define PWR_CSR_EWUP3_Pos          (10U)
7906 #define PWR_CSR_EWUP3_Msk          (0x1UL << PWR_CSR_EWUP3_Pos)                 /*!< 0x00000400 */
7907 #define PWR_CSR_EWUP3              PWR_CSR_EWUP3_Msk                           /*!< Enable WKUP pin 3 */
7908 #define PWR_CSR_EWUP4_Pos          (11U)
7909 #define PWR_CSR_EWUP4_Msk          (0x1UL << PWR_CSR_EWUP4_Pos)                 /*!< 0x00000800 */
7910 #define PWR_CSR_EWUP4              PWR_CSR_EWUP4_Msk                           /*!< Enable WKUP pin 4 */
7911 #define PWR_CSR_EWUP5_Pos          (12U)
7912 #define PWR_CSR_EWUP5_Msk          (0x1UL << PWR_CSR_EWUP5_Pos)                 /*!< 0x00001000 */
7913 #define PWR_CSR_EWUP5              PWR_CSR_EWUP5_Msk                           /*!< Enable WKUP pin 5 */
7914 #define PWR_CSR_EWUP6_Pos          (13U)
7915 #define PWR_CSR_EWUP6_Msk          (0x1UL << PWR_CSR_EWUP6_Pos)                 /*!< 0x00002000 */
7916 #define PWR_CSR_EWUP6              PWR_CSR_EWUP6_Msk                           /*!< Enable WKUP pin 6 */
7917 #define PWR_CSR_EWUP7_Pos          (14U)
7918 #define PWR_CSR_EWUP7_Msk          (0x1UL << PWR_CSR_EWUP7_Pos)                 /*!< 0x00004000 */
7919 #define PWR_CSR_EWUP7              PWR_CSR_EWUP7_Msk                           /*!< Enable WKUP pin 7 */
7920 #define PWR_CSR_EWUP8_Pos          (15U)
7921 #define PWR_CSR_EWUP8_Msk          (0x1UL << PWR_CSR_EWUP8_Pos)                 /*!< 0x00008000 */
7922 #define PWR_CSR_EWUP8              PWR_CSR_EWUP8_Msk                           /*!< Enable WKUP pin 8 */
7923 
7924 /*****************************************************************************/
7925 /*                                                                           */
7926 /*                         Reset and Clock Control                           */
7927 /*                                                                           */
7928 /*****************************************************************************/
7929 /*
7930 * @brief Specific device feature definitions  (not present on all devices in the STM32F0 series)
7931 */
7932 #define RCC_HSI48_SUPPORT           /*!< HSI48 feature support */
7933 #define RCC_PLLSRC_PREDIV1_SUPPORT  /*!< PREDIV support used as PLL source input  */
7934 
7935 /********************  Bit definition for RCC_CR register  *******************/
7936 #define RCC_CR_HSION_Pos                         (0U)
7937 #define RCC_CR_HSION_Msk                         (0x1UL << RCC_CR_HSION_Pos)    /*!< 0x00000001 */
7938 #define RCC_CR_HSION                             RCC_CR_HSION_Msk              /*!< Internal High Speed clock enable */
7939 #define RCC_CR_HSIRDY_Pos                        (1U)
7940 #define RCC_CR_HSIRDY_Msk                        (0x1UL << RCC_CR_HSIRDY_Pos)   /*!< 0x00000002 */
7941 #define RCC_CR_HSIRDY                            RCC_CR_HSIRDY_Msk             /*!< Internal High Speed clock ready flag */
7942 
7943 #define RCC_CR_HSITRIM_Pos                       (3U)
7944 #define RCC_CR_HSITRIM_Msk                       (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
7945 #define RCC_CR_HSITRIM                           RCC_CR_HSITRIM_Msk            /*!< Internal High Speed clock trimming */
7946 #define RCC_CR_HSITRIM_0                         (0x01UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
7947 #define RCC_CR_HSITRIM_1                         (0x02UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
7948 #define RCC_CR_HSITRIM_2                         (0x04UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
7949 #define RCC_CR_HSITRIM_3                         (0x08UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
7950 #define RCC_CR_HSITRIM_4                         (0x10UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
7951 
7952 #define RCC_CR_HSICAL_Pos                        (8U)
7953 #define RCC_CR_HSICAL_Msk                        (0xFFUL << RCC_CR_HSICAL_Pos)  /*!< 0x0000FF00 */
7954 #define RCC_CR_HSICAL                            RCC_CR_HSICAL_Msk             /*!< Internal High Speed clock Calibration */
7955 #define RCC_CR_HSICAL_0                          (0x01UL << RCC_CR_HSICAL_Pos)  /*!< 0x00000100 */
7956 #define RCC_CR_HSICAL_1                          (0x02UL << RCC_CR_HSICAL_Pos)  /*!< 0x00000200 */
7957 #define RCC_CR_HSICAL_2                          (0x04UL << RCC_CR_HSICAL_Pos)  /*!< 0x00000400 */
7958 #define RCC_CR_HSICAL_3                          (0x08UL << RCC_CR_HSICAL_Pos)  /*!< 0x00000800 */
7959 #define RCC_CR_HSICAL_4                          (0x10UL << RCC_CR_HSICAL_Pos)  /*!< 0x00001000 */
7960 #define RCC_CR_HSICAL_5                          (0x20UL << RCC_CR_HSICAL_Pos)  /*!< 0x00002000 */
7961 #define RCC_CR_HSICAL_6                          (0x40UL << RCC_CR_HSICAL_Pos)  /*!< 0x00004000 */
7962 #define RCC_CR_HSICAL_7                          (0x80UL << RCC_CR_HSICAL_Pos)  /*!< 0x00008000 */
7963 
7964 #define RCC_CR_HSEON_Pos                         (16U)
7965 #define RCC_CR_HSEON_Msk                         (0x1UL << RCC_CR_HSEON_Pos)    /*!< 0x00010000 */
7966 #define RCC_CR_HSEON                             RCC_CR_HSEON_Msk              /*!< External High Speed clock enable */
7967 #define RCC_CR_HSERDY_Pos                        (17U)
7968 #define RCC_CR_HSERDY_Msk                        (0x1UL << RCC_CR_HSERDY_Pos)   /*!< 0x00020000 */
7969 #define RCC_CR_HSERDY                            RCC_CR_HSERDY_Msk             /*!< External High Speed clock ready flag */
7970 #define RCC_CR_HSEBYP_Pos                        (18U)
7971 #define RCC_CR_HSEBYP_Msk                        (0x1UL << RCC_CR_HSEBYP_Pos)   /*!< 0x00040000 */
7972 #define RCC_CR_HSEBYP                            RCC_CR_HSEBYP_Msk             /*!< External High Speed clock Bypass */
7973 #define RCC_CR_CSSON_Pos                         (19U)
7974 #define RCC_CR_CSSON_Msk                         (0x1UL << RCC_CR_CSSON_Pos)    /*!< 0x00080000 */
7975 #define RCC_CR_CSSON                             RCC_CR_CSSON_Msk              /*!< Clock Security System enable */
7976 #define RCC_CR_PLLON_Pos                         (24U)
7977 #define RCC_CR_PLLON_Msk                         (0x1UL << RCC_CR_PLLON_Pos)    /*!< 0x01000000 */
7978 #define RCC_CR_PLLON                             RCC_CR_PLLON_Msk              /*!< PLL enable */
7979 #define RCC_CR_PLLRDY_Pos                        (25U)
7980 #define RCC_CR_PLLRDY_Msk                        (0x1UL << RCC_CR_PLLRDY_Pos)   /*!< 0x02000000 */
7981 #define RCC_CR_PLLRDY                            RCC_CR_PLLRDY_Msk             /*!< PLL clock ready flag */
7982 
7983 /********************  Bit definition for RCC_CFGR register  *****************/
7984 /*!< SW configuration */
7985 #define RCC_CFGR_SW_Pos                          (0U)
7986 #define RCC_CFGR_SW_Msk                          (0x3UL << RCC_CFGR_SW_Pos)     /*!< 0x00000003 */
7987 #define RCC_CFGR_SW                              RCC_CFGR_SW_Msk               /*!< SW[1:0] bits (System clock Switch) */
7988 #define RCC_CFGR_SW_0                            (0x1UL << RCC_CFGR_SW_Pos)     /*!< 0x00000001 */
7989 #define RCC_CFGR_SW_1                            (0x2UL << RCC_CFGR_SW_Pos)     /*!< 0x00000002 */
7990 
7991 #define RCC_CFGR_SW_HSI                          (0x00000000U)                 /*!< HSI selected as system clock */
7992 #define RCC_CFGR_SW_HSE                          (0x00000001U)                 /*!< HSE selected as system clock */
7993 #define RCC_CFGR_SW_PLL                          (0x00000002U)                 /*!< PLL selected as system clock */
7994 #define RCC_CFGR_SW_HSI48                        (0x00000003U)                 /*!< HSI48 selected as system clock */
7995 
7996 /*!< SWS configuration */
7997 #define RCC_CFGR_SWS_Pos                         (2U)
7998 #define RCC_CFGR_SWS_Msk                         (0x3UL << RCC_CFGR_SWS_Pos)    /*!< 0x0000000C */
7999 #define RCC_CFGR_SWS                             RCC_CFGR_SWS_Msk              /*!< SWS[1:0] bits (System Clock Switch Status) */
8000 #define RCC_CFGR_SWS_0                           (0x1UL << RCC_CFGR_SWS_Pos)    /*!< 0x00000004 */
8001 #define RCC_CFGR_SWS_1                           (0x2UL << RCC_CFGR_SWS_Pos)    /*!< 0x00000008 */
8002 
8003 #define RCC_CFGR_SWS_HSI                         (0x00000000U)                 /*!< HSI oscillator used as system clock */
8004 #define RCC_CFGR_SWS_HSE                         (0x00000004U)                 /*!< HSE oscillator used as system clock */
8005 #define RCC_CFGR_SWS_PLL                         (0x00000008U)                 /*!< PLL used as system clock */
8006 #define RCC_CFGR_SWS_HSI48                       (0x0000000CU)                 /*!< HSI48 oscillator used as system clock */
8007 
8008 /*!< HPRE configuration */
8009 #define RCC_CFGR_HPRE_Pos                        (4U)
8010 #define RCC_CFGR_HPRE_Msk                        (0xFUL << RCC_CFGR_HPRE_Pos)   /*!< 0x000000F0 */
8011 #define RCC_CFGR_HPRE                            RCC_CFGR_HPRE_Msk             /*!< HPRE[3:0] bits (AHB prescaler) */
8012 #define RCC_CFGR_HPRE_0                          (0x1UL << RCC_CFGR_HPRE_Pos)   /*!< 0x00000010 */
8013 #define RCC_CFGR_HPRE_1                          (0x2UL << RCC_CFGR_HPRE_Pos)   /*!< 0x00000020 */
8014 #define RCC_CFGR_HPRE_2                          (0x4UL << RCC_CFGR_HPRE_Pos)   /*!< 0x00000040 */
8015 #define RCC_CFGR_HPRE_3                          (0x8UL << RCC_CFGR_HPRE_Pos)   /*!< 0x00000080 */
8016 
8017 #define RCC_CFGR_HPRE_DIV1                       (0x00000000U)                 /*!< SYSCLK not divided */
8018 #define RCC_CFGR_HPRE_DIV2                       (0x00000080U)                 /*!< SYSCLK divided by 2 */
8019 #define RCC_CFGR_HPRE_DIV4                       (0x00000090U)                 /*!< SYSCLK divided by 4 */
8020 #define RCC_CFGR_HPRE_DIV8                       (0x000000A0U)                 /*!< SYSCLK divided by 8 */
8021 #define RCC_CFGR_HPRE_DIV16                      (0x000000B0U)                 /*!< SYSCLK divided by 16 */
8022 #define RCC_CFGR_HPRE_DIV64                      (0x000000C0U)                 /*!< SYSCLK divided by 64 */
8023 #define RCC_CFGR_HPRE_DIV128                     (0x000000D0U)                 /*!< SYSCLK divided by 128 */
8024 #define RCC_CFGR_HPRE_DIV256                     (0x000000E0U)                 /*!< SYSCLK divided by 256 */
8025 #define RCC_CFGR_HPRE_DIV512                     (0x000000F0U)                 /*!< SYSCLK divided by 512 */
8026 
8027 /*!< PPRE configuration */
8028 #define RCC_CFGR_PPRE_Pos                        (8U)
8029 #define RCC_CFGR_PPRE_Msk                        (0x7UL << RCC_CFGR_PPRE_Pos)   /*!< 0x00000700 */
8030 #define RCC_CFGR_PPRE                            RCC_CFGR_PPRE_Msk             /*!< PRE[2:0] bits (APB prescaler) */
8031 #define RCC_CFGR_PPRE_0                          (0x1UL << RCC_CFGR_PPRE_Pos)   /*!< 0x00000100 */
8032 #define RCC_CFGR_PPRE_1                          (0x2UL << RCC_CFGR_PPRE_Pos)   /*!< 0x00000200 */
8033 #define RCC_CFGR_PPRE_2                          (0x4UL << RCC_CFGR_PPRE_Pos)   /*!< 0x00000400 */
8034 
8035 #define RCC_CFGR_PPRE_DIV1                       (0x00000000U)                 /*!< HCLK not divided */
8036 #define RCC_CFGR_PPRE_DIV2_Pos                   (10U)
8037 #define RCC_CFGR_PPRE_DIV2_Msk                   (0x1UL << RCC_CFGR_PPRE_DIV2_Pos) /*!< 0x00000400 */
8038 #define RCC_CFGR_PPRE_DIV2                       RCC_CFGR_PPRE_DIV2_Msk        /*!< HCLK divided by 2 */
8039 #define RCC_CFGR_PPRE_DIV4_Pos                   (8U)
8040 #define RCC_CFGR_PPRE_DIV4_Msk                   (0x5UL << RCC_CFGR_PPRE_DIV4_Pos) /*!< 0x00000500 */
8041 #define RCC_CFGR_PPRE_DIV4                       RCC_CFGR_PPRE_DIV4_Msk        /*!< HCLK divided by 4 */
8042 #define RCC_CFGR_PPRE_DIV8_Pos                   (9U)
8043 #define RCC_CFGR_PPRE_DIV8_Msk                   (0x3UL << RCC_CFGR_PPRE_DIV8_Pos) /*!< 0x00000600 */
8044 #define RCC_CFGR_PPRE_DIV8                       RCC_CFGR_PPRE_DIV8_Msk        /*!< HCLK divided by 8 */
8045 #define RCC_CFGR_PPRE_DIV16_Pos                  (8U)
8046 #define RCC_CFGR_PPRE_DIV16_Msk                  (0x7UL << RCC_CFGR_PPRE_DIV16_Pos) /*!< 0x00000700 */
8047 #define RCC_CFGR_PPRE_DIV16                      RCC_CFGR_PPRE_DIV16_Msk       /*!< HCLK divided by 16 */
8048 
8049 #define RCC_CFGR_PLLSRC_Pos                      (15U)
8050 #define RCC_CFGR_PLLSRC_Msk                      (0x3UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00018000 */
8051 #define RCC_CFGR_PLLSRC                          RCC_CFGR_PLLSRC_Msk           /*!< PLL entry clock source */
8052 #define RCC_CFGR_PLLSRC_HSI_DIV2                 (0x00000000U)                 /*!< HSI clock divided by 2 selected as PLL entry clock source */
8053 #define RCC_CFGR_PLLSRC_HSI_PREDIV               (0x00008000U)                 /*!< HSI/PREDIV clock selected as PLL entry clock source */
8054 #define RCC_CFGR_PLLSRC_HSE_PREDIV               (0x00010000U)                 /*!< HSE/PREDIV clock selected as PLL entry clock source */
8055 #define RCC_CFGR_PLLSRC_HSI48_PREDIV             (0x00018000U)                 /*!< HSI48/PREDIV clock selected as PLL entry clock source */
8056 
8057 #define RCC_CFGR_PLLXTPRE_Pos                    (17U)
8058 #define RCC_CFGR_PLLXTPRE_Msk                    (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
8059 #define RCC_CFGR_PLLXTPRE                        RCC_CFGR_PLLXTPRE_Msk         /*!< HSE divider for PLL entry */
8060 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1        (0x00000000U)                 /*!< HSE/PREDIV clock not divided for PLL entry */
8061 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2        (0x00020000U)                 /*!< HSE/PREDIV clock divided by 2 for PLL entry */
8062 
8063 /*!< PLLMUL configuration */
8064 #define RCC_CFGR_PLLMUL_Pos                      (18U)
8065 #define RCC_CFGR_PLLMUL_Msk                      (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
8066 #define RCC_CFGR_PLLMUL                          RCC_CFGR_PLLMUL_Msk           /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
8067 #define RCC_CFGR_PLLMUL_0                        (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
8068 #define RCC_CFGR_PLLMUL_1                        (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
8069 #define RCC_CFGR_PLLMUL_2                        (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
8070 #define RCC_CFGR_PLLMUL_3                        (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
8071 
8072 #define RCC_CFGR_PLLMUL2                         (0x00000000U)                 /*!< PLL input clock*2 */
8073 #define RCC_CFGR_PLLMUL3                         (0x00040000U)                 /*!< PLL input clock*3 */
8074 #define RCC_CFGR_PLLMUL4                         (0x00080000U)                 /*!< PLL input clock*4 */
8075 #define RCC_CFGR_PLLMUL5                         (0x000C0000U)                 /*!< PLL input clock*5 */
8076 #define RCC_CFGR_PLLMUL6                         (0x00100000U)                 /*!< PLL input clock*6 */
8077 #define RCC_CFGR_PLLMUL7                         (0x00140000U)                 /*!< PLL input clock*7 */
8078 #define RCC_CFGR_PLLMUL8                         (0x00180000U)                 /*!< PLL input clock*8 */
8079 #define RCC_CFGR_PLLMUL9                         (0x001C0000U)                 /*!< PLL input clock*9 */
8080 #define RCC_CFGR_PLLMUL10                        (0x00200000U)                 /*!< PLL input clock10 */
8081 #define RCC_CFGR_PLLMUL11                        (0x00240000U)                 /*!< PLL input clock*11 */
8082 #define RCC_CFGR_PLLMUL12                        (0x00280000U)                 /*!< PLL input clock*12 */
8083 #define RCC_CFGR_PLLMUL13                        (0x002C0000U)                 /*!< PLL input clock*13 */
8084 #define RCC_CFGR_PLLMUL14                        (0x00300000U)                 /*!< PLL input clock*14 */
8085 #define RCC_CFGR_PLLMUL15                        (0x00340000U)                 /*!< PLL input clock*15 */
8086 #define RCC_CFGR_PLLMUL16                        (0x00380000U)                 /*!< PLL input clock*16 */
8087 
8088 /*!< MCO configuration */
8089 #define RCC_CFGR_MCO_Pos                         (24U)
8090 #define RCC_CFGR_MCO_Msk                         (0xFUL << RCC_CFGR_MCO_Pos)    /*!< 0x0F000000 */
8091 #define RCC_CFGR_MCO                             RCC_CFGR_MCO_Msk              /*!< MCO[3:0] bits (Microcontroller Clock Output) */
8092 #define RCC_CFGR_MCO_0                           (0x1UL << RCC_CFGR_MCO_Pos)    /*!< 0x01000000 */
8093 #define RCC_CFGR_MCO_1                           (0x2UL << RCC_CFGR_MCO_Pos)    /*!< 0x02000000 */
8094 #define RCC_CFGR_MCO_2                           (0x4UL << RCC_CFGR_MCO_Pos)    /*!< 0x04000000 */
8095 #define RCC_CFGR_MCO_3                           (0x08000000U)                 /*!< Bit 3 */
8096 
8097 #define RCC_CFGR_MCO_NOCLOCK                     (0x00000000U)                 /*!< No clock */
8098 #define RCC_CFGR_MCO_HSI14                       (0x01000000U)                 /*!< HSI14 clock selected as MCO source */
8099 #define RCC_CFGR_MCO_LSI                         (0x02000000U)                 /*!< LSI clock selected as MCO source */
8100 #define RCC_CFGR_MCO_LSE                         (0x03000000U)                 /*!< LSE clock selected as MCO source */
8101 #define RCC_CFGR_MCO_SYSCLK                      (0x04000000U)                 /*!< System clock selected as MCO source */
8102 #define RCC_CFGR_MCO_HSI                         (0x05000000U)                 /*!< HSI clock selected as MCO source */
8103 #define RCC_CFGR_MCO_HSE                         (0x06000000U)                 /*!< HSE clock selected as MCO source  */
8104 #define RCC_CFGR_MCO_PLL                         (0x07000000U)                 /*!< PLL clock divided by 2 selected as MCO source */
8105 #define RCC_CFGR_MCO_HSI48                       (0x08000000U)                 /*!< HSI48 clock selected as MCO source */
8106 
8107 #define RCC_CFGR_MCOPRE_Pos                      (28U)
8108 #define RCC_CFGR_MCOPRE_Msk                      (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
8109 #define RCC_CFGR_MCOPRE                          RCC_CFGR_MCOPRE_Msk           /*!< MCO prescaler  */
8110 #define RCC_CFGR_MCOPRE_DIV1                     (0x00000000U)                 /*!< MCO is divided by 1  */
8111 #define RCC_CFGR_MCOPRE_DIV2                     (0x10000000U)                 /*!< MCO is divided by 2  */
8112 #define RCC_CFGR_MCOPRE_DIV4                     (0x20000000U)                 /*!< MCO is divided by 4  */
8113 #define RCC_CFGR_MCOPRE_DIV8                     (0x30000000U)                 /*!< MCO is divided by 8  */
8114 #define RCC_CFGR_MCOPRE_DIV16                    (0x40000000U)                 /*!< MCO is divided by 16  */
8115 #define RCC_CFGR_MCOPRE_DIV32                    (0x50000000U)                 /*!< MCO is divided by 32  */
8116 #define RCC_CFGR_MCOPRE_DIV64                    (0x60000000U)                 /*!< MCO is divided by 64  */
8117 #define RCC_CFGR_MCOPRE_DIV128                   (0x70000000U)                 /*!< MCO is divided by 128  */
8118 
8119 #define RCC_CFGR_PLLNODIV_Pos                    (31U)
8120 #define RCC_CFGR_PLLNODIV_Msk                    (0x1UL << RCC_CFGR_PLLNODIV_Pos) /*!< 0x80000000 */
8121 #define RCC_CFGR_PLLNODIV                        RCC_CFGR_PLLNODIV_Msk         /*!< PLL is not divided to MCO  */
8122 
8123 /* Reference defines */
8124 #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCO
8125 #define RCC_CFGR_MCOSEL_0                    RCC_CFGR_MCO_0
8126 #define RCC_CFGR_MCOSEL_1                    RCC_CFGR_MCO_1
8127 #define RCC_CFGR_MCOSEL_2                    RCC_CFGR_MCO_2
8128 #define RCC_CFGR_MCOSEL_3                    RCC_CFGR_MCO_3
8129 #define RCC_CFGR_MCOSEL_NOCLOCK              RCC_CFGR_MCO_NOCLOCK
8130 #define RCC_CFGR_MCOSEL_HSI14                RCC_CFGR_MCO_HSI14
8131 #define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCO_LSI
8132 #define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCO_LSE
8133 #define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCO_SYSCLK
8134 #define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCO_HSI
8135 #define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCO_HSE
8136 #define RCC_CFGR_MCOSEL_PLL_DIV2             RCC_CFGR_MCO_PLL
8137 #define RCC_CFGR_MCOSEL_HSI48                RCC_CFGR_MCO_HSI48
8138 
8139 /*!<******************  Bit definition for RCC_CIR register  *****************/
8140 #define RCC_CIR_LSIRDYF_Pos                      (0U)
8141 #define RCC_CIR_LSIRDYF_Msk                      (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
8142 #define RCC_CIR_LSIRDYF                          RCC_CIR_LSIRDYF_Msk           /*!< LSI Ready Interrupt flag */
8143 #define RCC_CIR_LSERDYF_Pos                      (1U)
8144 #define RCC_CIR_LSERDYF_Msk                      (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
8145 #define RCC_CIR_LSERDYF                          RCC_CIR_LSERDYF_Msk           /*!< LSE Ready Interrupt flag */
8146 #define RCC_CIR_HSIRDYF_Pos                      (2U)
8147 #define RCC_CIR_HSIRDYF_Msk                      (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
8148 #define RCC_CIR_HSIRDYF                          RCC_CIR_HSIRDYF_Msk           /*!< HSI Ready Interrupt flag */
8149 #define RCC_CIR_HSERDYF_Pos                      (3U)
8150 #define RCC_CIR_HSERDYF_Msk                      (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
8151 #define RCC_CIR_HSERDYF                          RCC_CIR_HSERDYF_Msk           /*!< HSE Ready Interrupt flag */
8152 #define RCC_CIR_PLLRDYF_Pos                      (4U)
8153 #define RCC_CIR_PLLRDYF_Msk                      (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
8154 #define RCC_CIR_PLLRDYF                          RCC_CIR_PLLRDYF_Msk           /*!< PLL Ready Interrupt flag */
8155 #define RCC_CIR_HSI14RDYF_Pos                    (5U)
8156 #define RCC_CIR_HSI14RDYF_Msk                    (0x1UL << RCC_CIR_HSI14RDYF_Pos) /*!< 0x00000020 */
8157 #define RCC_CIR_HSI14RDYF                        RCC_CIR_HSI14RDYF_Msk         /*!< HSI14 Ready Interrupt flag */
8158 #define RCC_CIR_HSI48RDYF_Pos                    (6U)
8159 #define RCC_CIR_HSI48RDYF_Msk                    (0x1UL << RCC_CIR_HSI48RDYF_Pos) /*!< 0x00000040 */
8160 #define RCC_CIR_HSI48RDYF                        RCC_CIR_HSI48RDYF_Msk         /*!< HSI48 Ready Interrupt flag */
8161 #define RCC_CIR_CSSF_Pos                         (7U)
8162 #define RCC_CIR_CSSF_Msk                         (0x1UL << RCC_CIR_CSSF_Pos)    /*!< 0x00000080 */
8163 #define RCC_CIR_CSSF                             RCC_CIR_CSSF_Msk              /*!< Clock Security System Interrupt flag */
8164 #define RCC_CIR_LSIRDYIE_Pos                     (8U)
8165 #define RCC_CIR_LSIRDYIE_Msk                     (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
8166 #define RCC_CIR_LSIRDYIE                         RCC_CIR_LSIRDYIE_Msk          /*!< LSI Ready Interrupt Enable */
8167 #define RCC_CIR_LSERDYIE_Pos                     (9U)
8168 #define RCC_CIR_LSERDYIE_Msk                     (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
8169 #define RCC_CIR_LSERDYIE                         RCC_CIR_LSERDYIE_Msk          /*!< LSE Ready Interrupt Enable */
8170 #define RCC_CIR_HSIRDYIE_Pos                     (10U)
8171 #define RCC_CIR_HSIRDYIE_Msk                     (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
8172 #define RCC_CIR_HSIRDYIE                         RCC_CIR_HSIRDYIE_Msk          /*!< HSI Ready Interrupt Enable */
8173 #define RCC_CIR_HSERDYIE_Pos                     (11U)
8174 #define RCC_CIR_HSERDYIE_Msk                     (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
8175 #define RCC_CIR_HSERDYIE                         RCC_CIR_HSERDYIE_Msk          /*!< HSE Ready Interrupt Enable */
8176 #define RCC_CIR_PLLRDYIE_Pos                     (12U)
8177 #define RCC_CIR_PLLRDYIE_Msk                     (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
8178 #define RCC_CIR_PLLRDYIE                         RCC_CIR_PLLRDYIE_Msk          /*!< PLL Ready Interrupt Enable */
8179 #define RCC_CIR_HSI14RDYIE_Pos                   (13U)
8180 #define RCC_CIR_HSI14RDYIE_Msk                   (0x1UL << RCC_CIR_HSI14RDYIE_Pos) /*!< 0x00002000 */
8181 #define RCC_CIR_HSI14RDYIE                       RCC_CIR_HSI14RDYIE_Msk        /*!< HSI14 Ready Interrupt Enable */
8182 #define RCC_CIR_HSI48RDYIE_Pos                   (14U)
8183 #define RCC_CIR_HSI48RDYIE_Msk                   (0x1UL << RCC_CIR_HSI48RDYIE_Pos) /*!< 0x00004000 */
8184 #define RCC_CIR_HSI48RDYIE                       RCC_CIR_HSI48RDYIE_Msk        /*!< HSI48 Ready Interrupt Enable */
8185 #define RCC_CIR_LSIRDYC_Pos                      (16U)
8186 #define RCC_CIR_LSIRDYC_Msk                      (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
8187 #define RCC_CIR_LSIRDYC                          RCC_CIR_LSIRDYC_Msk           /*!< LSI Ready Interrupt Clear */
8188 #define RCC_CIR_LSERDYC_Pos                      (17U)
8189 #define RCC_CIR_LSERDYC_Msk                      (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
8190 #define RCC_CIR_LSERDYC                          RCC_CIR_LSERDYC_Msk           /*!< LSE Ready Interrupt Clear */
8191 #define RCC_CIR_HSIRDYC_Pos                      (18U)
8192 #define RCC_CIR_HSIRDYC_Msk                      (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
8193 #define RCC_CIR_HSIRDYC                          RCC_CIR_HSIRDYC_Msk           /*!< HSI Ready Interrupt Clear */
8194 #define RCC_CIR_HSERDYC_Pos                      (19U)
8195 #define RCC_CIR_HSERDYC_Msk                      (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
8196 #define RCC_CIR_HSERDYC                          RCC_CIR_HSERDYC_Msk           /*!< HSE Ready Interrupt Clear */
8197 #define RCC_CIR_PLLRDYC_Pos                      (20U)
8198 #define RCC_CIR_PLLRDYC_Msk                      (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
8199 #define RCC_CIR_PLLRDYC                          RCC_CIR_PLLRDYC_Msk           /*!< PLL Ready Interrupt Clear */
8200 #define RCC_CIR_HSI14RDYC_Pos                    (21U)
8201 #define RCC_CIR_HSI14RDYC_Msk                    (0x1UL << RCC_CIR_HSI14RDYC_Pos) /*!< 0x00200000 */
8202 #define RCC_CIR_HSI14RDYC                        RCC_CIR_HSI14RDYC_Msk         /*!< HSI14 Ready Interrupt Clear */
8203 #define RCC_CIR_HSI48RDYC_Pos                    (22U)
8204 #define RCC_CIR_HSI48RDYC_Msk                    (0x1UL << RCC_CIR_HSI48RDYC_Pos) /*!< 0x00400000 */
8205 #define RCC_CIR_HSI48RDYC                        RCC_CIR_HSI48RDYC_Msk         /*!< HSI48 Ready Interrupt Clear */
8206 #define RCC_CIR_CSSC_Pos                         (23U)
8207 #define RCC_CIR_CSSC_Msk                         (0x1UL << RCC_CIR_CSSC_Pos)    /*!< 0x00800000 */
8208 #define RCC_CIR_CSSC                             RCC_CIR_CSSC_Msk              /*!< Clock Security System Interrupt Clear */
8209 
8210 /*****************  Bit definition for RCC_APB2RSTR register  ****************/
8211 #define RCC_APB2RSTR_SYSCFGRST_Pos               (0U)
8212 #define RCC_APB2RSTR_SYSCFGRST_Msk               (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
8213 #define RCC_APB2RSTR_SYSCFGRST                   RCC_APB2RSTR_SYSCFGRST_Msk    /*!< SYSCFG reset */
8214 #define RCC_APB2RSTR_USART6RST_Pos               (5U)
8215 #define RCC_APB2RSTR_USART6RST_Msk               (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
8216 #define RCC_APB2RSTR_USART6RST                   RCC_APB2RSTR_USART6RST_Msk    /*!< USART6 reset */
8217 #define RCC_APB2RSTR_USART7RST_Pos               (6U)
8218 #define RCC_APB2RSTR_USART7RST_Msk               (0x1UL << RCC_APB2RSTR_USART7RST_Pos) /*!< 0x00000040 */
8219 #define RCC_APB2RSTR_USART7RST                   RCC_APB2RSTR_USART7RST_Msk    /*!< USART7 reset */
8220 #define RCC_APB2RSTR_USART8RST_Pos               (7U)
8221 #define RCC_APB2RSTR_USART8RST_Msk               (0x1UL << RCC_APB2RSTR_USART8RST_Pos) /*!< 0x00000080 */
8222 #define RCC_APB2RSTR_USART8RST                   RCC_APB2RSTR_USART8RST_Msk    /*!< USART8 reset */
8223 #define RCC_APB2RSTR_ADCRST_Pos                  (9U)
8224 #define RCC_APB2RSTR_ADCRST_Msk                  (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
8225 #define RCC_APB2RSTR_ADCRST                      RCC_APB2RSTR_ADCRST_Msk       /*!< ADC reset */
8226 #define RCC_APB2RSTR_TIM1RST_Pos                 (11U)
8227 #define RCC_APB2RSTR_TIM1RST_Msk                 (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
8228 #define RCC_APB2RSTR_TIM1RST                     RCC_APB2RSTR_TIM1RST_Msk      /*!< TIM1 reset */
8229 #define RCC_APB2RSTR_SPI1RST_Pos                 (12U)
8230 #define RCC_APB2RSTR_SPI1RST_Msk                 (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
8231 #define RCC_APB2RSTR_SPI1RST                     RCC_APB2RSTR_SPI1RST_Msk      /*!< SPI1 reset */
8232 #define RCC_APB2RSTR_USART1RST_Pos               (14U)
8233 #define RCC_APB2RSTR_USART1RST_Msk               (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
8234 #define RCC_APB2RSTR_USART1RST                   RCC_APB2RSTR_USART1RST_Msk    /*!< USART1 reset */
8235 #define RCC_APB2RSTR_TIM15RST_Pos                (16U)
8236 #define RCC_APB2RSTR_TIM15RST_Msk                (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
8237 #define RCC_APB2RSTR_TIM15RST                    RCC_APB2RSTR_TIM15RST_Msk     /*!< TIM15 reset */
8238 #define RCC_APB2RSTR_TIM16RST_Pos                (17U)
8239 #define RCC_APB2RSTR_TIM16RST_Msk                (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
8240 #define RCC_APB2RSTR_TIM16RST                    RCC_APB2RSTR_TIM16RST_Msk     /*!< TIM16 reset */
8241 #define RCC_APB2RSTR_TIM17RST_Pos                (18U)
8242 #define RCC_APB2RSTR_TIM17RST_Msk                (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
8243 #define RCC_APB2RSTR_TIM17RST                    RCC_APB2RSTR_TIM17RST_Msk     /*!< TIM17 reset */
8244 #define RCC_APB2RSTR_DBGMCURST_Pos               (22U)
8245 #define RCC_APB2RSTR_DBGMCURST_Msk               (0x1UL << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */
8246 #define RCC_APB2RSTR_DBGMCURST                   RCC_APB2RSTR_DBGMCURST_Msk    /*!< DBGMCU reset */
8247 
8248 /*!< Old ADC1 reset bit definition maintained for legacy purpose */
8249 #define  RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST
8250 
8251 /*****************  Bit definition for RCC_APB1RSTR register  ****************/
8252 #define RCC_APB1RSTR_TIM2RST_Pos                 (0U)
8253 #define RCC_APB1RSTR_TIM2RST_Msk                 (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
8254 #define RCC_APB1RSTR_TIM2RST                     RCC_APB1RSTR_TIM2RST_Msk      /*!< Timer 2 reset */
8255 #define RCC_APB1RSTR_TIM3RST_Pos                 (1U)
8256 #define RCC_APB1RSTR_TIM3RST_Msk                 (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
8257 #define RCC_APB1RSTR_TIM3RST                     RCC_APB1RSTR_TIM3RST_Msk      /*!< Timer 3 reset */
8258 #define RCC_APB1RSTR_TIM6RST_Pos                 (4U)
8259 #define RCC_APB1RSTR_TIM6RST_Msk                 (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
8260 #define RCC_APB1RSTR_TIM6RST                     RCC_APB1RSTR_TIM6RST_Msk      /*!< Timer 6 reset */
8261 #define RCC_APB1RSTR_TIM7RST_Pos                 (5U)
8262 #define RCC_APB1RSTR_TIM7RST_Msk                 (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
8263 #define RCC_APB1RSTR_TIM7RST                     RCC_APB1RSTR_TIM7RST_Msk      /*!< Timer 7 reset */
8264 #define RCC_APB1RSTR_TIM14RST_Pos                (8U)
8265 #define RCC_APB1RSTR_TIM14RST_Msk                (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
8266 #define RCC_APB1RSTR_TIM14RST                    RCC_APB1RSTR_TIM14RST_Msk     /*!< Timer 14 reset */
8267 #define RCC_APB1RSTR_WWDGRST_Pos                 (11U)
8268 #define RCC_APB1RSTR_WWDGRST_Msk                 (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
8269 #define RCC_APB1RSTR_WWDGRST                     RCC_APB1RSTR_WWDGRST_Msk      /*!< Window Watchdog reset */
8270 #define RCC_APB1RSTR_SPI2RST_Pos                 (14U)
8271 #define RCC_APB1RSTR_SPI2RST_Msk                 (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
8272 #define RCC_APB1RSTR_SPI2RST                     RCC_APB1RSTR_SPI2RST_Msk      /*!< SPI2 reset */
8273 #define RCC_APB1RSTR_USART2RST_Pos               (17U)
8274 #define RCC_APB1RSTR_USART2RST_Msk               (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
8275 #define RCC_APB1RSTR_USART2RST                   RCC_APB1RSTR_USART2RST_Msk    /*!< USART 2 reset */
8276 #define RCC_APB1RSTR_USART3RST_Pos               (18U)
8277 #define RCC_APB1RSTR_USART3RST_Msk               (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
8278 #define RCC_APB1RSTR_USART3RST                   RCC_APB1RSTR_USART3RST_Msk    /*!< USART 3 reset */
8279 #define RCC_APB1RSTR_USART4RST_Pos               (19U)
8280 #define RCC_APB1RSTR_USART4RST_Msk               (0x1UL << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */
8281 #define RCC_APB1RSTR_USART4RST                   RCC_APB1RSTR_USART4RST_Msk    /*!< USART 4 reset */
8282 #define RCC_APB1RSTR_USART5RST_Pos               (20U)
8283 #define RCC_APB1RSTR_USART5RST_Msk               (0x1UL << RCC_APB1RSTR_USART5RST_Pos) /*!< 0x00100000 */
8284 #define RCC_APB1RSTR_USART5RST                   RCC_APB1RSTR_USART5RST_Msk    /*!< USART 5 reset */
8285 #define RCC_APB1RSTR_I2C1RST_Pos                 (21U)
8286 #define RCC_APB1RSTR_I2C1RST_Msk                 (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
8287 #define RCC_APB1RSTR_I2C1RST                     RCC_APB1RSTR_I2C1RST_Msk      /*!< I2C 1 reset */
8288 #define RCC_APB1RSTR_I2C2RST_Pos                 (22U)
8289 #define RCC_APB1RSTR_I2C2RST_Msk                 (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
8290 #define RCC_APB1RSTR_I2C2RST                     RCC_APB1RSTR_I2C2RST_Msk      /*!< I2C 2 reset */
8291 #define RCC_APB1RSTR_CANRST_Pos                  (25U)
8292 #define RCC_APB1RSTR_CANRST_Msk                  (0x1UL << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */
8293 #define RCC_APB1RSTR_CANRST                      RCC_APB1RSTR_CANRST_Msk       /*!< CAN reset */
8294 #define RCC_APB1RSTR_CRSRST_Pos                  (27U)
8295 #define RCC_APB1RSTR_CRSRST_Msk                  (0x1UL << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */
8296 #define RCC_APB1RSTR_CRSRST                      RCC_APB1RSTR_CRSRST_Msk       /*!< CRS reset */
8297 #define RCC_APB1RSTR_PWRRST_Pos                  (28U)
8298 #define RCC_APB1RSTR_PWRRST_Msk                  (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
8299 #define RCC_APB1RSTR_PWRRST                      RCC_APB1RSTR_PWRRST_Msk       /*!< PWR reset */
8300 #define RCC_APB1RSTR_DACRST_Pos                  (29U)
8301 #define RCC_APB1RSTR_DACRST_Msk                  (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
8302 #define RCC_APB1RSTR_DACRST                      RCC_APB1RSTR_DACRST_Msk       /*!< DAC reset */
8303 #define RCC_APB1RSTR_CECRST_Pos                  (30U)
8304 #define RCC_APB1RSTR_CECRST_Msk                  (0x1UL << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */
8305 #define RCC_APB1RSTR_CECRST                      RCC_APB1RSTR_CECRST_Msk       /*!< CEC reset */
8306 
8307 /******************  Bit definition for RCC_AHBENR register  *****************/
8308 #define RCC_AHBENR_DMAEN_Pos                     (0U)
8309 #define RCC_AHBENR_DMAEN_Msk                     (0x1UL << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
8310 #define RCC_AHBENR_DMAEN                         RCC_AHBENR_DMAEN_Msk          /*!< DMA1 clock enable */
8311 #define RCC_AHBENR_DMA2EN_Pos                    (1U)
8312 #define RCC_AHBENR_DMA2EN_Msk                    (0x1UL << RCC_AHBENR_DMA2EN_Pos) /*!< 0x00000002 */
8313 #define RCC_AHBENR_DMA2EN                        RCC_AHBENR_DMA2EN_Msk         /*!< DMA2 clock enable */
8314 #define RCC_AHBENR_SRAMEN_Pos                    (2U)
8315 #define RCC_AHBENR_SRAMEN_Msk                    (0x1UL << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
8316 #define RCC_AHBENR_SRAMEN                        RCC_AHBENR_SRAMEN_Msk         /*!< SRAM interface clock enable */
8317 #define RCC_AHBENR_FLITFEN_Pos                   (4U)
8318 #define RCC_AHBENR_FLITFEN_Msk                   (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
8319 #define RCC_AHBENR_FLITFEN                       RCC_AHBENR_FLITFEN_Msk        /*!< FLITF clock enable */
8320 #define RCC_AHBENR_CRCEN_Pos                     (6U)
8321 #define RCC_AHBENR_CRCEN_Msk                     (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
8322 #define RCC_AHBENR_CRCEN                         RCC_AHBENR_CRCEN_Msk          /*!< CRC clock enable */
8323 #define RCC_AHBENR_GPIOAEN_Pos                   (17U)
8324 #define RCC_AHBENR_GPIOAEN_Msk                   (0x1UL << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00020000 */
8325 #define RCC_AHBENR_GPIOAEN                       RCC_AHBENR_GPIOAEN_Msk        /*!< GPIOA clock enable */
8326 #define RCC_AHBENR_GPIOBEN_Pos                   (18U)
8327 #define RCC_AHBENR_GPIOBEN_Msk                   (0x1UL << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00040000 */
8328 #define RCC_AHBENR_GPIOBEN                       RCC_AHBENR_GPIOBEN_Msk        /*!< GPIOB clock enable */
8329 #define RCC_AHBENR_GPIOCEN_Pos                   (19U)
8330 #define RCC_AHBENR_GPIOCEN_Msk                   (0x1UL << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00080000 */
8331 #define RCC_AHBENR_GPIOCEN                       RCC_AHBENR_GPIOCEN_Msk        /*!< GPIOC clock enable */
8332 #define RCC_AHBENR_GPIODEN_Pos                   (20U)
8333 #define RCC_AHBENR_GPIODEN_Msk                   (0x1UL << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00100000 */
8334 #define RCC_AHBENR_GPIODEN                       RCC_AHBENR_GPIODEN_Msk        /*!< GPIOD clock enable */
8335 #define RCC_AHBENR_GPIOEEN_Pos                   (21U)
8336 #define RCC_AHBENR_GPIOEEN_Msk                   (0x1UL << RCC_AHBENR_GPIOEEN_Pos) /*!< 0x00200000 */
8337 #define RCC_AHBENR_GPIOEEN                       RCC_AHBENR_GPIOEEN_Msk        /*!< GPIOE clock enable */
8338 #define RCC_AHBENR_GPIOFEN_Pos                   (22U)
8339 #define RCC_AHBENR_GPIOFEN_Msk                   (0x1UL << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00400000 */
8340 #define RCC_AHBENR_GPIOFEN                       RCC_AHBENR_GPIOFEN_Msk        /*!< GPIOF clock enable */
8341 #define RCC_AHBENR_TSCEN_Pos                     (24U)
8342 #define RCC_AHBENR_TSCEN_Msk                     (0x1UL << RCC_AHBENR_TSCEN_Pos) /*!< 0x01000000 */
8343 #define RCC_AHBENR_TSCEN                         RCC_AHBENR_TSCEN_Msk          /*!< TS controller clock enable */
8344 
8345 /* Old Bit definition maintained for legacy purpose */
8346 #define  RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN        /*!< DMA1 clock enable */
8347 #define  RCC_AHBENR_TSEN                     RCC_AHBENR_TSCEN        /*!< TS clock enable */
8348 
8349 /*****************  Bit definition for RCC_APB2ENR register  *****************/
8350 #define RCC_APB2ENR_SYSCFGCOMPEN_Pos             (0U)
8351 #define RCC_APB2ENR_SYSCFGCOMPEN_Msk             (0x1UL << RCC_APB2ENR_SYSCFGCOMPEN_Pos) /*!< 0x00000001 */
8352 #define RCC_APB2ENR_SYSCFGCOMPEN                 RCC_APB2ENR_SYSCFGCOMPEN_Msk  /*!< SYSCFG and comparator clock enable */
8353 #define RCC_APB2ENR_USART6EN_Pos                 (5U)
8354 #define RCC_APB2ENR_USART6EN_Msk                 (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
8355 #define RCC_APB2ENR_USART6EN                     RCC_APB2ENR_USART6EN_Msk      /*!< USART6 clock enable */
8356 #define RCC_APB2ENR_USART7EN_Pos                 (6U)
8357 #define RCC_APB2ENR_USART7EN_Msk                 (0x1UL << RCC_APB2ENR_USART7EN_Pos) /*!< 0x00000040 */
8358 #define RCC_APB2ENR_USART7EN                     RCC_APB2ENR_USART7EN_Msk      /*!< USART7 clock enable */
8359 #define RCC_APB2ENR_USART8EN_Pos                 (7U)
8360 #define RCC_APB2ENR_USART8EN_Msk                 (0x1UL << RCC_APB2ENR_USART8EN_Pos) /*!< 0x00000080 */
8361 #define RCC_APB2ENR_USART8EN                     RCC_APB2ENR_USART8EN_Msk      /*!< USART8 clock enable */
8362 #define RCC_APB2ENR_ADCEN_Pos                    (9U)
8363 #define RCC_APB2ENR_ADCEN_Msk                    (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
8364 #define RCC_APB2ENR_ADCEN                        RCC_APB2ENR_ADCEN_Msk         /*!< ADC1 clock enable */
8365 #define RCC_APB2ENR_TIM1EN_Pos                   (11U)
8366 #define RCC_APB2ENR_TIM1EN_Msk                   (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
8367 #define RCC_APB2ENR_TIM1EN                       RCC_APB2ENR_TIM1EN_Msk        /*!< TIM1 clock enable */
8368 #define RCC_APB2ENR_SPI1EN_Pos                   (12U)
8369 #define RCC_APB2ENR_SPI1EN_Msk                   (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
8370 #define RCC_APB2ENR_SPI1EN                       RCC_APB2ENR_SPI1EN_Msk        /*!< SPI1 clock enable */
8371 #define RCC_APB2ENR_USART1EN_Pos                 (14U)
8372 #define RCC_APB2ENR_USART1EN_Msk                 (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
8373 #define RCC_APB2ENR_USART1EN                     RCC_APB2ENR_USART1EN_Msk      /*!< USART1 clock enable */
8374 #define RCC_APB2ENR_TIM15EN_Pos                  (16U)
8375 #define RCC_APB2ENR_TIM15EN_Msk                  (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
8376 #define RCC_APB2ENR_TIM15EN                      RCC_APB2ENR_TIM15EN_Msk       /*!< TIM15 clock enable */
8377 #define RCC_APB2ENR_TIM16EN_Pos                  (17U)
8378 #define RCC_APB2ENR_TIM16EN_Msk                  (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
8379 #define RCC_APB2ENR_TIM16EN                      RCC_APB2ENR_TIM16EN_Msk       /*!< TIM16 clock enable */
8380 #define RCC_APB2ENR_TIM17EN_Pos                  (18U)
8381 #define RCC_APB2ENR_TIM17EN_Msk                  (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
8382 #define RCC_APB2ENR_TIM17EN                      RCC_APB2ENR_TIM17EN_Msk       /*!< TIM17 clock enable */
8383 #define RCC_APB2ENR_DBGMCUEN_Pos                 (22U)
8384 #define RCC_APB2ENR_DBGMCUEN_Msk                 (0x1UL << RCC_APB2ENR_DBGMCUEN_Pos) /*!< 0x00400000 */
8385 #define RCC_APB2ENR_DBGMCUEN                     RCC_APB2ENR_DBGMCUEN_Msk      /*!< DBGMCU clock enable */
8386 
8387 /* Old Bit definition maintained for legacy purpose */
8388 #define  RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGCOMPEN        /*!< SYSCFG clock enable */
8389 #define  RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN               /*!< ADC1 clock enable */
8390 
8391 /*****************  Bit definition for RCC_APB1ENR register  *****************/
8392 #define RCC_APB1ENR_TIM2EN_Pos                   (0U)
8393 #define RCC_APB1ENR_TIM2EN_Msk                   (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
8394 #define RCC_APB1ENR_TIM2EN                       RCC_APB1ENR_TIM2EN_Msk        /*!< Timer 2 clock enable */
8395 #define RCC_APB1ENR_TIM3EN_Pos                   (1U)
8396 #define RCC_APB1ENR_TIM3EN_Msk                   (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
8397 #define RCC_APB1ENR_TIM3EN                       RCC_APB1ENR_TIM3EN_Msk        /*!< Timer 3 clock enable */
8398 #define RCC_APB1ENR_TIM6EN_Pos                   (4U)
8399 #define RCC_APB1ENR_TIM6EN_Msk                   (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
8400 #define RCC_APB1ENR_TIM6EN                       RCC_APB1ENR_TIM6EN_Msk        /*!< Timer 6 clock enable */
8401 #define RCC_APB1ENR_TIM7EN_Pos                   (5U)
8402 #define RCC_APB1ENR_TIM7EN_Msk                   (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
8403 #define RCC_APB1ENR_TIM7EN                       RCC_APB1ENR_TIM7EN_Msk        /*!< Timer 7 clock enable */
8404 #define RCC_APB1ENR_TIM14EN_Pos                  (8U)
8405 #define RCC_APB1ENR_TIM14EN_Msk                  (0x1UL << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
8406 #define RCC_APB1ENR_TIM14EN                      RCC_APB1ENR_TIM14EN_Msk       /*!< Timer 14 clock enable */
8407 #define RCC_APB1ENR_WWDGEN_Pos                   (11U)
8408 #define RCC_APB1ENR_WWDGEN_Msk                   (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
8409 #define RCC_APB1ENR_WWDGEN                       RCC_APB1ENR_WWDGEN_Msk        /*!< Window Watchdog clock enable */
8410 #define RCC_APB1ENR_SPI2EN_Pos                   (14U)
8411 #define RCC_APB1ENR_SPI2EN_Msk                   (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
8412 #define RCC_APB1ENR_SPI2EN                       RCC_APB1ENR_SPI2EN_Msk        /*!< SPI2 clock enable */
8413 #define RCC_APB1ENR_USART2EN_Pos                 (17U)
8414 #define RCC_APB1ENR_USART2EN_Msk                 (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
8415 #define RCC_APB1ENR_USART2EN                     RCC_APB1ENR_USART2EN_Msk      /*!< USART2 clock enable */
8416 #define RCC_APB1ENR_USART3EN_Pos                 (18U)
8417 #define RCC_APB1ENR_USART3EN_Msk                 (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
8418 #define RCC_APB1ENR_USART3EN                     RCC_APB1ENR_USART3EN_Msk      /*!< USART3 clock enable */
8419 #define RCC_APB1ENR_USART4EN_Pos                 (19U)
8420 #define RCC_APB1ENR_USART4EN_Msk                 (0x1UL << RCC_APB1ENR_USART4EN_Pos) /*!< 0x00080000 */
8421 #define RCC_APB1ENR_USART4EN                     RCC_APB1ENR_USART4EN_Msk      /*!< USART4 clock enable */
8422 #define RCC_APB1ENR_USART5EN_Pos                 (20U)
8423 #define RCC_APB1ENR_USART5EN_Msk                 (0x1UL << RCC_APB1ENR_USART5EN_Pos) /*!< 0x00100000 */
8424 #define RCC_APB1ENR_USART5EN                     RCC_APB1ENR_USART5EN_Msk      /*!< USART5 clock enable */
8425 #define RCC_APB1ENR_I2C1EN_Pos                   (21U)
8426 #define RCC_APB1ENR_I2C1EN_Msk                   (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
8427 #define RCC_APB1ENR_I2C1EN                       RCC_APB1ENR_I2C1EN_Msk        /*!< I2C1 clock enable */
8428 #define RCC_APB1ENR_I2C2EN_Pos                   (22U)
8429 #define RCC_APB1ENR_I2C2EN_Msk                   (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
8430 #define RCC_APB1ENR_I2C2EN                       RCC_APB1ENR_I2C2EN_Msk        /*!< I2C2 clock enable */
8431 #define RCC_APB1ENR_CANEN_Pos                    (25U)
8432 #define RCC_APB1ENR_CANEN_Msk                    (0x1UL << RCC_APB1ENR_CANEN_Pos) /*!< 0x02000000 */
8433 #define RCC_APB1ENR_CANEN                        RCC_APB1ENR_CANEN_Msk         /*!< CAN clock enable */
8434 #define RCC_APB1ENR_CRSEN_Pos                    (27U)
8435 #define RCC_APB1ENR_CRSEN_Msk                    (0x1UL << RCC_APB1ENR_CRSEN_Pos) /*!< 0x08000000 */
8436 #define RCC_APB1ENR_CRSEN                        RCC_APB1ENR_CRSEN_Msk         /*!< CRS clock enable */
8437 #define RCC_APB1ENR_PWREN_Pos                    (28U)
8438 #define RCC_APB1ENR_PWREN_Msk                    (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
8439 #define RCC_APB1ENR_PWREN                        RCC_APB1ENR_PWREN_Msk         /*!< PWR clock enable */
8440 #define RCC_APB1ENR_DACEN_Pos                    (29U)
8441 #define RCC_APB1ENR_DACEN_Msk                    (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
8442 #define RCC_APB1ENR_DACEN                        RCC_APB1ENR_DACEN_Msk         /*!< DAC clock enable */
8443 #define RCC_APB1ENR_CECEN_Pos                    (30U)
8444 #define RCC_APB1ENR_CECEN_Msk                    (0x1UL << RCC_APB1ENR_CECEN_Pos) /*!< 0x40000000 */
8445 #define RCC_APB1ENR_CECEN                        RCC_APB1ENR_CECEN_Msk         /*!< CEC clock enable */
8446 
8447 /*******************  Bit definition for RCC_BDCR register  ******************/
8448 #define RCC_BDCR_LSEON_Pos                       (0U)
8449 #define RCC_BDCR_LSEON_Msk                       (0x1UL << RCC_BDCR_LSEON_Pos)  /*!< 0x00000001 */
8450 #define RCC_BDCR_LSEON                           RCC_BDCR_LSEON_Msk            /*!< External Low Speed oscillator enable */
8451 #define RCC_BDCR_LSERDY_Pos                      (1U)
8452 #define RCC_BDCR_LSERDY_Msk                      (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
8453 #define RCC_BDCR_LSERDY                          RCC_BDCR_LSERDY_Msk           /*!< External Low Speed oscillator Ready */
8454 #define RCC_BDCR_LSEBYP_Pos                      (2U)
8455 #define RCC_BDCR_LSEBYP_Msk                      (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
8456 #define RCC_BDCR_LSEBYP                          RCC_BDCR_LSEBYP_Msk           /*!< External Low Speed oscillator Bypass */
8457 
8458 #define RCC_BDCR_LSEDRV_Pos                      (3U)
8459 #define RCC_BDCR_LSEDRV_Msk                      (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
8460 #define RCC_BDCR_LSEDRV                          RCC_BDCR_LSEDRV_Msk           /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
8461 #define RCC_BDCR_LSEDRV_0                        (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
8462 #define RCC_BDCR_LSEDRV_1                        (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
8463 
8464 #define RCC_BDCR_RTCSEL_Pos                      (8U)
8465 #define RCC_BDCR_RTCSEL_Msk                      (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
8466 #define RCC_BDCR_RTCSEL                          RCC_BDCR_RTCSEL_Msk           /*!< RTCSEL[1:0] bits (RTC clock source selection) */
8467 #define RCC_BDCR_RTCSEL_0                        (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
8468 #define RCC_BDCR_RTCSEL_1                        (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
8469 
8470 /*!< RTC configuration */
8471 #define RCC_BDCR_RTCSEL_NOCLOCK                  (0x00000000U)                 /*!< No clock */
8472 #define RCC_BDCR_RTCSEL_LSE                      (0x00000100U)                 /*!< LSE oscillator clock used as RTC clock */
8473 #define RCC_BDCR_RTCSEL_LSI                      (0x00000200U)                 /*!< LSI oscillator clock used as RTC clock */
8474 #define RCC_BDCR_RTCSEL_HSE                      (0x00000300U)                 /*!< HSE oscillator clock divided by 128 used as RTC clock */
8475 
8476 #define RCC_BDCR_RTCEN_Pos                       (15U)
8477 #define RCC_BDCR_RTCEN_Msk                       (0x1UL << RCC_BDCR_RTCEN_Pos)  /*!< 0x00008000 */
8478 #define RCC_BDCR_RTCEN                           RCC_BDCR_RTCEN_Msk            /*!< RTC clock enable */
8479 #define RCC_BDCR_BDRST_Pos                       (16U)
8480 #define RCC_BDCR_BDRST_Msk                       (0x1UL << RCC_BDCR_BDRST_Pos)  /*!< 0x00010000 */
8481 #define RCC_BDCR_BDRST                           RCC_BDCR_BDRST_Msk            /*!< Backup domain software reset  */
8482 
8483 /*******************  Bit definition for RCC_CSR register  *******************/
8484 #define RCC_CSR_LSION_Pos                        (0U)
8485 #define RCC_CSR_LSION_Msk                        (0x1UL << RCC_CSR_LSION_Pos)   /*!< 0x00000001 */
8486 #define RCC_CSR_LSION                            RCC_CSR_LSION_Msk             /*!< Internal Low Speed oscillator enable */
8487 #define RCC_CSR_LSIRDY_Pos                       (1U)
8488 #define RCC_CSR_LSIRDY_Msk                       (0x1UL << RCC_CSR_LSIRDY_Pos)  /*!< 0x00000002 */
8489 #define RCC_CSR_LSIRDY                           RCC_CSR_LSIRDY_Msk            /*!< Internal Low Speed oscillator Ready */
8490 #define RCC_CSR_V18PWRRSTF_Pos                   (23U)
8491 #define RCC_CSR_V18PWRRSTF_Msk                   (0x1UL << RCC_CSR_V18PWRRSTF_Pos) /*!< 0x00800000 */
8492 #define RCC_CSR_V18PWRRSTF                       RCC_CSR_V18PWRRSTF_Msk        /*!< V1.8 power domain reset flag */
8493 #define RCC_CSR_RMVF_Pos                         (24U)
8494 #define RCC_CSR_RMVF_Msk                         (0x1UL << RCC_CSR_RMVF_Pos)    /*!< 0x01000000 */
8495 #define RCC_CSR_RMVF                             RCC_CSR_RMVF_Msk              /*!< Remove reset flag */
8496 #define RCC_CSR_OBLRSTF_Pos                      (25U)
8497 #define RCC_CSR_OBLRSTF_Msk                      (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
8498 #define RCC_CSR_OBLRSTF                          RCC_CSR_OBLRSTF_Msk           /*!< OBL reset flag */
8499 #define RCC_CSR_PINRSTF_Pos                      (26U)
8500 #define RCC_CSR_PINRSTF_Msk                      (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
8501 #define RCC_CSR_PINRSTF                          RCC_CSR_PINRSTF_Msk           /*!< PIN reset flag */
8502 #define RCC_CSR_PORRSTF_Pos                      (27U)
8503 #define RCC_CSR_PORRSTF_Msk                      (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
8504 #define RCC_CSR_PORRSTF                          RCC_CSR_PORRSTF_Msk           /*!< POR/PDR reset flag */
8505 #define RCC_CSR_SFTRSTF_Pos                      (28U)
8506 #define RCC_CSR_SFTRSTF_Msk                      (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
8507 #define RCC_CSR_SFTRSTF                          RCC_CSR_SFTRSTF_Msk           /*!< Software Reset flag */
8508 #define RCC_CSR_IWDGRSTF_Pos                     (29U)
8509 #define RCC_CSR_IWDGRSTF_Msk                     (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
8510 #define RCC_CSR_IWDGRSTF                         RCC_CSR_IWDGRSTF_Msk          /*!< Independent Watchdog reset flag */
8511 #define RCC_CSR_WWDGRSTF_Pos                     (30U)
8512 #define RCC_CSR_WWDGRSTF_Msk                     (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
8513 #define RCC_CSR_WWDGRSTF                         RCC_CSR_WWDGRSTF_Msk          /*!< Window watchdog reset flag */
8514 #define RCC_CSR_LPWRRSTF_Pos                     (31U)
8515 #define RCC_CSR_LPWRRSTF_Msk                     (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
8516 #define RCC_CSR_LPWRRSTF                         RCC_CSR_LPWRRSTF_Msk          /*!< Low-Power reset flag */
8517 
8518 /* Old Bit definition maintained for legacy purpose */
8519 #define  RCC_CSR_OBL                         RCC_CSR_OBLRSTF        /*!< OBL reset flag */
8520 
8521 /*******************  Bit definition for RCC_AHBRSTR register  ***************/
8522 #define RCC_AHBRSTR_GPIOARST_Pos                 (17U)
8523 #define RCC_AHBRSTR_GPIOARST_Msk                 (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
8524 #define RCC_AHBRSTR_GPIOARST                     RCC_AHBRSTR_GPIOARST_Msk      /*!< GPIOA reset */
8525 #define RCC_AHBRSTR_GPIOBRST_Pos                 (18U)
8526 #define RCC_AHBRSTR_GPIOBRST_Msk                 (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
8527 #define RCC_AHBRSTR_GPIOBRST                     RCC_AHBRSTR_GPIOBRST_Msk      /*!< GPIOB reset */
8528 #define RCC_AHBRSTR_GPIOCRST_Pos                 (19U)
8529 #define RCC_AHBRSTR_GPIOCRST_Msk                 (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
8530 #define RCC_AHBRSTR_GPIOCRST                     RCC_AHBRSTR_GPIOCRST_Msk      /*!< GPIOC reset */
8531 #define RCC_AHBRSTR_GPIODRST_Pos                 (20U)
8532 #define RCC_AHBRSTR_GPIODRST_Msk                 (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */
8533 #define RCC_AHBRSTR_GPIODRST                     RCC_AHBRSTR_GPIODRST_Msk      /*!< GPIOD reset */
8534 #define RCC_AHBRSTR_GPIOERST_Pos                 (21U)
8535 #define RCC_AHBRSTR_GPIOERST_Msk                 (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00200000 */
8536 #define RCC_AHBRSTR_GPIOERST                     RCC_AHBRSTR_GPIOERST_Msk      /*!< GPIOE reset */
8537 #define RCC_AHBRSTR_GPIOFRST_Pos                 (22U)
8538 #define RCC_AHBRSTR_GPIOFRST_Msk                 (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
8539 #define RCC_AHBRSTR_GPIOFRST                     RCC_AHBRSTR_GPIOFRST_Msk      /*!< GPIOF reset */
8540 #define RCC_AHBRSTR_TSCRST_Pos                   (24U)
8541 #define RCC_AHBRSTR_TSCRST_Msk                   (0x1UL << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */
8542 #define RCC_AHBRSTR_TSCRST                       RCC_AHBRSTR_TSCRST_Msk        /*!< TS reset */
8543 
8544 /* Old Bit definition maintained for legacy purpose */
8545 #define  RCC_AHBRSTR_TSRST                   RCC_AHBRSTR_TSCRST         /*!< TS reset */
8546 
8547 /*******************  Bit definition for RCC_CFGR2 register  *****************/
8548 /*!< PREDIV configuration */
8549 #define RCC_CFGR2_PREDIV_Pos                     (0U)
8550 #define RCC_CFGR2_PREDIV_Msk                     (0xFUL << RCC_CFGR2_PREDIV_Pos) /*!< 0x0000000F */
8551 #define RCC_CFGR2_PREDIV                         RCC_CFGR2_PREDIV_Msk          /*!< PREDIV[3:0] bits */
8552 #define RCC_CFGR2_PREDIV_0                       (0x1UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000001 */
8553 #define RCC_CFGR2_PREDIV_1                       (0x2UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000002 */
8554 #define RCC_CFGR2_PREDIV_2                       (0x4UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000004 */
8555 #define RCC_CFGR2_PREDIV_3                       (0x8UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000008 */
8556 
8557 #define RCC_CFGR2_PREDIV_DIV1                    (0x00000000U)                 /*!< PREDIV input clock not divided */
8558 #define RCC_CFGR2_PREDIV_DIV2                    (0x00000001U)                 /*!< PREDIV input clock divided by 2 */
8559 #define RCC_CFGR2_PREDIV_DIV3                    (0x00000002U)                 /*!< PREDIV input clock divided by 3 */
8560 #define RCC_CFGR2_PREDIV_DIV4                    (0x00000003U)                 /*!< PREDIV input clock divided by 4 */
8561 #define RCC_CFGR2_PREDIV_DIV5                    (0x00000004U)                 /*!< PREDIV input clock divided by 5 */
8562 #define RCC_CFGR2_PREDIV_DIV6                    (0x00000005U)                 /*!< PREDIV input clock divided by 6 */
8563 #define RCC_CFGR2_PREDIV_DIV7                    (0x00000006U)                 /*!< PREDIV input clock divided by 7 */
8564 #define RCC_CFGR2_PREDIV_DIV8                    (0x00000007U)                 /*!< PREDIV input clock divided by 8 */
8565 #define RCC_CFGR2_PREDIV_DIV9                    (0x00000008U)                 /*!< PREDIV input clock divided by 9 */
8566 #define RCC_CFGR2_PREDIV_DIV10                   (0x00000009U)                 /*!< PREDIV input clock divided by 10 */
8567 #define RCC_CFGR2_PREDIV_DIV11                   (0x0000000AU)                 /*!< PREDIV input clock divided by 11 */
8568 #define RCC_CFGR2_PREDIV_DIV12                   (0x0000000BU)                 /*!< PREDIV input clock divided by 12 */
8569 #define RCC_CFGR2_PREDIV_DIV13                   (0x0000000CU)                 /*!< PREDIV input clock divided by 13 */
8570 #define RCC_CFGR2_PREDIV_DIV14                   (0x0000000DU)                 /*!< PREDIV input clock divided by 14 */
8571 #define RCC_CFGR2_PREDIV_DIV15                   (0x0000000EU)                 /*!< PREDIV input clock divided by 15 */
8572 #define RCC_CFGR2_PREDIV_DIV16                   (0x0000000FU)                 /*!< PREDIV input clock divided by 16 */
8573 
8574 /*******************  Bit definition for RCC_CFGR3 register  *****************/
8575 /*!< USART1 Clock source selection */
8576 #define RCC_CFGR3_USART1SW_Pos                   (0U)
8577 #define RCC_CFGR3_USART1SW_Msk                   (0x3UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000003 */
8578 #define RCC_CFGR3_USART1SW                       RCC_CFGR3_USART1SW_Msk        /*!< USART1SW[1:0] bits */
8579 #define RCC_CFGR3_USART1SW_0                     (0x1UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000001 */
8580 #define RCC_CFGR3_USART1SW_1                     (0x2UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000002 */
8581 
8582 #define RCC_CFGR3_USART1SW_PCLK                  (0x00000000U)                 /*!< PCLK clock used as USART1 clock source */
8583 #define RCC_CFGR3_USART1SW_SYSCLK                (0x00000001U)                 /*!< System clock selected as USART1 clock source */
8584 #define RCC_CFGR3_USART1SW_LSE                   (0x00000002U)                 /*!< LSE oscillator clock used as USART1 clock source */
8585 #define RCC_CFGR3_USART1SW_HSI                   (0x00000003U)                 /*!< HSI oscillator clock used as USART1 clock source */
8586 
8587 /*!< I2C1 Clock source selection */
8588 #define RCC_CFGR3_I2C1SW_Pos                     (4U)
8589 #define RCC_CFGR3_I2C1SW_Msk                     (0x1UL << RCC_CFGR3_I2C1SW_Pos) /*!< 0x00000010 */
8590 #define RCC_CFGR3_I2C1SW                         RCC_CFGR3_I2C1SW_Msk          /*!< I2C1SW bits */
8591 
8592 #define RCC_CFGR3_I2C1SW_HSI                     (0x00000000U)                 /*!< HSI oscillator clock used as I2C1 clock source */
8593 #define RCC_CFGR3_I2C1SW_SYSCLK_Pos              (4U)
8594 #define RCC_CFGR3_I2C1SW_SYSCLK_Msk              (0x1UL << RCC_CFGR3_I2C1SW_SYSCLK_Pos) /*!< 0x00000010 */
8595 #define RCC_CFGR3_I2C1SW_SYSCLK                  RCC_CFGR3_I2C1SW_SYSCLK_Msk   /*!< System clock selected as I2C1 clock source */
8596 
8597 /*!< CEC Clock source selection */
8598 #define RCC_CFGR3_CECSW_Pos                      (6U)
8599 #define RCC_CFGR3_CECSW_Msk                      (0x1UL << RCC_CFGR3_CECSW_Pos) /*!< 0x00000040 */
8600 #define RCC_CFGR3_CECSW                          RCC_CFGR3_CECSW_Msk           /*!< CECSW bits */
8601 
8602 #define RCC_CFGR3_CECSW_HSI_DIV244               (0x00000000U)                 /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
8603 #define RCC_CFGR3_CECSW_LSE_Pos                  (6U)
8604 #define RCC_CFGR3_CECSW_LSE_Msk                  (0x1UL << RCC_CFGR3_CECSW_LSE_Pos) /*!< 0x00000040 */
8605 #define RCC_CFGR3_CECSW_LSE                      RCC_CFGR3_CECSW_LSE_Msk       /*!< LSE clock selected as HDMI CEC entry clock source */
8606 
8607 /*!< USART2 Clock source selection */
8608 #define RCC_CFGR3_USART2SW_Pos                   (16U)
8609 #define RCC_CFGR3_USART2SW_Msk                   (0x3UL << RCC_CFGR3_USART2SW_Pos) /*!< 0x00030000 */
8610 #define RCC_CFGR3_USART2SW                       RCC_CFGR3_USART2SW_Msk        /*!< USART2SW[1:0] bits */
8611 #define RCC_CFGR3_USART2SW_0                     (0x1UL << RCC_CFGR3_USART2SW_Pos) /*!< 0x00010000 */
8612 #define RCC_CFGR3_USART2SW_1                     (0x2UL << RCC_CFGR3_USART2SW_Pos) /*!< 0x00020000 */
8613 
8614 #define RCC_CFGR3_USART2SW_PCLK                  (0x00000000U)                 /*!< PCLK clock used as USART2 clock source */
8615 #define RCC_CFGR3_USART2SW_SYSCLK                (0x00010000U)                 /*!< System clock selected as USART2 clock source */
8616 #define RCC_CFGR3_USART2SW_LSE                   (0x00020000U)                 /*!< LSE oscillator clock used as USART2 clock source */
8617 #define RCC_CFGR3_USART2SW_HSI                   (0x00030000U)                 /*!< HSI oscillator clock used as USART2 clock source */
8618 
8619 /*!< USART3 Clock source selection */
8620 #define RCC_CFGR3_USART3SW_Pos                   (18U)
8621 #define RCC_CFGR3_USART3SW_Msk                   (0x3UL << RCC_CFGR3_USART3SW_Pos) /*!< 0x000C0000 */
8622 #define RCC_CFGR3_USART3SW                       RCC_CFGR3_USART3SW_Msk        /*!< USART3SW[1:0] bits */
8623 #define RCC_CFGR3_USART3SW_0                     (0x1UL << RCC_CFGR3_USART3SW_Pos) /*!< 0x00040000 */
8624 #define RCC_CFGR3_USART3SW_1                     (0x2UL << RCC_CFGR3_USART3SW_Pos) /*!< 0x00080000 */
8625 
8626 #define RCC_CFGR3_USART3SW_PCLK                  (0x00000000U)                 /*!< PCLK clock used as USART3 clock source */
8627 #define RCC_CFGR3_USART3SW_SYSCLK                (0x00040000U)                 /*!< System clock selected as USART3 clock source */
8628 #define RCC_CFGR3_USART3SW_LSE                   (0x00080000U)                 /*!< LSE oscillator clock used as USART3 clock source */
8629 #define RCC_CFGR3_USART3SW_HSI                   (0x000C0000U)                 /*!< HSI oscillator clock used as USART3 clock source */
8630 
8631 /*******************  Bit definition for RCC_CR2 register  *******************/
8632 #define RCC_CR2_HSI14ON_Pos                      (0U)
8633 #define RCC_CR2_HSI14ON_Msk                      (0x1UL << RCC_CR2_HSI14ON_Pos) /*!< 0x00000001 */
8634 #define RCC_CR2_HSI14ON                          RCC_CR2_HSI14ON_Msk           /*!< Internal High Speed 14MHz clock enable */
8635 #define RCC_CR2_HSI14RDY_Pos                     (1U)
8636 #define RCC_CR2_HSI14RDY_Msk                     (0x1UL << RCC_CR2_HSI14RDY_Pos) /*!< 0x00000002 */
8637 #define RCC_CR2_HSI14RDY                         RCC_CR2_HSI14RDY_Msk          /*!< Internal High Speed 14MHz clock ready flag */
8638 #define RCC_CR2_HSI14DIS_Pos                     (2U)
8639 #define RCC_CR2_HSI14DIS_Msk                     (0x1UL << RCC_CR2_HSI14DIS_Pos) /*!< 0x00000004 */
8640 #define RCC_CR2_HSI14DIS                         RCC_CR2_HSI14DIS_Msk          /*!< Internal High Speed 14MHz clock disable */
8641 #define RCC_CR2_HSI14TRIM_Pos                    (3U)
8642 #define RCC_CR2_HSI14TRIM_Msk                    (0x1FUL << RCC_CR2_HSI14TRIM_Pos) /*!< 0x000000F8 */
8643 #define RCC_CR2_HSI14TRIM                        RCC_CR2_HSI14TRIM_Msk         /*!< Internal High Speed 14MHz clock trimming */
8644 #define RCC_CR2_HSI14CAL_Pos                     (8U)
8645 #define RCC_CR2_HSI14CAL_Msk                     (0xFFUL << RCC_CR2_HSI14CAL_Pos) /*!< 0x0000FF00 */
8646 #define RCC_CR2_HSI14CAL                         RCC_CR2_HSI14CAL_Msk          /*!< Internal High Speed 14MHz clock Calibration */
8647 #define RCC_CR2_HSI48ON_Pos                      (16U)
8648 #define RCC_CR2_HSI48ON_Msk                      (0x1UL << RCC_CR2_HSI48ON_Pos) /*!< 0x00010000 */
8649 #define RCC_CR2_HSI48ON                          RCC_CR2_HSI48ON_Msk           /*!< Internal High Speed 48MHz clock enable */
8650 #define RCC_CR2_HSI48RDY_Pos                     (17U)
8651 #define RCC_CR2_HSI48RDY_Msk                     (0x1UL << RCC_CR2_HSI48RDY_Pos) /*!< 0x00020000 */
8652 #define RCC_CR2_HSI48RDY                         RCC_CR2_HSI48RDY_Msk          /*!< Internal High Speed 48MHz clock ready flag */
8653 #define RCC_CR2_HSI48CAL_Pos                     (24U)
8654 #define RCC_CR2_HSI48CAL_Msk                     (0xFFUL << RCC_CR2_HSI48CAL_Pos) /*!< 0xFF000000 */
8655 #define RCC_CR2_HSI48CAL                         RCC_CR2_HSI48CAL_Msk          /*!< Internal High Speed 48MHz clock Calibration */
8656 
8657 /*****************************************************************************/
8658 /*                                                                           */
8659 /*                           Real-Time Clock (RTC)                           */
8660 /*                                                                           */
8661 /*****************************************************************************/
8662 /*
8663 * @brief Specific device feature definitions  (not present on all devices in the STM32F0 series)
8664 */
8665 #define RTC_TAMPER1_SUPPORT  /*!< TAMPER 1 feature support */
8666 #define RTC_TAMPER2_SUPPORT  /*!< TAMPER 2 feature support */
8667 #define RTC_TAMPER3_SUPPORT  /*!< TAMPER 3 feature support */
8668 #define RTC_BACKUP_SUPPORT   /*!< BACKUP register feature support */
8669 #define RTC_WAKEUP_SUPPORT   /*!< WAKEUP feature support */
8670 
8671 /********************  Bits definition for RTC_TR register  ******************/
8672 #define RTC_TR_PM_Pos                (22U)
8673 #define RTC_TR_PM_Msk                (0x1UL << RTC_TR_PM_Pos)                   /*!< 0x00400000 */
8674 #define RTC_TR_PM                    RTC_TR_PM_Msk
8675 #define RTC_TR_HT_Pos                (20U)
8676 #define RTC_TR_HT_Msk                (0x3UL << RTC_TR_HT_Pos)                   /*!< 0x00300000 */
8677 #define RTC_TR_HT                    RTC_TR_HT_Msk
8678 #define RTC_TR_HT_0                  (0x1UL << RTC_TR_HT_Pos)                   /*!< 0x00100000 */
8679 #define RTC_TR_HT_1                  (0x2UL << RTC_TR_HT_Pos)                   /*!< 0x00200000 */
8680 #define RTC_TR_HU_Pos                (16U)
8681 #define RTC_TR_HU_Msk                (0xFUL << RTC_TR_HU_Pos)                   /*!< 0x000F0000 */
8682 #define RTC_TR_HU                    RTC_TR_HU_Msk
8683 #define RTC_TR_HU_0                  (0x1UL << RTC_TR_HU_Pos)                   /*!< 0x00010000 */
8684 #define RTC_TR_HU_1                  (0x2UL << RTC_TR_HU_Pos)                   /*!< 0x00020000 */
8685 #define RTC_TR_HU_2                  (0x4UL << RTC_TR_HU_Pos)                   /*!< 0x00040000 */
8686 #define RTC_TR_HU_3                  (0x8UL << RTC_TR_HU_Pos)                   /*!< 0x00080000 */
8687 #define RTC_TR_MNT_Pos               (12U)
8688 #define RTC_TR_MNT_Msk               (0x7UL << RTC_TR_MNT_Pos)                  /*!< 0x00007000 */
8689 #define RTC_TR_MNT                   RTC_TR_MNT_Msk
8690 #define RTC_TR_MNT_0                 (0x1UL << RTC_TR_MNT_Pos)                  /*!< 0x00001000 */
8691 #define RTC_TR_MNT_1                 (0x2UL << RTC_TR_MNT_Pos)                  /*!< 0x00002000 */
8692 #define RTC_TR_MNT_2                 (0x4UL << RTC_TR_MNT_Pos)                  /*!< 0x00004000 */
8693 #define RTC_TR_MNU_Pos               (8U)
8694 #define RTC_TR_MNU_Msk               (0xFUL << RTC_TR_MNU_Pos)                  /*!< 0x00000F00 */
8695 #define RTC_TR_MNU                   RTC_TR_MNU_Msk
8696 #define RTC_TR_MNU_0                 (0x1UL << RTC_TR_MNU_Pos)                  /*!< 0x00000100 */
8697 #define RTC_TR_MNU_1                 (0x2UL << RTC_TR_MNU_Pos)                  /*!< 0x00000200 */
8698 #define RTC_TR_MNU_2                 (0x4UL << RTC_TR_MNU_Pos)                  /*!< 0x00000400 */
8699 #define RTC_TR_MNU_3                 (0x8UL << RTC_TR_MNU_Pos)                  /*!< 0x00000800 */
8700 #define RTC_TR_ST_Pos                (4U)
8701 #define RTC_TR_ST_Msk                (0x7UL << RTC_TR_ST_Pos)                   /*!< 0x00000070 */
8702 #define RTC_TR_ST                    RTC_TR_ST_Msk
8703 #define RTC_TR_ST_0                  (0x1UL << RTC_TR_ST_Pos)                   /*!< 0x00000010 */
8704 #define RTC_TR_ST_1                  (0x2UL << RTC_TR_ST_Pos)                   /*!< 0x00000020 */
8705 #define RTC_TR_ST_2                  (0x4UL << RTC_TR_ST_Pos)                   /*!< 0x00000040 */
8706 #define RTC_TR_SU_Pos                (0U)
8707 #define RTC_TR_SU_Msk                (0xFUL << RTC_TR_SU_Pos)                   /*!< 0x0000000F */
8708 #define RTC_TR_SU                    RTC_TR_SU_Msk
8709 #define RTC_TR_SU_0                  (0x1UL << RTC_TR_SU_Pos)                   /*!< 0x00000001 */
8710 #define RTC_TR_SU_1                  (0x2UL << RTC_TR_SU_Pos)                   /*!< 0x00000002 */
8711 #define RTC_TR_SU_2                  (0x4UL << RTC_TR_SU_Pos)                   /*!< 0x00000004 */
8712 #define RTC_TR_SU_3                  (0x8UL << RTC_TR_SU_Pos)                   /*!< 0x00000008 */
8713 
8714 /********************  Bits definition for RTC_DR register  ******************/
8715 #define RTC_DR_YT_Pos                (20U)
8716 #define RTC_DR_YT_Msk                (0xFUL << RTC_DR_YT_Pos)                   /*!< 0x00F00000 */
8717 #define RTC_DR_YT                    RTC_DR_YT_Msk
8718 #define RTC_DR_YT_0                  (0x1UL << RTC_DR_YT_Pos)                   /*!< 0x00100000 */
8719 #define RTC_DR_YT_1                  (0x2UL << RTC_DR_YT_Pos)                   /*!< 0x00200000 */
8720 #define RTC_DR_YT_2                  (0x4UL << RTC_DR_YT_Pos)                   /*!< 0x00400000 */
8721 #define RTC_DR_YT_3                  (0x8UL << RTC_DR_YT_Pos)                   /*!< 0x00800000 */
8722 #define RTC_DR_YU_Pos                (16U)
8723 #define RTC_DR_YU_Msk                (0xFUL << RTC_DR_YU_Pos)                   /*!< 0x000F0000 */
8724 #define RTC_DR_YU                    RTC_DR_YU_Msk
8725 #define RTC_DR_YU_0                  (0x1UL << RTC_DR_YU_Pos)                   /*!< 0x00010000 */
8726 #define RTC_DR_YU_1                  (0x2UL << RTC_DR_YU_Pos)                   /*!< 0x00020000 */
8727 #define RTC_DR_YU_2                  (0x4UL << RTC_DR_YU_Pos)                   /*!< 0x00040000 */
8728 #define RTC_DR_YU_3                  (0x8UL << RTC_DR_YU_Pos)                   /*!< 0x00080000 */
8729 #define RTC_DR_WDU_Pos               (13U)
8730 #define RTC_DR_WDU_Msk               (0x7UL << RTC_DR_WDU_Pos)                  /*!< 0x0000E000 */
8731 #define RTC_DR_WDU                   RTC_DR_WDU_Msk
8732 #define RTC_DR_WDU_0                 (0x1UL << RTC_DR_WDU_Pos)                  /*!< 0x00002000 */
8733 #define RTC_DR_WDU_1                 (0x2UL << RTC_DR_WDU_Pos)                  /*!< 0x00004000 */
8734 #define RTC_DR_WDU_2                 (0x4UL << RTC_DR_WDU_Pos)                  /*!< 0x00008000 */
8735 #define RTC_DR_MT_Pos                (12U)
8736 #define RTC_DR_MT_Msk                (0x1UL << RTC_DR_MT_Pos)                   /*!< 0x00001000 */
8737 #define RTC_DR_MT                    RTC_DR_MT_Msk
8738 #define RTC_DR_MU_Pos                (8U)
8739 #define RTC_DR_MU_Msk                (0xFUL << RTC_DR_MU_Pos)                   /*!< 0x00000F00 */
8740 #define RTC_DR_MU                    RTC_DR_MU_Msk
8741 #define RTC_DR_MU_0                  (0x1UL << RTC_DR_MU_Pos)                   /*!< 0x00000100 */
8742 #define RTC_DR_MU_1                  (0x2UL << RTC_DR_MU_Pos)                   /*!< 0x00000200 */
8743 #define RTC_DR_MU_2                  (0x4UL << RTC_DR_MU_Pos)                   /*!< 0x00000400 */
8744 #define RTC_DR_MU_3                  (0x8UL << RTC_DR_MU_Pos)                   /*!< 0x00000800 */
8745 #define RTC_DR_DT_Pos                (4U)
8746 #define RTC_DR_DT_Msk                (0x3UL << RTC_DR_DT_Pos)                   /*!< 0x00000030 */
8747 #define RTC_DR_DT                    RTC_DR_DT_Msk
8748 #define RTC_DR_DT_0                  (0x1UL << RTC_DR_DT_Pos)                   /*!< 0x00000010 */
8749 #define RTC_DR_DT_1                  (0x2UL << RTC_DR_DT_Pos)                   /*!< 0x00000020 */
8750 #define RTC_DR_DU_Pos                (0U)
8751 #define RTC_DR_DU_Msk                (0xFUL << RTC_DR_DU_Pos)                   /*!< 0x0000000F */
8752 #define RTC_DR_DU                    RTC_DR_DU_Msk
8753 #define RTC_DR_DU_0                  (0x1UL << RTC_DR_DU_Pos)                   /*!< 0x00000001 */
8754 #define RTC_DR_DU_1                  (0x2UL << RTC_DR_DU_Pos)                   /*!< 0x00000002 */
8755 #define RTC_DR_DU_2                  (0x4UL << RTC_DR_DU_Pos)                   /*!< 0x00000004 */
8756 #define RTC_DR_DU_3                  (0x8UL << RTC_DR_DU_Pos)                   /*!< 0x00000008 */
8757 
8758 /********************  Bits definition for RTC_CR register  ******************/
8759 #define RTC_CR_COE_Pos               (23U)
8760 #define RTC_CR_COE_Msk               (0x1UL << RTC_CR_COE_Pos)                  /*!< 0x00800000 */
8761 #define RTC_CR_COE                   RTC_CR_COE_Msk
8762 #define RTC_CR_OSEL_Pos              (21U)
8763 #define RTC_CR_OSEL_Msk              (0x3UL << RTC_CR_OSEL_Pos)                 /*!< 0x00600000 */
8764 #define RTC_CR_OSEL                  RTC_CR_OSEL_Msk
8765 #define RTC_CR_OSEL_0                (0x1UL << RTC_CR_OSEL_Pos)                 /*!< 0x00200000 */
8766 #define RTC_CR_OSEL_1                (0x2UL << RTC_CR_OSEL_Pos)                 /*!< 0x00400000 */
8767 #define RTC_CR_POL_Pos               (20U)
8768 #define RTC_CR_POL_Msk               (0x1UL << RTC_CR_POL_Pos)                  /*!< 0x00100000 */
8769 #define RTC_CR_POL                   RTC_CR_POL_Msk
8770 #define RTC_CR_COSEL_Pos             (19U)
8771 #define RTC_CR_COSEL_Msk             (0x1UL << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */
8772 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk
8773 #define RTC_CR_BKP_Pos               (18U)
8774 #define RTC_CR_BKP_Msk               (0x1UL << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */
8775 #define RTC_CR_BKP                   RTC_CR_BKP_Msk
8776 #define RTC_CR_SUB1H_Pos             (17U)
8777 #define RTC_CR_SUB1H_Msk             (0x1UL << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */
8778 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk
8779 #define RTC_CR_ADD1H_Pos             (16U)
8780 #define RTC_CR_ADD1H_Msk             (0x1UL << RTC_CR_ADD1H_Pos)                /*!< 0x00010000 */
8781 #define RTC_CR_ADD1H                 RTC_CR_ADD1H_Msk
8782 #define RTC_CR_TSIE_Pos              (15U)
8783 #define RTC_CR_TSIE_Msk              (0x1UL << RTC_CR_TSIE_Pos)                 /*!< 0x00008000 */
8784 #define RTC_CR_TSIE                  RTC_CR_TSIE_Msk
8785 #define RTC_CR_WUTIE_Pos             (14U)
8786 #define RTC_CR_WUTIE_Msk             (0x1UL << RTC_CR_WUTIE_Pos)                /*!< 0x00004000 */
8787 #define RTC_CR_WUTIE                 RTC_CR_WUTIE_Msk
8788 #define RTC_CR_ALRAIE_Pos            (12U)
8789 #define RTC_CR_ALRAIE_Msk            (0x1UL << RTC_CR_ALRAIE_Pos)               /*!< 0x00001000 */
8790 #define RTC_CR_ALRAIE                RTC_CR_ALRAIE_Msk
8791 #define RTC_CR_TSE_Pos               (11U)
8792 #define RTC_CR_TSE_Msk               (0x1UL << RTC_CR_TSE_Pos)                  /*!< 0x00000800 */
8793 #define RTC_CR_TSE                   RTC_CR_TSE_Msk
8794 #define RTC_CR_WUTE_Pos              (10U)
8795 #define RTC_CR_WUTE_Msk              (0x1UL << RTC_CR_WUTE_Pos)                 /*!< 0x00000400 */
8796 #define RTC_CR_WUTE                  RTC_CR_WUTE_Msk
8797 #define RTC_CR_ALRAE_Pos             (8U)
8798 #define RTC_CR_ALRAE_Msk             (0x1UL << RTC_CR_ALRAE_Pos)                /*!< 0x00000100 */
8799 #define RTC_CR_ALRAE                 RTC_CR_ALRAE_Msk
8800 #define RTC_CR_FMT_Pos               (6U)
8801 #define RTC_CR_FMT_Msk               (0x1UL << RTC_CR_FMT_Pos)                  /*!< 0x00000040 */
8802 #define RTC_CR_FMT                   RTC_CR_FMT_Msk
8803 #define RTC_CR_BYPSHAD_Pos           (5U)
8804 #define RTC_CR_BYPSHAD_Msk           (0x1UL << RTC_CR_BYPSHAD_Pos)              /*!< 0x00000020 */
8805 #define RTC_CR_BYPSHAD               RTC_CR_BYPSHAD_Msk
8806 #define RTC_CR_REFCKON_Pos           (4U)
8807 #define RTC_CR_REFCKON_Msk           (0x1UL << RTC_CR_REFCKON_Pos)              /*!< 0x00000010 */
8808 #define RTC_CR_REFCKON               RTC_CR_REFCKON_Msk
8809 #define RTC_CR_TSEDGE_Pos            (3U)
8810 #define RTC_CR_TSEDGE_Msk            (0x1UL << RTC_CR_TSEDGE_Pos)               /*!< 0x00000008 */
8811 #define RTC_CR_TSEDGE                RTC_CR_TSEDGE_Msk
8812 #define RTC_CR_WUCKSEL_Pos           (0U)
8813 #define RTC_CR_WUCKSEL_Msk           (0x7UL << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000007 */
8814 #define RTC_CR_WUCKSEL               RTC_CR_WUCKSEL_Msk
8815 #define RTC_CR_WUCKSEL_0             (0x1UL << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000001 */
8816 #define RTC_CR_WUCKSEL_1             (0x2UL << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000002 */
8817 #define RTC_CR_WUCKSEL_2             (0x4UL << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000004 */
8818 
8819 /* Legacy defines */
8820 #define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos
8821 #define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk
8822 #define RTC_CR_BCK                   RTC_CR_BKP
8823 
8824 /********************  Bits definition for RTC_ISR register  *****************/
8825 #define RTC_ISR_RECALPF_Pos          (16U)
8826 #define RTC_ISR_RECALPF_Msk          (0x1UL << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */
8827 #define RTC_ISR_RECALPF              RTC_ISR_RECALPF_Msk
8828 #define RTC_ISR_TAMP3F_Pos           (15U)
8829 #define RTC_ISR_TAMP3F_Msk           (0x1UL << RTC_ISR_TAMP3F_Pos)              /*!< 0x00008000 */
8830 #define RTC_ISR_TAMP3F               RTC_ISR_TAMP3F_Msk
8831 #define RTC_ISR_TAMP2F_Pos           (14U)
8832 #define RTC_ISR_TAMP2F_Msk           (0x1UL << RTC_ISR_TAMP2F_Pos)              /*!< 0x00004000 */
8833 #define RTC_ISR_TAMP2F               RTC_ISR_TAMP2F_Msk
8834 #define RTC_ISR_TAMP1F_Pos           (13U)
8835 #define RTC_ISR_TAMP1F_Msk           (0x1UL << RTC_ISR_TAMP1F_Pos)              /*!< 0x00002000 */
8836 #define RTC_ISR_TAMP1F               RTC_ISR_TAMP1F_Msk
8837 #define RTC_ISR_TSOVF_Pos            (12U)
8838 #define RTC_ISR_TSOVF_Msk            (0x1UL << RTC_ISR_TSOVF_Pos)               /*!< 0x00001000 */
8839 #define RTC_ISR_TSOVF                RTC_ISR_TSOVF_Msk
8840 #define RTC_ISR_TSF_Pos              (11U)
8841 #define RTC_ISR_TSF_Msk              (0x1UL << RTC_ISR_TSF_Pos)                 /*!< 0x00000800 */
8842 #define RTC_ISR_TSF                  RTC_ISR_TSF_Msk
8843 #define RTC_ISR_WUTF_Pos             (10U)
8844 #define RTC_ISR_WUTF_Msk             (0x1UL << RTC_ISR_WUTF_Pos)                /*!< 0x00000400 */
8845 #define RTC_ISR_WUTF                 RTC_ISR_WUTF_Msk
8846 #define RTC_ISR_ALRAF_Pos            (8U)
8847 #define RTC_ISR_ALRAF_Msk            (0x1UL << RTC_ISR_ALRAF_Pos)               /*!< 0x00000100 */
8848 #define RTC_ISR_ALRAF                RTC_ISR_ALRAF_Msk
8849 #define RTC_ISR_INIT_Pos             (7U)
8850 #define RTC_ISR_INIT_Msk             (0x1UL << RTC_ISR_INIT_Pos)                /*!< 0x00000080 */
8851 #define RTC_ISR_INIT                 RTC_ISR_INIT_Msk
8852 #define RTC_ISR_INITF_Pos            (6U)
8853 #define RTC_ISR_INITF_Msk            (0x1UL << RTC_ISR_INITF_Pos)               /*!< 0x00000040 */
8854 #define RTC_ISR_INITF                RTC_ISR_INITF_Msk
8855 #define RTC_ISR_RSF_Pos              (5U)
8856 #define RTC_ISR_RSF_Msk              (0x1UL << RTC_ISR_RSF_Pos)                 /*!< 0x00000020 */
8857 #define RTC_ISR_RSF                  RTC_ISR_RSF_Msk
8858 #define RTC_ISR_INITS_Pos            (4U)
8859 #define RTC_ISR_INITS_Msk            (0x1UL << RTC_ISR_INITS_Pos)               /*!< 0x00000010 */
8860 #define RTC_ISR_INITS                RTC_ISR_INITS_Msk
8861 #define RTC_ISR_SHPF_Pos             (3U)
8862 #define RTC_ISR_SHPF_Msk             (0x1UL << RTC_ISR_SHPF_Pos)                /*!< 0x00000008 */
8863 #define RTC_ISR_SHPF                 RTC_ISR_SHPF_Msk
8864 #define RTC_ISR_WUTWF_Pos            (2U)
8865 #define RTC_ISR_WUTWF_Msk            (0x1UL << RTC_ISR_WUTWF_Pos)               /*!< 0x00000004 */
8866 #define RTC_ISR_WUTWF                RTC_ISR_WUTWF_Msk
8867 #define RTC_ISR_ALRAWF_Pos           (0U)
8868 #define RTC_ISR_ALRAWF_Msk           (0x1UL << RTC_ISR_ALRAWF_Pos)              /*!< 0x00000001 */
8869 #define RTC_ISR_ALRAWF               RTC_ISR_ALRAWF_Msk
8870 
8871 /********************  Bits definition for RTC_PRER register  ****************/
8872 #define RTC_PRER_PREDIV_A_Pos        (16U)
8873 #define RTC_PRER_PREDIV_A_Msk        (0x7FUL << RTC_PRER_PREDIV_A_Pos)          /*!< 0x007F0000 */
8874 #define RTC_PRER_PREDIV_A            RTC_PRER_PREDIV_A_Msk
8875 #define RTC_PRER_PREDIV_S_Pos        (0U)
8876 #define RTC_PRER_PREDIV_S_Msk        (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)        /*!< 0x00007FFF */
8877 #define RTC_PRER_PREDIV_S            RTC_PRER_PREDIV_S_Msk
8878 
8879 /********************  Bits definition for RTC_WUTR register  ****************/
8880 #define RTC_WUTR_WUT_Pos             (0U)
8881 #define RTC_WUTR_WUT_Msk             (0xFFFFUL << RTC_WUTR_WUT_Pos)             /*!< 0x0000FFFF */
8882 #define RTC_WUTR_WUT                 RTC_WUTR_WUT_Msk
8883 
8884 /********************  Bits definition for RTC_ALRMAR register  **************/
8885 #define RTC_ALRMAR_MSK4_Pos          (31U)
8886 #define RTC_ALRMAR_MSK4_Msk          (0x1UL << RTC_ALRMAR_MSK4_Pos)             /*!< 0x80000000 */
8887 #define RTC_ALRMAR_MSK4              RTC_ALRMAR_MSK4_Msk
8888 #define RTC_ALRMAR_WDSEL_Pos         (30U)
8889 #define RTC_ALRMAR_WDSEL_Msk         (0x1UL << RTC_ALRMAR_WDSEL_Pos)            /*!< 0x40000000 */
8890 #define RTC_ALRMAR_WDSEL             RTC_ALRMAR_WDSEL_Msk
8891 #define RTC_ALRMAR_DT_Pos            (28U)
8892 #define RTC_ALRMAR_DT_Msk            (0x3UL << RTC_ALRMAR_DT_Pos)               /*!< 0x30000000 */
8893 #define RTC_ALRMAR_DT                RTC_ALRMAR_DT_Msk
8894 #define RTC_ALRMAR_DT_0              (0x1UL << RTC_ALRMAR_DT_Pos)               /*!< 0x10000000 */
8895 #define RTC_ALRMAR_DT_1              (0x2UL << RTC_ALRMAR_DT_Pos)               /*!< 0x20000000 */
8896 #define RTC_ALRMAR_DU_Pos            (24U)
8897 #define RTC_ALRMAR_DU_Msk            (0xFUL << RTC_ALRMAR_DU_Pos)               /*!< 0x0F000000 */
8898 #define RTC_ALRMAR_DU                RTC_ALRMAR_DU_Msk
8899 #define RTC_ALRMAR_DU_0              (0x1UL << RTC_ALRMAR_DU_Pos)               /*!< 0x01000000 */
8900 #define RTC_ALRMAR_DU_1              (0x2UL << RTC_ALRMAR_DU_Pos)               /*!< 0x02000000 */
8901 #define RTC_ALRMAR_DU_2              (0x4UL << RTC_ALRMAR_DU_Pos)               /*!< 0x04000000 */
8902 #define RTC_ALRMAR_DU_3              (0x8UL << RTC_ALRMAR_DU_Pos)               /*!< 0x08000000 */
8903 #define RTC_ALRMAR_MSK3_Pos          (23U)
8904 #define RTC_ALRMAR_MSK3_Msk          (0x1UL << RTC_ALRMAR_MSK3_Pos)             /*!< 0x00800000 */
8905 #define RTC_ALRMAR_MSK3              RTC_ALRMAR_MSK3_Msk
8906 #define RTC_ALRMAR_PM_Pos            (22U)
8907 #define RTC_ALRMAR_PM_Msk            (0x1UL << RTC_ALRMAR_PM_Pos)               /*!< 0x00400000 */
8908 #define RTC_ALRMAR_PM                RTC_ALRMAR_PM_Msk
8909 #define RTC_ALRMAR_HT_Pos            (20U)
8910 #define RTC_ALRMAR_HT_Msk            (0x3UL << RTC_ALRMAR_HT_Pos)               /*!< 0x00300000 */
8911 #define RTC_ALRMAR_HT                RTC_ALRMAR_HT_Msk
8912 #define RTC_ALRMAR_HT_0              (0x1UL << RTC_ALRMAR_HT_Pos)               /*!< 0x00100000 */
8913 #define RTC_ALRMAR_HT_1              (0x2UL << RTC_ALRMAR_HT_Pos)               /*!< 0x00200000 */
8914 #define RTC_ALRMAR_HU_Pos            (16U)
8915 #define RTC_ALRMAR_HU_Msk            (0xFUL << RTC_ALRMAR_HU_Pos)               /*!< 0x000F0000 */
8916 #define RTC_ALRMAR_HU                RTC_ALRMAR_HU_Msk
8917 #define RTC_ALRMAR_HU_0              (0x1UL << RTC_ALRMAR_HU_Pos)               /*!< 0x00010000 */
8918 #define RTC_ALRMAR_HU_1              (0x2UL << RTC_ALRMAR_HU_Pos)               /*!< 0x00020000 */
8919 #define RTC_ALRMAR_HU_2              (0x4UL << RTC_ALRMAR_HU_Pos)               /*!< 0x00040000 */
8920 #define RTC_ALRMAR_HU_3              (0x8UL << RTC_ALRMAR_HU_Pos)               /*!< 0x00080000 */
8921 #define RTC_ALRMAR_MSK2_Pos          (15U)
8922 #define RTC_ALRMAR_MSK2_Msk          (0x1UL << RTC_ALRMAR_MSK2_Pos)             /*!< 0x00008000 */
8923 #define RTC_ALRMAR_MSK2              RTC_ALRMAR_MSK2_Msk
8924 #define RTC_ALRMAR_MNT_Pos           (12U)
8925 #define RTC_ALRMAR_MNT_Msk           (0x7UL << RTC_ALRMAR_MNT_Pos)              /*!< 0x00007000 */
8926 #define RTC_ALRMAR_MNT               RTC_ALRMAR_MNT_Msk
8927 #define RTC_ALRMAR_MNT_0             (0x1UL << RTC_ALRMAR_MNT_Pos)              /*!< 0x00001000 */
8928 #define RTC_ALRMAR_MNT_1             (0x2UL << RTC_ALRMAR_MNT_Pos)              /*!< 0x00002000 */
8929 #define RTC_ALRMAR_MNT_2             (0x4UL << RTC_ALRMAR_MNT_Pos)              /*!< 0x00004000 */
8930 #define RTC_ALRMAR_MNU_Pos           (8U)
8931 #define RTC_ALRMAR_MNU_Msk           (0xFUL << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000F00 */
8932 #define RTC_ALRMAR_MNU               RTC_ALRMAR_MNU_Msk
8933 #define RTC_ALRMAR_MNU_0             (0x1UL << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000100 */
8934 #define RTC_ALRMAR_MNU_1             (0x2UL << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000200 */
8935 #define RTC_ALRMAR_MNU_2             (0x4UL << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000400 */
8936 #define RTC_ALRMAR_MNU_3             (0x8UL << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000800 */
8937 #define RTC_ALRMAR_MSK1_Pos          (7U)
8938 #define RTC_ALRMAR_MSK1_Msk          (0x1UL << RTC_ALRMAR_MSK1_Pos)             /*!< 0x00000080 */
8939 #define RTC_ALRMAR_MSK1              RTC_ALRMAR_MSK1_Msk
8940 #define RTC_ALRMAR_ST_Pos            (4U)
8941 #define RTC_ALRMAR_ST_Msk            (0x7UL << RTC_ALRMAR_ST_Pos)               /*!< 0x00000070 */
8942 #define RTC_ALRMAR_ST                RTC_ALRMAR_ST_Msk
8943 #define RTC_ALRMAR_ST_0              (0x1UL << RTC_ALRMAR_ST_Pos)               /*!< 0x00000010 */
8944 #define RTC_ALRMAR_ST_1              (0x2UL << RTC_ALRMAR_ST_Pos)               /*!< 0x00000020 */
8945 #define RTC_ALRMAR_ST_2              (0x4UL << RTC_ALRMAR_ST_Pos)               /*!< 0x00000040 */
8946 #define RTC_ALRMAR_SU_Pos            (0U)
8947 #define RTC_ALRMAR_SU_Msk            (0xFUL << RTC_ALRMAR_SU_Pos)               /*!< 0x0000000F */
8948 #define RTC_ALRMAR_SU                RTC_ALRMAR_SU_Msk
8949 #define RTC_ALRMAR_SU_0              (0x1UL << RTC_ALRMAR_SU_Pos)               /*!< 0x00000001 */
8950 #define RTC_ALRMAR_SU_1              (0x2UL << RTC_ALRMAR_SU_Pos)               /*!< 0x00000002 */
8951 #define RTC_ALRMAR_SU_2              (0x4UL << RTC_ALRMAR_SU_Pos)               /*!< 0x00000004 */
8952 #define RTC_ALRMAR_SU_3              (0x8UL << RTC_ALRMAR_SU_Pos)               /*!< 0x00000008 */
8953 
8954 /********************  Bits definition for RTC_WPR register  *****************/
8955 #define RTC_WPR_KEY_Pos              (0U)
8956 #define RTC_WPR_KEY_Msk              (0xFFUL << RTC_WPR_KEY_Pos)                /*!< 0x000000FF */
8957 #define RTC_WPR_KEY                  RTC_WPR_KEY_Msk
8958 
8959 /********************  Bits definition for RTC_SSR register  *****************/
8960 #define RTC_SSR_SS_Pos               (0U)
8961 #define RTC_SSR_SS_Msk               (0xFFFFUL << RTC_SSR_SS_Pos)               /*!< 0x0000FFFF */
8962 #define RTC_SSR_SS                   RTC_SSR_SS_Msk
8963 
8964 /********************  Bits definition for RTC_SHIFTR register  **************/
8965 #define RTC_SHIFTR_SUBFS_Pos         (0U)
8966 #define RTC_SHIFTR_SUBFS_Msk         (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)         /*!< 0x00007FFF */
8967 #define RTC_SHIFTR_SUBFS             RTC_SHIFTR_SUBFS_Msk
8968 #define RTC_SHIFTR_ADD1S_Pos         (31U)
8969 #define RTC_SHIFTR_ADD1S_Msk         (0x1UL << RTC_SHIFTR_ADD1S_Pos)            /*!< 0x80000000 */
8970 #define RTC_SHIFTR_ADD1S             RTC_SHIFTR_ADD1S_Msk
8971 
8972 /********************  Bits definition for RTC_TSTR register  ****************/
8973 #define RTC_TSTR_PM_Pos              (22U)
8974 #define RTC_TSTR_PM_Msk              (0x1UL << RTC_TSTR_PM_Pos)                 /*!< 0x00400000 */
8975 #define RTC_TSTR_PM                  RTC_TSTR_PM_Msk
8976 #define RTC_TSTR_HT_Pos              (20U)
8977 #define RTC_TSTR_HT_Msk              (0x3UL << RTC_TSTR_HT_Pos)                 /*!< 0x00300000 */
8978 #define RTC_TSTR_HT                  RTC_TSTR_HT_Msk
8979 #define RTC_TSTR_HT_0                (0x1UL << RTC_TSTR_HT_Pos)                 /*!< 0x00100000 */
8980 #define RTC_TSTR_HT_1                (0x2UL << RTC_TSTR_HT_Pos)                 /*!< 0x00200000 */
8981 #define RTC_TSTR_HU_Pos              (16U)
8982 #define RTC_TSTR_HU_Msk              (0xFUL << RTC_TSTR_HU_Pos)                 /*!< 0x000F0000 */
8983 #define RTC_TSTR_HU                  RTC_TSTR_HU_Msk
8984 #define RTC_TSTR_HU_0                (0x1UL << RTC_TSTR_HU_Pos)                 /*!< 0x00010000 */
8985 #define RTC_TSTR_HU_1                (0x2UL << RTC_TSTR_HU_Pos)                 /*!< 0x00020000 */
8986 #define RTC_TSTR_HU_2                (0x4UL << RTC_TSTR_HU_Pos)                 /*!< 0x00040000 */
8987 #define RTC_TSTR_HU_3                (0x8UL << RTC_TSTR_HU_Pos)                 /*!< 0x00080000 */
8988 #define RTC_TSTR_MNT_Pos             (12U)
8989 #define RTC_TSTR_MNT_Msk             (0x7UL << RTC_TSTR_MNT_Pos)                /*!< 0x00007000 */
8990 #define RTC_TSTR_MNT                 RTC_TSTR_MNT_Msk
8991 #define RTC_TSTR_MNT_0               (0x1UL << RTC_TSTR_MNT_Pos)                /*!< 0x00001000 */
8992 #define RTC_TSTR_MNT_1               (0x2UL << RTC_TSTR_MNT_Pos)                /*!< 0x00002000 */
8993 #define RTC_TSTR_MNT_2               (0x4UL << RTC_TSTR_MNT_Pos)                /*!< 0x00004000 */
8994 #define RTC_TSTR_MNU_Pos             (8U)
8995 #define RTC_TSTR_MNU_Msk             (0xFUL << RTC_TSTR_MNU_Pos)                /*!< 0x00000F00 */
8996 #define RTC_TSTR_MNU                 RTC_TSTR_MNU_Msk
8997 #define RTC_TSTR_MNU_0               (0x1UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000100 */
8998 #define RTC_TSTR_MNU_1               (0x2UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000200 */
8999 #define RTC_TSTR_MNU_2               (0x4UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000400 */
9000 #define RTC_TSTR_MNU_3               (0x8UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000800 */
9001 #define RTC_TSTR_ST_Pos              (4U)
9002 #define RTC_TSTR_ST_Msk              (0x7UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000070 */
9003 #define RTC_TSTR_ST                  RTC_TSTR_ST_Msk
9004 #define RTC_TSTR_ST_0                (0x1UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000010 */
9005 #define RTC_TSTR_ST_1                (0x2UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000020 */
9006 #define RTC_TSTR_ST_2                (0x4UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000040 */
9007 #define RTC_TSTR_SU_Pos              (0U)
9008 #define RTC_TSTR_SU_Msk              (0xFUL << RTC_TSTR_SU_Pos)                 /*!< 0x0000000F */
9009 #define RTC_TSTR_SU                  RTC_TSTR_SU_Msk
9010 #define RTC_TSTR_SU_0                (0x1UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000001 */
9011 #define RTC_TSTR_SU_1                (0x2UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000002 */
9012 #define RTC_TSTR_SU_2                (0x4UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000004 */
9013 #define RTC_TSTR_SU_3                (0x8UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000008 */
9014 
9015 /********************  Bits definition for RTC_TSDR register  ****************/
9016 #define RTC_TSDR_WDU_Pos             (13U)
9017 #define RTC_TSDR_WDU_Msk             (0x7UL << RTC_TSDR_WDU_Pos)                /*!< 0x0000E000 */
9018 #define RTC_TSDR_WDU                 RTC_TSDR_WDU_Msk
9019 #define RTC_TSDR_WDU_0               (0x1UL << RTC_TSDR_WDU_Pos)                /*!< 0x00002000 */
9020 #define RTC_TSDR_WDU_1               (0x2UL << RTC_TSDR_WDU_Pos)                /*!< 0x00004000 */
9021 #define RTC_TSDR_WDU_2               (0x4UL << RTC_TSDR_WDU_Pos)                /*!< 0x00008000 */
9022 #define RTC_TSDR_MT_Pos              (12U)
9023 #define RTC_TSDR_MT_Msk              (0x1UL << RTC_TSDR_MT_Pos)                 /*!< 0x00001000 */
9024 #define RTC_TSDR_MT                  RTC_TSDR_MT_Msk
9025 #define RTC_TSDR_MU_Pos              (8U)
9026 #define RTC_TSDR_MU_Msk              (0xFUL << RTC_TSDR_MU_Pos)                 /*!< 0x00000F00 */
9027 #define RTC_TSDR_MU                  RTC_TSDR_MU_Msk
9028 #define RTC_TSDR_MU_0                (0x1UL << RTC_TSDR_MU_Pos)                 /*!< 0x00000100 */
9029 #define RTC_TSDR_MU_1                (0x2UL << RTC_TSDR_MU_Pos)                 /*!< 0x00000200 */
9030 #define RTC_TSDR_MU_2                (0x4UL << RTC_TSDR_MU_Pos)                 /*!< 0x00000400 */
9031 #define RTC_TSDR_MU_3                (0x8UL << RTC_TSDR_MU_Pos)                 /*!< 0x00000800 */
9032 #define RTC_TSDR_DT_Pos              (4U)
9033 #define RTC_TSDR_DT_Msk              (0x3UL << RTC_TSDR_DT_Pos)                 /*!< 0x00000030 */
9034 #define RTC_TSDR_DT                  RTC_TSDR_DT_Msk
9035 #define RTC_TSDR_DT_0                (0x1UL << RTC_TSDR_DT_Pos)                 /*!< 0x00000010 */
9036 #define RTC_TSDR_DT_1                (0x2UL << RTC_TSDR_DT_Pos)                 /*!< 0x00000020 */
9037 #define RTC_TSDR_DU_Pos              (0U)
9038 #define RTC_TSDR_DU_Msk              (0xFUL << RTC_TSDR_DU_Pos)                 /*!< 0x0000000F */
9039 #define RTC_TSDR_DU                  RTC_TSDR_DU_Msk
9040 #define RTC_TSDR_DU_0                (0x1UL << RTC_TSDR_DU_Pos)                 /*!< 0x00000001 */
9041 #define RTC_TSDR_DU_1                (0x2UL << RTC_TSDR_DU_Pos)                 /*!< 0x00000002 */
9042 #define RTC_TSDR_DU_2                (0x4UL << RTC_TSDR_DU_Pos)                 /*!< 0x00000004 */
9043 #define RTC_TSDR_DU_3                (0x8UL << RTC_TSDR_DU_Pos)                 /*!< 0x00000008 */
9044 
9045 /********************  Bits definition for RTC_TSSSR register  ***************/
9046 #define RTC_TSSSR_SS_Pos             (0U)
9047 #define RTC_TSSSR_SS_Msk             (0xFFFFUL << RTC_TSSSR_SS_Pos)             /*!< 0x0000FFFF */
9048 #define RTC_TSSSR_SS                 RTC_TSSSR_SS_Msk
9049 
9050 /********************  Bits definition for RTC_CALR register  ****************/
9051 #define RTC_CALR_CALP_Pos            (15U)
9052 #define RTC_CALR_CALP_Msk            (0x1UL << RTC_CALR_CALP_Pos)               /*!< 0x00008000 */
9053 #define RTC_CALR_CALP                RTC_CALR_CALP_Msk
9054 #define RTC_CALR_CALW8_Pos           (14U)
9055 #define RTC_CALR_CALW8_Msk           (0x1UL << RTC_CALR_CALW8_Pos)              /*!< 0x00004000 */
9056 #define RTC_CALR_CALW8               RTC_CALR_CALW8_Msk
9057 #define RTC_CALR_CALW16_Pos          (13U)
9058 #define RTC_CALR_CALW16_Msk          (0x1UL << RTC_CALR_CALW16_Pos)             /*!< 0x00002000 */
9059 #define RTC_CALR_CALW16              RTC_CALR_CALW16_Msk
9060 #define RTC_CALR_CALM_Pos            (0U)
9061 #define RTC_CALR_CALM_Msk            (0x1FFUL << RTC_CALR_CALM_Pos)             /*!< 0x000001FF */
9062 #define RTC_CALR_CALM                RTC_CALR_CALM_Msk
9063 #define RTC_CALR_CALM_0              (0x001UL << RTC_CALR_CALM_Pos)             /*!< 0x00000001 */
9064 #define RTC_CALR_CALM_1              (0x002UL << RTC_CALR_CALM_Pos)             /*!< 0x00000002 */
9065 #define RTC_CALR_CALM_2              (0x004UL << RTC_CALR_CALM_Pos)             /*!< 0x00000004 */
9066 #define RTC_CALR_CALM_3              (0x008UL << RTC_CALR_CALM_Pos)             /*!< 0x00000008 */
9067 #define RTC_CALR_CALM_4              (0x010UL << RTC_CALR_CALM_Pos)             /*!< 0x00000010 */
9068 #define RTC_CALR_CALM_5              (0x020UL << RTC_CALR_CALM_Pos)             /*!< 0x00000020 */
9069 #define RTC_CALR_CALM_6              (0x040UL << RTC_CALR_CALM_Pos)             /*!< 0x00000040 */
9070 #define RTC_CALR_CALM_7              (0x080UL << RTC_CALR_CALM_Pos)             /*!< 0x00000080 */
9071 #define RTC_CALR_CALM_8              (0x100UL << RTC_CALR_CALM_Pos)             /*!< 0x00000100 */
9072 
9073 /********************  Bits definition for RTC_TAFCR register  ***************/
9074 #define RTC_TAFCR_PC15MODE_Pos       (23U)
9075 #define RTC_TAFCR_PC15MODE_Msk       (0x1UL << RTC_TAFCR_PC15MODE_Pos)          /*!< 0x00800000 */
9076 #define RTC_TAFCR_PC15MODE           RTC_TAFCR_PC15MODE_Msk
9077 #define RTC_TAFCR_PC15VALUE_Pos      (22U)
9078 #define RTC_TAFCR_PC15VALUE_Msk      (0x1UL << RTC_TAFCR_PC15VALUE_Pos)         /*!< 0x00400000 */
9079 #define RTC_TAFCR_PC15VALUE          RTC_TAFCR_PC15VALUE_Msk
9080 #define RTC_TAFCR_PC14MODE_Pos       (21U)
9081 #define RTC_TAFCR_PC14MODE_Msk       (0x1UL << RTC_TAFCR_PC14MODE_Pos)          /*!< 0x00200000 */
9082 #define RTC_TAFCR_PC14MODE           RTC_TAFCR_PC14MODE_Msk
9083 #define RTC_TAFCR_PC14VALUE_Pos      (20U)
9084 #define RTC_TAFCR_PC14VALUE_Msk      (0x1UL << RTC_TAFCR_PC14VALUE_Pos)         /*!< 0x00100000 */
9085 #define RTC_TAFCR_PC14VALUE          RTC_TAFCR_PC14VALUE_Msk
9086 #define RTC_TAFCR_PC13MODE_Pos       (19U)
9087 #define RTC_TAFCR_PC13MODE_Msk       (0x1UL << RTC_TAFCR_PC13MODE_Pos)          /*!< 0x00080000 */
9088 #define RTC_TAFCR_PC13MODE           RTC_TAFCR_PC13MODE_Msk
9089 #define RTC_TAFCR_PC13VALUE_Pos      (18U)
9090 #define RTC_TAFCR_PC13VALUE_Msk      (0x1UL << RTC_TAFCR_PC13VALUE_Pos)         /*!< 0x00040000 */
9091 #define RTC_TAFCR_PC13VALUE          RTC_TAFCR_PC13VALUE_Msk
9092 #define RTC_TAFCR_TAMPPUDIS_Pos      (15U)
9093 #define RTC_TAFCR_TAMPPUDIS_Msk      (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)         /*!< 0x00008000 */
9094 #define RTC_TAFCR_TAMPPUDIS          RTC_TAFCR_TAMPPUDIS_Msk
9095 #define RTC_TAFCR_TAMPPRCH_Pos       (13U)
9096 #define RTC_TAFCR_TAMPPRCH_Msk       (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)          /*!< 0x00006000 */
9097 #define RTC_TAFCR_TAMPPRCH           RTC_TAFCR_TAMPPRCH_Msk
9098 #define RTC_TAFCR_TAMPPRCH_0         (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)          /*!< 0x00002000 */
9099 #define RTC_TAFCR_TAMPPRCH_1         (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)          /*!< 0x00004000 */
9100 #define RTC_TAFCR_TAMPFLT_Pos        (11U)
9101 #define RTC_TAFCR_TAMPFLT_Msk        (0x3UL << RTC_TAFCR_TAMPFLT_Pos)           /*!< 0x00001800 */
9102 #define RTC_TAFCR_TAMPFLT            RTC_TAFCR_TAMPFLT_Msk
9103 #define RTC_TAFCR_TAMPFLT_0          (0x1UL << RTC_TAFCR_TAMPFLT_Pos)           /*!< 0x00000800 */
9104 #define RTC_TAFCR_TAMPFLT_1          (0x2UL << RTC_TAFCR_TAMPFLT_Pos)           /*!< 0x00001000 */
9105 #define RTC_TAFCR_TAMPFREQ_Pos       (8U)
9106 #define RTC_TAFCR_TAMPFREQ_Msk       (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)          /*!< 0x00000700 */
9107 #define RTC_TAFCR_TAMPFREQ           RTC_TAFCR_TAMPFREQ_Msk
9108 #define RTC_TAFCR_TAMPFREQ_0         (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)          /*!< 0x00000100 */
9109 #define RTC_TAFCR_TAMPFREQ_1         (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)          /*!< 0x00000200 */
9110 #define RTC_TAFCR_TAMPFREQ_2         (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)          /*!< 0x00000400 */
9111 #define RTC_TAFCR_TAMPTS_Pos         (7U)
9112 #define RTC_TAFCR_TAMPTS_Msk         (0x1UL << RTC_TAFCR_TAMPTS_Pos)            /*!< 0x00000080 */
9113 #define RTC_TAFCR_TAMPTS             RTC_TAFCR_TAMPTS_Msk
9114 #define RTC_TAFCR_TAMP3TRG_Pos       (6U)
9115 #define RTC_TAFCR_TAMP3TRG_Msk       (0x1UL << RTC_TAFCR_TAMP3TRG_Pos)          /*!< 0x00000040 */
9116 #define RTC_TAFCR_TAMP3TRG           RTC_TAFCR_TAMP3TRG_Msk
9117 #define RTC_TAFCR_TAMP3E_Pos         (5U)
9118 #define RTC_TAFCR_TAMP3E_Msk         (0x1UL << RTC_TAFCR_TAMP3E_Pos)            /*!< 0x00000020 */
9119 #define RTC_TAFCR_TAMP3E             RTC_TAFCR_TAMP3E_Msk
9120 #define RTC_TAFCR_TAMP2TRG_Pos       (4U)
9121 #define RTC_TAFCR_TAMP2TRG_Msk       (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)          /*!< 0x00000010 */
9122 #define RTC_TAFCR_TAMP2TRG           RTC_TAFCR_TAMP2TRG_Msk
9123 #define RTC_TAFCR_TAMP2E_Pos         (3U)
9124 #define RTC_TAFCR_TAMP2E_Msk         (0x1UL << RTC_TAFCR_TAMP2E_Pos)            /*!< 0x00000008 */
9125 #define RTC_TAFCR_TAMP2E             RTC_TAFCR_TAMP2E_Msk
9126 #define RTC_TAFCR_TAMPIE_Pos         (2U)
9127 #define RTC_TAFCR_TAMPIE_Msk         (0x1UL << RTC_TAFCR_TAMPIE_Pos)            /*!< 0x00000004 */
9128 #define RTC_TAFCR_TAMPIE             RTC_TAFCR_TAMPIE_Msk
9129 #define RTC_TAFCR_TAMP1TRG_Pos       (1U)
9130 #define RTC_TAFCR_TAMP1TRG_Msk       (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)          /*!< 0x00000002 */
9131 #define RTC_TAFCR_TAMP1TRG           RTC_TAFCR_TAMP1TRG_Msk
9132 #define RTC_TAFCR_TAMP1E_Pos         (0U)
9133 #define RTC_TAFCR_TAMP1E_Msk         (0x1UL << RTC_TAFCR_TAMP1E_Pos)            /*!< 0x00000001 */
9134 #define RTC_TAFCR_TAMP1E             RTC_TAFCR_TAMP1E_Msk
9135 
9136 /* Reference defines */
9137 #define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_PC13VALUE
9138 
9139 /********************  Bits definition for RTC_ALRMASSR register  ************/
9140 #define RTC_ALRMASSR_MASKSS_Pos      (24U)
9141 #define RTC_ALRMASSR_MASKSS_Msk      (0xFUL << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x0F000000 */
9142 #define RTC_ALRMASSR_MASKSS          RTC_ALRMASSR_MASKSS_Msk
9143 #define RTC_ALRMASSR_MASKSS_0        (0x1UL << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x01000000 */
9144 #define RTC_ALRMASSR_MASKSS_1        (0x2UL << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x02000000 */
9145 #define RTC_ALRMASSR_MASKSS_2        (0x4UL << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x04000000 */
9146 #define RTC_ALRMASSR_MASKSS_3        (0x8UL << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x08000000 */
9147 #define RTC_ALRMASSR_SS_Pos          (0U)
9148 #define RTC_ALRMASSR_SS_Msk          (0x7FFFUL << RTC_ALRMASSR_SS_Pos)          /*!< 0x00007FFF */
9149 #define RTC_ALRMASSR_SS              RTC_ALRMASSR_SS_Msk
9150 
9151 /********************  Bits definition for RTC_BKP0R register  ***************/
9152 #define RTC_BKP0R_Pos                (0U)
9153 #define RTC_BKP0R_Msk                (0xFFFFFFFFUL << RTC_BKP0R_Pos)            /*!< 0xFFFFFFFF */
9154 #define RTC_BKP0R                    RTC_BKP0R_Msk
9155 
9156 /********************  Bits definition for RTC_BKP1R register  ***************/
9157 #define RTC_BKP1R_Pos                (0U)
9158 #define RTC_BKP1R_Msk                (0xFFFFFFFFUL << RTC_BKP1R_Pos)            /*!< 0xFFFFFFFF */
9159 #define RTC_BKP1R                    RTC_BKP1R_Msk
9160 
9161 /********************  Bits definition for RTC_BKP2R register  ***************/
9162 #define RTC_BKP2R_Pos                (0U)
9163 #define RTC_BKP2R_Msk                (0xFFFFFFFFUL << RTC_BKP2R_Pos)            /*!< 0xFFFFFFFF */
9164 #define RTC_BKP2R                    RTC_BKP2R_Msk
9165 
9166 /********************  Bits definition for RTC_BKP3R register  ***************/
9167 #define RTC_BKP3R_Pos                (0U)
9168 #define RTC_BKP3R_Msk                (0xFFFFFFFFUL << RTC_BKP3R_Pos)            /*!< 0xFFFFFFFF */
9169 #define RTC_BKP3R                    RTC_BKP3R_Msk
9170 
9171 /********************  Bits definition for RTC_BKP4R register  ***************/
9172 #define RTC_BKP4R_Pos                (0U)
9173 #define RTC_BKP4R_Msk                (0xFFFFFFFFUL << RTC_BKP4R_Pos)            /*!< 0xFFFFFFFF */
9174 #define RTC_BKP4R                    RTC_BKP4R_Msk
9175 
9176 /******************** Number of backup registers ******************************/
9177 #define RTC_BKP_NUMBER                       0x00000005U
9178 
9179 /*****************************************************************************/
9180 /*                                                                           */
9181 /*                        Serial Peripheral Interface (SPI)                  */
9182 /*                                                                           */
9183 /*****************************************************************************/
9184 
9185 /*
9186  * @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
9187  */
9188 #define SPI_I2S_SUPPORT                       /*!< I2S support */
9189 
9190 /*******************  Bit definition for SPI_CR1 register  *******************/
9191 #define SPI_CR1_CPHA_Pos            (0U)
9192 #define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
9193 #define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
9194 #define SPI_CR1_CPOL_Pos            (1U)
9195 #define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
9196 #define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
9197 #define SPI_CR1_MSTR_Pos            (2U)
9198 #define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
9199 #define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
9200 #define SPI_CR1_BR_Pos              (3U)
9201 #define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
9202 #define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
9203 #define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
9204 #define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
9205 #define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
9206 #define SPI_CR1_SPE_Pos             (6U)
9207 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
9208 #define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
9209 #define SPI_CR1_LSBFIRST_Pos        (7U)
9210 #define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
9211 #define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
9212 #define SPI_CR1_SSI_Pos             (8U)
9213 #define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
9214 #define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
9215 #define SPI_CR1_SSM_Pos             (9U)
9216 #define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
9217 #define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
9218 #define SPI_CR1_RXONLY_Pos          (10U)
9219 #define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
9220 #define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
9221 #define SPI_CR1_CRCL_Pos            (11U)
9222 #define SPI_CR1_CRCL_Msk            (0x1UL << SPI_CR1_CRCL_Pos)                 /*!< 0x00000800 */
9223 #define SPI_CR1_CRCL                SPI_CR1_CRCL_Msk                           /*!< CRC Length */
9224 #define SPI_CR1_CRCNEXT_Pos         (12U)
9225 #define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
9226 #define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
9227 #define SPI_CR1_CRCEN_Pos           (13U)
9228 #define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
9229 #define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
9230 #define SPI_CR1_BIDIOE_Pos          (14U)
9231 #define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
9232 #define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
9233 #define SPI_CR1_BIDIMODE_Pos        (15U)
9234 #define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
9235 #define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
9236 
9237 /*******************  Bit definition for SPI_CR2 register  *******************/
9238 #define SPI_CR2_RXDMAEN_Pos         (0U)
9239 #define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
9240 #define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
9241 #define SPI_CR2_TXDMAEN_Pos         (1U)
9242 #define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
9243 #define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
9244 #define SPI_CR2_SSOE_Pos            (2U)
9245 #define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
9246 #define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
9247 #define SPI_CR2_NSSP_Pos            (3U)
9248 #define SPI_CR2_NSSP_Msk            (0x1UL << SPI_CR2_NSSP_Pos)                 /*!< 0x00000008 */
9249 #define SPI_CR2_NSSP                SPI_CR2_NSSP_Msk                           /*!< NSS pulse management Enable */
9250 #define SPI_CR2_FRF_Pos             (4U)
9251 #define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
9252 #define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
9253 #define SPI_CR2_ERRIE_Pos           (5U)
9254 #define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
9255 #define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
9256 #define SPI_CR2_RXNEIE_Pos          (6U)
9257 #define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
9258 #define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
9259 #define SPI_CR2_TXEIE_Pos           (7U)
9260 #define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
9261 #define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
9262 #define SPI_CR2_DS_Pos              (8U)
9263 #define SPI_CR2_DS_Msk              (0xFUL << SPI_CR2_DS_Pos)                   /*!< 0x00000F00 */
9264 #define SPI_CR2_DS                  SPI_CR2_DS_Msk                             /*!< DS[3:0] Data Size */
9265 #define SPI_CR2_DS_0                (0x1UL << SPI_CR2_DS_Pos)                   /*!< 0x00000100 */
9266 #define SPI_CR2_DS_1                (0x2UL << SPI_CR2_DS_Pos)                   /*!< 0x00000200 */
9267 #define SPI_CR2_DS_2                (0x4UL << SPI_CR2_DS_Pos)                   /*!< 0x00000400 */
9268 #define SPI_CR2_DS_3                (0x8UL << SPI_CR2_DS_Pos)                   /*!< 0x00000800 */
9269 #define SPI_CR2_FRXTH_Pos           (12U)
9270 #define SPI_CR2_FRXTH_Msk           (0x1UL << SPI_CR2_FRXTH_Pos)                /*!< 0x00001000 */
9271 #define SPI_CR2_FRXTH               SPI_CR2_FRXTH_Msk                          /*!< FIFO reception Threshold */
9272 #define SPI_CR2_LDMARX_Pos          (13U)
9273 #define SPI_CR2_LDMARX_Msk          (0x1UL << SPI_CR2_LDMARX_Pos)               /*!< 0x00002000 */
9274 #define SPI_CR2_LDMARX              SPI_CR2_LDMARX_Msk                         /*!< Last DMA transfer for reception */
9275 #define SPI_CR2_LDMATX_Pos          (14U)
9276 #define SPI_CR2_LDMATX_Msk          (0x1UL << SPI_CR2_LDMATX_Pos)               /*!< 0x00004000 */
9277 #define SPI_CR2_LDMATX              SPI_CR2_LDMATX_Msk                         /*!< Last DMA transfer for transmission */
9278 
9279 /********************  Bit definition for SPI_SR register  *******************/
9280 #define SPI_SR_RXNE_Pos             (0U)
9281 #define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
9282 #define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
9283 #define SPI_SR_TXE_Pos              (1U)
9284 #define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
9285 #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
9286 #define SPI_SR_CHSIDE_Pos           (2U)
9287 #define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
9288 #define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
9289 #define SPI_SR_UDR_Pos              (3U)
9290 #define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
9291 #define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
9292 #define SPI_SR_CRCERR_Pos           (4U)
9293 #define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
9294 #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
9295 #define SPI_SR_MODF_Pos             (5U)
9296 #define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
9297 #define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
9298 #define SPI_SR_OVR_Pos              (6U)
9299 #define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
9300 #define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
9301 #define SPI_SR_BSY_Pos              (7U)
9302 #define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
9303 #define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
9304 #define SPI_SR_FRE_Pos              (8U)
9305 #define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
9306 #define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */
9307 #define SPI_SR_FRLVL_Pos            (9U)
9308 #define SPI_SR_FRLVL_Msk            (0x3UL << SPI_SR_FRLVL_Pos)                 /*!< 0x00000600 */
9309 #define SPI_SR_FRLVL                SPI_SR_FRLVL_Msk                           /*!< FIFO Reception Level */
9310 #define SPI_SR_FRLVL_0              (0x1UL << SPI_SR_FRLVL_Pos)                 /*!< 0x00000200 */
9311 #define SPI_SR_FRLVL_1              (0x2UL << SPI_SR_FRLVL_Pos)                 /*!< 0x00000400 */
9312 #define SPI_SR_FTLVL_Pos            (11U)
9313 #define SPI_SR_FTLVL_Msk            (0x3UL << SPI_SR_FTLVL_Pos)                 /*!< 0x00001800 */
9314 #define SPI_SR_FTLVL                SPI_SR_FTLVL_Msk                           /*!< FIFO Transmission Level */
9315 #define SPI_SR_FTLVL_0              (0x1UL << SPI_SR_FTLVL_Pos)                 /*!< 0x00000800 */
9316 #define SPI_SR_FTLVL_1              (0x2UL << SPI_SR_FTLVL_Pos)                 /*!< 0x00001000 */
9317 
9318 /********************  Bit definition for SPI_DR register  *******************/
9319 #define SPI_DR_DR_Pos               (0U)
9320 #define SPI_DR_DR_Msk               (0xFFFFFFFFUL << SPI_DR_DR_Pos)             /*!< 0xFFFFFFFF */
9321 #define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
9322 
9323 /*******************  Bit definition for SPI_CRCPR register  *****************/
9324 #define SPI_CRCPR_CRCPOLY_Pos       (0U)
9325 #define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFFFFFUL << SPI_CRCPR_CRCPOLY_Pos)     /*!< 0xFFFFFFFF */
9326 #define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
9327 
9328 /******************  Bit definition for SPI_RXCRCR register  *****************/
9329 #define SPI_RXCRCR_RXCRC_Pos        (0U)
9330 #define SPI_RXCRCR_RXCRC_Msk        (0xFFFFFFFFUL << SPI_RXCRCR_RXCRC_Pos)      /*!< 0xFFFFFFFF */
9331 #define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
9332 
9333 /******************  Bit definition for SPI_TXCRCR register  *****************/
9334 #define SPI_TXCRCR_TXCRC_Pos        (0U)
9335 #define SPI_TXCRCR_TXCRC_Msk        (0xFFFFFFFFUL << SPI_TXCRCR_TXCRC_Pos)      /*!< 0xFFFFFFFF */
9336 #define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
9337 
9338 /******************  Bit definition for SPI_I2SCFGR register  ****************/
9339 #define SPI_I2SCFGR_CHLEN_Pos       (0U)
9340 #define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
9341 #define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
9342 #define SPI_I2SCFGR_DATLEN_Pos      (1U)
9343 #define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
9344 #define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
9345 #define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
9346 #define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
9347 #define SPI_I2SCFGR_CKPOL_Pos       (3U)
9348 #define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
9349 #define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
9350 #define SPI_I2SCFGR_I2SSTD_Pos      (4U)
9351 #define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
9352 #define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
9353 #define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
9354 #define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
9355 #define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
9356 #define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
9357 #define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
9358 #define SPI_I2SCFGR_I2SCFG_Pos      (8U)
9359 #define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
9360 #define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
9361 #define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
9362 #define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
9363 #define SPI_I2SCFGR_I2SE_Pos        (10U)
9364 #define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
9365 #define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
9366 #define SPI_I2SCFGR_I2SMOD_Pos      (11U)
9367 #define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
9368 #define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
9369 
9370 /******************  Bit definition for SPI_I2SPR register  ******************/
9371 #define SPI_I2SPR_I2SDIV_Pos        (0U)
9372 #define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
9373 #define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
9374 #define SPI_I2SPR_ODD_Pos           (8U)
9375 #define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
9376 #define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
9377 #define SPI_I2SPR_MCKOE_Pos         (9U)
9378 #define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
9379 #define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
9380 
9381 /*****************************************************************************/
9382 /*                                                                           */
9383 /*                       System Configuration (SYSCFG)                       */
9384 /*                                                                           */
9385 /*****************************************************************************/
9386 /*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
9387 #define SYSCFG_CFGR1_MEM_MODE_Pos            (0U)
9388 #define SYSCFG_CFGR1_MEM_MODE_Msk            (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
9389 #define SYSCFG_CFGR1_MEM_MODE                SYSCFG_CFGR1_MEM_MODE_Msk           /*!< SYSCFG_Memory Remap Config */
9390 #define SYSCFG_CFGR1_MEM_MODE_0              (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
9391 #define SYSCFG_CFGR1_MEM_MODE_1              (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
9392 #define SYSCFG_CFGR1_IR_MOD_Pos              (6U)
9393 #define SYSCFG_CFGR1_IR_MOD_Msk              (0x3UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x000000C0 */
9394 #define SYSCFG_CFGR1_IR_MOD                  SYSCFG_CFGR1_IR_MOD_Msk           /*!< IR_MOD config */
9395 #define SYSCFG_CFGR1_IR_MOD_0                (0x1UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000040 */
9396 #define SYSCFG_CFGR1_IR_MOD_1                (0x2UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000080 */
9397 
9398 /* Alias for legacy purposes */
9399 #define SYSCFG_CFGR1_IRDA_ENV_SEL            SYSCFG_CFGR1_IR_MOD
9400 #define SYSCFG_CFGR1_IRDA_ENV_SEL_0          SYSCFG_CFGR1_IR_MOD_0
9401 #define SYSCFG_CFGR1_IRDA_ENV_SEL_1          SYSCFG_CFGR1_IR_MOD_1
9402 
9403 
9404 
9405 #define SYSCFG_CFGR1_I2C_FMP_PB6_Pos         (16U)
9406 #define SYSCFG_CFGR1_I2C_FMP_PB6_Msk         (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB6_Pos) /*!< 0x00010000 */
9407 #define SYSCFG_CFGR1_I2C_FMP_PB6             SYSCFG_CFGR1_I2C_FMP_PB6_Msk      /*!< I2C PB6 Fast mode plus */
9408 #define SYSCFG_CFGR1_I2C_FMP_PB7_Pos         (17U)
9409 #define SYSCFG_CFGR1_I2C_FMP_PB7_Msk         (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB7_Pos) /*!< 0x00020000 */
9410 #define SYSCFG_CFGR1_I2C_FMP_PB7             SYSCFG_CFGR1_I2C_FMP_PB7_Msk      /*!< I2C PB7 Fast mode plus */
9411 #define SYSCFG_CFGR1_I2C_FMP_PB8_Pos         (18U)
9412 #define SYSCFG_CFGR1_I2C_FMP_PB8_Msk         (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB8_Pos) /*!< 0x00040000 */
9413 #define SYSCFG_CFGR1_I2C_FMP_PB8             SYSCFG_CFGR1_I2C_FMP_PB8_Msk      /*!< I2C PB8 Fast mode plus */
9414 #define SYSCFG_CFGR1_I2C_FMP_PB9_Pos         (19U)
9415 #define SYSCFG_CFGR1_I2C_FMP_PB9_Msk         (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB9_Pos) /*!< 0x00080000 */
9416 #define SYSCFG_CFGR1_I2C_FMP_PB9             SYSCFG_CFGR1_I2C_FMP_PB9_Msk      /*!< I2C PB9 Fast mode plus */
9417 #define SYSCFG_CFGR1_I2C_FMP_I2C1_Pos        (20U)
9418 #define SYSCFG_CFGR1_I2C_FMP_I2C1_Msk        (0x1UL << SYSCFG_CFGR1_I2C_FMP_I2C1_Pos) /*!< 0x00100000 */
9419 #define SYSCFG_CFGR1_I2C_FMP_I2C1            SYSCFG_CFGR1_I2C_FMP_I2C1_Msk     /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7  */
9420 #define SYSCFG_CFGR1_I2C_FMP_I2C2_Pos        (21U)
9421 #define SYSCFG_CFGR1_I2C_FMP_I2C2_Msk        (0x1UL << SYSCFG_CFGR1_I2C_FMP_I2C2_Pos) /*!< 0x00200000 */
9422 #define SYSCFG_CFGR1_I2C_FMP_I2C2            SYSCFG_CFGR1_I2C_FMP_I2C2_Msk     /*!< Enable I2C2 Fast mode plus  */
9423 #define SYSCFG_CFGR1_I2C_FMP_PA9_Pos         (22U)
9424 #define SYSCFG_CFGR1_I2C_FMP_PA9_Msk         (0x1UL << SYSCFG_CFGR1_I2C_FMP_PA9_Pos) /*!< 0x00400000 */
9425 #define SYSCFG_CFGR1_I2C_FMP_PA9             SYSCFG_CFGR1_I2C_FMP_PA9_Msk      /*!< Enable Fast Mode Plus on PA9  */
9426 #define SYSCFG_CFGR1_I2C_FMP_PA10_Pos        (23U)
9427 #define SYSCFG_CFGR1_I2C_FMP_PA10_Msk        (0x1UL << SYSCFG_CFGR1_I2C_FMP_PA10_Pos) /*!< 0x00800000 */
9428 #define SYSCFG_CFGR1_I2C_FMP_PA10            SYSCFG_CFGR1_I2C_FMP_PA10_Msk     /*!< Enable Fast Mode Plus on PA10 */
9429 
9430 /*****************  Bit definition for SYSCFG_EXTICR1 register  **************/
9431 #define SYSCFG_EXTICR1_EXTI0_Pos             (0U)
9432 #define SYSCFG_EXTICR1_EXTI0_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
9433 #define SYSCFG_EXTICR1_EXTI0                 SYSCFG_EXTICR1_EXTI0_Msk          /*!< EXTI 0 configuration */
9434 #define SYSCFG_EXTICR1_EXTI1_Pos             (4U)
9435 #define SYSCFG_EXTICR1_EXTI1_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
9436 #define SYSCFG_EXTICR1_EXTI1                 SYSCFG_EXTICR1_EXTI1_Msk          /*!< EXTI 1 configuration */
9437 #define SYSCFG_EXTICR1_EXTI2_Pos             (8U)
9438 #define SYSCFG_EXTICR1_EXTI2_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
9439 #define SYSCFG_EXTICR1_EXTI2                 SYSCFG_EXTICR1_EXTI2_Msk          /*!< EXTI 2 configuration */
9440 #define SYSCFG_EXTICR1_EXTI3_Pos             (12U)
9441 #define SYSCFG_EXTICR1_EXTI3_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
9442 #define SYSCFG_EXTICR1_EXTI3                 SYSCFG_EXTICR1_EXTI3_Msk          /*!< EXTI 3 configuration */
9443 
9444 /**
9445   * @brief  EXTI0 configuration
9446   */
9447 #define SYSCFG_EXTICR1_EXTI0_PA              (0x00000000U)                     /*!< PA[0] pin */
9448 #define SYSCFG_EXTICR1_EXTI0_PB              (0x00000001U)                     /*!< PB[0] pin */
9449 #define SYSCFG_EXTICR1_EXTI0_PC              (0x00000002U)                     /*!< PC[0] pin */
9450 #define SYSCFG_EXTICR1_EXTI0_PD              (0x00000003U)                     /*!< PD[0] pin */
9451 #define SYSCFG_EXTICR1_EXTI0_PE              (0x00000004U)                     /*!< PE[0] pin */
9452 #define SYSCFG_EXTICR1_EXTI0_PF              (0x00000005U)                     /*!< PF[0] pin */
9453 
9454 /**
9455   * @brief  EXTI1 configuration
9456   */
9457 #define SYSCFG_EXTICR1_EXTI1_PA              (0x00000000U)                     /*!< PA[1] pin */
9458 #define SYSCFG_EXTICR1_EXTI1_PB              (0x00000010U)                     /*!< PB[1] pin */
9459 #define SYSCFG_EXTICR1_EXTI1_PC              (0x00000020U)                     /*!< PC[1] pin */
9460 #define SYSCFG_EXTICR1_EXTI1_PD              (0x00000030U)                     /*!< PD[1] pin */
9461 #define SYSCFG_EXTICR1_EXTI1_PE              (0x00000040U)                     /*!< PE[1] pin */
9462 #define SYSCFG_EXTICR1_EXTI1_PF              (0x00000050U)                     /*!< PF[1] pin */
9463 
9464 /**
9465   * @brief  EXTI2 configuration
9466   */
9467 #define SYSCFG_EXTICR1_EXTI2_PA              (0x00000000U)                     /*!< PA[2] pin */
9468 #define SYSCFG_EXTICR1_EXTI2_PB              (0x00000100U)                     /*!< PB[2] pin */
9469 #define SYSCFG_EXTICR1_EXTI2_PC              (0x00000200U)                     /*!< PC[2] pin */
9470 #define SYSCFG_EXTICR1_EXTI2_PD              (0x00000300U)                     /*!< PD[2] pin */
9471 #define SYSCFG_EXTICR1_EXTI2_PE              (0x00000400U)                     /*!< PE[2] pin */
9472 #define SYSCFG_EXTICR1_EXTI2_PF              (0x00000500U)                     /*!< PF[2] pin */
9473 
9474 /**
9475   * @brief  EXTI3 configuration
9476   */
9477 #define SYSCFG_EXTICR1_EXTI3_PA              (0x00000000U)                     /*!< PA[3] pin */
9478 #define SYSCFG_EXTICR1_EXTI3_PB              (0x00001000U)                     /*!< PB[3] pin */
9479 #define SYSCFG_EXTICR1_EXTI3_PC              (0x00002000U)                     /*!< PC[3] pin */
9480 #define SYSCFG_EXTICR1_EXTI3_PD              (0x00003000U)                     /*!< PD[3] pin */
9481 #define SYSCFG_EXTICR1_EXTI3_PE              (0x00004000U)                     /*!< PE[3] pin */
9482 #define SYSCFG_EXTICR1_EXTI3_PF              (0x00005000U)                     /*!< PF[3] pin */
9483 
9484 /*****************  Bit definition for SYSCFG_EXTICR2 register  **************/
9485 #define SYSCFG_EXTICR2_EXTI4_Pos             (0U)
9486 #define SYSCFG_EXTICR2_EXTI4_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
9487 #define SYSCFG_EXTICR2_EXTI4                 SYSCFG_EXTICR2_EXTI4_Msk          /*!< EXTI 4 configuration */
9488 #define SYSCFG_EXTICR2_EXTI5_Pos             (4U)
9489 #define SYSCFG_EXTICR2_EXTI5_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
9490 #define SYSCFG_EXTICR2_EXTI5                 SYSCFG_EXTICR2_EXTI5_Msk          /*!< EXTI 5 configuration */
9491 #define SYSCFG_EXTICR2_EXTI6_Pos             (8U)
9492 #define SYSCFG_EXTICR2_EXTI6_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
9493 #define SYSCFG_EXTICR2_EXTI6                 SYSCFG_EXTICR2_EXTI6_Msk          /*!< EXTI 6 configuration */
9494 #define SYSCFG_EXTICR2_EXTI7_Pos             (12U)
9495 #define SYSCFG_EXTICR2_EXTI7_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
9496 #define SYSCFG_EXTICR2_EXTI7                 SYSCFG_EXTICR2_EXTI7_Msk          /*!< EXTI 7 configuration */
9497 
9498 /**
9499   * @brief  EXTI4 configuration
9500   */
9501 #define SYSCFG_EXTICR2_EXTI4_PA              (0x00000000U)                     /*!< PA[4] pin */
9502 #define SYSCFG_EXTICR2_EXTI4_PB              (0x00000001U)                     /*!< PB[4] pin */
9503 #define SYSCFG_EXTICR2_EXTI4_PC              (0x00000002U)                     /*!< PC[4] pin */
9504 #define SYSCFG_EXTICR2_EXTI4_PD              (0x00000003U)                     /*!< PD[4] pin */
9505 #define SYSCFG_EXTICR2_EXTI4_PE              (0x00000004U)                     /*!< PE[4] pin */
9506 #define SYSCFG_EXTICR2_EXTI4_PF              (0x00000005U)                     /*!< PF[4] pin */
9507 
9508 /**
9509   * @brief  EXTI5 configuration
9510   */
9511 #define SYSCFG_EXTICR2_EXTI5_PA              (0x00000000U)                     /*!< PA[5] pin */
9512 #define SYSCFG_EXTICR2_EXTI5_PB              (0x00000010U)                     /*!< PB[5] pin */
9513 #define SYSCFG_EXTICR2_EXTI5_PC              (0x00000020U)                     /*!< PC[5] pin */
9514 #define SYSCFG_EXTICR2_EXTI5_PD              (0x00000030U)                     /*!< PD[5] pin */
9515 #define SYSCFG_EXTICR2_EXTI5_PE              (0x00000040U)                     /*!< PE[5] pin */
9516 #define SYSCFG_EXTICR2_EXTI5_PF              (0x00000050U)                     /*!< PF[5] pin */
9517 
9518 /**
9519   * @brief  EXTI6 configuration
9520   */
9521 #define SYSCFG_EXTICR2_EXTI6_PA              (0x00000000U)                     /*!< PA[6] pin */
9522 #define SYSCFG_EXTICR2_EXTI6_PB              (0x00000100U)                     /*!< PB[6] pin */
9523 #define SYSCFG_EXTICR2_EXTI6_PC              (0x00000200U)                     /*!< PC[6] pin */
9524 #define SYSCFG_EXTICR2_EXTI6_PD              (0x00000300U)                     /*!< PD[6] pin */
9525 #define SYSCFG_EXTICR2_EXTI6_PE              (0x00000400U)                     /*!< PE[6] pin */
9526 #define SYSCFG_EXTICR2_EXTI6_PF              (0x00000500U)                     /*!< PF[6] pin */
9527 
9528 /**
9529   * @brief  EXTI7 configuration
9530   */
9531 #define SYSCFG_EXTICR2_EXTI7_PA              (0x00000000U)                     /*!< PA[7] pin */
9532 #define SYSCFG_EXTICR2_EXTI7_PB              (0x00001000U)                     /*!< PB[7] pin */
9533 #define SYSCFG_EXTICR2_EXTI7_PC              (0x00002000U)                     /*!< PC[7] pin */
9534 #define SYSCFG_EXTICR2_EXTI7_PD              (0x00003000U)                     /*!< PD[7] pin */
9535 #define SYSCFG_EXTICR2_EXTI7_PE              (0x00004000U)                     /*!< PE[7] pin */
9536 #define SYSCFG_EXTICR2_EXTI7_PF              (0x00005000U)                     /*!< PF[7] pin */
9537 
9538 /*****************  Bit definition for SYSCFG_EXTICR3 register  **************/
9539 #define SYSCFG_EXTICR3_EXTI8_Pos             (0U)
9540 #define SYSCFG_EXTICR3_EXTI8_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
9541 #define SYSCFG_EXTICR3_EXTI8                 SYSCFG_EXTICR3_EXTI8_Msk          /*!< EXTI 8 configuration */
9542 #define SYSCFG_EXTICR3_EXTI9_Pos             (4U)
9543 #define SYSCFG_EXTICR3_EXTI9_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
9544 #define SYSCFG_EXTICR3_EXTI9                 SYSCFG_EXTICR3_EXTI9_Msk          /*!< EXTI 9 configuration */
9545 #define SYSCFG_EXTICR3_EXTI10_Pos            (8U)
9546 #define SYSCFG_EXTICR3_EXTI10_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
9547 #define SYSCFG_EXTICR3_EXTI10                SYSCFG_EXTICR3_EXTI10_Msk         /*!< EXTI 10 configuration */
9548 #define SYSCFG_EXTICR3_EXTI11_Pos            (12U)
9549 #define SYSCFG_EXTICR3_EXTI11_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
9550 #define SYSCFG_EXTICR3_EXTI11                SYSCFG_EXTICR3_EXTI11_Msk         /*!< EXTI 11 configuration */
9551 
9552 /**
9553   * @brief  EXTI8 configuration
9554   */
9555 #define SYSCFG_EXTICR3_EXTI8_PA              (0x00000000U)                     /*!< PA[8] pin */
9556 #define SYSCFG_EXTICR3_EXTI8_PB              (0x00000001U)                     /*!< PB[8] pin */
9557 #define SYSCFG_EXTICR3_EXTI8_PC              (0x00000002U)                     /*!< PC[8] pin */
9558 #define SYSCFG_EXTICR3_EXTI8_PD              (0x00000003U)                     /*!< PD[8] pin */
9559 #define SYSCFG_EXTICR3_EXTI8_PE              (0x00000004U)                     /*!< PE[8] pin */
9560 
9561 
9562 /**
9563   * @brief  EXTI9 configuration
9564   */
9565 #define SYSCFG_EXTICR3_EXTI9_PA              (0x00000000U)                     /*!< PA[9] pin */
9566 #define SYSCFG_EXTICR3_EXTI9_PB              (0x00000010U)                     /*!< PB[9] pin */
9567 #define SYSCFG_EXTICR3_EXTI9_PC              (0x00000020U)                     /*!< PC[9] pin */
9568 #define SYSCFG_EXTICR3_EXTI9_PD              (0x00000030U)                     /*!< PD[9] pin */
9569 #define SYSCFG_EXTICR3_EXTI9_PE              (0x00000040U)                     /*!< PE[9] pin */
9570 #define SYSCFG_EXTICR3_EXTI9_PF              (0x00000050U)                     /*!< PF[9] pin */
9571 
9572 /**
9573   * @brief  EXTI10 configuration
9574   */
9575 #define SYSCFG_EXTICR3_EXTI10_PA             (0x00000000U)                     /*!< PA[10] pin */
9576 #define SYSCFG_EXTICR3_EXTI10_PB             (0x00000100U)                     /*!< PB[10] pin */
9577 #define SYSCFG_EXTICR3_EXTI10_PC             (0x00000200U)                     /*!< PC[10] pin */
9578 #define SYSCFG_EXTICR3_EXTI10_PD             (0x00000300U)                     /*!< PD[10] pin */
9579 #define SYSCFG_EXTICR3_EXTI10_PE             (0x00000400U)                     /*!< PE[10] pin */
9580 #define SYSCFG_EXTICR3_EXTI10_PF             (0x00000500U)                     /*!< PF[10] pin */
9581 
9582 /**
9583   * @brief  EXTI11 configuration
9584   */
9585 #define SYSCFG_EXTICR3_EXTI11_PA             (0x00000000U)                     /*!< PA[11] pin */
9586 #define SYSCFG_EXTICR3_EXTI11_PB             (0x00001000U)                     /*!< PB[11] pin */
9587 #define SYSCFG_EXTICR3_EXTI11_PC             (0x00002000U)                     /*!< PC[11] pin */
9588 #define SYSCFG_EXTICR3_EXTI11_PD             (0x00003000U)                     /*!< PD[11] pin */
9589 #define SYSCFG_EXTICR3_EXTI11_PE             (0x00004000U)                     /*!< PE[11] pin */
9590 
9591 /*****************  Bit definition for SYSCFG_EXTICR4 register  **************/
9592 #define SYSCFG_EXTICR4_EXTI12_Pos            (0U)
9593 #define SYSCFG_EXTICR4_EXTI12_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
9594 #define SYSCFG_EXTICR4_EXTI12                SYSCFG_EXTICR4_EXTI12_Msk         /*!< EXTI 12 configuration */
9595 #define SYSCFG_EXTICR4_EXTI13_Pos            (4U)
9596 #define SYSCFG_EXTICR4_EXTI13_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
9597 #define SYSCFG_EXTICR4_EXTI13                SYSCFG_EXTICR4_EXTI13_Msk         /*!< EXTI 13 configuration */
9598 #define SYSCFG_EXTICR4_EXTI14_Pos            (8U)
9599 #define SYSCFG_EXTICR4_EXTI14_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
9600 #define SYSCFG_EXTICR4_EXTI14                SYSCFG_EXTICR4_EXTI14_Msk         /*!< EXTI 14 configuration */
9601 #define SYSCFG_EXTICR4_EXTI15_Pos            (12U)
9602 #define SYSCFG_EXTICR4_EXTI15_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
9603 #define SYSCFG_EXTICR4_EXTI15                SYSCFG_EXTICR4_EXTI15_Msk         /*!< EXTI 15 configuration */
9604 
9605 /**
9606   * @brief  EXTI12 configuration
9607   */
9608 #define SYSCFG_EXTICR4_EXTI12_PA             (0x00000000U)                     /*!< PA[12] pin */
9609 #define SYSCFG_EXTICR4_EXTI12_PB             (0x00000001U)                     /*!< PB[12] pin */
9610 #define SYSCFG_EXTICR4_EXTI12_PC             (0x00000002U)                     /*!< PC[12] pin */
9611 #define SYSCFG_EXTICR4_EXTI12_PD             (0x00000003U)                     /*!< PD[12] pin */
9612 #define SYSCFG_EXTICR4_EXTI12_PE             (0x00000004U)                     /*!< PE[12] pin */
9613 
9614 /**
9615   * @brief  EXTI13 configuration
9616   */
9617 #define SYSCFG_EXTICR4_EXTI13_PA             (0x00000000U)                     /*!< PA[13] pin */
9618 #define SYSCFG_EXTICR4_EXTI13_PB             (0x00000010U)                     /*!< PB[13] pin */
9619 #define SYSCFG_EXTICR4_EXTI13_PC             (0x00000020U)                     /*!< PC[13] pin */
9620 #define SYSCFG_EXTICR4_EXTI13_PD             (0x00000030U)                     /*!< PD[13] pin */
9621 #define SYSCFG_EXTICR4_EXTI13_PE             (0x00000040U)                     /*!< PE[13] pin */
9622 
9623 /**
9624   * @brief  EXTI14 configuration
9625   */
9626 #define SYSCFG_EXTICR4_EXTI14_PA             (0x00000000U)                     /*!< PA[14] pin */
9627 #define SYSCFG_EXTICR4_EXTI14_PB             (0x00000100U)                     /*!< PB[14] pin */
9628 #define SYSCFG_EXTICR4_EXTI14_PC             (0x00000200U)                     /*!< PC[14] pin */
9629 #define SYSCFG_EXTICR4_EXTI14_PD             (0x00000300U)                     /*!< PD[14] pin */
9630 #define SYSCFG_EXTICR4_EXTI14_PE             (0x00000400U)                     /*!< PE[14] pin */
9631 
9632 /**
9633   * @brief  EXTI15 configuration
9634   */
9635 #define SYSCFG_EXTICR4_EXTI15_PA             (0x00000000U)                     /*!< PA[15] pin */
9636 #define SYSCFG_EXTICR4_EXTI15_PB             (0x00001000U)                     /*!< PB[15] pin */
9637 #define SYSCFG_EXTICR4_EXTI15_PC             (0x00002000U)                     /*!< PC[15] pin */
9638 #define SYSCFG_EXTICR4_EXTI15_PD             (0x00003000U)                     /*!< PD[15] pin */
9639 #define SYSCFG_EXTICR4_EXTI15_PE             (0x00004000U)                     /*!< PE[15] pin */
9640 
9641 /*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
9642 #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos         (0U)
9643 #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk         (0x1UL << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */
9644 #define SYSCFG_CFGR2_LOCKUP_LOCK             SYSCFG_CFGR2_LOCKUP_LOCK_Msk      /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
9645 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos    (1U)
9646 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk    (0x1UL << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos) /*!< 0x00000002 */
9647 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK        SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
9648 #define SYSCFG_CFGR2_PVD_LOCK_Pos            (2U)
9649 #define SYSCFG_CFGR2_PVD_LOCK_Msk            (0x1UL << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */
9650 #define SYSCFG_CFGR2_PVD_LOCK                SYSCFG_CFGR2_PVD_LOCK_Msk         /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
9651 #define SYSCFG_CFGR2_SRAM_PEF_Pos            (8U)
9652 #define SYSCFG_CFGR2_SRAM_PEF_Msk            (0x1UL << SYSCFG_CFGR2_SRAM_PEF_Pos) /*!< 0x00000100 */
9653 #define SYSCFG_CFGR2_SRAM_PEF                SYSCFG_CFGR2_SRAM_PEF_Msk         /*!< SRAM Parity error flag */
9654 #define SYSCFG_CFGR2_SRAM_PE                 SYSCFG_CFGR2_SRAM_PEF  /*!< SRAM Parity error flag (define maintained for legacy purpose) */
9655 
9656 /*****************  Bit definition for SYSCFG_xxx ISR Wrapper register  ****************/
9657 #define SYSCFG_ITLINE0_SR_EWDG_Pos           (0U)
9658 #define SYSCFG_ITLINE0_SR_EWDG_Msk           (0x1UL << SYSCFG_ITLINE0_SR_EWDG_Pos) /*!< 0x00000001 */
9659 #define SYSCFG_ITLINE0_SR_EWDG               SYSCFG_ITLINE0_SR_EWDG_Msk        /*!< EWDG interrupt */
9660 #define SYSCFG_ITLINE1_SR_PVDOUT_Pos         (0U)
9661 #define SYSCFG_ITLINE1_SR_PVDOUT_Msk         (0x1UL << SYSCFG_ITLINE1_SR_PVDOUT_Pos) /*!< 0x00000001 */
9662 #define SYSCFG_ITLINE1_SR_PVDOUT             SYSCFG_ITLINE1_SR_PVDOUT_Msk      /*!< Power voltage detection -> exti[31] Interrupt */
9663 #define SYSCFG_ITLINE1_SR_VDDIO2_Pos         (1U)
9664 #define SYSCFG_ITLINE1_SR_VDDIO2_Msk         (0x1UL << SYSCFG_ITLINE1_SR_VDDIO2_Pos) /*!< 0x00000002 */
9665 #define SYSCFG_ITLINE1_SR_VDDIO2             SYSCFG_ITLINE1_SR_VDDIO2_Msk      /*!< VDDIO2 -> exti[16] Interrupt */
9666 #define SYSCFG_ITLINE2_SR_RTC_ALRA_Pos       (0U)
9667 #define SYSCFG_ITLINE2_SR_RTC_ALRA_Msk       (0x1UL << SYSCFG_ITLINE2_SR_RTC_ALRA_Pos) /*!< 0x00000001 */
9668 #define SYSCFG_ITLINE2_SR_RTC_ALRA           SYSCFG_ITLINE2_SR_RTC_ALRA_Msk    /*!< RTC Alarm -> exti[17] interrupt .... */
9669 #define SYSCFG_ITLINE2_SR_RTC_TSTAMP_Pos     (1U)
9670 #define SYSCFG_ITLINE2_SR_RTC_TSTAMP_Msk     (0x1UL << SYSCFG_ITLINE2_SR_RTC_TSTAMP_Pos) /*!< 0x00000002 */
9671 #define SYSCFG_ITLINE2_SR_RTC_TSTAMP         SYSCFG_ITLINE2_SR_RTC_TSTAMP_Msk  /*!< RTC Time Stamp -> exti[19] interrupt */
9672 #define SYSCFG_ITLINE2_SR_RTC_WAKEUP_Pos     (2U)
9673 #define SYSCFG_ITLINE2_SR_RTC_WAKEUP_Msk     (0x1UL << SYSCFG_ITLINE2_SR_RTC_WAKEUP_Pos) /*!< 0x00000004 */
9674 #define SYSCFG_ITLINE2_SR_RTC_WAKEUP         SYSCFG_ITLINE2_SR_RTC_WAKEUP_Msk  /*!< RTC WAKEUP -> exti[20] Interrupt */
9675 #define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos      (0U)
9676 #define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk      (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos) /*!< 0x00000001 */
9677 #define SYSCFG_ITLINE3_SR_FLASH_ITF          SYSCFG_ITLINE3_SR_FLASH_ITF_Msk   /*!< Flash ITF Interrupt */
9678 #define SYSCFG_ITLINE4_SR_CRS_Pos            (0U)
9679 #define SYSCFG_ITLINE4_SR_CRS_Msk            (0x1UL << SYSCFG_ITLINE4_SR_CRS_Pos) /*!< 0x00000001 */
9680 #define SYSCFG_ITLINE4_SR_CRS                SYSCFG_ITLINE4_SR_CRS_Msk         /*!< CRS interrupt */
9681 #define SYSCFG_ITLINE4_SR_CLK_CTRL_Pos       (1U)
9682 #define SYSCFG_ITLINE4_SR_CLK_CTRL_Msk       (0x1UL << SYSCFG_ITLINE4_SR_CLK_CTRL_Pos) /*!< 0x00000002 */
9683 #define SYSCFG_ITLINE4_SR_CLK_CTRL           SYSCFG_ITLINE4_SR_CLK_CTRL_Msk    /*!< CLK CTRL interrupt */
9684 #define SYSCFG_ITLINE5_SR_EXTI0_Pos          (0U)
9685 #define SYSCFG_ITLINE5_SR_EXTI0_Msk          (0x1UL << SYSCFG_ITLINE5_SR_EXTI0_Pos) /*!< 0x00000001 */
9686 #define SYSCFG_ITLINE5_SR_EXTI0              SYSCFG_ITLINE5_SR_EXTI0_Msk       /*!< External Interrupt 0 */
9687 #define SYSCFG_ITLINE5_SR_EXTI1_Pos          (1U)
9688 #define SYSCFG_ITLINE5_SR_EXTI1_Msk          (0x1UL << SYSCFG_ITLINE5_SR_EXTI1_Pos) /*!< 0x00000002 */
9689 #define SYSCFG_ITLINE5_SR_EXTI1              SYSCFG_ITLINE5_SR_EXTI1_Msk       /*!< External Interrupt 1 */
9690 #define SYSCFG_ITLINE6_SR_EXTI2_Pos          (0U)
9691 #define SYSCFG_ITLINE6_SR_EXTI2_Msk          (0x1UL << SYSCFG_ITLINE6_SR_EXTI2_Pos) /*!< 0x00000001 */
9692 #define SYSCFG_ITLINE6_SR_EXTI2              SYSCFG_ITLINE6_SR_EXTI2_Msk       /*!< External Interrupt 2 */
9693 #define SYSCFG_ITLINE6_SR_EXTI3_Pos          (1U)
9694 #define SYSCFG_ITLINE6_SR_EXTI3_Msk          (0x1UL << SYSCFG_ITLINE6_SR_EXTI3_Pos) /*!< 0x00000002 */
9695 #define SYSCFG_ITLINE6_SR_EXTI3              SYSCFG_ITLINE6_SR_EXTI3_Msk       /*!< External Interrupt 3 */
9696 #define SYSCFG_ITLINE7_SR_EXTI4_Pos          (0U)
9697 #define SYSCFG_ITLINE7_SR_EXTI4_Msk          (0x1UL << SYSCFG_ITLINE7_SR_EXTI4_Pos) /*!< 0x00000001 */
9698 #define SYSCFG_ITLINE7_SR_EXTI4              SYSCFG_ITLINE7_SR_EXTI4_Msk       /*!< External Interrupt 15 to 4 */
9699 #define SYSCFG_ITLINE7_SR_EXTI5_Pos          (1U)
9700 #define SYSCFG_ITLINE7_SR_EXTI5_Msk          (0x1UL << SYSCFG_ITLINE7_SR_EXTI5_Pos) /*!< 0x00000002 */
9701 #define SYSCFG_ITLINE7_SR_EXTI5              SYSCFG_ITLINE7_SR_EXTI5_Msk       /*!< External Interrupt 15 to 4 */
9702 #define SYSCFG_ITLINE7_SR_EXTI6_Pos          (2U)
9703 #define SYSCFG_ITLINE7_SR_EXTI6_Msk          (0x1UL << SYSCFG_ITLINE7_SR_EXTI6_Pos) /*!< 0x00000004 */
9704 #define SYSCFG_ITLINE7_SR_EXTI6              SYSCFG_ITLINE7_SR_EXTI6_Msk       /*!< External Interrupt 15 to 4 */
9705 #define SYSCFG_ITLINE7_SR_EXTI7_Pos          (3U)
9706 #define SYSCFG_ITLINE7_SR_EXTI7_Msk          (0x1UL << SYSCFG_ITLINE7_SR_EXTI7_Pos) /*!< 0x00000008 */
9707 #define SYSCFG_ITLINE7_SR_EXTI7              SYSCFG_ITLINE7_SR_EXTI7_Msk       /*!< External Interrupt 15 to 4 */
9708 #define SYSCFG_ITLINE7_SR_EXTI8_Pos          (4U)
9709 #define SYSCFG_ITLINE7_SR_EXTI8_Msk          (0x1UL << SYSCFG_ITLINE7_SR_EXTI8_Pos) /*!< 0x00000010 */
9710 #define SYSCFG_ITLINE7_SR_EXTI8              SYSCFG_ITLINE7_SR_EXTI8_Msk       /*!< External Interrupt 15 to 4 */
9711 #define SYSCFG_ITLINE7_SR_EXTI9_Pos          (5U)
9712 #define SYSCFG_ITLINE7_SR_EXTI9_Msk          (0x1UL << SYSCFG_ITLINE7_SR_EXTI9_Pos) /*!< 0x00000020 */
9713 #define SYSCFG_ITLINE7_SR_EXTI9              SYSCFG_ITLINE7_SR_EXTI9_Msk       /*!< External Interrupt 15 to 4 */
9714 #define SYSCFG_ITLINE7_SR_EXTI10_Pos         (6U)
9715 #define SYSCFG_ITLINE7_SR_EXTI10_Msk         (0x1UL << SYSCFG_ITLINE7_SR_EXTI10_Pos) /*!< 0x00000040 */
9716 #define SYSCFG_ITLINE7_SR_EXTI10             SYSCFG_ITLINE7_SR_EXTI10_Msk      /*!< External Interrupt 15 to 4 */
9717 #define SYSCFG_ITLINE7_SR_EXTI11_Pos         (7U)
9718 #define SYSCFG_ITLINE7_SR_EXTI11_Msk         (0x1UL << SYSCFG_ITLINE7_SR_EXTI11_Pos) /*!< 0x00000080 */
9719 #define SYSCFG_ITLINE7_SR_EXTI11             SYSCFG_ITLINE7_SR_EXTI11_Msk      /*!< External Interrupt 15 to 4 */
9720 #define SYSCFG_ITLINE7_SR_EXTI12_Pos         (8U)
9721 #define SYSCFG_ITLINE7_SR_EXTI12_Msk         (0x1UL << SYSCFG_ITLINE7_SR_EXTI12_Pos) /*!< 0x00000100 */
9722 #define SYSCFG_ITLINE7_SR_EXTI12             SYSCFG_ITLINE7_SR_EXTI12_Msk      /*!< External Interrupt 15 to 4 */
9723 #define SYSCFG_ITLINE7_SR_EXTI13_Pos         (9U)
9724 #define SYSCFG_ITLINE7_SR_EXTI13_Msk         (0x1UL << SYSCFG_ITLINE7_SR_EXTI13_Pos) /*!< 0x00000200 */
9725 #define SYSCFG_ITLINE7_SR_EXTI13             SYSCFG_ITLINE7_SR_EXTI13_Msk      /*!< External Interrupt 15 to 4 */
9726 #define SYSCFG_ITLINE7_SR_EXTI14_Pos         (10U)
9727 #define SYSCFG_ITLINE7_SR_EXTI14_Msk         (0x1UL << SYSCFG_ITLINE7_SR_EXTI14_Pos) /*!< 0x00000400 */
9728 #define SYSCFG_ITLINE7_SR_EXTI14             SYSCFG_ITLINE7_SR_EXTI14_Msk      /*!< External Interrupt 15 to 4 */
9729 #define SYSCFG_ITLINE7_SR_EXTI15_Pos         (11U)
9730 #define SYSCFG_ITLINE7_SR_EXTI15_Msk         (0x1UL << SYSCFG_ITLINE7_SR_EXTI15_Pos) /*!< 0x00000800 */
9731 #define SYSCFG_ITLINE7_SR_EXTI15             SYSCFG_ITLINE7_SR_EXTI15_Msk      /*!< External Interrupt 15 to 4 */
9732 #define SYSCFG_ITLINE8_SR_TSC_EOA_Pos        (0U)
9733 #define SYSCFG_ITLINE8_SR_TSC_EOA_Msk        (0x1UL << SYSCFG_ITLINE8_SR_TSC_EOA_Pos) /*!< 0x00000001 */
9734 #define SYSCFG_ITLINE8_SR_TSC_EOA            SYSCFG_ITLINE8_SR_TSC_EOA_Msk     /*!< Touch control EOA Interrupt */
9735 #define SYSCFG_ITLINE8_SR_TSC_MCE_Pos        (1U)
9736 #define SYSCFG_ITLINE8_SR_TSC_MCE_Msk        (0x1UL << SYSCFG_ITLINE8_SR_TSC_MCE_Pos) /*!< 0x00000002 */
9737 #define SYSCFG_ITLINE8_SR_TSC_MCE            SYSCFG_ITLINE8_SR_TSC_MCE_Msk     /*!< Touch control MCE Interrupt */
9738 #define SYSCFG_ITLINE9_SR_DMA1_CH1_Pos       (0U)
9739 #define SYSCFG_ITLINE9_SR_DMA1_CH1_Msk       (0x1UL << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos) /*!< 0x00000001 */
9740 #define SYSCFG_ITLINE9_SR_DMA1_CH1           SYSCFG_ITLINE9_SR_DMA1_CH1_Msk    /*!< DMA1 Channel 1 Interrupt */
9741 #define SYSCFG_ITLINE10_SR_DMA1_CH2_Pos      (0U)
9742 #define SYSCFG_ITLINE10_SR_DMA1_CH2_Msk      (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos) /*!< 0x00000001 */
9743 #define SYSCFG_ITLINE10_SR_DMA1_CH2          SYSCFG_ITLINE10_SR_DMA1_CH2_Msk   /*!< DMA1 Channel 2 Interrupt */
9744 #define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos      (1U)
9745 #define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk      (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */
9746 #define SYSCFG_ITLINE10_SR_DMA1_CH3          SYSCFG_ITLINE10_SR_DMA1_CH3_Msk   /*!< DMA2 Channel 3 Interrupt */
9747 #define SYSCFG_ITLINE10_SR_DMA2_CH1_Pos      (2U)
9748 #define SYSCFG_ITLINE10_SR_DMA2_CH1_Msk      (0x1UL << SYSCFG_ITLINE10_SR_DMA2_CH1_Pos) /*!< 0x00000004 */
9749 #define SYSCFG_ITLINE10_SR_DMA2_CH1          SYSCFG_ITLINE10_SR_DMA2_CH1_Msk   /*!< DMA2 Channel 1 Interrupt */
9750 #define SYSCFG_ITLINE10_SR_DMA2_CH2_Pos      (3U)
9751 #define SYSCFG_ITLINE10_SR_DMA2_CH2_Msk      (0x1UL << SYSCFG_ITLINE10_SR_DMA2_CH2_Pos) /*!< 0x00000008 */
9752 #define SYSCFG_ITLINE10_SR_DMA2_CH2          SYSCFG_ITLINE10_SR_DMA2_CH2_Msk   /*!< DMA2 Channel 2 Interrupt */
9753 #define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos      (0U)
9754 #define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk      (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos) /*!< 0x00000001 */
9755 #define SYSCFG_ITLINE11_SR_DMA1_CH4          SYSCFG_ITLINE11_SR_DMA1_CH4_Msk   /*!< DMA1 Channel 4 Interrupt */
9756 #define SYSCFG_ITLINE11_SR_DMA1_CH5_Pos      (1U)
9757 #define SYSCFG_ITLINE11_SR_DMA1_CH5_Msk      (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH5_Pos) /*!< 0x00000002 */
9758 #define SYSCFG_ITLINE11_SR_DMA1_CH5          SYSCFG_ITLINE11_SR_DMA1_CH5_Msk   /*!< DMA1 Channel 5 Interrupt */
9759 #define SYSCFG_ITLINE11_SR_DMA1_CH6_Pos      (2U)
9760 #define SYSCFG_ITLINE11_SR_DMA1_CH6_Msk      (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH6_Pos) /*!< 0x00000004 */
9761 #define SYSCFG_ITLINE11_SR_DMA1_CH6          SYSCFG_ITLINE11_SR_DMA1_CH6_Msk   /*!< DMA1 Channel 6 Interrupt */
9762 #define SYSCFG_ITLINE11_SR_DMA1_CH7_Pos      (3U)
9763 #define SYSCFG_ITLINE11_SR_DMA1_CH7_Msk      (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH7_Pos) /*!< 0x00000008 */
9764 #define SYSCFG_ITLINE11_SR_DMA1_CH7          SYSCFG_ITLINE11_SR_DMA1_CH7_Msk   /*!< DMA1 Channel 7 Interrupt */
9765 #define SYSCFG_ITLINE11_SR_DMA2_CH3_Pos      (4U)
9766 #define SYSCFG_ITLINE11_SR_DMA2_CH3_Msk      (0x1UL << SYSCFG_ITLINE11_SR_DMA2_CH3_Pos) /*!< 0x00000010 */
9767 #define SYSCFG_ITLINE11_SR_DMA2_CH3          SYSCFG_ITLINE11_SR_DMA2_CH3_Msk   /*!< DMA2 Channel 3 Interrupt */
9768 #define SYSCFG_ITLINE11_SR_DMA2_CH4_Pos      (5U)
9769 #define SYSCFG_ITLINE11_SR_DMA2_CH4_Msk      (0x1UL << SYSCFG_ITLINE11_SR_DMA2_CH4_Pos) /*!< 0x00000020 */
9770 #define SYSCFG_ITLINE11_SR_DMA2_CH4          SYSCFG_ITLINE11_SR_DMA2_CH4_Msk   /*!< DMA2 Channel 4 Interrupt */
9771 #define SYSCFG_ITLINE11_SR_DMA2_CH5_Pos      (6U)
9772 #define SYSCFG_ITLINE11_SR_DMA2_CH5_Msk      (0x1UL << SYSCFG_ITLINE11_SR_DMA2_CH5_Pos) /*!< 0x00000040 */
9773 #define SYSCFG_ITLINE11_SR_DMA2_CH5          SYSCFG_ITLINE11_SR_DMA2_CH5_Msk   /*!< DMA2 Channel 5 Interrupt */
9774 #define SYSCFG_ITLINE12_SR_ADC_Pos           (0U)
9775 #define SYSCFG_ITLINE12_SR_ADC_Msk           (0x1UL << SYSCFG_ITLINE12_SR_ADC_Pos) /*!< 0x00000001 */
9776 #define SYSCFG_ITLINE12_SR_ADC               SYSCFG_ITLINE12_SR_ADC_Msk        /*!< ADC Interrupt */
9777 #define SYSCFG_ITLINE12_SR_COMP1_Pos         (1U)
9778 #define SYSCFG_ITLINE12_SR_COMP1_Msk         (0x1UL << SYSCFG_ITLINE12_SR_COMP1_Pos) /*!< 0x00000002 */
9779 #define SYSCFG_ITLINE12_SR_COMP1             SYSCFG_ITLINE12_SR_COMP1_Msk      /*!< COMP1 Interrupt -> exti[21] */
9780 #define SYSCFG_ITLINE12_SR_COMP2_Pos         (2U)
9781 #define SYSCFG_ITLINE12_SR_COMP2_Msk         (0x1UL << SYSCFG_ITLINE12_SR_COMP2_Pos) /*!< 0x00000004 */
9782 #define SYSCFG_ITLINE12_SR_COMP2             SYSCFG_ITLINE12_SR_COMP2_Msk      /*!< COMP2 Interrupt -> exti[22] */
9783 #define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos      (0U)
9784 #define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk      (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000001 */
9785 #define SYSCFG_ITLINE13_SR_TIM1_BRK          SYSCFG_ITLINE13_SR_TIM1_BRK_Msk   /*!< TIM1 BRK Interrupt */
9786 #define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos      (1U)
9787 #define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk      (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000002 */
9788 #define SYSCFG_ITLINE13_SR_TIM1_UPD          SYSCFG_ITLINE13_SR_TIM1_UPD_Msk   /*!< TIM1 UPD Interrupt */
9789 #define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos      (2U)
9790 #define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk      (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000004 */
9791 #define SYSCFG_ITLINE13_SR_TIM1_TRG          SYSCFG_ITLINE13_SR_TIM1_TRG_Msk   /*!< TIM1 TRG Interrupt */
9792 #define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos      (3U)
9793 #define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk      (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000008 */
9794 #define SYSCFG_ITLINE13_SR_TIM1_CCU          SYSCFG_ITLINE13_SR_TIM1_CCU_Msk   /*!< TIM1 CCU Interrupt */
9795 #define SYSCFG_ITLINE14_SR_TIM1_CC_Pos       (0U)
9796 #define SYSCFG_ITLINE14_SR_TIM1_CC_Msk       (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC_Pos) /*!< 0x00000001 */
9797 #define SYSCFG_ITLINE14_SR_TIM1_CC           SYSCFG_ITLINE14_SR_TIM1_CC_Msk    /*!< TIM1 CC Interrupt */
9798 #define SYSCFG_ITLINE15_SR_TIM2_GLB_Pos      (0U)
9799 #define SYSCFG_ITLINE15_SR_TIM2_GLB_Msk      (0x1UL << SYSCFG_ITLINE15_SR_TIM2_GLB_Pos) /*!< 0x00000001 */
9800 #define SYSCFG_ITLINE15_SR_TIM2_GLB          SYSCFG_ITLINE15_SR_TIM2_GLB_Msk   /*!< TIM2 GLB Interrupt */
9801 #define SYSCFG_ITLINE16_SR_TIM3_GLB_Pos      (0U)
9802 #define SYSCFG_ITLINE16_SR_TIM3_GLB_Msk      (0x1UL << SYSCFG_ITLINE16_SR_TIM3_GLB_Pos) /*!< 0x00000001 */
9803 #define SYSCFG_ITLINE16_SR_TIM3_GLB          SYSCFG_ITLINE16_SR_TIM3_GLB_Msk   /*!< TIM3 GLB Interrupt */
9804 #define SYSCFG_ITLINE17_SR_DAC_Pos           (0U)
9805 #define SYSCFG_ITLINE17_SR_DAC_Msk           (0x1UL << SYSCFG_ITLINE17_SR_DAC_Pos) /*!< 0x00000001 */
9806 #define SYSCFG_ITLINE17_SR_DAC               SYSCFG_ITLINE17_SR_DAC_Msk        /*!< DAC Interrupt */
9807 #define SYSCFG_ITLINE17_SR_TIM6_GLB_Pos      (1U)
9808 #define SYSCFG_ITLINE17_SR_TIM6_GLB_Msk      (0x1UL << SYSCFG_ITLINE17_SR_TIM6_GLB_Pos) /*!< 0x00000002 */
9809 #define SYSCFG_ITLINE17_SR_TIM6_GLB          SYSCFG_ITLINE17_SR_TIM6_GLB_Msk   /*!< TIM6 GLB Interrupt */
9810 #define SYSCFG_ITLINE18_SR_TIM7_GLB_Pos      (0U)
9811 #define SYSCFG_ITLINE18_SR_TIM7_GLB_Msk      (0x1UL << SYSCFG_ITLINE18_SR_TIM7_GLB_Pos) /*!< 0x00000001 */
9812 #define SYSCFG_ITLINE18_SR_TIM7_GLB          SYSCFG_ITLINE18_SR_TIM7_GLB_Msk   /*!< TIM7 GLB Interrupt */
9813 #define SYSCFG_ITLINE19_SR_TIM14_GLB_Pos     (0U)
9814 #define SYSCFG_ITLINE19_SR_TIM14_GLB_Msk     (0x1UL << SYSCFG_ITLINE19_SR_TIM14_GLB_Pos) /*!< 0x00000001 */
9815 #define SYSCFG_ITLINE19_SR_TIM14_GLB         SYSCFG_ITLINE19_SR_TIM14_GLB_Msk  /*!< TIM14 GLB Interrupt */
9816 #define SYSCFG_ITLINE20_SR_TIM15_GLB_Pos     (0U)
9817 #define SYSCFG_ITLINE20_SR_TIM15_GLB_Msk     (0x1UL << SYSCFG_ITLINE20_SR_TIM15_GLB_Pos) /*!< 0x00000001 */
9818 #define SYSCFG_ITLINE20_SR_TIM15_GLB         SYSCFG_ITLINE20_SR_TIM15_GLB_Msk  /*!< TIM15 GLB Interrupt */
9819 #define SYSCFG_ITLINE21_SR_TIM16_GLB_Pos     (0U)
9820 #define SYSCFG_ITLINE21_SR_TIM16_GLB_Msk     (0x1UL << SYSCFG_ITLINE21_SR_TIM16_GLB_Pos) /*!< 0x00000001 */
9821 #define SYSCFG_ITLINE21_SR_TIM16_GLB         SYSCFG_ITLINE21_SR_TIM16_GLB_Msk  /*!< TIM16 GLB Interrupt */
9822 #define SYSCFG_ITLINE22_SR_TIM17_GLB_Pos     (0U)
9823 #define SYSCFG_ITLINE22_SR_TIM17_GLB_Msk     (0x1UL << SYSCFG_ITLINE22_SR_TIM17_GLB_Pos) /*!< 0x00000001 */
9824 #define SYSCFG_ITLINE22_SR_TIM17_GLB         SYSCFG_ITLINE22_SR_TIM17_GLB_Msk  /*!< TIM17 GLB Interrupt */
9825 #define SYSCFG_ITLINE23_SR_I2C1_GLB_Pos      (0U)
9826 #define SYSCFG_ITLINE23_SR_I2C1_GLB_Msk      (0x1UL << SYSCFG_ITLINE23_SR_I2C1_GLB_Pos) /*!< 0x00000001 */
9827 #define SYSCFG_ITLINE23_SR_I2C1_GLB          SYSCFG_ITLINE23_SR_I2C1_GLB_Msk   /*!< I2C1 GLB Interrupt -> exti[23] */
9828 #define SYSCFG_ITLINE24_SR_I2C2_GLB_Pos      (0U)
9829 #define SYSCFG_ITLINE24_SR_I2C2_GLB_Msk      (0x1UL << SYSCFG_ITLINE24_SR_I2C2_GLB_Pos) /*!< 0x00000001 */
9830 #define SYSCFG_ITLINE24_SR_I2C2_GLB          SYSCFG_ITLINE24_SR_I2C2_GLB_Msk   /*!< I2C2 GLB Interrupt */
9831 #define SYSCFG_ITLINE25_SR_SPI1_Pos          (0U)
9832 #define SYSCFG_ITLINE25_SR_SPI1_Msk          (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */
9833 #define SYSCFG_ITLINE25_SR_SPI1              SYSCFG_ITLINE25_SR_SPI1_Msk       /*!< SPI1 Interrupt */
9834 #define SYSCFG_ITLINE26_SR_SPI2_Pos          (0U)
9835 #define SYSCFG_ITLINE26_SR_SPI2_Msk          (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */
9836 #define SYSCFG_ITLINE26_SR_SPI2              SYSCFG_ITLINE26_SR_SPI2_Msk       /*!< SPI2  Interrupt */
9837 #define SYSCFG_ITLINE27_SR_USART1_GLB_Pos    (0U)
9838 #define SYSCFG_ITLINE27_SR_USART1_GLB_Msk    (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */
9839 #define SYSCFG_ITLINE27_SR_USART1_GLB        SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt -> exti[25] */
9840 #define SYSCFG_ITLINE28_SR_USART2_GLB_Pos    (0U)
9841 #define SYSCFG_ITLINE28_SR_USART2_GLB_Msk    (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */
9842 #define SYSCFG_ITLINE28_SR_USART2_GLB        SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt -> exti[26] */
9843 #define SYSCFG_ITLINE29_SR_USART3_GLB_Pos    (0U)
9844 #define SYSCFG_ITLINE29_SR_USART3_GLB_Msk    (0x1UL << SYSCFG_ITLINE29_SR_USART3_GLB_Pos) /*!< 0x00000001 */
9845 #define SYSCFG_ITLINE29_SR_USART3_GLB        SYSCFG_ITLINE29_SR_USART3_GLB_Msk /*!< USART3 GLB Interrupt -> exti[28] */
9846 #define SYSCFG_ITLINE29_SR_USART4_GLB_Pos    (1U)
9847 #define SYSCFG_ITLINE29_SR_USART4_GLB_Msk    (0x1UL << SYSCFG_ITLINE29_SR_USART4_GLB_Pos) /*!< 0x00000002 */
9848 #define SYSCFG_ITLINE29_SR_USART4_GLB        SYSCFG_ITLINE29_SR_USART4_GLB_Msk /*!< USART4 GLB Interrupt */
9849 #define SYSCFG_ITLINE29_SR_USART5_GLB_Pos    (2U)
9850 #define SYSCFG_ITLINE29_SR_USART5_GLB_Msk    (0x1UL << SYSCFG_ITLINE29_SR_USART5_GLB_Pos) /*!< 0x00000004 */
9851 #define SYSCFG_ITLINE29_SR_USART5_GLB        SYSCFG_ITLINE29_SR_USART5_GLB_Msk /*!< USART5 GLB Interrupt */
9852 #define SYSCFG_ITLINE29_SR_USART6_GLB_Pos    (3U)
9853 #define SYSCFG_ITLINE29_SR_USART6_GLB_Msk    (0x1UL << SYSCFG_ITLINE29_SR_USART6_GLB_Pos) /*!< 0x00000008 */
9854 #define SYSCFG_ITLINE29_SR_USART6_GLB        SYSCFG_ITLINE29_SR_USART6_GLB_Msk /*!< USART6 GLB Interrupt */
9855 #define SYSCFG_ITLINE29_SR_USART7_GLB_Pos    (4U)
9856 #define SYSCFG_ITLINE29_SR_USART7_GLB_Msk    (0x1UL << SYSCFG_ITLINE29_SR_USART7_GLB_Pos) /*!< 0x00000010 */
9857 #define SYSCFG_ITLINE29_SR_USART7_GLB        SYSCFG_ITLINE29_SR_USART7_GLB_Msk /*!< USART7 GLB Interrupt */
9858 #define SYSCFG_ITLINE29_SR_USART8_GLB_Pos    (5U)
9859 #define SYSCFG_ITLINE29_SR_USART8_GLB_Msk    (0x1UL << SYSCFG_ITLINE29_SR_USART8_GLB_Pos) /*!< 0x00000020 */
9860 #define SYSCFG_ITLINE29_SR_USART8_GLB        SYSCFG_ITLINE29_SR_USART8_GLB_Msk /*!< USART8 GLB Interrupt */
9861 #define SYSCFG_ITLINE30_SR_CAN_Pos           (0U)
9862 #define SYSCFG_ITLINE30_SR_CAN_Msk           (0x1UL << SYSCFG_ITLINE30_SR_CAN_Pos) /*!< 0x00000001 */
9863 #define SYSCFG_ITLINE30_SR_CAN               SYSCFG_ITLINE30_SR_CAN_Msk        /*!< CAN Interrupt */
9864 #define SYSCFG_ITLINE30_SR_CEC_Pos           (1U)
9865 #define SYSCFG_ITLINE30_SR_CEC_Msk           (0x1UL << SYSCFG_ITLINE30_SR_CEC_Pos) /*!< 0x00000002 */
9866 #define SYSCFG_ITLINE30_SR_CEC               SYSCFG_ITLINE30_SR_CEC_Msk        /*!< CEC Interrupt */
9867 
9868 /*****************************************************************************/
9869 /*                                                                           */
9870 /*                               Timers (TIM)                                */
9871 /*                                                                           */
9872 /*****************************************************************************/
9873 /*******************  Bit definition for TIM_CR1 register  *******************/
9874 #define TIM_CR1_CEN_Pos           (0U)
9875 #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
9876 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
9877 #define TIM_CR1_UDIS_Pos          (1U)
9878 #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
9879 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
9880 #define TIM_CR1_URS_Pos           (2U)
9881 #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
9882 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
9883 #define TIM_CR1_OPM_Pos           (3U)
9884 #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
9885 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
9886 #define TIM_CR1_DIR_Pos           (4U)
9887 #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
9888 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
9889 
9890 #define TIM_CR1_CMS_Pos           (5U)
9891 #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
9892 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
9893 #define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
9894 #define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
9895 
9896 #define TIM_CR1_ARPE_Pos          (7U)
9897 #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
9898 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
9899 
9900 #define TIM_CR1_CKD_Pos           (8U)
9901 #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
9902 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
9903 #define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
9904 #define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
9905 
9906 /*******************  Bit definition for TIM_CR2 register  *******************/
9907 #define TIM_CR2_CCPC_Pos          (0U)
9908 #define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */
9909 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
9910 #define TIM_CR2_CCUS_Pos          (2U)
9911 #define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */
9912 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
9913 #define TIM_CR2_CCDS_Pos          (3U)
9914 #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
9915 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
9916 
9917 #define TIM_CR2_MMS_Pos           (4U)
9918 #define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
9919 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
9920 #define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
9921 #define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
9922 #define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
9923 
9924 #define TIM_CR2_TI1S_Pos          (7U)
9925 #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
9926 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
9927 #define TIM_CR2_OIS1_Pos          (8U)
9928 #define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */
9929 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
9930 #define TIM_CR2_OIS1N_Pos         (9U)
9931 #define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */
9932 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
9933 #define TIM_CR2_OIS2_Pos          (10U)
9934 #define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */
9935 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
9936 #define TIM_CR2_OIS2N_Pos         (11U)
9937 #define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */
9938 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
9939 #define TIM_CR2_OIS3_Pos          (12U)
9940 #define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */
9941 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
9942 #define TIM_CR2_OIS3N_Pos         (13U)
9943 #define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */
9944 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
9945 #define TIM_CR2_OIS4_Pos          (14U)
9946 #define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */
9947 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
9948 
9949 /*******************  Bit definition for TIM_SMCR register  ******************/
9950 #define TIM_SMCR_SMS_Pos          (0U)
9951 #define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
9952 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
9953 #define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000001 */
9954 #define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000002 */
9955 #define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000004 */
9956 
9957 #define TIM_SMCR_OCCS_Pos         (3U)
9958 #define TIM_SMCR_OCCS_Msk         (0x1UL << TIM_SMCR_OCCS_Pos)                  /*!< 0x00000008 */
9959 #define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
9960 
9961 #define TIM_SMCR_TS_Pos           (4U)
9962 #define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
9963 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
9964 #define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
9965 #define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
9966 #define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
9967 
9968 #define TIM_SMCR_MSM_Pos          (7U)
9969 #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
9970 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
9971 
9972 #define TIM_SMCR_ETF_Pos          (8U)
9973 #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
9974 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
9975 #define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
9976 #define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
9977 #define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
9978 #define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
9979 
9980 #define TIM_SMCR_ETPS_Pos         (12U)
9981 #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
9982 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
9983 #define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
9984 #define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
9985 
9986 #define TIM_SMCR_ECE_Pos          (14U)
9987 #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
9988 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
9989 #define TIM_SMCR_ETP_Pos          (15U)
9990 #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
9991 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
9992 
9993 /*******************  Bit definition for TIM_DIER register  ******************/
9994 #define TIM_DIER_UIE_Pos          (0U)
9995 #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
9996 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
9997 #define TIM_DIER_CC1IE_Pos        (1U)
9998 #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
9999 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
10000 #define TIM_DIER_CC2IE_Pos        (2U)
10001 #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
10002 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
10003 #define TIM_DIER_CC3IE_Pos        (3U)
10004 #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
10005 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
10006 #define TIM_DIER_CC4IE_Pos        (4U)
10007 #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
10008 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
10009 #define TIM_DIER_COMIE_Pos        (5U)
10010 #define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */
10011 #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
10012 #define TIM_DIER_TIE_Pos          (6U)
10013 #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
10014 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
10015 #define TIM_DIER_BIE_Pos          (7U)
10016 #define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */
10017 #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
10018 #define TIM_DIER_UDE_Pos          (8U)
10019 #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
10020 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
10021 #define TIM_DIER_CC1DE_Pos        (9U)
10022 #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
10023 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
10024 #define TIM_DIER_CC2DE_Pos        (10U)
10025 #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
10026 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
10027 #define TIM_DIER_CC3DE_Pos        (11U)
10028 #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
10029 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
10030 #define TIM_DIER_CC4DE_Pos        (12U)
10031 #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
10032 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
10033 #define TIM_DIER_COMDE_Pos        (13U)
10034 #define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */
10035 #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
10036 #define TIM_DIER_TDE_Pos          (14U)
10037 #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
10038 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
10039 
10040 /********************  Bit definition for TIM_SR register  *******************/
10041 #define TIM_SR_UIF_Pos            (0U)
10042 #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
10043 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
10044 #define TIM_SR_CC1IF_Pos          (1U)
10045 #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
10046 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
10047 #define TIM_SR_CC2IF_Pos          (2U)
10048 #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
10049 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
10050 #define TIM_SR_CC3IF_Pos          (3U)
10051 #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
10052 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
10053 #define TIM_SR_CC4IF_Pos          (4U)
10054 #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
10055 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
10056 #define TIM_SR_COMIF_Pos          (5U)
10057 #define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */
10058 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
10059 #define TIM_SR_TIF_Pos            (6U)
10060 #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
10061 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
10062 #define TIM_SR_BIF_Pos            (7U)
10063 #define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */
10064 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
10065 #define TIM_SR_CC1OF_Pos          (9U)
10066 #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
10067 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
10068 #define TIM_SR_CC2OF_Pos          (10U)
10069 #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
10070 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
10071 #define TIM_SR_CC3OF_Pos          (11U)
10072 #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
10073 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
10074 #define TIM_SR_CC4OF_Pos          (12U)
10075 #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
10076 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
10077 
10078 /*******************  Bit definition for TIM_EGR register  *******************/
10079 #define TIM_EGR_UG_Pos            (0U)
10080 #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
10081 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
10082 #define TIM_EGR_CC1G_Pos          (1U)
10083 #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
10084 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
10085 #define TIM_EGR_CC2G_Pos          (2U)
10086 #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
10087 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
10088 #define TIM_EGR_CC3G_Pos          (3U)
10089 #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
10090 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
10091 #define TIM_EGR_CC4G_Pos          (4U)
10092 #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
10093 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
10094 #define TIM_EGR_COMG_Pos          (5U)
10095 #define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */
10096 #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
10097 #define TIM_EGR_TG_Pos            (6U)
10098 #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
10099 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
10100 #define TIM_EGR_BG_Pos            (7U)
10101 #define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */
10102 #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
10103 
10104 /******************  Bit definition for TIM_CCMR1 register  ******************/
10105 #define TIM_CCMR1_CC1S_Pos        (0U)
10106 #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
10107 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
10108 #define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
10109 #define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
10110 
10111 #define TIM_CCMR1_OC1FE_Pos       (2U)
10112 #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
10113 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
10114 #define TIM_CCMR1_OC1PE_Pos       (3U)
10115 #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
10116 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
10117 
10118 #define TIM_CCMR1_OC1M_Pos        (4U)
10119 #define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
10120 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
10121 #define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000010 */
10122 #define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000020 */
10123 #define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000040 */
10124 
10125 #define TIM_CCMR1_OC1CE_Pos       (7U)
10126 #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
10127 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
10128 
10129 #define TIM_CCMR1_CC2S_Pos        (8U)
10130 #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
10131 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
10132 #define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
10133 #define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
10134 
10135 #define TIM_CCMR1_OC2FE_Pos       (10U)
10136 #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
10137 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
10138 #define TIM_CCMR1_OC2PE_Pos       (11U)
10139 #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
10140 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
10141 
10142 #define TIM_CCMR1_OC2M_Pos        (12U)
10143 #define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
10144 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
10145 #define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00001000 */
10146 #define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00002000 */
10147 #define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00004000 */
10148 
10149 #define TIM_CCMR1_OC2CE_Pos       (15U)
10150 #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
10151 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
10152 
10153 /*---------------------------------------------------------------------------*/
10154 
10155 #define TIM_CCMR1_IC1PSC_Pos      (2U)
10156 #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
10157 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
10158 #define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
10159 #define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
10160 
10161 #define TIM_CCMR1_IC1F_Pos        (4U)
10162 #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
10163 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
10164 #define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
10165 #define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
10166 #define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
10167 #define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
10168 
10169 #define TIM_CCMR1_IC2PSC_Pos      (10U)
10170 #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
10171 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
10172 #define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
10173 #define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
10174 
10175 #define TIM_CCMR1_IC2F_Pos        (12U)
10176 #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
10177 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
10178 #define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
10179 #define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
10180 #define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
10181 #define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
10182 
10183 /******************  Bit definition for TIM_CCMR2 register  ******************/
10184 #define TIM_CCMR2_CC3S_Pos        (0U)
10185 #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
10186 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
10187 #define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
10188 #define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
10189 
10190 #define TIM_CCMR2_OC3FE_Pos       (2U)
10191 #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
10192 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
10193 #define TIM_CCMR2_OC3PE_Pos       (3U)
10194 #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
10195 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
10196 
10197 #define TIM_CCMR2_OC3M_Pos        (4U)
10198 #define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
10199 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
10200 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
10201 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
10202 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
10203 
10204 #define TIM_CCMR2_OC3CE_Pos       (7U)
10205 #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
10206 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
10207 
10208 #define TIM_CCMR2_CC4S_Pos        (8U)
10209 #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
10210 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
10211 #define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
10212 #define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
10213 
10214 #define TIM_CCMR2_OC4FE_Pos       (10U)
10215 #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
10216 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
10217 #define TIM_CCMR2_OC4PE_Pos       (11U)
10218 #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
10219 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
10220 
10221 #define TIM_CCMR2_OC4M_Pos        (12U)
10222 #define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
10223 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
10224 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
10225 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
10226 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
10227 
10228 #define TIM_CCMR2_OC4CE_Pos       (15U)
10229 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
10230 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
10231 
10232 /*---------------------------------------------------------------------------*/
10233 
10234 #define TIM_CCMR2_IC3PSC_Pos      (2U)
10235 #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
10236 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
10237 #define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
10238 #define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
10239 
10240 #define TIM_CCMR2_IC3F_Pos        (4U)
10241 #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
10242 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
10243 #define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
10244 #define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
10245 #define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
10246 #define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
10247 
10248 #define TIM_CCMR2_IC4PSC_Pos      (10U)
10249 #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
10250 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
10251 #define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
10252 #define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
10253 
10254 #define TIM_CCMR2_IC4F_Pos        (12U)
10255 #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
10256 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
10257 #define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
10258 #define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
10259 #define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
10260 #define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
10261 
10262 /*******************  Bit definition for TIM_CCER register  ******************/
10263 #define TIM_CCER_CC1E_Pos         (0U)
10264 #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
10265 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
10266 #define TIM_CCER_CC1P_Pos         (1U)
10267 #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
10268 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
10269 #define TIM_CCER_CC1NE_Pos        (2U)
10270 #define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */
10271 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
10272 #define TIM_CCER_CC1NP_Pos        (3U)
10273 #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
10274 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
10275 #define TIM_CCER_CC2E_Pos         (4U)
10276 #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
10277 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
10278 #define TIM_CCER_CC2P_Pos         (5U)
10279 #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
10280 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
10281 #define TIM_CCER_CC2NE_Pos        (6U)
10282 #define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */
10283 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
10284 #define TIM_CCER_CC2NP_Pos        (7U)
10285 #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
10286 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
10287 #define TIM_CCER_CC3E_Pos         (8U)
10288 #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
10289 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
10290 #define TIM_CCER_CC3P_Pos         (9U)
10291 #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
10292 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
10293 #define TIM_CCER_CC3NE_Pos        (10U)
10294 #define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */
10295 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
10296 #define TIM_CCER_CC3NP_Pos        (11U)
10297 #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
10298 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
10299 #define TIM_CCER_CC4E_Pos         (12U)
10300 #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
10301 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
10302 #define TIM_CCER_CC4P_Pos         (13U)
10303 #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
10304 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
10305 #define TIM_CCER_CC4NP_Pos        (15U)
10306 #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
10307 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
10308 
10309 /*******************  Bit definition for TIM_CNT register  *******************/
10310 #define TIM_CNT_CNT_Pos           (0U)
10311 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)             /*!< 0xFFFFFFFF */
10312 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
10313 
10314 /*******************  Bit definition for TIM_PSC register  *******************/
10315 #define TIM_PSC_PSC_Pos           (0U)
10316 #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
10317 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
10318 
10319 /*******************  Bit definition for TIM_ARR register  *******************/
10320 #define TIM_ARR_ARR_Pos           (0U)
10321 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */
10322 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
10323 
10324 /*******************  Bit definition for TIM_RCR register  *******************/
10325 #define TIM_RCR_REP_Pos           (0U)
10326 #define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                   /*!< 0x000000FF */
10327 #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
10328 
10329 /*******************  Bit definition for TIM_CCR1 register  ******************/
10330 #define TIM_CCR1_CCR1_Pos         (0U)
10331 #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
10332 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
10333 
10334 /*******************  Bit definition for TIM_CCR2 register  ******************/
10335 #define TIM_CCR2_CCR2_Pos         (0U)
10336 #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
10337 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
10338 
10339 /*******************  Bit definition for TIM_CCR3 register  ******************/
10340 #define TIM_CCR3_CCR3_Pos         (0U)
10341 #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
10342 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
10343 
10344 /*******************  Bit definition for TIM_CCR4 register  ******************/
10345 #define TIM_CCR4_CCR4_Pos         (0U)
10346 #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
10347 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
10348 
10349 /*******************  Bit definition for TIM_BDTR register  ******************/
10350 #define TIM_BDTR_DTG_Pos          (0U)
10351 #define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */
10352 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
10353 #define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */
10354 #define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */
10355 #define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */
10356 #define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */
10357 #define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */
10358 #define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */
10359 #define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */
10360 #define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */
10361 
10362 #define TIM_BDTR_LOCK_Pos         (8U)
10363 #define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */
10364 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
10365 #define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */
10366 #define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */
10367 
10368 #define TIM_BDTR_OSSI_Pos         (10U)
10369 #define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */
10370 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
10371 #define TIM_BDTR_OSSR_Pos         (11U)
10372 #define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */
10373 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
10374 #define TIM_BDTR_BKE_Pos          (12U)
10375 #define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */
10376 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable */
10377 #define TIM_BDTR_BKP_Pos          (13U)
10378 #define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */
10379 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity */
10380 #define TIM_BDTR_AOE_Pos          (14U)
10381 #define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */
10382 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
10383 #define TIM_BDTR_MOE_Pos          (15U)
10384 #define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */
10385 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
10386 
10387 /*******************  Bit definition for TIM_DCR register  *******************/
10388 #define TIM_DCR_DBA_Pos           (0U)
10389 #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
10390 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
10391 #define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
10392 #define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
10393 #define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
10394 #define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
10395 #define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
10396 
10397 #define TIM_DCR_DBL_Pos           (8U)
10398 #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
10399 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
10400 #define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
10401 #define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
10402 #define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
10403 #define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
10404 #define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
10405 
10406 /*******************  Bit definition for TIM_DMAR register  ******************/
10407 #define TIM_DMAR_DMAB_Pos         (0U)
10408 #define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
10409 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
10410 
10411 /*******************  Bit definition for TIM14_OR register  ********************/
10412 #define TIM14_OR_TI1_RMP_Pos      (0U)
10413 #define TIM14_OR_TI1_RMP_Msk      (0x3UL << TIM14_OR_TI1_RMP_Pos)               /*!< 0x00000003 */
10414 #define TIM14_OR_TI1_RMP          TIM14_OR_TI1_RMP_Msk                         /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
10415 #define TIM14_OR_TI1_RMP_0        (0x1UL << TIM14_OR_TI1_RMP_Pos)               /*!< 0x00000001 */
10416 #define TIM14_OR_TI1_RMP_1        (0x2UL << TIM14_OR_TI1_RMP_Pos)               /*!< 0x00000002 */
10417 
10418 /******************************************************************************/
10419 /*                                                                            */
10420 /*                          Touch Sensing Controller (TSC)                    */
10421 /*                                                                            */
10422 /******************************************************************************/
10423 /*******************  Bit definition for TSC_CR register  *********************/
10424 #define TSC_CR_TSCE_Pos          (0U)
10425 #define TSC_CR_TSCE_Msk          (0x1UL << TSC_CR_TSCE_Pos)                     /*!< 0x00000001 */
10426 #define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
10427 #define TSC_CR_START_Pos         (1U)
10428 #define TSC_CR_START_Msk         (0x1UL << TSC_CR_START_Pos)                    /*!< 0x00000002 */
10429 #define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
10430 #define TSC_CR_AM_Pos            (2U)
10431 #define TSC_CR_AM_Msk            (0x1UL << TSC_CR_AM_Pos)                       /*!< 0x00000004 */
10432 #define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
10433 #define TSC_CR_SYNCPOL_Pos       (3U)
10434 #define TSC_CR_SYNCPOL_Msk       (0x1UL << TSC_CR_SYNCPOL_Pos)                  /*!< 0x00000008 */
10435 #define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
10436 #define TSC_CR_IODEF_Pos         (4U)
10437 #define TSC_CR_IODEF_Msk         (0x1UL << TSC_CR_IODEF_Pos)                    /*!< 0x00000010 */
10438 #define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
10439 
10440 #define TSC_CR_MCV_Pos           (5U)
10441 #define TSC_CR_MCV_Msk           (0x7UL << TSC_CR_MCV_Pos)                      /*!< 0x000000E0 */
10442 #define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
10443 #define TSC_CR_MCV_0             (0x1UL << TSC_CR_MCV_Pos)                      /*!< 0x00000020 */
10444 #define TSC_CR_MCV_1             (0x2UL << TSC_CR_MCV_Pos)                      /*!< 0x00000040 */
10445 #define TSC_CR_MCV_2             (0x4UL << TSC_CR_MCV_Pos)                      /*!< 0x00000080 */
10446 
10447 #define TSC_CR_PGPSC_Pos         (12U)
10448 #define TSC_CR_PGPSC_Msk         (0x7UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00007000 */
10449 #define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
10450 #define TSC_CR_PGPSC_0           (0x1UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00001000 */
10451 #define TSC_CR_PGPSC_1           (0x2UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00002000 */
10452 #define TSC_CR_PGPSC_2           (0x4UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00004000 */
10453 
10454 #define TSC_CR_SSPSC_Pos         (15U)
10455 #define TSC_CR_SSPSC_Msk         (0x1UL << TSC_CR_SSPSC_Pos)                    /*!< 0x00008000 */
10456 #define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
10457 #define TSC_CR_SSE_Pos           (16U)
10458 #define TSC_CR_SSE_Msk           (0x1UL << TSC_CR_SSE_Pos)                      /*!< 0x00010000 */
10459 #define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
10460 
10461 #define TSC_CR_SSD_Pos           (17U)
10462 #define TSC_CR_SSD_Msk           (0x7FUL << TSC_CR_SSD_Pos)                     /*!< 0x00FE0000 */
10463 #define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
10464 #define TSC_CR_SSD_0             (0x01UL << TSC_CR_SSD_Pos)                     /*!< 0x00020000 */
10465 #define TSC_CR_SSD_1             (0x02UL << TSC_CR_SSD_Pos)                     /*!< 0x00040000 */
10466 #define TSC_CR_SSD_2             (0x04UL << TSC_CR_SSD_Pos)                     /*!< 0x00080000 */
10467 #define TSC_CR_SSD_3             (0x08UL << TSC_CR_SSD_Pos)                     /*!< 0x00100000 */
10468 #define TSC_CR_SSD_4             (0x10UL << TSC_CR_SSD_Pos)                     /*!< 0x00200000 */
10469 #define TSC_CR_SSD_5             (0x20UL << TSC_CR_SSD_Pos)                     /*!< 0x00400000 */
10470 #define TSC_CR_SSD_6             (0x40UL << TSC_CR_SSD_Pos)                     /*!< 0x00800000 */
10471 
10472 #define TSC_CR_CTPL_Pos          (24U)
10473 #define TSC_CR_CTPL_Msk          (0xFUL << TSC_CR_CTPL_Pos)                     /*!< 0x0F000000 */
10474 #define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
10475 #define TSC_CR_CTPL_0            (0x1UL << TSC_CR_CTPL_Pos)                     /*!< 0x01000000 */
10476 #define TSC_CR_CTPL_1            (0x2UL << TSC_CR_CTPL_Pos)                     /*!< 0x02000000 */
10477 #define TSC_CR_CTPL_2            (0x4UL << TSC_CR_CTPL_Pos)                     /*!< 0x04000000 */
10478 #define TSC_CR_CTPL_3            (0x8UL << TSC_CR_CTPL_Pos)                     /*!< 0x08000000 */
10479 
10480 #define TSC_CR_CTPH_Pos          (28U)
10481 #define TSC_CR_CTPH_Msk          (0xFUL << TSC_CR_CTPH_Pos)                     /*!< 0xF0000000 */
10482 #define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
10483 #define TSC_CR_CTPH_0            (0x1UL << TSC_CR_CTPH_Pos)                     /*!< 0x10000000 */
10484 #define TSC_CR_CTPH_1            (0x2UL << TSC_CR_CTPH_Pos)                     /*!< 0x20000000 */
10485 #define TSC_CR_CTPH_2            (0x4UL << TSC_CR_CTPH_Pos)                     /*!< 0x40000000 */
10486 #define TSC_CR_CTPH_3            (0x8UL << TSC_CR_CTPH_Pos)                     /*!< 0x80000000 */
10487 
10488 /*******************  Bit definition for TSC_IER register  ********************/
10489 #define TSC_IER_EOAIE_Pos        (0U)
10490 #define TSC_IER_EOAIE_Msk        (0x1UL << TSC_IER_EOAIE_Pos)                   /*!< 0x00000001 */
10491 #define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
10492 #define TSC_IER_MCEIE_Pos        (1U)
10493 #define TSC_IER_MCEIE_Msk        (0x1UL << TSC_IER_MCEIE_Pos)                   /*!< 0x00000002 */
10494 #define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
10495 
10496 /*******************  Bit definition for TSC_ICR register  ********************/
10497 #define TSC_ICR_EOAIC_Pos        (0U)
10498 #define TSC_ICR_EOAIC_Msk        (0x1UL << TSC_ICR_EOAIC_Pos)                   /*!< 0x00000001 */
10499 #define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
10500 #define TSC_ICR_MCEIC_Pos        (1U)
10501 #define TSC_ICR_MCEIC_Msk        (0x1UL << TSC_ICR_MCEIC_Pos)                   /*!< 0x00000002 */
10502 #define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
10503 
10504 /*******************  Bit definition for TSC_ISR register  ********************/
10505 #define TSC_ISR_EOAF_Pos         (0U)
10506 #define TSC_ISR_EOAF_Msk         (0x1UL << TSC_ISR_EOAF_Pos)                    /*!< 0x00000001 */
10507 #define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
10508 #define TSC_ISR_MCEF_Pos         (1U)
10509 #define TSC_ISR_MCEF_Msk         (0x1UL << TSC_ISR_MCEF_Pos)                    /*!< 0x00000002 */
10510 #define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
10511 
10512 /*******************  Bit definition for TSC_IOHCR register  ******************/
10513 #define TSC_IOHCR_G1_IO1_Pos     (0U)
10514 #define TSC_IOHCR_G1_IO1_Msk     (0x1UL << TSC_IOHCR_G1_IO1_Pos)                /*!< 0x00000001 */
10515 #define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
10516 #define TSC_IOHCR_G1_IO2_Pos     (1U)
10517 #define TSC_IOHCR_G1_IO2_Msk     (0x1UL << TSC_IOHCR_G1_IO2_Pos)                /*!< 0x00000002 */
10518 #define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
10519 #define TSC_IOHCR_G1_IO3_Pos     (2U)
10520 #define TSC_IOHCR_G1_IO3_Msk     (0x1UL << TSC_IOHCR_G1_IO3_Pos)                /*!< 0x00000004 */
10521 #define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
10522 #define TSC_IOHCR_G1_IO4_Pos     (3U)
10523 #define TSC_IOHCR_G1_IO4_Msk     (0x1UL << TSC_IOHCR_G1_IO4_Pos)                /*!< 0x00000008 */
10524 #define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
10525 #define TSC_IOHCR_G2_IO1_Pos     (4U)
10526 #define TSC_IOHCR_G2_IO1_Msk     (0x1UL << TSC_IOHCR_G2_IO1_Pos)                /*!< 0x00000010 */
10527 #define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
10528 #define TSC_IOHCR_G2_IO2_Pos     (5U)
10529 #define TSC_IOHCR_G2_IO2_Msk     (0x1UL << TSC_IOHCR_G2_IO2_Pos)                /*!< 0x00000020 */
10530 #define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
10531 #define TSC_IOHCR_G2_IO3_Pos     (6U)
10532 #define TSC_IOHCR_G2_IO3_Msk     (0x1UL << TSC_IOHCR_G2_IO3_Pos)                /*!< 0x00000040 */
10533 #define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
10534 #define TSC_IOHCR_G2_IO4_Pos     (7U)
10535 #define TSC_IOHCR_G2_IO4_Msk     (0x1UL << TSC_IOHCR_G2_IO4_Pos)                /*!< 0x00000080 */
10536 #define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
10537 #define TSC_IOHCR_G3_IO1_Pos     (8U)
10538 #define TSC_IOHCR_G3_IO1_Msk     (0x1UL << TSC_IOHCR_G3_IO1_Pos)                /*!< 0x00000100 */
10539 #define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
10540 #define TSC_IOHCR_G3_IO2_Pos     (9U)
10541 #define TSC_IOHCR_G3_IO2_Msk     (0x1UL << TSC_IOHCR_G3_IO2_Pos)                /*!< 0x00000200 */
10542 #define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
10543 #define TSC_IOHCR_G3_IO3_Pos     (10U)
10544 #define TSC_IOHCR_G3_IO3_Msk     (0x1UL << TSC_IOHCR_G3_IO3_Pos)                /*!< 0x00000400 */
10545 #define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
10546 #define TSC_IOHCR_G3_IO4_Pos     (11U)
10547 #define TSC_IOHCR_G3_IO4_Msk     (0x1UL << TSC_IOHCR_G3_IO4_Pos)                /*!< 0x00000800 */
10548 #define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
10549 #define TSC_IOHCR_G4_IO1_Pos     (12U)
10550 #define TSC_IOHCR_G4_IO1_Msk     (0x1UL << TSC_IOHCR_G4_IO1_Pos)                /*!< 0x00001000 */
10551 #define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
10552 #define TSC_IOHCR_G4_IO2_Pos     (13U)
10553 #define TSC_IOHCR_G4_IO2_Msk     (0x1UL << TSC_IOHCR_G4_IO2_Pos)                /*!< 0x00002000 */
10554 #define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
10555 #define TSC_IOHCR_G4_IO3_Pos     (14U)
10556 #define TSC_IOHCR_G4_IO3_Msk     (0x1UL << TSC_IOHCR_G4_IO3_Pos)                /*!< 0x00004000 */
10557 #define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
10558 #define TSC_IOHCR_G4_IO4_Pos     (15U)
10559 #define TSC_IOHCR_G4_IO4_Msk     (0x1UL << TSC_IOHCR_G4_IO4_Pos)                /*!< 0x00008000 */
10560 #define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
10561 #define TSC_IOHCR_G5_IO1_Pos     (16U)
10562 #define TSC_IOHCR_G5_IO1_Msk     (0x1UL << TSC_IOHCR_G5_IO1_Pos)                /*!< 0x00010000 */
10563 #define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
10564 #define TSC_IOHCR_G5_IO2_Pos     (17U)
10565 #define TSC_IOHCR_G5_IO2_Msk     (0x1UL << TSC_IOHCR_G5_IO2_Pos)                /*!< 0x00020000 */
10566 #define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
10567 #define TSC_IOHCR_G5_IO3_Pos     (18U)
10568 #define TSC_IOHCR_G5_IO3_Msk     (0x1UL << TSC_IOHCR_G5_IO3_Pos)                /*!< 0x00040000 */
10569 #define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
10570 #define TSC_IOHCR_G5_IO4_Pos     (19U)
10571 #define TSC_IOHCR_G5_IO4_Msk     (0x1UL << TSC_IOHCR_G5_IO4_Pos)                /*!< 0x00080000 */
10572 #define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
10573 #define TSC_IOHCR_G6_IO1_Pos     (20U)
10574 #define TSC_IOHCR_G6_IO1_Msk     (0x1UL << TSC_IOHCR_G6_IO1_Pos)                /*!< 0x00100000 */
10575 #define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
10576 #define TSC_IOHCR_G6_IO2_Pos     (21U)
10577 #define TSC_IOHCR_G6_IO2_Msk     (0x1UL << TSC_IOHCR_G6_IO2_Pos)                /*!< 0x00200000 */
10578 #define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
10579 #define TSC_IOHCR_G6_IO3_Pos     (22U)
10580 #define TSC_IOHCR_G6_IO3_Msk     (0x1UL << TSC_IOHCR_G6_IO3_Pos)                /*!< 0x00400000 */
10581 #define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
10582 #define TSC_IOHCR_G6_IO4_Pos     (23U)
10583 #define TSC_IOHCR_G6_IO4_Msk     (0x1UL << TSC_IOHCR_G6_IO4_Pos)                /*!< 0x00800000 */
10584 #define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
10585 #define TSC_IOHCR_G7_IO1_Pos     (24U)
10586 #define TSC_IOHCR_G7_IO1_Msk     (0x1UL << TSC_IOHCR_G7_IO1_Pos)                /*!< 0x01000000 */
10587 #define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
10588 #define TSC_IOHCR_G7_IO2_Pos     (25U)
10589 #define TSC_IOHCR_G7_IO2_Msk     (0x1UL << TSC_IOHCR_G7_IO2_Pos)                /*!< 0x02000000 */
10590 #define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
10591 #define TSC_IOHCR_G7_IO3_Pos     (26U)
10592 #define TSC_IOHCR_G7_IO3_Msk     (0x1UL << TSC_IOHCR_G7_IO3_Pos)                /*!< 0x04000000 */
10593 #define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
10594 #define TSC_IOHCR_G7_IO4_Pos     (27U)
10595 #define TSC_IOHCR_G7_IO4_Msk     (0x1UL << TSC_IOHCR_G7_IO4_Pos)                /*!< 0x08000000 */
10596 #define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
10597 #define TSC_IOHCR_G8_IO1_Pos     (28U)
10598 #define TSC_IOHCR_G8_IO1_Msk     (0x1UL << TSC_IOHCR_G8_IO1_Pos)                /*!< 0x10000000 */
10599 #define TSC_IOHCR_G8_IO1         TSC_IOHCR_G8_IO1_Msk                          /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
10600 #define TSC_IOHCR_G8_IO2_Pos     (29U)
10601 #define TSC_IOHCR_G8_IO2_Msk     (0x1UL << TSC_IOHCR_G8_IO2_Pos)                /*!< 0x20000000 */
10602 #define TSC_IOHCR_G8_IO2         TSC_IOHCR_G8_IO2_Msk                          /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
10603 #define TSC_IOHCR_G8_IO3_Pos     (30U)
10604 #define TSC_IOHCR_G8_IO3_Msk     (0x1UL << TSC_IOHCR_G8_IO3_Pos)                /*!< 0x40000000 */
10605 #define TSC_IOHCR_G8_IO3         TSC_IOHCR_G8_IO3_Msk                          /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
10606 #define TSC_IOHCR_G8_IO4_Pos     (31U)
10607 #define TSC_IOHCR_G8_IO4_Msk     (0x1UL << TSC_IOHCR_G8_IO4_Pos)                /*!< 0x80000000 */
10608 #define TSC_IOHCR_G8_IO4         TSC_IOHCR_G8_IO4_Msk                          /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
10609 
10610 /*******************  Bit definition for TSC_IOASCR register  *****************/
10611 #define TSC_IOASCR_G1_IO1_Pos    (0U)
10612 #define TSC_IOASCR_G1_IO1_Msk    (0x1UL << TSC_IOASCR_G1_IO1_Pos)               /*!< 0x00000001 */
10613 #define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
10614 #define TSC_IOASCR_G1_IO2_Pos    (1U)
10615 #define TSC_IOASCR_G1_IO2_Msk    (0x1UL << TSC_IOASCR_G1_IO2_Pos)               /*!< 0x00000002 */
10616 #define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
10617 #define TSC_IOASCR_G1_IO3_Pos    (2U)
10618 #define TSC_IOASCR_G1_IO3_Msk    (0x1UL << TSC_IOASCR_G1_IO3_Pos)               /*!< 0x00000004 */
10619 #define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
10620 #define TSC_IOASCR_G1_IO4_Pos    (3U)
10621 #define TSC_IOASCR_G1_IO4_Msk    (0x1UL << TSC_IOASCR_G1_IO4_Pos)               /*!< 0x00000008 */
10622 #define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
10623 #define TSC_IOASCR_G2_IO1_Pos    (4U)
10624 #define TSC_IOASCR_G2_IO1_Msk    (0x1UL << TSC_IOASCR_G2_IO1_Pos)               /*!< 0x00000010 */
10625 #define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
10626 #define TSC_IOASCR_G2_IO2_Pos    (5U)
10627 #define TSC_IOASCR_G2_IO2_Msk    (0x1UL << TSC_IOASCR_G2_IO2_Pos)               /*!< 0x00000020 */
10628 #define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
10629 #define TSC_IOASCR_G2_IO3_Pos    (6U)
10630 #define TSC_IOASCR_G2_IO3_Msk    (0x1UL << TSC_IOASCR_G2_IO3_Pos)               /*!< 0x00000040 */
10631 #define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
10632 #define TSC_IOASCR_G2_IO4_Pos    (7U)
10633 #define TSC_IOASCR_G2_IO4_Msk    (0x1UL << TSC_IOASCR_G2_IO4_Pos)               /*!< 0x00000080 */
10634 #define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
10635 #define TSC_IOASCR_G3_IO1_Pos    (8U)
10636 #define TSC_IOASCR_G3_IO1_Msk    (0x1UL << TSC_IOASCR_G3_IO1_Pos)               /*!< 0x00000100 */
10637 #define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
10638 #define TSC_IOASCR_G3_IO2_Pos    (9U)
10639 #define TSC_IOASCR_G3_IO2_Msk    (0x1UL << TSC_IOASCR_G3_IO2_Pos)               /*!< 0x00000200 */
10640 #define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
10641 #define TSC_IOASCR_G3_IO3_Pos    (10U)
10642 #define TSC_IOASCR_G3_IO3_Msk    (0x1UL << TSC_IOASCR_G3_IO3_Pos)               /*!< 0x00000400 */
10643 #define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
10644 #define TSC_IOASCR_G3_IO4_Pos    (11U)
10645 #define TSC_IOASCR_G3_IO4_Msk    (0x1UL << TSC_IOASCR_G3_IO4_Pos)               /*!< 0x00000800 */
10646 #define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
10647 #define TSC_IOASCR_G4_IO1_Pos    (12U)
10648 #define TSC_IOASCR_G4_IO1_Msk    (0x1UL << TSC_IOASCR_G4_IO1_Pos)               /*!< 0x00001000 */
10649 #define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
10650 #define TSC_IOASCR_G4_IO2_Pos    (13U)
10651 #define TSC_IOASCR_G4_IO2_Msk    (0x1UL << TSC_IOASCR_G4_IO2_Pos)               /*!< 0x00002000 */
10652 #define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
10653 #define TSC_IOASCR_G4_IO3_Pos    (14U)
10654 #define TSC_IOASCR_G4_IO3_Msk    (0x1UL << TSC_IOASCR_G4_IO3_Pos)               /*!< 0x00004000 */
10655 #define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
10656 #define TSC_IOASCR_G4_IO4_Pos    (15U)
10657 #define TSC_IOASCR_G4_IO4_Msk    (0x1UL << TSC_IOASCR_G4_IO4_Pos)               /*!< 0x00008000 */
10658 #define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
10659 #define TSC_IOASCR_G5_IO1_Pos    (16U)
10660 #define TSC_IOASCR_G5_IO1_Msk    (0x1UL << TSC_IOASCR_G5_IO1_Pos)               /*!< 0x00010000 */
10661 #define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
10662 #define TSC_IOASCR_G5_IO2_Pos    (17U)
10663 #define TSC_IOASCR_G5_IO2_Msk    (0x1UL << TSC_IOASCR_G5_IO2_Pos)               /*!< 0x00020000 */
10664 #define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
10665 #define TSC_IOASCR_G5_IO3_Pos    (18U)
10666 #define TSC_IOASCR_G5_IO3_Msk    (0x1UL << TSC_IOASCR_G5_IO3_Pos)               /*!< 0x00040000 */
10667 #define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
10668 #define TSC_IOASCR_G5_IO4_Pos    (19U)
10669 #define TSC_IOASCR_G5_IO4_Msk    (0x1UL << TSC_IOASCR_G5_IO4_Pos)               /*!< 0x00080000 */
10670 #define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
10671 #define TSC_IOASCR_G6_IO1_Pos    (20U)
10672 #define TSC_IOASCR_G6_IO1_Msk    (0x1UL << TSC_IOASCR_G6_IO1_Pos)               /*!< 0x00100000 */
10673 #define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
10674 #define TSC_IOASCR_G6_IO2_Pos    (21U)
10675 #define TSC_IOASCR_G6_IO2_Msk    (0x1UL << TSC_IOASCR_G6_IO2_Pos)               /*!< 0x00200000 */
10676 #define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
10677 #define TSC_IOASCR_G6_IO3_Pos    (22U)
10678 #define TSC_IOASCR_G6_IO3_Msk    (0x1UL << TSC_IOASCR_G6_IO3_Pos)               /*!< 0x00400000 */
10679 #define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
10680 #define TSC_IOASCR_G6_IO4_Pos    (23U)
10681 #define TSC_IOASCR_G6_IO4_Msk    (0x1UL << TSC_IOASCR_G6_IO4_Pos)               /*!< 0x00800000 */
10682 #define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
10683 #define TSC_IOASCR_G7_IO1_Pos    (24U)
10684 #define TSC_IOASCR_G7_IO1_Msk    (0x1UL << TSC_IOASCR_G7_IO1_Pos)               /*!< 0x01000000 */
10685 #define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
10686 #define TSC_IOASCR_G7_IO2_Pos    (25U)
10687 #define TSC_IOASCR_G7_IO2_Msk    (0x1UL << TSC_IOASCR_G7_IO2_Pos)               /*!< 0x02000000 */
10688 #define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
10689 #define TSC_IOASCR_G7_IO3_Pos    (26U)
10690 #define TSC_IOASCR_G7_IO3_Msk    (0x1UL << TSC_IOASCR_G7_IO3_Pos)               /*!< 0x04000000 */
10691 #define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
10692 #define TSC_IOASCR_G7_IO4_Pos    (27U)
10693 #define TSC_IOASCR_G7_IO4_Msk    (0x1UL << TSC_IOASCR_G7_IO4_Pos)               /*!< 0x08000000 */
10694 #define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
10695 #define TSC_IOASCR_G8_IO1_Pos    (28U)
10696 #define TSC_IOASCR_G8_IO1_Msk    (0x1UL << TSC_IOASCR_G8_IO1_Pos)               /*!< 0x10000000 */
10697 #define TSC_IOASCR_G8_IO1        TSC_IOASCR_G8_IO1_Msk                         /*!<GROUP8_IO1 analog switch enable */
10698 #define TSC_IOASCR_G8_IO2_Pos    (29U)
10699 #define TSC_IOASCR_G8_IO2_Msk    (0x1UL << TSC_IOASCR_G8_IO2_Pos)               /*!< 0x20000000 */
10700 #define TSC_IOASCR_G8_IO2        TSC_IOASCR_G8_IO2_Msk                         /*!<GROUP8_IO2 analog switch enable */
10701 #define TSC_IOASCR_G8_IO3_Pos    (30U)
10702 #define TSC_IOASCR_G8_IO3_Msk    (0x1UL << TSC_IOASCR_G8_IO3_Pos)               /*!< 0x40000000 */
10703 #define TSC_IOASCR_G8_IO3        TSC_IOASCR_G8_IO3_Msk                         /*!<GROUP8_IO3 analog switch enable */
10704 #define TSC_IOASCR_G8_IO4_Pos    (31U)
10705 #define TSC_IOASCR_G8_IO4_Msk    (0x1UL << TSC_IOASCR_G8_IO4_Pos)               /*!< 0x80000000 */
10706 #define TSC_IOASCR_G8_IO4        TSC_IOASCR_G8_IO4_Msk                         /*!<GROUP8_IO4 analog switch enable */
10707 
10708 /*******************  Bit definition for TSC_IOSCR register  ******************/
10709 #define TSC_IOSCR_G1_IO1_Pos     (0U)
10710 #define TSC_IOSCR_G1_IO1_Msk     (0x1UL << TSC_IOSCR_G1_IO1_Pos)                /*!< 0x00000001 */
10711 #define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
10712 #define TSC_IOSCR_G1_IO2_Pos     (1U)
10713 #define TSC_IOSCR_G1_IO2_Msk     (0x1UL << TSC_IOSCR_G1_IO2_Pos)                /*!< 0x00000002 */
10714 #define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
10715 #define TSC_IOSCR_G1_IO3_Pos     (2U)
10716 #define TSC_IOSCR_G1_IO3_Msk     (0x1UL << TSC_IOSCR_G1_IO3_Pos)                /*!< 0x00000004 */
10717 #define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
10718 #define TSC_IOSCR_G1_IO4_Pos     (3U)
10719 #define TSC_IOSCR_G1_IO4_Msk     (0x1UL << TSC_IOSCR_G1_IO4_Pos)                /*!< 0x00000008 */
10720 #define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
10721 #define TSC_IOSCR_G2_IO1_Pos     (4U)
10722 #define TSC_IOSCR_G2_IO1_Msk     (0x1UL << TSC_IOSCR_G2_IO1_Pos)                /*!< 0x00000010 */
10723 #define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
10724 #define TSC_IOSCR_G2_IO2_Pos     (5U)
10725 #define TSC_IOSCR_G2_IO2_Msk     (0x1UL << TSC_IOSCR_G2_IO2_Pos)                /*!< 0x00000020 */
10726 #define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
10727 #define TSC_IOSCR_G2_IO3_Pos     (6U)
10728 #define TSC_IOSCR_G2_IO3_Msk     (0x1UL << TSC_IOSCR_G2_IO3_Pos)                /*!< 0x00000040 */
10729 #define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
10730 #define TSC_IOSCR_G2_IO4_Pos     (7U)
10731 #define TSC_IOSCR_G2_IO4_Msk     (0x1UL << TSC_IOSCR_G2_IO4_Pos)                /*!< 0x00000080 */
10732 #define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
10733 #define TSC_IOSCR_G3_IO1_Pos     (8U)
10734 #define TSC_IOSCR_G3_IO1_Msk     (0x1UL << TSC_IOSCR_G3_IO1_Pos)                /*!< 0x00000100 */
10735 #define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
10736 #define TSC_IOSCR_G3_IO2_Pos     (9U)
10737 #define TSC_IOSCR_G3_IO2_Msk     (0x1UL << TSC_IOSCR_G3_IO2_Pos)                /*!< 0x00000200 */
10738 #define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
10739 #define TSC_IOSCR_G3_IO3_Pos     (10U)
10740 #define TSC_IOSCR_G3_IO3_Msk     (0x1UL << TSC_IOSCR_G3_IO3_Pos)                /*!< 0x00000400 */
10741 #define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
10742 #define TSC_IOSCR_G3_IO4_Pos     (11U)
10743 #define TSC_IOSCR_G3_IO4_Msk     (0x1UL << TSC_IOSCR_G3_IO4_Pos)                /*!< 0x00000800 */
10744 #define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
10745 #define TSC_IOSCR_G4_IO1_Pos     (12U)
10746 #define TSC_IOSCR_G4_IO1_Msk     (0x1UL << TSC_IOSCR_G4_IO1_Pos)                /*!< 0x00001000 */
10747 #define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
10748 #define TSC_IOSCR_G4_IO2_Pos     (13U)
10749 #define TSC_IOSCR_G4_IO2_Msk     (0x1UL << TSC_IOSCR_G4_IO2_Pos)                /*!< 0x00002000 */
10750 #define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
10751 #define TSC_IOSCR_G4_IO3_Pos     (14U)
10752 #define TSC_IOSCR_G4_IO3_Msk     (0x1UL << TSC_IOSCR_G4_IO3_Pos)                /*!< 0x00004000 */
10753 #define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
10754 #define TSC_IOSCR_G4_IO4_Pos     (15U)
10755 #define TSC_IOSCR_G4_IO4_Msk     (0x1UL << TSC_IOSCR_G4_IO4_Pos)                /*!< 0x00008000 */
10756 #define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
10757 #define TSC_IOSCR_G5_IO1_Pos     (16U)
10758 #define TSC_IOSCR_G5_IO1_Msk     (0x1UL << TSC_IOSCR_G5_IO1_Pos)                /*!< 0x00010000 */
10759 #define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
10760 #define TSC_IOSCR_G5_IO2_Pos     (17U)
10761 #define TSC_IOSCR_G5_IO2_Msk     (0x1UL << TSC_IOSCR_G5_IO2_Pos)                /*!< 0x00020000 */
10762 #define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
10763 #define TSC_IOSCR_G5_IO3_Pos     (18U)
10764 #define TSC_IOSCR_G5_IO3_Msk     (0x1UL << TSC_IOSCR_G5_IO3_Pos)                /*!< 0x00040000 */
10765 #define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
10766 #define TSC_IOSCR_G5_IO4_Pos     (19U)
10767 #define TSC_IOSCR_G5_IO4_Msk     (0x1UL << TSC_IOSCR_G5_IO4_Pos)                /*!< 0x00080000 */
10768 #define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
10769 #define TSC_IOSCR_G6_IO1_Pos     (20U)
10770 #define TSC_IOSCR_G6_IO1_Msk     (0x1UL << TSC_IOSCR_G6_IO1_Pos)                /*!< 0x00100000 */
10771 #define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
10772 #define TSC_IOSCR_G6_IO2_Pos     (21U)
10773 #define TSC_IOSCR_G6_IO2_Msk     (0x1UL << TSC_IOSCR_G6_IO2_Pos)                /*!< 0x00200000 */
10774 #define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
10775 #define TSC_IOSCR_G6_IO3_Pos     (22U)
10776 #define TSC_IOSCR_G6_IO3_Msk     (0x1UL << TSC_IOSCR_G6_IO3_Pos)                /*!< 0x00400000 */
10777 #define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
10778 #define TSC_IOSCR_G6_IO4_Pos     (23U)
10779 #define TSC_IOSCR_G6_IO4_Msk     (0x1UL << TSC_IOSCR_G6_IO4_Pos)                /*!< 0x00800000 */
10780 #define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
10781 #define TSC_IOSCR_G7_IO1_Pos     (24U)
10782 #define TSC_IOSCR_G7_IO1_Msk     (0x1UL << TSC_IOSCR_G7_IO1_Pos)                /*!< 0x01000000 */
10783 #define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
10784 #define TSC_IOSCR_G7_IO2_Pos     (25U)
10785 #define TSC_IOSCR_G7_IO2_Msk     (0x1UL << TSC_IOSCR_G7_IO2_Pos)                /*!< 0x02000000 */
10786 #define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
10787 #define TSC_IOSCR_G7_IO3_Pos     (26U)
10788 #define TSC_IOSCR_G7_IO3_Msk     (0x1UL << TSC_IOSCR_G7_IO3_Pos)                /*!< 0x04000000 */
10789 #define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
10790 #define TSC_IOSCR_G7_IO4_Pos     (27U)
10791 #define TSC_IOSCR_G7_IO4_Msk     (0x1UL << TSC_IOSCR_G7_IO4_Pos)                /*!< 0x08000000 */
10792 #define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
10793 #define TSC_IOSCR_G8_IO1_Pos     (28U)
10794 #define TSC_IOSCR_G8_IO1_Msk     (0x1UL << TSC_IOSCR_G8_IO1_Pos)                /*!< 0x10000000 */
10795 #define TSC_IOSCR_G8_IO1         TSC_IOSCR_G8_IO1_Msk                          /*!<GROUP8_IO1 sampling mode */
10796 #define TSC_IOSCR_G8_IO2_Pos     (29U)
10797 #define TSC_IOSCR_G8_IO2_Msk     (0x1UL << TSC_IOSCR_G8_IO2_Pos)                /*!< 0x20000000 */
10798 #define TSC_IOSCR_G8_IO2         TSC_IOSCR_G8_IO2_Msk                          /*!<GROUP8_IO2 sampling mode */
10799 #define TSC_IOSCR_G8_IO3_Pos     (30U)
10800 #define TSC_IOSCR_G8_IO3_Msk     (0x1UL << TSC_IOSCR_G8_IO3_Pos)                /*!< 0x40000000 */
10801 #define TSC_IOSCR_G8_IO3         TSC_IOSCR_G8_IO3_Msk                          /*!<GROUP8_IO3 sampling mode */
10802 #define TSC_IOSCR_G8_IO4_Pos     (31U)
10803 #define TSC_IOSCR_G8_IO4_Msk     (0x1UL << TSC_IOSCR_G8_IO4_Pos)                /*!< 0x80000000 */
10804 #define TSC_IOSCR_G8_IO4         TSC_IOSCR_G8_IO4_Msk                          /*!<GROUP8_IO4 sampling mode */
10805 
10806 /*******************  Bit definition for TSC_IOCCR register  ******************/
10807 #define TSC_IOCCR_G1_IO1_Pos     (0U)
10808 #define TSC_IOCCR_G1_IO1_Msk     (0x1UL << TSC_IOCCR_G1_IO1_Pos)                /*!< 0x00000001 */
10809 #define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
10810 #define TSC_IOCCR_G1_IO2_Pos     (1U)
10811 #define TSC_IOCCR_G1_IO2_Msk     (0x1UL << TSC_IOCCR_G1_IO2_Pos)                /*!< 0x00000002 */
10812 #define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
10813 #define TSC_IOCCR_G1_IO3_Pos     (2U)
10814 #define TSC_IOCCR_G1_IO3_Msk     (0x1UL << TSC_IOCCR_G1_IO3_Pos)                /*!< 0x00000004 */
10815 #define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
10816 #define TSC_IOCCR_G1_IO4_Pos     (3U)
10817 #define TSC_IOCCR_G1_IO4_Msk     (0x1UL << TSC_IOCCR_G1_IO4_Pos)                /*!< 0x00000008 */
10818 #define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
10819 #define TSC_IOCCR_G2_IO1_Pos     (4U)
10820 #define TSC_IOCCR_G2_IO1_Msk     (0x1UL << TSC_IOCCR_G2_IO1_Pos)                /*!< 0x00000010 */
10821 #define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
10822 #define TSC_IOCCR_G2_IO2_Pos     (5U)
10823 #define TSC_IOCCR_G2_IO2_Msk     (0x1UL << TSC_IOCCR_G2_IO2_Pos)                /*!< 0x00000020 */
10824 #define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
10825 #define TSC_IOCCR_G2_IO3_Pos     (6U)
10826 #define TSC_IOCCR_G2_IO3_Msk     (0x1UL << TSC_IOCCR_G2_IO3_Pos)                /*!< 0x00000040 */
10827 #define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
10828 #define TSC_IOCCR_G2_IO4_Pos     (7U)
10829 #define TSC_IOCCR_G2_IO4_Msk     (0x1UL << TSC_IOCCR_G2_IO4_Pos)                /*!< 0x00000080 */
10830 #define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
10831 #define TSC_IOCCR_G3_IO1_Pos     (8U)
10832 #define TSC_IOCCR_G3_IO1_Msk     (0x1UL << TSC_IOCCR_G3_IO1_Pos)                /*!< 0x00000100 */
10833 #define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
10834 #define TSC_IOCCR_G3_IO2_Pos     (9U)
10835 #define TSC_IOCCR_G3_IO2_Msk     (0x1UL << TSC_IOCCR_G3_IO2_Pos)                /*!< 0x00000200 */
10836 #define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
10837 #define TSC_IOCCR_G3_IO3_Pos     (10U)
10838 #define TSC_IOCCR_G3_IO3_Msk     (0x1UL << TSC_IOCCR_G3_IO3_Pos)                /*!< 0x00000400 */
10839 #define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
10840 #define TSC_IOCCR_G3_IO4_Pos     (11U)
10841 #define TSC_IOCCR_G3_IO4_Msk     (0x1UL << TSC_IOCCR_G3_IO4_Pos)                /*!< 0x00000800 */
10842 #define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
10843 #define TSC_IOCCR_G4_IO1_Pos     (12U)
10844 #define TSC_IOCCR_G4_IO1_Msk     (0x1UL << TSC_IOCCR_G4_IO1_Pos)                /*!< 0x00001000 */
10845 #define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
10846 #define TSC_IOCCR_G4_IO2_Pos     (13U)
10847 #define TSC_IOCCR_G4_IO2_Msk     (0x1UL << TSC_IOCCR_G4_IO2_Pos)                /*!< 0x00002000 */
10848 #define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
10849 #define TSC_IOCCR_G4_IO3_Pos     (14U)
10850 #define TSC_IOCCR_G4_IO3_Msk     (0x1UL << TSC_IOCCR_G4_IO3_Pos)                /*!< 0x00004000 */
10851 #define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
10852 #define TSC_IOCCR_G4_IO4_Pos     (15U)
10853 #define TSC_IOCCR_G4_IO4_Msk     (0x1UL << TSC_IOCCR_G4_IO4_Pos)                /*!< 0x00008000 */
10854 #define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
10855 #define TSC_IOCCR_G5_IO1_Pos     (16U)
10856 #define TSC_IOCCR_G5_IO1_Msk     (0x1UL << TSC_IOCCR_G5_IO1_Pos)                /*!< 0x00010000 */
10857 #define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
10858 #define TSC_IOCCR_G5_IO2_Pos     (17U)
10859 #define TSC_IOCCR_G5_IO2_Msk     (0x1UL << TSC_IOCCR_G5_IO2_Pos)                /*!< 0x00020000 */
10860 #define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
10861 #define TSC_IOCCR_G5_IO3_Pos     (18U)
10862 #define TSC_IOCCR_G5_IO3_Msk     (0x1UL << TSC_IOCCR_G5_IO3_Pos)                /*!< 0x00040000 */
10863 #define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
10864 #define TSC_IOCCR_G5_IO4_Pos     (19U)
10865 #define TSC_IOCCR_G5_IO4_Msk     (0x1UL << TSC_IOCCR_G5_IO4_Pos)                /*!< 0x00080000 */
10866 #define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
10867 #define TSC_IOCCR_G6_IO1_Pos     (20U)
10868 #define TSC_IOCCR_G6_IO1_Msk     (0x1UL << TSC_IOCCR_G6_IO1_Pos)                /*!< 0x00100000 */
10869 #define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
10870 #define TSC_IOCCR_G6_IO2_Pos     (21U)
10871 #define TSC_IOCCR_G6_IO2_Msk     (0x1UL << TSC_IOCCR_G6_IO2_Pos)                /*!< 0x00200000 */
10872 #define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
10873 #define TSC_IOCCR_G6_IO3_Pos     (22U)
10874 #define TSC_IOCCR_G6_IO3_Msk     (0x1UL << TSC_IOCCR_G6_IO3_Pos)                /*!< 0x00400000 */
10875 #define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
10876 #define TSC_IOCCR_G6_IO4_Pos     (23U)
10877 #define TSC_IOCCR_G6_IO4_Msk     (0x1UL << TSC_IOCCR_G6_IO4_Pos)                /*!< 0x00800000 */
10878 #define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
10879 #define TSC_IOCCR_G7_IO1_Pos     (24U)
10880 #define TSC_IOCCR_G7_IO1_Msk     (0x1UL << TSC_IOCCR_G7_IO1_Pos)                /*!< 0x01000000 */
10881 #define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
10882 #define TSC_IOCCR_G7_IO2_Pos     (25U)
10883 #define TSC_IOCCR_G7_IO2_Msk     (0x1UL << TSC_IOCCR_G7_IO2_Pos)                /*!< 0x02000000 */
10884 #define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
10885 #define TSC_IOCCR_G7_IO3_Pos     (26U)
10886 #define TSC_IOCCR_G7_IO3_Msk     (0x1UL << TSC_IOCCR_G7_IO3_Pos)                /*!< 0x04000000 */
10887 #define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
10888 #define TSC_IOCCR_G7_IO4_Pos     (27U)
10889 #define TSC_IOCCR_G7_IO4_Msk     (0x1UL << TSC_IOCCR_G7_IO4_Pos)                /*!< 0x08000000 */
10890 #define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
10891 #define TSC_IOCCR_G8_IO1_Pos     (28U)
10892 #define TSC_IOCCR_G8_IO1_Msk     (0x1UL << TSC_IOCCR_G8_IO1_Pos)                /*!< 0x10000000 */
10893 #define TSC_IOCCR_G8_IO1         TSC_IOCCR_G8_IO1_Msk                          /*!<GROUP8_IO1 channel mode */
10894 #define TSC_IOCCR_G8_IO2_Pos     (29U)
10895 #define TSC_IOCCR_G8_IO2_Msk     (0x1UL << TSC_IOCCR_G8_IO2_Pos)                /*!< 0x20000000 */
10896 #define TSC_IOCCR_G8_IO2         TSC_IOCCR_G8_IO2_Msk                          /*!<GROUP8_IO2 channel mode */
10897 #define TSC_IOCCR_G8_IO3_Pos     (30U)
10898 #define TSC_IOCCR_G8_IO3_Msk     (0x1UL << TSC_IOCCR_G8_IO3_Pos)                /*!< 0x40000000 */
10899 #define TSC_IOCCR_G8_IO3         TSC_IOCCR_G8_IO3_Msk                          /*!<GROUP8_IO3 channel mode */
10900 #define TSC_IOCCR_G8_IO4_Pos     (31U)
10901 #define TSC_IOCCR_G8_IO4_Msk     (0x1UL << TSC_IOCCR_G8_IO4_Pos)                /*!< 0x80000000 */
10902 #define TSC_IOCCR_G8_IO4         TSC_IOCCR_G8_IO4_Msk                          /*!<GROUP8_IO4 channel mode */
10903 
10904 /*******************  Bit definition for TSC_IOGCSR register  *****************/
10905 #define TSC_IOGCSR_G1E_Pos       (0U)
10906 #define TSC_IOGCSR_G1E_Msk       (0x1UL << TSC_IOGCSR_G1E_Pos)                  /*!< 0x00000001 */
10907 #define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
10908 #define TSC_IOGCSR_G2E_Pos       (1U)
10909 #define TSC_IOGCSR_G2E_Msk       (0x1UL << TSC_IOGCSR_G2E_Pos)                  /*!< 0x00000002 */
10910 #define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
10911 #define TSC_IOGCSR_G3E_Pos       (2U)
10912 #define TSC_IOGCSR_G3E_Msk       (0x1UL << TSC_IOGCSR_G3E_Pos)                  /*!< 0x00000004 */
10913 #define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
10914 #define TSC_IOGCSR_G4E_Pos       (3U)
10915 #define TSC_IOGCSR_G4E_Msk       (0x1UL << TSC_IOGCSR_G4E_Pos)                  /*!< 0x00000008 */
10916 #define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
10917 #define TSC_IOGCSR_G5E_Pos       (4U)
10918 #define TSC_IOGCSR_G5E_Msk       (0x1UL << TSC_IOGCSR_G5E_Pos)                  /*!< 0x00000010 */
10919 #define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
10920 #define TSC_IOGCSR_G6E_Pos       (5U)
10921 #define TSC_IOGCSR_G6E_Msk       (0x1UL << TSC_IOGCSR_G6E_Pos)                  /*!< 0x00000020 */
10922 #define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
10923 #define TSC_IOGCSR_G7E_Pos       (6U)
10924 #define TSC_IOGCSR_G7E_Msk       (0x1UL << TSC_IOGCSR_G7E_Pos)                  /*!< 0x00000040 */
10925 #define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
10926 #define TSC_IOGCSR_G8E_Pos       (7U)
10927 #define TSC_IOGCSR_G8E_Msk       (0x1UL << TSC_IOGCSR_G8E_Pos)                  /*!< 0x00000080 */
10928 #define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */
10929 #define TSC_IOGCSR_G1S_Pos       (16U)
10930 #define TSC_IOGCSR_G1S_Msk       (0x1UL << TSC_IOGCSR_G1S_Pos)                  /*!< 0x00010000 */
10931 #define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
10932 #define TSC_IOGCSR_G2S_Pos       (17U)
10933 #define TSC_IOGCSR_G2S_Msk       (0x1UL << TSC_IOGCSR_G2S_Pos)                  /*!< 0x00020000 */
10934 #define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
10935 #define TSC_IOGCSR_G3S_Pos       (18U)
10936 #define TSC_IOGCSR_G3S_Msk       (0x1UL << TSC_IOGCSR_G3S_Pos)                  /*!< 0x00040000 */
10937 #define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
10938 #define TSC_IOGCSR_G4S_Pos       (19U)
10939 #define TSC_IOGCSR_G4S_Msk       (0x1UL << TSC_IOGCSR_G4S_Pos)                  /*!< 0x00080000 */
10940 #define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
10941 #define TSC_IOGCSR_G5S_Pos       (20U)
10942 #define TSC_IOGCSR_G5S_Msk       (0x1UL << TSC_IOGCSR_G5S_Pos)                  /*!< 0x00100000 */
10943 #define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
10944 #define TSC_IOGCSR_G6S_Pos       (21U)
10945 #define TSC_IOGCSR_G6S_Msk       (0x1UL << TSC_IOGCSR_G6S_Pos)                  /*!< 0x00200000 */
10946 #define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
10947 #define TSC_IOGCSR_G7S_Pos       (22U)
10948 #define TSC_IOGCSR_G7S_Msk       (0x1UL << TSC_IOGCSR_G7S_Pos)                  /*!< 0x00400000 */
10949 #define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
10950 #define TSC_IOGCSR_G8S_Pos       (23U)
10951 #define TSC_IOGCSR_G8S_Msk       (0x1UL << TSC_IOGCSR_G8S_Pos)                  /*!< 0x00800000 */
10952 #define TSC_IOGCSR_G8S           TSC_IOGCSR_G8S_Msk                            /*!<Analog IO GROUP8 status */
10953 
10954 /*******************  Bit definition for TSC_IOGXCR register  *****************/
10955 #define TSC_IOGXCR_CNT_Pos       (0U)
10956 #define TSC_IOGXCR_CNT_Msk       (0x3FFFUL << TSC_IOGXCR_CNT_Pos)               /*!< 0x00003FFF */
10957 #define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
10958 
10959 /******************************************************************************/
10960 /*                                                                            */
10961 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
10962 /*                                                                            */
10963 /******************************************************************************/
10964 
10965 /*
10966 * @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
10967 */
10968 
10969 /* Support of 7 bits data length feature */
10970 #define USART_7BITS_SUPPORT
10971 
10972 /* Support of LIN feature */
10973 #define USART_LIN_SUPPORT
10974 
10975 /* Support of Smartcard feature */
10976 #define USART_SMARTCARD_SUPPORT
10977 
10978 /* Support of Irda feature */
10979 #define USART_IRDA_SUPPORT
10980 
10981 /* Support of Wake Up from Stop Mode feature */
10982 #define USART_WUSM_SUPPORT
10983 
10984 /* Support of Full Auto Baud rate feature (4 modes) activation */
10985 #define USART_FABR_SUPPORT
10986 
10987 /******************  Bit definition for USART_CR1 register  *******************/
10988 #define USART_CR1_UE_Pos              (0U)
10989 #define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
10990 #define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
10991 #define USART_CR1_UESM_Pos            (1U)
10992 #define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
10993 #define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
10994 #define USART_CR1_RE_Pos              (2U)
10995 #define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
10996 #define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
10997 #define USART_CR1_TE_Pos              (3U)
10998 #define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
10999 #define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
11000 #define USART_CR1_IDLEIE_Pos          (4U)
11001 #define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
11002 #define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
11003 #define USART_CR1_RXNEIE_Pos          (5U)
11004 #define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
11005 #define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
11006 #define USART_CR1_TCIE_Pos            (6U)
11007 #define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
11008 #define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
11009 #define USART_CR1_TXEIE_Pos           (7U)
11010 #define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
11011 #define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
11012 #define USART_CR1_PEIE_Pos            (8U)
11013 #define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
11014 #define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
11015 #define USART_CR1_PS_Pos              (9U)
11016 #define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
11017 #define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
11018 #define USART_CR1_PCE_Pos             (10U)
11019 #define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
11020 #define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
11021 #define USART_CR1_WAKE_Pos            (11U)
11022 #define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
11023 #define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
11024 #define USART_CR1_M0_Pos              (12U)
11025 #define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
11026 #define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length bit 0 */
11027 #define USART_CR1_MME_Pos             (13U)
11028 #define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
11029 #define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
11030 #define USART_CR1_CMIE_Pos            (14U)
11031 #define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
11032 #define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
11033 #define USART_CR1_OVER8_Pos           (15U)
11034 #define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
11035 #define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
11036 #define USART_CR1_DEDT_Pos            (16U)
11037 #define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
11038 #define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
11039 #define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
11040 #define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
11041 #define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
11042 #define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
11043 #define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
11044 #define USART_CR1_DEAT_Pos            (21U)
11045 #define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
11046 #define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
11047 #define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
11048 #define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
11049 #define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
11050 #define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
11051 #define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
11052 #define USART_CR1_RTOIE_Pos           (26U)
11053 #define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
11054 #define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
11055 #define USART_CR1_EOBIE_Pos           (27U)
11056 #define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
11057 #define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
11058 #define USART_CR1_M1_Pos              (28U)
11059 #define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
11060 #define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length bit 1 */
11061 #define USART_CR1_M_Pos               (12U)
11062 #define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
11063 #define USART_CR1_M                   USART_CR1_M_Msk                          /*!< [M1:M0] Word length */
11064 
11065 /******************  Bit definition for USART_CR2 register  *******************/
11066 #define USART_CR2_ADDM7_Pos           (4U)
11067 #define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
11068 #define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
11069 #define USART_CR2_LBDL_Pos            (5U)
11070 #define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
11071 #define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
11072 #define USART_CR2_LBDIE_Pos           (6U)
11073 #define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
11074 #define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
11075 #define USART_CR2_LBCL_Pos            (8U)
11076 #define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
11077 #define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
11078 #define USART_CR2_CPHA_Pos            (9U)
11079 #define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
11080 #define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
11081 #define USART_CR2_CPOL_Pos            (10U)
11082 #define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
11083 #define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
11084 #define USART_CR2_CLKEN_Pos           (11U)
11085 #define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
11086 #define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
11087 #define USART_CR2_STOP_Pos            (12U)
11088 #define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
11089 #define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
11090 #define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
11091 #define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
11092 #define USART_CR2_LINEN_Pos           (14U)
11093 #define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
11094 #define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
11095 #define USART_CR2_SWAP_Pos            (15U)
11096 #define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
11097 #define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
11098 #define USART_CR2_RXINV_Pos           (16U)
11099 #define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
11100 #define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
11101 #define USART_CR2_TXINV_Pos           (17U)
11102 #define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
11103 #define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
11104 #define USART_CR2_DATAINV_Pos         (18U)
11105 #define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
11106 #define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
11107 #define USART_CR2_MSBFIRST_Pos        (19U)
11108 #define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
11109 #define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
11110 #define USART_CR2_ABREN_Pos           (20U)
11111 #define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
11112 #define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
11113 #define USART_CR2_ABRMODE_Pos         (21U)
11114 #define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
11115 #define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
11116 #define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
11117 #define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
11118 #define USART_CR2_RTOEN_Pos           (23U)
11119 #define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
11120 #define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
11121 #define USART_CR2_ADD_Pos             (24U)
11122 #define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
11123 #define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
11124 
11125 /******************  Bit definition for USART_CR3 register  *******************/
11126 #define USART_CR3_EIE_Pos             (0U)
11127 #define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
11128 #define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
11129 #define USART_CR3_IREN_Pos            (1U)
11130 #define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
11131 #define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
11132 #define USART_CR3_IRLP_Pos            (2U)
11133 #define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
11134 #define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
11135 #define USART_CR3_HDSEL_Pos           (3U)
11136 #define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
11137 #define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
11138 #define USART_CR3_NACK_Pos            (4U)
11139 #define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
11140 #define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
11141 #define USART_CR3_SCEN_Pos            (5U)
11142 #define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
11143 #define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
11144 #define USART_CR3_DMAR_Pos            (6U)
11145 #define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
11146 #define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
11147 #define USART_CR3_DMAT_Pos            (7U)
11148 #define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
11149 #define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
11150 #define USART_CR3_RTSE_Pos            (8U)
11151 #define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
11152 #define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
11153 #define USART_CR3_CTSE_Pos            (9U)
11154 #define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
11155 #define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
11156 #define USART_CR3_CTSIE_Pos           (10U)
11157 #define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
11158 #define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
11159 #define USART_CR3_ONEBIT_Pos          (11U)
11160 #define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
11161 #define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
11162 #define USART_CR3_OVRDIS_Pos          (12U)
11163 #define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
11164 #define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
11165 #define USART_CR3_DDRE_Pos            (13U)
11166 #define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
11167 #define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
11168 #define USART_CR3_DEM_Pos             (14U)
11169 #define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
11170 #define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
11171 #define USART_CR3_DEP_Pos             (15U)
11172 #define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
11173 #define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
11174 #define USART_CR3_SCARCNT_Pos         (17U)
11175 #define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
11176 #define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
11177 #define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
11178 #define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
11179 #define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
11180 #define USART_CR3_WUS_Pos             (20U)
11181 #define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
11182 #define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
11183 #define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
11184 #define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
11185 #define USART_CR3_WUFIE_Pos           (22U)
11186 #define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
11187 #define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
11188 
11189 /******************  Bit definition for USART_BRR register  *******************/
11190 #define USART_BRR_DIV_FRACTION_Pos    (0U)
11191 #define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
11192 #define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
11193 #define USART_BRR_DIV_MANTISSA_Pos    (4U)
11194 #define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
11195 #define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
11196 
11197 /******************  Bit definition for USART_GTPR register  ******************/
11198 #define USART_GTPR_PSC_Pos            (0U)
11199 #define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
11200 #define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
11201 #define USART_GTPR_GT_Pos             (8U)
11202 #define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
11203 #define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
11204 
11205 
11206 /*******************  Bit definition for USART_RTOR register  *****************/
11207 #define USART_RTOR_RTO_Pos            (0U)
11208 #define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
11209 #define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
11210 #define USART_RTOR_BLEN_Pos           (24U)
11211 #define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
11212 #define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
11213 
11214 /*******************  Bit definition for USART_RQR register  ******************/
11215 #define USART_RQR_ABRRQ_Pos           (0U)
11216 #define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
11217 #define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
11218 #define USART_RQR_SBKRQ_Pos           (1U)
11219 #define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
11220 #define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
11221 #define USART_RQR_MMRQ_Pos            (2U)
11222 #define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
11223 #define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
11224 #define USART_RQR_RXFRQ_Pos           (3U)
11225 #define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
11226 #define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
11227 #define USART_RQR_TXFRQ_Pos           (4U)
11228 #define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
11229 #define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
11230 
11231 /*******************  Bit definition for USART_ISR register  ******************/
11232 #define USART_ISR_PE_Pos              (0U)
11233 #define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
11234 #define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
11235 #define USART_ISR_FE_Pos              (1U)
11236 #define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
11237 #define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
11238 #define USART_ISR_NE_Pos              (2U)
11239 #define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
11240 #define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
11241 #define USART_ISR_ORE_Pos             (3U)
11242 #define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
11243 #define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
11244 #define USART_ISR_IDLE_Pos            (4U)
11245 #define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
11246 #define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
11247 #define USART_ISR_RXNE_Pos            (5U)
11248 #define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
11249 #define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
11250 #define USART_ISR_TC_Pos              (6U)
11251 #define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
11252 #define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
11253 #define USART_ISR_TXE_Pos             (7U)
11254 #define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
11255 #define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
11256 #define USART_ISR_LBDF_Pos            (8U)
11257 #define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
11258 #define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
11259 #define USART_ISR_CTSIF_Pos           (9U)
11260 #define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
11261 #define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
11262 #define USART_ISR_CTS_Pos             (10U)
11263 #define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
11264 #define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
11265 #define USART_ISR_RTOF_Pos            (11U)
11266 #define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
11267 #define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
11268 #define USART_ISR_EOBF_Pos            (12U)
11269 #define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
11270 #define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
11271 #define USART_ISR_ABRE_Pos            (14U)
11272 #define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
11273 #define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
11274 #define USART_ISR_ABRF_Pos            (15U)
11275 #define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
11276 #define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
11277 #define USART_ISR_BUSY_Pos            (16U)
11278 #define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
11279 #define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
11280 #define USART_ISR_CMF_Pos             (17U)
11281 #define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
11282 #define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
11283 #define USART_ISR_SBKF_Pos            (18U)
11284 #define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
11285 #define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
11286 #define USART_ISR_RWU_Pos             (19U)
11287 #define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
11288 #define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
11289 #define USART_ISR_WUF_Pos             (20U)
11290 #define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
11291 #define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
11292 #define USART_ISR_TEACK_Pos           (21U)
11293 #define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
11294 #define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
11295 #define USART_ISR_REACK_Pos           (22U)
11296 #define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
11297 #define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
11298 
11299 /*******************  Bit definition for USART_ICR register  ******************/
11300 #define USART_ICR_PECF_Pos            (0U)
11301 #define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
11302 #define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
11303 #define USART_ICR_FECF_Pos            (1U)
11304 #define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
11305 #define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
11306 #define USART_ICR_NCF_Pos             (2U)
11307 #define USART_ICR_NCF_Msk             (0x1UL << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
11308 #define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
11309 #define USART_ICR_ORECF_Pos           (3U)
11310 #define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
11311 #define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
11312 #define USART_ICR_IDLECF_Pos          (4U)
11313 #define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
11314 #define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
11315 #define USART_ICR_TCCF_Pos            (6U)
11316 #define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
11317 #define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
11318 #define USART_ICR_LBDCF_Pos           (8U)
11319 #define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
11320 #define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
11321 #define USART_ICR_CTSCF_Pos           (9U)
11322 #define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
11323 #define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
11324 #define USART_ICR_RTOCF_Pos           (11U)
11325 #define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
11326 #define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
11327 #define USART_ICR_EOBCF_Pos           (12U)
11328 #define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
11329 #define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
11330 #define USART_ICR_CMCF_Pos            (17U)
11331 #define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
11332 #define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
11333 #define USART_ICR_WUCF_Pos            (20U)
11334 #define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
11335 #define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
11336 
11337 /*******************  Bit definition for USART_RDR register  ******************/
11338 #define USART_RDR_RDR                 ((uint16_t)0x01FFU)                      /*!< RDR[8:0] bits (Receive Data value) */
11339 
11340 /*******************  Bit definition for USART_TDR register  ******************/
11341 #define USART_TDR_TDR                 ((uint16_t)0x01FFU)                      /*!< TDR[8:0] bits (Transmit Data value) */
11342 
11343 /******************************************************************************/
11344 /*                                                                            */
11345 /*                         Window WATCHDOG (WWDG)                             */
11346 /*                                                                            */
11347 /******************************************************************************/
11348 
11349 /*******************  Bit definition for WWDG_CR register  ********************/
11350 #define WWDG_CR_T_Pos           (0U)
11351 #define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
11352 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
11353 #define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
11354 #define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
11355 #define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
11356 #define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
11357 #define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
11358 #define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
11359 #define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
11360 
11361 /* Legacy defines */
11362 #define  WWDG_CR_T0 WWDG_CR_T_0
11363 #define  WWDG_CR_T1 WWDG_CR_T_1
11364 #define  WWDG_CR_T2 WWDG_CR_T_2
11365 #define  WWDG_CR_T3 WWDG_CR_T_3
11366 #define  WWDG_CR_T4 WWDG_CR_T_4
11367 #define  WWDG_CR_T5 WWDG_CR_T_5
11368 #define  WWDG_CR_T6 WWDG_CR_T_6
11369 
11370 #define WWDG_CR_WDGA_Pos        (7U)
11371 #define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
11372 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!< Activation bit */
11373 
11374 /*******************  Bit definition for WWDG_CFR register  *******************/
11375 #define WWDG_CFR_W_Pos          (0U)
11376 #define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
11377 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
11378 #define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
11379 #define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
11380 #define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
11381 #define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
11382 #define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
11383 #define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
11384 #define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
11385 
11386 /* Legacy defines */
11387 #define  WWDG_CFR_W0 WWDG_CFR_W_0
11388 #define  WWDG_CFR_W1 WWDG_CFR_W_1
11389 #define  WWDG_CFR_W2 WWDG_CFR_W_2
11390 #define  WWDG_CFR_W3 WWDG_CFR_W_3
11391 #define  WWDG_CFR_W4 WWDG_CFR_W_4
11392 #define  WWDG_CFR_W5 WWDG_CFR_W_5
11393 #define  WWDG_CFR_W6 WWDG_CFR_W_6
11394 
11395 #define WWDG_CFR_WDGTB_Pos      (7U)
11396 #define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
11397 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
11398 #define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
11399 #define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
11400 
11401 /* Legacy defines */
11402 #define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
11403 #define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
11404 
11405 #define WWDG_CFR_EWI_Pos        (9U)
11406 #define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
11407 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!< Early Wakeup Interrupt */
11408 
11409 /*******************  Bit definition for WWDG_SR register  ********************/
11410 #define WWDG_SR_EWIF_Pos        (0U)
11411 #define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
11412 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!< Early Wakeup Interrupt Flag */
11413 
11414 /**
11415   * @}
11416   */
11417 
11418  /**
11419   * @}
11420   */
11421 
11422 
11423 /** @addtogroup Exported_macro
11424   * @{
11425   */
11426 
11427 /****************************** ADC Instances *********************************/
11428 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
11429 
11430 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
11431 
11432 /******************************* CAN Instances ********************************/
11433 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
11434 
11435 /****************************** COMP Instances *********************************/
11436 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
11437                                         ((INSTANCE) == COMP2))
11438 
11439 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
11440 
11441 #define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
11442 
11443 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
11444 
11445 /****************************** CEC Instances *********************************/
11446 #define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
11447 
11448 /****************************** CRC Instances *********************************/
11449 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
11450 
11451 /******************************* DAC Instances ********************************/
11452 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
11453 
11454 /******************************* DMA Instances ********************************/
11455 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
11456                                        ((INSTANCE) == DMA1_Channel2) || \
11457                                        ((INSTANCE) == DMA1_Channel3) || \
11458                                        ((INSTANCE) == DMA1_Channel4) || \
11459                                        ((INSTANCE) == DMA1_Channel5) || \
11460                                        ((INSTANCE) == DMA1_Channel6) || \
11461                                        ((INSTANCE) == DMA1_Channel7) || \
11462                                        ((INSTANCE) == DMA2_Channel1) || \
11463                                        ((INSTANCE) == DMA2_Channel2) || \
11464                                        ((INSTANCE) == DMA2_Channel3) || \
11465                                        ((INSTANCE) == DMA2_Channel4) || \
11466                                        ((INSTANCE) == DMA2_Channel5))
11467 
11468 /****************************** GPIO Instances ********************************/
11469 #define IS_GPIO_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
11470                                          ((INSTANCE) == GPIOB) || \
11471                                          ((INSTANCE) == GPIOC) || \
11472                                          ((INSTANCE) == GPIOD) || \
11473                                          ((INSTANCE) == GPIOE) || \
11474                                          ((INSTANCE) == GPIOF))
11475 
11476 /**************************** GPIO Alternate Function Instances ***************/
11477 #define IS_GPIO_AF_INSTANCE(INSTANCE)   (((INSTANCE) == GPIOA) || \
11478                                          ((INSTANCE) == GPIOB) || \
11479                                          ((INSTANCE) == GPIOC) || \
11480                                          ((INSTANCE) == GPIOD) || \
11481                                          ((INSTANCE) == GPIOE) || \
11482                                          ((INSTANCE) == GPIOF))
11483 
11484 /****************************** GPIO Lock Instances ***************************/
11485 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
11486                                          ((INSTANCE) == GPIOB))
11487 
11488 /****************************** I2C Instances *********************************/
11489 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
11490                                        ((INSTANCE) == I2C2))
11491 
11492 /****************** I2C Instances : wakeup capability from stop modes *********/
11493 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
11494 
11495 /****************************** I2S Instances *********************************/
11496 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
11497                                        ((INSTANCE) == SPI2))
11498 
11499 /****************************** IWDG Instances ********************************/
11500 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
11501 
11502 /****************************** RTC Instances *********************************/
11503 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
11504 
11505 /****************************** SMBUS Instances *********************************/
11506 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
11507 
11508 /****************************** SPI Instances *********************************/
11509 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
11510                                        ((INSTANCE) == SPI2))
11511 
11512 /****************************** TIM Instances *********************************/
11513 #define IS_TIM_INSTANCE(INSTANCE)\
11514   (((INSTANCE) == TIM1)    || \
11515    ((INSTANCE) == TIM2)    || \
11516    ((INSTANCE) == TIM3)    || \
11517    ((INSTANCE) == TIM6)    || \
11518    ((INSTANCE) == TIM7)    || \
11519    ((INSTANCE) == TIM14)   || \
11520    ((INSTANCE) == TIM15)   || \
11521    ((INSTANCE) == TIM16)   || \
11522    ((INSTANCE) == TIM17))
11523 
11524 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
11525   (((INSTANCE) == TIM1)    || \
11526    ((INSTANCE) == TIM2)    || \
11527    ((INSTANCE) == TIM3)    || \
11528    ((INSTANCE) == TIM14)   || \
11529    ((INSTANCE) == TIM15)   || \
11530    ((INSTANCE) == TIM16)   || \
11531    ((INSTANCE) == TIM17))
11532 
11533 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
11534   (((INSTANCE) == TIM1)    || \
11535    ((INSTANCE) == TIM2)    || \
11536    ((INSTANCE) == TIM3)    || \
11537    ((INSTANCE) == TIM15))
11538 
11539 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
11540   (((INSTANCE) == TIM1)    || \
11541    ((INSTANCE) == TIM2)    || \
11542    ((INSTANCE) == TIM3))
11543 
11544 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
11545   (((INSTANCE) == TIM1)    || \
11546    ((INSTANCE) == TIM2)    || \
11547    ((INSTANCE) == TIM3))
11548 
11549 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
11550   (((INSTANCE) == TIM1)    || \
11551    ((INSTANCE) == TIM2)    || \
11552    ((INSTANCE) == TIM3))
11553 
11554 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
11555   (((INSTANCE) == TIM1)    || \
11556    ((INSTANCE) == TIM2)    || \
11557    ((INSTANCE) == TIM3))
11558 
11559 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
11560   (((INSTANCE) == TIM1)    || \
11561    ((INSTANCE) == TIM2)    || \
11562    ((INSTANCE) == TIM3)    || \
11563    ((INSTANCE) == TIM15))
11564 
11565 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
11566   (((INSTANCE) == TIM1)    || \
11567    ((INSTANCE) == TIM2)    || \
11568    ((INSTANCE) == TIM3)    || \
11569    ((INSTANCE) == TIM15))
11570 
11571 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
11572   (((INSTANCE) == TIM1)    || \
11573    ((INSTANCE) == TIM2)    || \
11574    ((INSTANCE) == TIM3))
11575 
11576 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
11577   (((INSTANCE) == TIM1)    || \
11578    ((INSTANCE) == TIM2)    || \
11579    ((INSTANCE) == TIM3))
11580 
11581 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
11582   (((INSTANCE) == TIM1))
11583 
11584 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\
11585   (((INSTANCE) == TIM1))
11586 
11587 #define IS_TIM_ETR_INSTANCE(INSTANCE)\
11588   (((INSTANCE) == TIM1)    || \
11589    ((INSTANCE) == TIM2)    || \
11590    ((INSTANCE) == TIM3))
11591 
11592 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
11593   (((INSTANCE) == TIM1)    || \
11594    ((INSTANCE) == TIM2)    || \
11595    ((INSTANCE) == TIM3))
11596 
11597 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
11598   (((INSTANCE) == TIM1)    || \
11599    ((INSTANCE) == TIM2)    || \
11600    ((INSTANCE) == TIM3)    || \
11601    ((INSTANCE) == TIM6)    || \
11602    ((INSTANCE) == TIM7)    || \
11603    ((INSTANCE) == TIM15))
11604 
11605 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
11606   (((INSTANCE) == TIM1)    || \
11607    ((INSTANCE) == TIM2)    || \
11608    ((INSTANCE) == TIM3)    || \
11609    ((INSTANCE) == TIM15))
11610 
11611 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
11612     ((INSTANCE) == TIM2)
11613 
11614 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
11615     (((INSTANCE) == TIM1)    || \
11616      ((INSTANCE) == TIM2)    || \
11617      ((INSTANCE) == TIM3)    || \
11618      ((INSTANCE) == TIM15)   || \
11619      ((INSTANCE) == TIM16)   || \
11620      ((INSTANCE) == TIM17))
11621 
11622 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
11623       (((INSTANCE) == TIM1)    || \
11624        ((INSTANCE) == TIM15)   || \
11625        ((INSTANCE) == TIM16)   || \
11626        ((INSTANCE) == TIM17))
11627 
11628 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
11629     ((((INSTANCE) == TIM1) &&                   \
11630      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11631       ((CHANNEL) == TIM_CHANNEL_2) ||          \
11632       ((CHANNEL) == TIM_CHANNEL_3) ||          \
11633       ((CHANNEL) == TIM_CHANNEL_4)))           \
11634     ||                                         \
11635     (((INSTANCE) == TIM2) &&                   \
11636      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11637       ((CHANNEL) == TIM_CHANNEL_2) ||          \
11638       ((CHANNEL) == TIM_CHANNEL_3) ||          \
11639       ((CHANNEL) == TIM_CHANNEL_4)))           \
11640     ||                                         \
11641     (((INSTANCE) == TIM3) &&                   \
11642      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11643       ((CHANNEL) == TIM_CHANNEL_2) ||          \
11644       ((CHANNEL) == TIM_CHANNEL_3) ||          \
11645       ((CHANNEL) == TIM_CHANNEL_4)))           \
11646     ||                                         \
11647     (((INSTANCE) == TIM14) &&                  \
11648      (((CHANNEL) == TIM_CHANNEL_1)))           \
11649     ||                                         \
11650     (((INSTANCE) == TIM15) &&                  \
11651      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11652       ((CHANNEL) == TIM_CHANNEL_2)))           \
11653     ||                                         \
11654     (((INSTANCE) == TIM16) &&                  \
11655      (((CHANNEL) == TIM_CHANNEL_1)))           \
11656     ||                                         \
11657     (((INSTANCE) == TIM17) &&                  \
11658      (((CHANNEL) == TIM_CHANNEL_1))))
11659 
11660 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
11661    ((((INSTANCE) == TIM1) &&                    \
11662      (((CHANNEL) == TIM_CHANNEL_1) ||           \
11663       ((CHANNEL) == TIM_CHANNEL_2) ||           \
11664       ((CHANNEL) == TIM_CHANNEL_3)))            \
11665     ||                                          \
11666     (((INSTANCE) == TIM15) &&                   \
11667       ((CHANNEL) == TIM_CHANNEL_1))             \
11668     ||                                          \
11669     (((INSTANCE) == TIM16) &&                   \
11670      ((CHANNEL) == TIM_CHANNEL_1))              \
11671     ||                                          \
11672     (((INSTANCE) == TIM17) &&                   \
11673      ((CHANNEL) == TIM_CHANNEL_1)))
11674 
11675 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
11676   (((INSTANCE) == TIM1)    || \
11677    ((INSTANCE) == TIM2)    || \
11678    ((INSTANCE) == TIM3))
11679 
11680 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
11681   (((INSTANCE) == TIM1)    || \
11682    ((INSTANCE) == TIM15)   || \
11683    ((INSTANCE) == TIM16)   || \
11684    ((INSTANCE) == TIM17))
11685 
11686 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
11687   (((INSTANCE) == TIM1)    || \
11688    ((INSTANCE) == TIM2)    || \
11689    ((INSTANCE) == TIM3)    || \
11690    ((INSTANCE) == TIM14)   || \
11691    ((INSTANCE) == TIM15)   || \
11692    ((INSTANCE) == TIM16)   || \
11693    ((INSTANCE) == TIM17))
11694 
11695 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
11696   (((INSTANCE) == TIM1)    || \
11697    ((INSTANCE) == TIM2)    || \
11698    ((INSTANCE) == TIM3)    || \
11699    ((INSTANCE) == TIM6)    || \
11700    ((INSTANCE) == TIM7)    || \
11701    ((INSTANCE) == TIM15)   || \
11702    ((INSTANCE) == TIM16)   || \
11703    ((INSTANCE) == TIM17))
11704 
11705 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
11706   (((INSTANCE) == TIM1)    || \
11707    ((INSTANCE) == TIM2)    || \
11708    ((INSTANCE) == TIM3)    || \
11709    ((INSTANCE) == TIM15)   || \
11710    ((INSTANCE) == TIM16)   || \
11711    ((INSTANCE) == TIM17))
11712 
11713 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
11714   (((INSTANCE) == TIM1)    || \
11715    ((INSTANCE) == TIM15)   || \
11716    ((INSTANCE) == TIM16)   || \
11717    ((INSTANCE) == TIM17))
11718 
11719 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
11720   ((INSTANCE) == TIM14)
11721 
11722 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
11723   ((INSTANCE) == TIM1)
11724 
11725 /****************************** TSC Instances *********************************/
11726 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
11727 
11728 /*********************** UART Instances : IRDA mode ***************************/
11729 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11730                                     ((INSTANCE) == USART2) || \
11731                                     ((INSTANCE) == USART3))
11732 
11733 /********************* UART Instances : Smard card mode ***********************/
11734 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11735                                          ((INSTANCE) == USART2) || \
11736                                          ((INSTANCE) == USART3))
11737 
11738 /******************** USART Instances : Synchronous mode **********************/
11739 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11740                                      ((INSTANCE) == USART2) || \
11741                                      ((INSTANCE) == USART3) || \
11742                                      ((INSTANCE) == USART4) || \
11743                                      ((INSTANCE) == USART5) || \
11744                                      ((INSTANCE) == USART6) || \
11745                                      ((INSTANCE) == USART7) || \
11746                                      ((INSTANCE) == USART8))
11747 
11748 /******************** USART Instances : auto Baud rate detection **************/
11749 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11750                                                             ((INSTANCE) == USART2) || \
11751                                                             ((INSTANCE) == USART3))
11752 
11753 /******************** UART Instances : Asynchronous mode **********************/
11754 #define IS_UART_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
11755                                       ((INSTANCE) == USART2) || \
11756                                       ((INSTANCE) == USART3) || \
11757                                       ((INSTANCE) == USART4) || \
11758                                       ((INSTANCE) == USART5) || \
11759                                       ((INSTANCE) == USART6) || \
11760                                       ((INSTANCE) == USART7) || \
11761                                       ((INSTANCE) == USART8))
11762 
11763 /******************** UART Instances : Half-Duplex mode **********************/
11764 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
11765                                                  ((INSTANCE) == USART2) || \
11766                                                  ((INSTANCE) == USART3) || \
11767                                                  ((INSTANCE) == USART4) || \
11768                                                  ((INSTANCE) == USART5) || \
11769                                                  ((INSTANCE) == USART6) || \
11770                                                  ((INSTANCE) == USART7) || \
11771                                                  ((INSTANCE) == USART8))
11772 
11773 /****************** UART Instances : Hardware Flow control ********************/
11774 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11775                                            ((INSTANCE) == USART2) || \
11776                                            ((INSTANCE) == USART3) || \
11777                                            ((INSTANCE) == USART4))
11778 
11779 /****************** UART Instances : LIN mode ********************/
11780 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11781                                         ((INSTANCE) == USART2) || \
11782                                         ((INSTANCE) == USART3))
11783 
11784 /****************** UART Instances : wakeup from stop mode ********************/
11785 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11786                                                     ((INSTANCE) == USART2) || \
11787                                                     ((INSTANCE) == USART3))
11788 /* Old macro definition maintained for legacy purpose */
11789 #define IS_UART_WAKEUP_INSTANCE         IS_UART_WAKEUP_FROMSTOP_INSTANCE
11790 
11791 /****************** UART Instances : Driver enable detection ********************/
11792 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11793                                                   ((INSTANCE) == USART2) || \
11794                                                   ((INSTANCE) == USART3) || \
11795                                                   ((INSTANCE) == USART4) || \
11796                                                   ((INSTANCE) == USART5) || \
11797                                                   ((INSTANCE) == USART6) || \
11798                                                   ((INSTANCE) == USART7) || \
11799                                                   ((INSTANCE) == USART8))
11800 
11801 /****************************** WWDG Instances ********************************/
11802 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
11803 
11804 /**
11805   * @}
11806   */
11807 
11808 
11809 /******************************************************************************/
11810 /*  For a painless codes migration between the STM32F0xx device product       */
11811 /*  lines, the aliases defined below are put in place to overcome the         */
11812 /*  differences in the interrupt handlers and IRQn definitions.               */
11813 /*  No need to update developed interrupt code when moving across             */
11814 /*  product lines within the same STM32F0 Family                              */
11815 /******************************************************************************/
11816 
11817 /* Aliases for __IRQn */
11818 #define ADC1_IRQn                ADC1_COMP_IRQn
11819 #define DMA1_Channel1_IRQn       DMA1_Ch1_IRQn
11820 #define DMA1_Channel2_3_IRQn     DMA1_Ch2_3_DMA2_Ch1_2_IRQn
11821 #define DMA1_Channel4_5_6_7_IRQn DMA1_Ch4_7_DMA2_Ch3_5_IRQn
11822 #define DMA1_Channel4_5_IRQn     DMA1_Ch4_7_DMA2_Ch3_5_IRQn
11823 #define PVD_IRQn                 PVD_VDDIO2_IRQn
11824 #define VDDIO2_IRQn              PVD_VDDIO2_IRQn
11825 #define RCC_IRQn                 RCC_CRS_IRQn
11826 #define TIM6_IRQn                TIM6_DAC_IRQn
11827 #define USART3_6_IRQn            USART3_8_IRQn
11828 #define USART3_4_IRQn            USART3_8_IRQn
11829 
11830 #define SVC_IRQn                 SVCall_IRQn
11831 
11832 /* Aliases for __IRQHandler */
11833 #define ADC1_IRQHandler                ADC1_COMP_IRQHandler
11834 #define DMA1_Channel1_IRQHandler       DMA1_Ch1_IRQHandler
11835 #define DMA1_Channel2_3_IRQHandler     DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
11836 #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
11837 #define DMA1_Channel4_5_IRQHandler     DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
11838 #define PVD_IRQHandler                 PVD_VDDIO2_IRQHandler
11839 #define VDDIO2_IRQHandler              PVD_VDDIO2_IRQHandler
11840 #define RCC_IRQHandler                 RCC_CRS_IRQHandler
11841 #define TIM6_IRQHandler                TIM6_DAC_IRQHandler
11842 #define USART3_6_IRQHandler            USART3_8_IRQHandler
11843 #define USART3_4_IRQHandler            USART3_8_IRQHandler
11844 
11845 #ifdef __cplusplus
11846 }
11847 #endif /* __cplusplus */
11848 
11849 #endif /* __STM32F091xC_H */
11850 
11851 /**
11852   * @}
11853   */
11854 
11855 /**
11856   * @}
11857   */
11858 
11859