1 /** 2 ****************************************************************************** 3 * @file stm32f030x8.h 4 * @author MCD Application Team 5 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. 6 * This file contains all the peripheral register's definitions, bits 7 * definitions and memory mapping for STM32F0xx devices. 8 * 9 * This file contains: 10 * - Data structures and the address mapping for all peripherals 11 * - Peripheral's registers declarations and bits definition 12 * - Macros to access peripheral's registers hardware 13 * 14 ****************************************************************************** 15 * @attention 16 * 17 * Copyright (c) 2016 STMicroelectronics. 18 * All rights reserved. 19 * 20 * This software is licensed under terms that can be found in the LICENSE file 21 * in the root directory of this software component. 22 * If no LICENSE file comes with this software, it is provided AS-IS. 23 * 24 ****************************************************************************** 25 */ 26 /** @addtogroup CMSIS 27 * @{ 28 */ 29 30 /** @addtogroup stm32f030x8 31 * @{ 32 */ 33 34 #ifndef __STM32F030x8_H 35 #define __STM32F030x8_H 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif /* __cplusplus */ 40 41 /** @addtogroup Configuration_section_for_CMSIS 42 * @{ 43 */ 44 /** 45 * @brief Configuration of the Cortex-M0 Processor and Core Peripherals 46 */ 47 #define __CM0_REV 0 /*!< Core Revision r0p0 */ 48 #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */ 49 #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */ 50 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 51 52 /** 53 * @} 54 */ 55 56 /** @addtogroup Peripheral_interrupt_number_definition 57 * @{ 58 */ 59 60 /** 61 * @brief STM32F0xx Interrupt Number Definition, according to the selected device 62 * in @ref Library_configuration_section 63 */ 64 65 /*!< Interrupt Number Definition */ 66 typedef enum 67 { 68 /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ 69 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 70 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ 71 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ 72 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ 73 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ 74 75 /****** STM32F0 specific Interrupt Numbers ******************************************************************/ 76 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 77 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */ 78 FLASH_IRQn = 3, /*!< FLASH global Interrupt */ 79 RCC_IRQn = 4, /*!< RCC global Interrupt */ 80 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupt */ 81 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupt */ 82 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupt */ 83 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ 84 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupt */ 85 DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt */ 86 ADC1_IRQn = 12, /*!< ADC1 Interrupt */ 87 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupt */ 88 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ 89 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ 90 TIM6_IRQn = 17, /*!< TIM6 global Interrupt */ 91 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ 92 TIM15_IRQn = 20, /*!< TIM15 global Interrupt */ 93 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ 94 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ 95 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt */ 96 I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */ 97 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ 98 SPI2_IRQn = 26, /*!< SPI2 global Interrupt */ 99 USART1_IRQn = 27, /*!< USART1 global Interrupt */ 100 USART2_IRQn = 28 /*!< USART2 global Interrupt */ 101 } IRQn_Type; 102 103 /** 104 * @} 105 */ 106 107 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ 108 #include "system_stm32f0xx.h" /* STM32F0xx System Header */ 109 #include <stdint.h> 110 111 /** @addtogroup Peripheral_registers_structures 112 * @{ 113 */ 114 115 /** 116 * @brief Analog to Digital Converter 117 */ 118 119 typedef struct 120 { 121 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ 122 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ 123 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ 124 __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ 125 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ 126 __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ 127 uint32_t RESERVED1; /*!< Reserved, 0x18 */ 128 uint32_t RESERVED2; /*!< Reserved, 0x1C */ 129 __IO uint32_t TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ 130 uint32_t RESERVED3; /*!< Reserved, 0x24 */ 131 __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ 132 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ 133 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ 134 } ADC_TypeDef; 135 136 typedef struct 137 { 138 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ 139 } ADC_Common_TypeDef; 140 141 /** 142 * @brief CRC calculation unit 143 */ 144 145 typedef struct 146 { 147 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ 148 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ 149 uint8_t RESERVED0; /*!< Reserved, 0x05 */ 150 uint16_t RESERVED1; /*!< Reserved, 0x06 */ 151 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ 152 uint32_t RESERVED2; /*!< Reserved, 0x0C */ 153 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ 154 __IO uint32_t RESERVED3; /*!< Reserved, 0x14 */ 155 } CRC_TypeDef; 156 157 /** 158 * @brief Debug MCU 159 */ 160 161 typedef struct 162 { 163 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ 164 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ 165 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ 166 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ 167 }DBGMCU_TypeDef; 168 169 /** 170 * @brief DMA Controller 171 */ 172 173 typedef struct 174 { 175 __IO uint32_t CCR; /*!< DMA channel x configuration register */ 176 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ 177 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ 178 __IO uint32_t CMAR; /*!< DMA channel x memory address register */ 179 } DMA_Channel_TypeDef; 180 181 typedef struct 182 { 183 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ 184 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ 185 } DMA_TypeDef; 186 187 /** 188 * @brief External Interrupt/Event Controller 189 */ 190 191 typedef struct 192 { 193 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */ 194 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */ 195 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */ 196 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */ 197 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */ 198 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */ 199 } EXTI_TypeDef; 200 201 /** 202 * @brief FLASH Registers 203 */ 204 typedef struct 205 { 206 __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */ 207 __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */ 208 __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */ 209 __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */ 210 __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */ 211 __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */ 212 __IO uint32_t RESERVED; /*!< Reserved, 0x18 */ 213 __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */ 214 __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */ 215 } FLASH_TypeDef; 216 217 /** 218 * @brief Option Bytes Registers 219 */ 220 typedef struct 221 { 222 __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */ 223 __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */ 224 __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */ 225 __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */ 226 __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */ 227 __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */ 228 } OB_TypeDef; 229 230 /** 231 * @brief General Purpose I/O 232 */ 233 234 typedef struct 235 { 236 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ 237 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ 238 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ 239 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ 240 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ 241 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ 242 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */ 243 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ 244 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */ 245 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ 246 } GPIO_TypeDef; 247 248 /** 249 * @brief SysTem Configuration 250 */ 251 252 typedef struct 253 { 254 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ 255 uint32_t RESERVED; /*!< Reserved, 0x04 */ 256 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */ 257 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ 258 } SYSCFG_TypeDef; 259 260 /** 261 * @brief Inter-integrated Circuit Interface 262 */ 263 264 typedef struct 265 { 266 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ 267 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ 268 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ 269 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ 270 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ 271 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ 272 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ 273 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ 274 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ 275 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ 276 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ 277 } I2C_TypeDef; 278 279 /** 280 * @brief Independent WATCHDOG 281 */ 282 283 typedef struct 284 { 285 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ 286 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ 287 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ 288 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ 289 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ 290 } IWDG_TypeDef; 291 292 /** 293 * @brief Power Control 294 */ 295 296 typedef struct 297 { 298 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ 299 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ 300 } PWR_TypeDef; 301 302 /** 303 * @brief Reset and Clock Control 304 */ 305 306 typedef struct 307 { 308 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ 309 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */ 310 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */ 311 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */ 312 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */ 313 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */ 314 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */ 315 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */ 316 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */ 317 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */ 318 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */ 319 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */ 320 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */ 321 __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */ 322 } RCC_TypeDef; 323 324 /** 325 * @brief Real-Time Clock 326 */ 327 typedef struct 328 { 329 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ 330 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ 331 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ 332 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ 333 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ 334 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ 335 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */ 336 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ 337 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */ 338 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ 339 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ 340 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ 341 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ 342 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ 343 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ 344 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ 345 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ 346 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ 347 } RTC_TypeDef; 348 349 /** 350 * @brief Serial Peripheral Interface 351 */ 352 353 typedef struct 354 { 355 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ 356 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ 357 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ 358 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ 359 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ 360 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ 361 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ 362 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ 363 } SPI_TypeDef; 364 365 /** 366 * @brief TIM 367 */ 368 typedef struct 369 { 370 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ 371 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ 372 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ 373 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 374 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ 375 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 376 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 377 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 378 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 379 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ 380 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ 381 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 382 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ 383 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 384 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 385 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 386 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 387 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ 388 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ 389 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ 390 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ 391 } TIM_TypeDef; 392 393 /** 394 * @brief Universal Synchronous Asynchronous Receiver Transmitter 395 */ 396 397 typedef struct 398 { 399 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ 400 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ 401 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ 402 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ 403 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ 404 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ 405 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ 406 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ 407 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ 408 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ 409 uint16_t RESERVED1; /*!< Reserved, 0x26 */ 410 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ 411 uint16_t RESERVED2; /*!< Reserved, 0x2A */ 412 } USART_TypeDef; 413 414 /** 415 * @brief Window WATCHDOG 416 */ 417 typedef struct 418 { 419 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ 420 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ 421 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ 422 } WWDG_TypeDef; 423 424 /** 425 * @} 426 */ 427 428 /** @addtogroup Peripheral_memory_map 429 * @{ 430 */ 431 432 #define FLASH_BASE 0x08000000UL /*!< FLASH base address in the alias region */ 433 #define FLASH_BANK1_END 0x0800FFFFUL /*!< FLASH END address of bank1 */ 434 #define SRAM_BASE 0x20000000UL /*!< SRAM base address in the alias region */ 435 #define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */ 436 437 /*!< Peripheral memory map */ 438 #define APBPERIPH_BASE PERIPH_BASE 439 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) 440 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) 441 442 /*!< APB peripherals */ 443 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL) 444 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL) 445 #define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL) 446 #define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) 447 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) 448 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) 449 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL) 450 #define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) 451 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) 452 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL) 453 #define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) 454 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) 455 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL) 456 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) 457 #define ADC_BASE (APBPERIPH_BASE + 0x00012708UL) 458 #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL) 459 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) 460 #define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) 461 #define TIM15_BASE (APBPERIPH_BASE + 0x00014000UL) 462 #define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL) 463 #define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL) 464 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL) 465 466 /*!< AHB peripherals */ 467 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) 468 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) 469 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) 470 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) 471 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) 472 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) 473 474 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) 475 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */ 476 #define OB_BASE 0x1FFFF800UL /*!< FLASH Option Bytes base address */ 477 #define FLASHSIZE_BASE 0x1FFFF7CCUL /*!< FLASH Size register base address */ 478 #define UID_BASE 0x1FFFF7ACUL /*!< Unique device ID register base address */ 479 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) 480 481 /*!< AHB2 peripherals */ 482 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000UL) 483 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400UL) 484 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800UL) 485 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00UL) 486 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400UL) 487 488 /** 489 * @} 490 */ 491 492 /** @addtogroup Peripheral_declaration 493 * @{ 494 */ 495 496 #define TIM3 ((TIM_TypeDef *) TIM3_BASE) 497 #define TIM6 ((TIM_TypeDef *) TIM6_BASE) 498 #define TIM14 ((TIM_TypeDef *) TIM14_BASE) 499 #define RTC ((RTC_TypeDef *) RTC_BASE) 500 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 501 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 502 #define USART2 ((USART_TypeDef *) USART2_BASE) 503 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 504 #define I2C2 ((I2C_TypeDef *) I2C2_BASE) 505 #define PWR ((PWR_TypeDef *) PWR_BASE) 506 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 507 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 508 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 509 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE) 510 #define ADC ((ADC_Common_TypeDef *) ADC_BASE) /* Kept for legacy purpose */ 511 #define TIM1 ((TIM_TypeDef *) TIM1_BASE) 512 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 513 #define SPI2 ((SPI_TypeDef *) SPI2_BASE) 514 #define USART1 ((USART_TypeDef *) USART1_BASE) 515 #define TIM15 ((TIM_TypeDef *) TIM15_BASE) 516 #define TIM16 ((TIM_TypeDef *) TIM16_BASE) 517 #define TIM17 ((TIM_TypeDef *) TIM17_BASE) 518 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 519 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 520 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) 521 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) 522 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) 523 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) 524 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) 525 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 526 #define OB ((OB_TypeDef *) OB_BASE) 527 #define RCC ((RCC_TypeDef *) RCC_BASE) 528 #define CRC ((CRC_TypeDef *) CRC_BASE) 529 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 530 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 531 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 532 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) 533 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) 534 /** 535 * @} 536 */ 537 538 /** @addtogroup Exported_constants 539 * @{ 540 */ 541 542 /** @addtogroup Hardware_Constant_Definition 543 * @{ 544 */ 545 #define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ 546 547 /** 548 * @} 549 */ 550 551 /** @addtogroup Peripheral_Registers_Bits_Definition 552 * @{ 553 */ 554 555 /******************************************************************************/ 556 /* Peripheral Registers Bits Definition */ 557 /******************************************************************************/ 558 559 /******************************************************************************/ 560 /* */ 561 /* Analog to Digital Converter (ADC) */ 562 /* */ 563 /******************************************************************************/ 564 565 /* 566 * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) 567 */ 568 /* Note: No specific macro feature on this device */ 569 570 /******************** Bits definition for ADC_ISR register ******************/ 571 #define ADC_ISR_ADRDY_Pos (0U) 572 #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ 573 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ 574 #define ADC_ISR_EOSMP_Pos (1U) 575 #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ 576 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ 577 #define ADC_ISR_EOC_Pos (2U) 578 #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ 579 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ 580 #define ADC_ISR_EOS_Pos (3U) 581 #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ 582 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ 583 #define ADC_ISR_OVR_Pos (4U) 584 #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ 585 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ 586 #define ADC_ISR_AWD1_Pos (7U) 587 #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ 588 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ 589 590 /* Legacy defines */ 591 #define ADC_ISR_AWD (ADC_ISR_AWD1) 592 #define ADC_ISR_EOSEQ (ADC_ISR_EOS) 593 594 /******************** Bits definition for ADC_IER register ******************/ 595 #define ADC_IER_ADRDYIE_Pos (0U) 596 #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ 597 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ 598 #define ADC_IER_EOSMPIE_Pos (1U) 599 #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ 600 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ 601 #define ADC_IER_EOCIE_Pos (2U) 602 #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ 603 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ 604 #define ADC_IER_EOSIE_Pos (3U) 605 #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ 606 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ 607 #define ADC_IER_OVRIE_Pos (4U) 608 #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ 609 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ 610 #define ADC_IER_AWD1IE_Pos (7U) 611 #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ 612 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ 613 614 /* Legacy defines */ 615 #define ADC_IER_AWDIE (ADC_IER_AWD1IE) 616 #define ADC_IER_EOSEQIE (ADC_IER_EOSIE) 617 618 /******************** Bits definition for ADC_CR register *******************/ 619 #define ADC_CR_ADEN_Pos (0U) 620 #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ 621 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ 622 #define ADC_CR_ADDIS_Pos (1U) 623 #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ 624 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ 625 #define ADC_CR_ADSTART_Pos (2U) 626 #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ 627 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ 628 #define ADC_CR_ADSTP_Pos (4U) 629 #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ 630 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ 631 #define ADC_CR_ADCAL_Pos (31U) 632 #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ 633 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ 634 635 /******************* Bits definition for ADC_CFGR1 register *****************/ 636 #define ADC_CFGR1_DMAEN_Pos (0U) 637 #define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ 638 #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ 639 #define ADC_CFGR1_DMACFG_Pos (1U) 640 #define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ 641 #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ 642 #define ADC_CFGR1_SCANDIR_Pos (2U) 643 #define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ 644 #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ 645 646 #define ADC_CFGR1_RES_Pos (3U) 647 #define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ 648 #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ 649 #define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ 650 #define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ 651 652 #define ADC_CFGR1_ALIGN_Pos (5U) 653 #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ 654 #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ 655 656 #define ADC_CFGR1_EXTSEL_Pos (6U) 657 #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ 658 #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ 659 #define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ 660 #define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ 661 #define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ 662 663 #define ADC_CFGR1_EXTEN_Pos (10U) 664 #define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ 665 #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ 666 #define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ 667 #define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ 668 669 #define ADC_CFGR1_OVRMOD_Pos (12U) 670 #define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ 671 #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ 672 #define ADC_CFGR1_CONT_Pos (13U) 673 #define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ 674 #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ 675 #define ADC_CFGR1_WAIT_Pos (14U) 676 #define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ 677 #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ 678 #define ADC_CFGR1_AUTOFF_Pos (15U) 679 #define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ 680 #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ 681 #define ADC_CFGR1_DISCEN_Pos (16U) 682 #define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ 683 #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ 684 685 #define ADC_CFGR1_AWD1SGL_Pos (22U) 686 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ 687 #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ 688 #define ADC_CFGR1_AWD1EN_Pos (23U) 689 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ 690 #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ 691 692 #define ADC_CFGR1_AWD1CH_Pos (26U) 693 #define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ 694 #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ 695 #define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ 696 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ 697 #define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ 698 #define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ 699 #define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ 700 701 /* Legacy defines */ 702 #define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) 703 #define ADC_CFGR1_AWDSGL (ADC_CFGR1_AWD1SGL) 704 #define ADC_CFGR1_AWDEN (ADC_CFGR1_AWD1EN) 705 #define ADC_CFGR1_AWDCH (ADC_CFGR1_AWD1CH) 706 #define ADC_CFGR1_AWDCH_0 (ADC_CFGR1_AWD1CH_0) 707 #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1) 708 #define ADC_CFGR1_AWDCH_2 (ADC_CFGR1_AWD1CH_2) 709 #define ADC_CFGR1_AWDCH_3 (ADC_CFGR1_AWD1CH_3) 710 #define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4) 711 712 /******************* Bits definition for ADC_CFGR2 register *****************/ 713 #define ADC_CFGR2_CKMODE_Pos (30U) 714 #define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ 715 #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ 716 #define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ 717 #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ 718 719 /* Legacy defines */ 720 #define ADC_CFGR2_JITOFFDIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC clocked by PCLK div4 */ 721 #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */ 722 723 /****************** Bit definition for ADC_SMPR register ********************/ 724 #define ADC_SMPR_SMP_Pos (0U) 725 #define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */ 726 #define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< ADC group of channels sampling time 2 */ 727 #define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */ 728 #define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */ 729 #define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */ 730 731 /* Legacy defines */ 732 #define ADC_SMPR1_SMPR (ADC_SMPR_SMP) /*!< SMP[2:0] bits (Sampling time selection) */ 733 #define ADC_SMPR1_SMPR_0 (ADC_SMPR_SMP_0) /*!< bit 0 */ 734 #define ADC_SMPR1_SMPR_1 (ADC_SMPR_SMP_1) /*!< bit 1 */ 735 #define ADC_SMPR1_SMPR_2 (ADC_SMPR_SMP_2) /*!< bit 2 */ 736 737 /******************* Bit definition for ADC_TR register ********************/ 738 #define ADC_TR1_LT1_Pos (0U) 739 #define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ 740 #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ 741 #define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ 742 #define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ 743 #define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ 744 #define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ 745 #define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ 746 #define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ 747 #define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ 748 #define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ 749 #define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ 750 #define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ 751 #define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ 752 #define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ 753 754 #define ADC_TR1_HT1_Pos (16U) 755 #define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ 756 #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ 757 #define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ 758 #define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ 759 #define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ 760 #define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ 761 #define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ 762 #define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ 763 #define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ 764 #define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ 765 #define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ 766 #define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ 767 #define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ 768 #define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ 769 770 /* Legacy defines */ 771 #define ADC_TR_HT (ADC_TR1_HT1) 772 #define ADC_TR_LT (ADC_TR1_LT1) 773 #define ADC_HTR_HT (ADC_TR1_HT1) 774 #define ADC_LTR_LT (ADC_TR1_LT1) 775 776 /****************** Bit definition for ADC_CHSELR register ******************/ 777 #define ADC_CHSELR_CHSEL_Pos (0U) 778 #define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ 779 #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ 780 #define ADC_CHSELR_CHSEL18_Pos (18U) 781 #define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ 782 #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ 783 #define ADC_CHSELR_CHSEL17_Pos (17U) 784 #define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ 785 #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ 786 #define ADC_CHSELR_CHSEL16_Pos (16U) 787 #define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ 788 #define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ 789 #define ADC_CHSELR_CHSEL15_Pos (15U) 790 #define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ 791 #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ 792 #define ADC_CHSELR_CHSEL14_Pos (14U) 793 #define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ 794 #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ 795 #define ADC_CHSELR_CHSEL13_Pos (13U) 796 #define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ 797 #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ 798 #define ADC_CHSELR_CHSEL12_Pos (12U) 799 #define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ 800 #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ 801 #define ADC_CHSELR_CHSEL11_Pos (11U) 802 #define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ 803 #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ 804 #define ADC_CHSELR_CHSEL10_Pos (10U) 805 #define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ 806 #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ 807 #define ADC_CHSELR_CHSEL9_Pos (9U) 808 #define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ 809 #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ 810 #define ADC_CHSELR_CHSEL8_Pos (8U) 811 #define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ 812 #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ 813 #define ADC_CHSELR_CHSEL7_Pos (7U) 814 #define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ 815 #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ 816 #define ADC_CHSELR_CHSEL6_Pos (6U) 817 #define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ 818 #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ 819 #define ADC_CHSELR_CHSEL5_Pos (5U) 820 #define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ 821 #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ 822 #define ADC_CHSELR_CHSEL4_Pos (4U) 823 #define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ 824 #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ 825 #define ADC_CHSELR_CHSEL3_Pos (3U) 826 #define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ 827 #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ 828 #define ADC_CHSELR_CHSEL2_Pos (2U) 829 #define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ 830 #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ 831 #define ADC_CHSELR_CHSEL1_Pos (1U) 832 #define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ 833 #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ 834 #define ADC_CHSELR_CHSEL0_Pos (0U) 835 #define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ 836 #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ 837 838 /******************** Bit definition for ADC_DR register ********************/ 839 #define ADC_DR_DATA_Pos (0U) 840 #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ 841 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ 842 #define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ 843 #define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ 844 #define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ 845 #define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ 846 #define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ 847 #define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ 848 #define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ 849 #define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ 850 #define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ 851 #define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ 852 #define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ 853 #define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ 854 #define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ 855 #define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ 856 #define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ 857 #define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ 858 859 /************************* ADC Common registers *****************************/ 860 /******************* Bit definition for ADC_CCR register ********************/ 861 #define ADC_CCR_VREFEN_Pos (22U) 862 #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ 863 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ 864 #define ADC_CCR_TSEN_Pos (23U) 865 #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ 866 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ 867 868 869 /******************************************************************************/ 870 /* */ 871 /* CRC calculation unit (CRC) */ 872 /* */ 873 /******************************************************************************/ 874 /******************* Bit definition for CRC_DR register *********************/ 875 #define CRC_DR_DR_Pos (0U) 876 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ 877 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ 878 879 /******************* Bit definition for CRC_IDR register ********************/ 880 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */ 881 882 /******************** Bit definition for CRC_CR register ********************/ 883 #define CRC_CR_RESET_Pos (0U) 884 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ 885 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ 886 #define CRC_CR_REV_IN_Pos (5U) 887 #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ 888 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ 889 #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ 890 #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ 891 #define CRC_CR_REV_OUT_Pos (7U) 892 #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ 893 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ 894 895 /******************* Bit definition for CRC_INIT register *******************/ 896 #define CRC_INIT_INIT_Pos (0U) 897 #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ 898 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ 899 900 /******************************************************************************/ 901 /* */ 902 /* Debug MCU (DBGMCU) */ 903 /* */ 904 /******************************************************************************/ 905 906 /**************** Bit definition for DBGMCU_IDCODE register *****************/ 907 #define DBGMCU_IDCODE_DEV_ID_Pos (0U) 908 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ 909 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ 910 911 #define DBGMCU_IDCODE_REV_ID_Pos (16U) 912 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ 913 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ 914 #define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ 915 #define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ 916 #define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ 917 #define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ 918 #define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ 919 #define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ 920 #define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ 921 #define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ 922 #define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ 923 #define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ 924 #define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ 925 #define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ 926 #define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ 927 #define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ 928 #define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ 929 #define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ 930 931 /****************** Bit definition for DBGMCU_CR register *******************/ 932 #define DBGMCU_CR_DBG_STOP_Pos (1U) 933 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ 934 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ 935 #define DBGMCU_CR_DBG_STANDBY_Pos (2U) 936 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ 937 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ 938 939 /****************** Bit definition for DBGMCU_APB1_FZ register **************/ 940 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U) 941 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ 942 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */ 943 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U) 944 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ 945 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */ 946 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U) 947 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */ 948 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk /*!< TIM14 counter stopped when core is halted */ 949 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) 950 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ 951 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */ 952 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) 953 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ 954 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ 955 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) 956 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ 957 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ 958 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U) 959 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */ 960 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ 961 962 /****************** Bit definition for DBGMCU_APB2_FZ register **************/ 963 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (11U) 964 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ 965 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */ 966 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos (16U) 967 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */ 968 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk /*!< TIM15 counter stopped when core is halted */ 969 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (17U) 970 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ 971 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk /*!< TIM16 counter stopped when core is halted */ 972 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (18U) 973 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ 974 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk /*!< TIM17 counter stopped when core is halted */ 975 976 /******************************************************************************/ 977 /* */ 978 /* DMA Controller (DMA) */ 979 /* */ 980 /******************************************************************************/ 981 /******************* Bit definition for DMA_ISR register ********************/ 982 #define DMA_ISR_GIF1_Pos (0U) 983 #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ 984 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ 985 #define DMA_ISR_TCIF1_Pos (1U) 986 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ 987 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ 988 #define DMA_ISR_HTIF1_Pos (2U) 989 #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ 990 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ 991 #define DMA_ISR_TEIF1_Pos (3U) 992 #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ 993 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ 994 #define DMA_ISR_GIF2_Pos (4U) 995 #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ 996 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ 997 #define DMA_ISR_TCIF2_Pos (5U) 998 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ 999 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ 1000 #define DMA_ISR_HTIF2_Pos (6U) 1001 #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ 1002 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ 1003 #define DMA_ISR_TEIF2_Pos (7U) 1004 #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ 1005 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ 1006 #define DMA_ISR_GIF3_Pos (8U) 1007 #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ 1008 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ 1009 #define DMA_ISR_TCIF3_Pos (9U) 1010 #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ 1011 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ 1012 #define DMA_ISR_HTIF3_Pos (10U) 1013 #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ 1014 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ 1015 #define DMA_ISR_TEIF3_Pos (11U) 1016 #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ 1017 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ 1018 #define DMA_ISR_GIF4_Pos (12U) 1019 #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ 1020 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ 1021 #define DMA_ISR_TCIF4_Pos (13U) 1022 #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ 1023 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ 1024 #define DMA_ISR_HTIF4_Pos (14U) 1025 #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ 1026 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ 1027 #define DMA_ISR_TEIF4_Pos (15U) 1028 #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ 1029 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ 1030 #define DMA_ISR_GIF5_Pos (16U) 1031 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ 1032 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ 1033 #define DMA_ISR_TCIF5_Pos (17U) 1034 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ 1035 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ 1036 #define DMA_ISR_HTIF5_Pos (18U) 1037 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ 1038 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ 1039 #define DMA_ISR_TEIF5_Pos (19U) 1040 #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ 1041 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ 1042 1043 /******************* Bit definition for DMA_IFCR register *******************/ 1044 #define DMA_IFCR_CGIF1_Pos (0U) 1045 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ 1046 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ 1047 #define DMA_IFCR_CTCIF1_Pos (1U) 1048 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ 1049 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ 1050 #define DMA_IFCR_CHTIF1_Pos (2U) 1051 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ 1052 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ 1053 #define DMA_IFCR_CTEIF1_Pos (3U) 1054 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ 1055 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ 1056 #define DMA_IFCR_CGIF2_Pos (4U) 1057 #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ 1058 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ 1059 #define DMA_IFCR_CTCIF2_Pos (5U) 1060 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ 1061 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ 1062 #define DMA_IFCR_CHTIF2_Pos (6U) 1063 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ 1064 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ 1065 #define DMA_IFCR_CTEIF2_Pos (7U) 1066 #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ 1067 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ 1068 #define DMA_IFCR_CGIF3_Pos (8U) 1069 #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ 1070 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ 1071 #define DMA_IFCR_CTCIF3_Pos (9U) 1072 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ 1073 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ 1074 #define DMA_IFCR_CHTIF3_Pos (10U) 1075 #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ 1076 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ 1077 #define DMA_IFCR_CTEIF3_Pos (11U) 1078 #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ 1079 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ 1080 #define DMA_IFCR_CGIF4_Pos (12U) 1081 #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ 1082 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ 1083 #define DMA_IFCR_CTCIF4_Pos (13U) 1084 #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ 1085 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ 1086 #define DMA_IFCR_CHTIF4_Pos (14U) 1087 #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ 1088 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ 1089 #define DMA_IFCR_CTEIF4_Pos (15U) 1090 #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ 1091 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ 1092 #define DMA_IFCR_CGIF5_Pos (16U) 1093 #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ 1094 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ 1095 #define DMA_IFCR_CTCIF5_Pos (17U) 1096 #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ 1097 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ 1098 #define DMA_IFCR_CHTIF5_Pos (18U) 1099 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ 1100 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ 1101 #define DMA_IFCR_CTEIF5_Pos (19U) 1102 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ 1103 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ 1104 1105 /******************* Bit definition for DMA_CCR register ********************/ 1106 #define DMA_CCR_EN_Pos (0U) 1107 #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ 1108 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ 1109 #define DMA_CCR_TCIE_Pos (1U) 1110 #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ 1111 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ 1112 #define DMA_CCR_HTIE_Pos (2U) 1113 #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ 1114 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ 1115 #define DMA_CCR_TEIE_Pos (3U) 1116 #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ 1117 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ 1118 #define DMA_CCR_DIR_Pos (4U) 1119 #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ 1120 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ 1121 #define DMA_CCR_CIRC_Pos (5U) 1122 #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ 1123 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ 1124 #define DMA_CCR_PINC_Pos (6U) 1125 #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ 1126 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ 1127 #define DMA_CCR_MINC_Pos (7U) 1128 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ 1129 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ 1130 1131 #define DMA_CCR_PSIZE_Pos (8U) 1132 #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ 1133 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ 1134 #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ 1135 #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ 1136 1137 #define DMA_CCR_MSIZE_Pos (10U) 1138 #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ 1139 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ 1140 #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ 1141 #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ 1142 1143 #define DMA_CCR_PL_Pos (12U) 1144 #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ 1145 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ 1146 #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ 1147 #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ 1148 1149 #define DMA_CCR_MEM2MEM_Pos (14U) 1150 #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ 1151 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ 1152 1153 /****************** Bit definition for DMA_CNDTR register *******************/ 1154 #define DMA_CNDTR_NDT_Pos (0U) 1155 #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ 1156 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ 1157 1158 /****************** Bit definition for DMA_CPAR register ********************/ 1159 #define DMA_CPAR_PA_Pos (0U) 1160 #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ 1161 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ 1162 1163 /****************** Bit definition for DMA_CMAR register ********************/ 1164 #define DMA_CMAR_MA_Pos (0U) 1165 #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ 1166 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ 1167 1168 /******************************************************************************/ 1169 /* */ 1170 /* External Interrupt/Event Controller (EXTI) */ 1171 /* */ 1172 /******************************************************************************/ 1173 /******************* Bit definition for EXTI_IMR register *******************/ 1174 #define EXTI_IMR_MR0_Pos (0U) 1175 #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ 1176 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ 1177 #define EXTI_IMR_MR1_Pos (1U) 1178 #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ 1179 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ 1180 #define EXTI_IMR_MR2_Pos (2U) 1181 #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ 1182 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ 1183 #define EXTI_IMR_MR3_Pos (3U) 1184 #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ 1185 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ 1186 #define EXTI_IMR_MR4_Pos (4U) 1187 #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ 1188 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ 1189 #define EXTI_IMR_MR5_Pos (5U) 1190 #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ 1191 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ 1192 #define EXTI_IMR_MR6_Pos (6U) 1193 #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ 1194 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ 1195 #define EXTI_IMR_MR7_Pos (7U) 1196 #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ 1197 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ 1198 #define EXTI_IMR_MR8_Pos (8U) 1199 #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ 1200 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ 1201 #define EXTI_IMR_MR9_Pos (9U) 1202 #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ 1203 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ 1204 #define EXTI_IMR_MR10_Pos (10U) 1205 #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ 1206 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ 1207 #define EXTI_IMR_MR11_Pos (11U) 1208 #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ 1209 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ 1210 #define EXTI_IMR_MR12_Pos (12U) 1211 #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ 1212 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ 1213 #define EXTI_IMR_MR13_Pos (13U) 1214 #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ 1215 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ 1216 #define EXTI_IMR_MR14_Pos (14U) 1217 #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ 1218 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ 1219 #define EXTI_IMR_MR15_Pos (15U) 1220 #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ 1221 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ 1222 #define EXTI_IMR_MR17_Pos (17U) 1223 #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ 1224 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ 1225 #define EXTI_IMR_MR19_Pos (19U) 1226 #define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ 1227 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ 1228 1229 /* References Defines */ 1230 #define EXTI_IMR_IM0 EXTI_IMR_MR0 1231 #define EXTI_IMR_IM1 EXTI_IMR_MR1 1232 #define EXTI_IMR_IM2 EXTI_IMR_MR2 1233 #define EXTI_IMR_IM3 EXTI_IMR_MR3 1234 #define EXTI_IMR_IM4 EXTI_IMR_MR4 1235 #define EXTI_IMR_IM5 EXTI_IMR_MR5 1236 #define EXTI_IMR_IM6 EXTI_IMR_MR6 1237 #define EXTI_IMR_IM7 EXTI_IMR_MR7 1238 #define EXTI_IMR_IM8 EXTI_IMR_MR8 1239 #define EXTI_IMR_IM9 EXTI_IMR_MR9 1240 #define EXTI_IMR_IM10 EXTI_IMR_MR10 1241 #define EXTI_IMR_IM11 EXTI_IMR_MR11 1242 #define EXTI_IMR_IM12 EXTI_IMR_MR12 1243 #define EXTI_IMR_IM13 EXTI_IMR_MR13 1244 #define EXTI_IMR_IM14 EXTI_IMR_MR14 1245 #define EXTI_IMR_IM15 EXTI_IMR_MR15 1246 #define EXTI_IMR_IM17 EXTI_IMR_MR17 1247 #define EXTI_IMR_IM19 EXTI_IMR_MR19 1248 1249 #define EXTI_IMR_IM_Pos (0U) 1250 #define EXTI_IMR_IM_Msk (0x8EFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x008EFFFF */ 1251 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ 1252 1253 1254 /****************** Bit definition for EXTI_EMR register ********************/ 1255 #define EXTI_EMR_MR0_Pos (0U) 1256 #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ 1257 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ 1258 #define EXTI_EMR_MR1_Pos (1U) 1259 #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ 1260 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ 1261 #define EXTI_EMR_MR2_Pos (2U) 1262 #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ 1263 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ 1264 #define EXTI_EMR_MR3_Pos (3U) 1265 #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ 1266 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ 1267 #define EXTI_EMR_MR4_Pos (4U) 1268 #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ 1269 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ 1270 #define EXTI_EMR_MR5_Pos (5U) 1271 #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ 1272 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ 1273 #define EXTI_EMR_MR6_Pos (6U) 1274 #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ 1275 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ 1276 #define EXTI_EMR_MR7_Pos (7U) 1277 #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ 1278 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ 1279 #define EXTI_EMR_MR8_Pos (8U) 1280 #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ 1281 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ 1282 #define EXTI_EMR_MR9_Pos (9U) 1283 #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ 1284 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ 1285 #define EXTI_EMR_MR10_Pos (10U) 1286 #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ 1287 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ 1288 #define EXTI_EMR_MR11_Pos (11U) 1289 #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ 1290 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ 1291 #define EXTI_EMR_MR12_Pos (12U) 1292 #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ 1293 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ 1294 #define EXTI_EMR_MR13_Pos (13U) 1295 #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ 1296 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ 1297 #define EXTI_EMR_MR14_Pos (14U) 1298 #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ 1299 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ 1300 #define EXTI_EMR_MR15_Pos (15U) 1301 #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ 1302 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ 1303 #define EXTI_EMR_MR17_Pos (17U) 1304 #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ 1305 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ 1306 #define EXTI_EMR_MR19_Pos (19U) 1307 #define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ 1308 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ 1309 1310 /* References Defines */ 1311 #define EXTI_EMR_EM0 EXTI_EMR_MR0 1312 #define EXTI_EMR_EM1 EXTI_EMR_MR1 1313 #define EXTI_EMR_EM2 EXTI_EMR_MR2 1314 #define EXTI_EMR_EM3 EXTI_EMR_MR3 1315 #define EXTI_EMR_EM4 EXTI_EMR_MR4 1316 #define EXTI_EMR_EM5 EXTI_EMR_MR5 1317 #define EXTI_EMR_EM6 EXTI_EMR_MR6 1318 #define EXTI_EMR_EM7 EXTI_EMR_MR7 1319 #define EXTI_EMR_EM8 EXTI_EMR_MR8 1320 #define EXTI_EMR_EM9 EXTI_EMR_MR9 1321 #define EXTI_EMR_EM10 EXTI_EMR_MR10 1322 #define EXTI_EMR_EM11 EXTI_EMR_MR11 1323 #define EXTI_EMR_EM12 EXTI_EMR_MR12 1324 #define EXTI_EMR_EM13 EXTI_EMR_MR13 1325 #define EXTI_EMR_EM14 EXTI_EMR_MR14 1326 #define EXTI_EMR_EM15 EXTI_EMR_MR15 1327 #define EXTI_EMR_EM17 EXTI_EMR_MR17 1328 #define EXTI_EMR_EM19 EXTI_EMR_MR19 1329 1330 /******************* Bit definition for EXTI_RTSR register ******************/ 1331 #define EXTI_RTSR_TR0_Pos (0U) 1332 #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ 1333 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ 1334 #define EXTI_RTSR_TR1_Pos (1U) 1335 #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ 1336 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ 1337 #define EXTI_RTSR_TR2_Pos (2U) 1338 #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ 1339 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ 1340 #define EXTI_RTSR_TR3_Pos (3U) 1341 #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ 1342 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ 1343 #define EXTI_RTSR_TR4_Pos (4U) 1344 #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ 1345 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ 1346 #define EXTI_RTSR_TR5_Pos (5U) 1347 #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ 1348 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ 1349 #define EXTI_RTSR_TR6_Pos (6U) 1350 #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ 1351 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ 1352 #define EXTI_RTSR_TR7_Pos (7U) 1353 #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ 1354 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ 1355 #define EXTI_RTSR_TR8_Pos (8U) 1356 #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ 1357 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ 1358 #define EXTI_RTSR_TR9_Pos (9U) 1359 #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ 1360 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ 1361 #define EXTI_RTSR_TR10_Pos (10U) 1362 #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ 1363 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ 1364 #define EXTI_RTSR_TR11_Pos (11U) 1365 #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ 1366 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ 1367 #define EXTI_RTSR_TR12_Pos (12U) 1368 #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ 1369 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ 1370 #define EXTI_RTSR_TR13_Pos (13U) 1371 #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ 1372 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ 1373 #define EXTI_RTSR_TR14_Pos (14U) 1374 #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ 1375 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ 1376 #define EXTI_RTSR_TR15_Pos (15U) 1377 #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ 1378 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ 1379 #define EXTI_RTSR_TR16_Pos (16U) 1380 #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ 1381 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ 1382 #define EXTI_RTSR_TR17_Pos (17U) 1383 #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ 1384 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ 1385 #define EXTI_RTSR_TR19_Pos (19U) 1386 #define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ 1387 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ 1388 1389 /* References Defines */ 1390 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 1391 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1 1392 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2 1393 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3 1394 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4 1395 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5 1396 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6 1397 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7 1398 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8 1399 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9 1400 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10 1401 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11 1402 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12 1403 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13 1404 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14 1405 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15 1406 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 1407 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 1408 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19 1409 1410 /******************* Bit definition for EXTI_FTSR register *******************/ 1411 #define EXTI_FTSR_TR0_Pos (0U) 1412 #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ 1413 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ 1414 #define EXTI_FTSR_TR1_Pos (1U) 1415 #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ 1416 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ 1417 #define EXTI_FTSR_TR2_Pos (2U) 1418 #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ 1419 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ 1420 #define EXTI_FTSR_TR3_Pos (3U) 1421 #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ 1422 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ 1423 #define EXTI_FTSR_TR4_Pos (4U) 1424 #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ 1425 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ 1426 #define EXTI_FTSR_TR5_Pos (5U) 1427 #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ 1428 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ 1429 #define EXTI_FTSR_TR6_Pos (6U) 1430 #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ 1431 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ 1432 #define EXTI_FTSR_TR7_Pos (7U) 1433 #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ 1434 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ 1435 #define EXTI_FTSR_TR8_Pos (8U) 1436 #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ 1437 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ 1438 #define EXTI_FTSR_TR9_Pos (9U) 1439 #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ 1440 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ 1441 #define EXTI_FTSR_TR10_Pos (10U) 1442 #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ 1443 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ 1444 #define EXTI_FTSR_TR11_Pos (11U) 1445 #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ 1446 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ 1447 #define EXTI_FTSR_TR12_Pos (12U) 1448 #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ 1449 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ 1450 #define EXTI_FTSR_TR13_Pos (13U) 1451 #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ 1452 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ 1453 #define EXTI_FTSR_TR14_Pos (14U) 1454 #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ 1455 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ 1456 #define EXTI_FTSR_TR15_Pos (15U) 1457 #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ 1458 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ 1459 #define EXTI_FTSR_TR16_Pos (16U) 1460 #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ 1461 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ 1462 #define EXTI_FTSR_TR17_Pos (17U) 1463 #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ 1464 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ 1465 #define EXTI_FTSR_TR19_Pos (19U) 1466 #define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ 1467 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ 1468 1469 /* References Defines */ 1470 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 1471 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1 1472 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2 1473 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3 1474 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4 1475 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5 1476 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6 1477 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7 1478 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8 1479 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9 1480 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10 1481 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11 1482 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12 1483 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13 1484 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14 1485 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15 1486 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 1487 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 1488 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19 1489 1490 /******************* Bit definition for EXTI_SWIER register *******************/ 1491 #define EXTI_SWIER_SWIER0_Pos (0U) 1492 #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ 1493 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ 1494 #define EXTI_SWIER_SWIER1_Pos (1U) 1495 #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ 1496 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ 1497 #define EXTI_SWIER_SWIER2_Pos (2U) 1498 #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ 1499 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ 1500 #define EXTI_SWIER_SWIER3_Pos (3U) 1501 #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ 1502 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ 1503 #define EXTI_SWIER_SWIER4_Pos (4U) 1504 #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ 1505 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ 1506 #define EXTI_SWIER_SWIER5_Pos (5U) 1507 #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ 1508 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ 1509 #define EXTI_SWIER_SWIER6_Pos (6U) 1510 #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ 1511 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ 1512 #define EXTI_SWIER_SWIER7_Pos (7U) 1513 #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ 1514 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ 1515 #define EXTI_SWIER_SWIER8_Pos (8U) 1516 #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ 1517 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ 1518 #define EXTI_SWIER_SWIER9_Pos (9U) 1519 #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ 1520 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ 1521 #define EXTI_SWIER_SWIER10_Pos (10U) 1522 #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ 1523 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ 1524 #define EXTI_SWIER_SWIER11_Pos (11U) 1525 #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ 1526 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ 1527 #define EXTI_SWIER_SWIER12_Pos (12U) 1528 #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ 1529 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ 1530 #define EXTI_SWIER_SWIER13_Pos (13U) 1531 #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ 1532 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ 1533 #define EXTI_SWIER_SWIER14_Pos (14U) 1534 #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ 1535 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ 1536 #define EXTI_SWIER_SWIER15_Pos (15U) 1537 #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ 1538 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ 1539 #define EXTI_SWIER_SWIER16_Pos (16U) 1540 #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ 1541 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ 1542 #define EXTI_SWIER_SWIER17_Pos (17U) 1543 #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ 1544 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ 1545 #define EXTI_SWIER_SWIER19_Pos (19U) 1546 #define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ 1547 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ 1548 1549 /* References Defines */ 1550 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 1551 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 1552 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 1553 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 1554 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 1555 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 1556 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 1557 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 1558 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 1559 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 1560 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 1561 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 1562 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 1563 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 1564 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 1565 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 1566 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 1567 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 1568 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19 1569 1570 /****************** Bit definition for EXTI_PR register *********************/ 1571 #define EXTI_PR_PR0_Pos (0U) 1572 #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ 1573 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit 0 */ 1574 #define EXTI_PR_PR1_Pos (1U) 1575 #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ 1576 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit 1 */ 1577 #define EXTI_PR_PR2_Pos (2U) 1578 #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ 1579 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit 2 */ 1580 #define EXTI_PR_PR3_Pos (3U) 1581 #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ 1582 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit 3 */ 1583 #define EXTI_PR_PR4_Pos (4U) 1584 #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ 1585 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit 4 */ 1586 #define EXTI_PR_PR5_Pos (5U) 1587 #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ 1588 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit 5 */ 1589 #define EXTI_PR_PR6_Pos (6U) 1590 #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ 1591 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit 6 */ 1592 #define EXTI_PR_PR7_Pos (7U) 1593 #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ 1594 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit 7 */ 1595 #define EXTI_PR_PR8_Pos (8U) 1596 #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ 1597 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit 8 */ 1598 #define EXTI_PR_PR9_Pos (9U) 1599 #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ 1600 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit 9 */ 1601 #define EXTI_PR_PR10_Pos (10U) 1602 #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ 1603 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit 10 */ 1604 #define EXTI_PR_PR11_Pos (11U) 1605 #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ 1606 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit 11 */ 1607 #define EXTI_PR_PR12_Pos (12U) 1608 #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ 1609 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit 12 */ 1610 #define EXTI_PR_PR13_Pos (13U) 1611 #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ 1612 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit 13 */ 1613 #define EXTI_PR_PR14_Pos (14U) 1614 #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ 1615 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit 14 */ 1616 #define EXTI_PR_PR15_Pos (15U) 1617 #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ 1618 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit 15 */ 1619 #define EXTI_PR_PR16_Pos (16U) 1620 #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ 1621 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit 16 */ 1622 #define EXTI_PR_PR17_Pos (17U) 1623 #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ 1624 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit 17 */ 1625 #define EXTI_PR_PR19_Pos (19U) 1626 #define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ 1627 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit 19 */ 1628 1629 /* References Defines */ 1630 #define EXTI_PR_PIF0 EXTI_PR_PR0 1631 #define EXTI_PR_PIF1 EXTI_PR_PR1 1632 #define EXTI_PR_PIF2 EXTI_PR_PR2 1633 #define EXTI_PR_PIF3 EXTI_PR_PR3 1634 #define EXTI_PR_PIF4 EXTI_PR_PR4 1635 #define EXTI_PR_PIF5 EXTI_PR_PR5 1636 #define EXTI_PR_PIF6 EXTI_PR_PR6 1637 #define EXTI_PR_PIF7 EXTI_PR_PR7 1638 #define EXTI_PR_PIF8 EXTI_PR_PR8 1639 #define EXTI_PR_PIF9 EXTI_PR_PR9 1640 #define EXTI_PR_PIF10 EXTI_PR_PR10 1641 #define EXTI_PR_PIF11 EXTI_PR_PR11 1642 #define EXTI_PR_PIF12 EXTI_PR_PR12 1643 #define EXTI_PR_PIF13 EXTI_PR_PR13 1644 #define EXTI_PR_PIF14 EXTI_PR_PR14 1645 #define EXTI_PR_PIF15 EXTI_PR_PR15 1646 #define EXTI_PR_PIF16 EXTI_PR_PR16 1647 #define EXTI_PR_PIF17 EXTI_PR_PR17 1648 #define EXTI_PR_PIF19 EXTI_PR_PR19 1649 1650 /******************************************************************************/ 1651 /* */ 1652 /* FLASH and Option Bytes Registers */ 1653 /* */ 1654 /******************************************************************************/ 1655 1656 /******************* Bit definition for FLASH_ACR register ******************/ 1657 #define FLASH_ACR_LATENCY_Pos (0U) 1658 #define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ 1659 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */ 1660 1661 #define FLASH_ACR_PRFTBE_Pos (4U) 1662 #define FLASH_ACR_PRFTBE_Msk (0x1UL << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */ 1663 #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */ 1664 #define FLASH_ACR_PRFTBS_Pos (5U) 1665 #define FLASH_ACR_PRFTBS_Msk (0x1UL << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */ 1666 #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */ 1667 1668 /****************** Bit definition for FLASH_KEYR register ******************/ 1669 #define FLASH_KEYR_FKEYR_Pos (0U) 1670 #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */ 1671 #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */ 1672 1673 /***************** Bit definition for FLASH_OPTKEYR register ****************/ 1674 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U) 1675 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ 1676 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */ 1677 1678 /****************** FLASH Keys **********************************************/ 1679 #define FLASH_KEY1_Pos (0U) 1680 #define FLASH_KEY1_Msk (0x45670123UL << FLASH_KEY1_Pos) /*!< 0x45670123 */ 1681 #define FLASH_KEY1 FLASH_KEY1_Msk /*!< Flash program erase key1 */ 1682 #define FLASH_KEY2_Pos (0U) 1683 #define FLASH_KEY2_Msk (0xCDEF89ABUL << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */ 1684 #define FLASH_KEY2 FLASH_KEY2_Msk /*!< Flash program erase key2: used with FLASH_PEKEY1 1685 to unlock the write access to the FPEC. */ 1686 1687 #define FLASH_OPTKEY1_Pos (0U) 1688 #define FLASH_OPTKEY1_Msk (0x45670123UL << FLASH_OPTKEY1_Pos) /*!< 0x45670123 */ 1689 #define FLASH_OPTKEY1 FLASH_OPTKEY1_Msk /*!< Flash option key1 */ 1690 #define FLASH_OPTKEY2_Pos (0U) 1691 #define FLASH_OPTKEY2_Msk (0xCDEF89ABUL << FLASH_OPTKEY2_Pos) /*!< 0xCDEF89AB */ 1692 #define FLASH_OPTKEY2 FLASH_OPTKEY2_Msk /*!< Flash option key2: used with FLASH_OPTKEY1 to 1693 unlock the write access to the option byte block */ 1694 1695 /****************** Bit definition for FLASH_SR register *******************/ 1696 #define FLASH_SR_BSY_Pos (0U) 1697 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ 1698 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ 1699 #define FLASH_SR_PGERR_Pos (2U) 1700 #define FLASH_SR_PGERR_Msk (0x1UL << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */ 1701 #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */ 1702 #define FLASH_SR_WRPRTERR_Pos (4U) 1703 #define FLASH_SR_WRPRTERR_Msk (0x1UL << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */ 1704 #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */ 1705 #define FLASH_SR_EOP_Pos (5U) 1706 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000020 */ 1707 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */ 1708 #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */ 1709 1710 /******************* Bit definition for FLASH_CR register *******************/ 1711 #define FLASH_CR_PG_Pos (0U) 1712 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ 1713 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */ 1714 #define FLASH_CR_PER_Pos (1U) 1715 #define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ 1716 #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */ 1717 #define FLASH_CR_MER_Pos (2U) 1718 #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */ 1719 #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */ 1720 #define FLASH_CR_OPTPG_Pos (4U) 1721 #define FLASH_CR_OPTPG_Msk (0x1UL << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */ 1722 #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */ 1723 #define FLASH_CR_OPTER_Pos (5U) 1724 #define FLASH_CR_OPTER_Msk (0x1UL << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */ 1725 #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */ 1726 #define FLASH_CR_STRT_Pos (6U) 1727 #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00000040 */ 1728 #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */ 1729 #define FLASH_CR_LOCK_Pos (7U) 1730 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */ 1731 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */ 1732 #define FLASH_CR_OPTWRE_Pos (9U) 1733 #define FLASH_CR_OPTWRE_Msk (0x1UL << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */ 1734 #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */ 1735 #define FLASH_CR_ERRIE_Pos (10U) 1736 #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */ 1737 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */ 1738 #define FLASH_CR_EOPIE_Pos (12U) 1739 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */ 1740 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ 1741 #define FLASH_CR_OBL_LAUNCH_Pos (13U) 1742 #define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x00002000 */ 1743 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Option Bytes Loader Launch */ 1744 1745 /******************* Bit definition for FLASH_AR register *******************/ 1746 #define FLASH_AR_FAR_Pos (0U) 1747 #define FLASH_AR_FAR_Msk (0xFFFFFFFFUL << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */ 1748 #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */ 1749 1750 /****************** Bit definition for FLASH_OBR register *******************/ 1751 #define FLASH_OBR_OPTERR_Pos (0U) 1752 #define FLASH_OBR_OPTERR_Msk (0x1UL << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */ 1753 #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */ 1754 #define FLASH_OBR_RDPRT1_Pos (1U) 1755 #define FLASH_OBR_RDPRT1_Msk (0x1UL << FLASH_OBR_RDPRT1_Pos) /*!< 0x00000002 */ 1756 #define FLASH_OBR_RDPRT1 FLASH_OBR_RDPRT1_Msk /*!< Read protection Level 1 */ 1757 #define FLASH_OBR_RDPRT2_Pos (2U) 1758 #define FLASH_OBR_RDPRT2_Msk (0x1UL << FLASH_OBR_RDPRT2_Pos) /*!< 0x00000004 */ 1759 #define FLASH_OBR_RDPRT2 FLASH_OBR_RDPRT2_Msk /*!< Read protection Level 2 */ 1760 1761 #define FLASH_OBR_USER_Pos (8U) 1762 #define FLASH_OBR_USER_Msk (0x77UL << FLASH_OBR_USER_Pos) /*!< 0x00007700 */ 1763 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */ 1764 #define FLASH_OBR_IWDG_SW_Pos (8U) 1765 #define FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000100 */ 1766 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */ 1767 #define FLASH_OBR_nRST_STOP_Pos (9U) 1768 #define FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000200 */ 1769 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */ 1770 #define FLASH_OBR_nRST_STDBY_Pos (10U) 1771 #define FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000400 */ 1772 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */ 1773 #define FLASH_OBR_nBOOT1_Pos (12U) 1774 #define FLASH_OBR_nBOOT1_Msk (0x1UL << FLASH_OBR_nBOOT1_Pos) /*!< 0x00001000 */ 1775 #define FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk /*!< nBOOT1 */ 1776 #define FLASH_OBR_VDDA_MONITOR_Pos (13U) 1777 #define FLASH_OBR_VDDA_MONITOR_Msk (0x1UL << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */ 1778 #define FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk /*!< VDDA power supply supervisor */ 1779 #define FLASH_OBR_RAM_PARITY_CHECK_Pos (14U) 1780 #define FLASH_OBR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OBR_RAM_PARITY_CHECK_Pos) /*!< 0x00004000 */ 1781 #define FLASH_OBR_RAM_PARITY_CHECK FLASH_OBR_RAM_PARITY_CHECK_Msk /*!< RAM parity check */ 1782 #define FLASH_OBR_DATA0_Pos (16U) 1783 #define FLASH_OBR_DATA0_Msk (0xFFUL << FLASH_OBR_DATA0_Pos) /*!< 0x00FF0000 */ 1784 #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */ 1785 #define FLASH_OBR_DATA1_Pos (24U) 1786 #define FLASH_OBR_DATA1_Msk (0xFFUL << FLASH_OBR_DATA1_Pos) /*!< 0xFF000000 */ 1787 #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */ 1788 1789 /* Old BOOT1 bit definition, maintained for legacy purpose */ 1790 #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1 1791 1792 /* Old OBR_VDDA bit definition, maintained for legacy purpose */ 1793 #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR 1794 1795 /****************** Bit definition for FLASH_WRPR register ******************/ 1796 #define FLASH_WRPR_WRP_Pos (0U) 1797 #define FLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */ 1798 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */ 1799 1800 /*----------------------------------------------------------------------------*/ 1801 1802 /****************** Bit definition for OB_RDP register **********************/ 1803 #define OB_RDP_RDP_Pos (0U) 1804 #define OB_RDP_RDP_Msk (0xFFUL << OB_RDP_RDP_Pos) /*!< 0x000000FF */ 1805 #define OB_RDP_RDP OB_RDP_RDP_Msk /*!< Read protection option byte */ 1806 #define OB_RDP_nRDP_Pos (8U) 1807 #define OB_RDP_nRDP_Msk (0xFFUL << OB_RDP_nRDP_Pos) /*!< 0x0000FF00 */ 1808 #define OB_RDP_nRDP OB_RDP_nRDP_Msk /*!< Read protection complemented option byte */ 1809 1810 /****************** Bit definition for OB_USER register *********************/ 1811 #define OB_USER_USER_Pos (16U) 1812 #define OB_USER_USER_Msk (0xFFUL << OB_USER_USER_Pos) /*!< 0x00FF0000 */ 1813 #define OB_USER_USER OB_USER_USER_Msk /*!< User option byte */ 1814 #define OB_USER_nUSER_Pos (24U) 1815 #define OB_USER_nUSER_Msk (0xFFUL << OB_USER_nUSER_Pos) /*!< 0xFF000000 */ 1816 #define OB_USER_nUSER OB_USER_nUSER_Msk /*!< User complemented option byte */ 1817 1818 /****************** Bit definition for OB_WRP0 register *********************/ 1819 #define OB_WRP0_WRP0_Pos (0U) 1820 #define OB_WRP0_WRP0_Msk (0xFFUL << OB_WRP0_WRP0_Pos) /*!< 0x000000FF */ 1821 #define OB_WRP0_WRP0 OB_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */ 1822 #define OB_WRP0_nWRP0_Pos (8U) 1823 #define OB_WRP0_nWRP0_Msk (0xFFUL << OB_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */ 1824 #define OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */ 1825 1826 /****************** Bit definition for OB_WRP1 register *********************/ 1827 #define OB_WRP1_WRP1_Pos (16U) 1828 #define OB_WRP1_WRP1_Msk (0xFFUL << OB_WRP1_WRP1_Pos) /*!< 0x00FF0000 */ 1829 #define OB_WRP1_WRP1 OB_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */ 1830 #define OB_WRP1_nWRP1_Pos (24U) 1831 #define OB_WRP1_nWRP1_Msk (0xFFUL << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */ 1832 #define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */ 1833 1834 /******************************************************************************/ 1835 /* */ 1836 /* General Purpose IOs (GPIO) */ 1837 /* */ 1838 /******************************************************************************/ 1839 /******************* Bit definition for GPIO_MODER register *****************/ 1840 #define GPIO_MODER_MODER0_Pos (0U) 1841 #define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ 1842 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk 1843 #define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ 1844 #define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ 1845 #define GPIO_MODER_MODER1_Pos (2U) 1846 #define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ 1847 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk 1848 #define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ 1849 #define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ 1850 #define GPIO_MODER_MODER2_Pos (4U) 1851 #define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ 1852 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk 1853 #define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ 1854 #define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ 1855 #define GPIO_MODER_MODER3_Pos (6U) 1856 #define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ 1857 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk 1858 #define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ 1859 #define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ 1860 #define GPIO_MODER_MODER4_Pos (8U) 1861 #define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ 1862 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk 1863 #define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ 1864 #define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ 1865 #define GPIO_MODER_MODER5_Pos (10U) 1866 #define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ 1867 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk 1868 #define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ 1869 #define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ 1870 #define GPIO_MODER_MODER6_Pos (12U) 1871 #define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ 1872 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk 1873 #define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ 1874 #define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ 1875 #define GPIO_MODER_MODER7_Pos (14U) 1876 #define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ 1877 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk 1878 #define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ 1879 #define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ 1880 #define GPIO_MODER_MODER8_Pos (16U) 1881 #define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ 1882 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk 1883 #define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ 1884 #define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ 1885 #define GPIO_MODER_MODER9_Pos (18U) 1886 #define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ 1887 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk 1888 #define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ 1889 #define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ 1890 #define GPIO_MODER_MODER10_Pos (20U) 1891 #define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ 1892 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk 1893 #define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ 1894 #define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ 1895 #define GPIO_MODER_MODER11_Pos (22U) 1896 #define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ 1897 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk 1898 #define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ 1899 #define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ 1900 #define GPIO_MODER_MODER12_Pos (24U) 1901 #define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ 1902 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk 1903 #define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ 1904 #define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ 1905 #define GPIO_MODER_MODER13_Pos (26U) 1906 #define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ 1907 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk 1908 #define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ 1909 #define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ 1910 #define GPIO_MODER_MODER14_Pos (28U) 1911 #define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ 1912 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk 1913 #define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ 1914 #define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ 1915 #define GPIO_MODER_MODER15_Pos (30U) 1916 #define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ 1917 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk 1918 #define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ 1919 #define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ 1920 1921 /****************** Bit definition for GPIO_OTYPER register *****************/ 1922 #define GPIO_OTYPER_OT_0 (0x00000001U) 1923 #define GPIO_OTYPER_OT_1 (0x00000002U) 1924 #define GPIO_OTYPER_OT_2 (0x00000004U) 1925 #define GPIO_OTYPER_OT_3 (0x00000008U) 1926 #define GPIO_OTYPER_OT_4 (0x00000010U) 1927 #define GPIO_OTYPER_OT_5 (0x00000020U) 1928 #define GPIO_OTYPER_OT_6 (0x00000040U) 1929 #define GPIO_OTYPER_OT_7 (0x00000080U) 1930 #define GPIO_OTYPER_OT_8 (0x00000100U) 1931 #define GPIO_OTYPER_OT_9 (0x00000200U) 1932 #define GPIO_OTYPER_OT_10 (0x00000400U) 1933 #define GPIO_OTYPER_OT_11 (0x00000800U) 1934 #define GPIO_OTYPER_OT_12 (0x00001000U) 1935 #define GPIO_OTYPER_OT_13 (0x00002000U) 1936 #define GPIO_OTYPER_OT_14 (0x00004000U) 1937 #define GPIO_OTYPER_OT_15 (0x00008000U) 1938 1939 /**************** Bit definition for GPIO_OSPEEDR register ******************/ 1940 #define GPIO_OSPEEDR_OSPEEDR0_Pos (0U) 1941 #define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */ 1942 #define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk 1943 #define GPIO_OSPEEDR_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */ 1944 #define GPIO_OSPEEDR_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */ 1945 #define GPIO_OSPEEDR_OSPEEDR1_Pos (2U) 1946 #define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */ 1947 #define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk 1948 #define GPIO_OSPEEDR_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */ 1949 #define GPIO_OSPEEDR_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */ 1950 #define GPIO_OSPEEDR_OSPEEDR2_Pos (4U) 1951 #define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */ 1952 #define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk 1953 #define GPIO_OSPEEDR_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */ 1954 #define GPIO_OSPEEDR_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */ 1955 #define GPIO_OSPEEDR_OSPEEDR3_Pos (6U) 1956 #define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */ 1957 #define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk 1958 #define GPIO_OSPEEDR_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */ 1959 #define GPIO_OSPEEDR_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */ 1960 #define GPIO_OSPEEDR_OSPEEDR4_Pos (8U) 1961 #define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */ 1962 #define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk 1963 #define GPIO_OSPEEDR_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */ 1964 #define GPIO_OSPEEDR_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */ 1965 #define GPIO_OSPEEDR_OSPEEDR5_Pos (10U) 1966 #define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */ 1967 #define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk 1968 #define GPIO_OSPEEDR_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */ 1969 #define GPIO_OSPEEDR_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */ 1970 #define GPIO_OSPEEDR_OSPEEDR6_Pos (12U) 1971 #define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */ 1972 #define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk 1973 #define GPIO_OSPEEDR_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */ 1974 #define GPIO_OSPEEDR_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */ 1975 #define GPIO_OSPEEDR_OSPEEDR7_Pos (14U) 1976 #define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */ 1977 #define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk 1978 #define GPIO_OSPEEDR_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */ 1979 #define GPIO_OSPEEDR_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */ 1980 #define GPIO_OSPEEDR_OSPEEDR8_Pos (16U) 1981 #define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */ 1982 #define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk 1983 #define GPIO_OSPEEDR_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */ 1984 #define GPIO_OSPEEDR_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */ 1985 #define GPIO_OSPEEDR_OSPEEDR9_Pos (18U) 1986 #define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */ 1987 #define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk 1988 #define GPIO_OSPEEDR_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */ 1989 #define GPIO_OSPEEDR_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */ 1990 #define GPIO_OSPEEDR_OSPEEDR10_Pos (20U) 1991 #define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */ 1992 #define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk 1993 #define GPIO_OSPEEDR_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */ 1994 #define GPIO_OSPEEDR_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */ 1995 #define GPIO_OSPEEDR_OSPEEDR11_Pos (22U) 1996 #define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */ 1997 #define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk 1998 #define GPIO_OSPEEDR_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */ 1999 #define GPIO_OSPEEDR_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */ 2000 #define GPIO_OSPEEDR_OSPEEDR12_Pos (24U) 2001 #define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */ 2002 #define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk 2003 #define GPIO_OSPEEDR_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */ 2004 #define GPIO_OSPEEDR_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */ 2005 #define GPIO_OSPEEDR_OSPEEDR13_Pos (26U) 2006 #define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */ 2007 #define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk 2008 #define GPIO_OSPEEDR_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */ 2009 #define GPIO_OSPEEDR_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */ 2010 #define GPIO_OSPEEDR_OSPEEDR14_Pos (28U) 2011 #define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */ 2012 #define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk 2013 #define GPIO_OSPEEDR_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */ 2014 #define GPIO_OSPEEDR_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */ 2015 #define GPIO_OSPEEDR_OSPEEDR15_Pos (30U) 2016 #define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */ 2017 #define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk 2018 #define GPIO_OSPEEDR_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */ 2019 #define GPIO_OSPEEDR_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */ 2020 2021 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */ 2022 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0 2023 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0 2024 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1 2025 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1 2026 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0 2027 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1 2028 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2 2029 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0 2030 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1 2031 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3 2032 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0 2033 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1 2034 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4 2035 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0 2036 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1 2037 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5 2038 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0 2039 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1 2040 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6 2041 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0 2042 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1 2043 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7 2044 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0 2045 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1 2046 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8 2047 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0 2048 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1 2049 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9 2050 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0 2051 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1 2052 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10 2053 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0 2054 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1 2055 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11 2056 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0 2057 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1 2058 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12 2059 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0 2060 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1 2061 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13 2062 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0 2063 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1 2064 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14 2065 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0 2066 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1 2067 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15 2068 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0 2069 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1 2070 2071 /******************* Bit definition for GPIO_PUPDR register ******************/ 2072 #define GPIO_PUPDR_PUPDR0_Pos (0U) 2073 #define GPIO_PUPDR_PUPDR0_Msk (0x3UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */ 2074 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk 2075 #define GPIO_PUPDR_PUPDR0_0 (0x1UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */ 2076 #define GPIO_PUPDR_PUPDR0_1 (0x2UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */ 2077 #define GPIO_PUPDR_PUPDR1_Pos (2U) 2078 #define GPIO_PUPDR_PUPDR1_Msk (0x3UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */ 2079 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk 2080 #define GPIO_PUPDR_PUPDR1_0 (0x1UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */ 2081 #define GPIO_PUPDR_PUPDR1_1 (0x2UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */ 2082 #define GPIO_PUPDR_PUPDR2_Pos (4U) 2083 #define GPIO_PUPDR_PUPDR2_Msk (0x3UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */ 2084 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk 2085 #define GPIO_PUPDR_PUPDR2_0 (0x1UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */ 2086 #define GPIO_PUPDR_PUPDR2_1 (0x2UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */ 2087 #define GPIO_PUPDR_PUPDR3_Pos (6U) 2088 #define GPIO_PUPDR_PUPDR3_Msk (0x3UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */ 2089 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk 2090 #define GPIO_PUPDR_PUPDR3_0 (0x1UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */ 2091 #define GPIO_PUPDR_PUPDR3_1 (0x2UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */ 2092 #define GPIO_PUPDR_PUPDR4_Pos (8U) 2093 #define GPIO_PUPDR_PUPDR4_Msk (0x3UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */ 2094 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk 2095 #define GPIO_PUPDR_PUPDR4_0 (0x1UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */ 2096 #define GPIO_PUPDR_PUPDR4_1 (0x2UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */ 2097 #define GPIO_PUPDR_PUPDR5_Pos (10U) 2098 #define GPIO_PUPDR_PUPDR5_Msk (0x3UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */ 2099 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk 2100 #define GPIO_PUPDR_PUPDR5_0 (0x1UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */ 2101 #define GPIO_PUPDR_PUPDR5_1 (0x2UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */ 2102 #define GPIO_PUPDR_PUPDR6_Pos (12U) 2103 #define GPIO_PUPDR_PUPDR6_Msk (0x3UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */ 2104 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk 2105 #define GPIO_PUPDR_PUPDR6_0 (0x1UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */ 2106 #define GPIO_PUPDR_PUPDR6_1 (0x2UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */ 2107 #define GPIO_PUPDR_PUPDR7_Pos (14U) 2108 #define GPIO_PUPDR_PUPDR7_Msk (0x3UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */ 2109 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk 2110 #define GPIO_PUPDR_PUPDR7_0 (0x1UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */ 2111 #define GPIO_PUPDR_PUPDR7_1 (0x2UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */ 2112 #define GPIO_PUPDR_PUPDR8_Pos (16U) 2113 #define GPIO_PUPDR_PUPDR8_Msk (0x3UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */ 2114 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk 2115 #define GPIO_PUPDR_PUPDR8_0 (0x1UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */ 2116 #define GPIO_PUPDR_PUPDR8_1 (0x2UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */ 2117 #define GPIO_PUPDR_PUPDR9_Pos (18U) 2118 #define GPIO_PUPDR_PUPDR9_Msk (0x3UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */ 2119 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk 2120 #define GPIO_PUPDR_PUPDR9_0 (0x1UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */ 2121 #define GPIO_PUPDR_PUPDR9_1 (0x2UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */ 2122 #define GPIO_PUPDR_PUPDR10_Pos (20U) 2123 #define GPIO_PUPDR_PUPDR10_Msk (0x3UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */ 2124 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk 2125 #define GPIO_PUPDR_PUPDR10_0 (0x1UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */ 2126 #define GPIO_PUPDR_PUPDR10_1 (0x2UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */ 2127 #define GPIO_PUPDR_PUPDR11_Pos (22U) 2128 #define GPIO_PUPDR_PUPDR11_Msk (0x3UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */ 2129 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk 2130 #define GPIO_PUPDR_PUPDR11_0 (0x1UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */ 2131 #define GPIO_PUPDR_PUPDR11_1 (0x2UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */ 2132 #define GPIO_PUPDR_PUPDR12_Pos (24U) 2133 #define GPIO_PUPDR_PUPDR12_Msk (0x3UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */ 2134 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk 2135 #define GPIO_PUPDR_PUPDR12_0 (0x1UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */ 2136 #define GPIO_PUPDR_PUPDR12_1 (0x2UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */ 2137 #define GPIO_PUPDR_PUPDR13_Pos (26U) 2138 #define GPIO_PUPDR_PUPDR13_Msk (0x3UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */ 2139 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk 2140 #define GPIO_PUPDR_PUPDR13_0 (0x1UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */ 2141 #define GPIO_PUPDR_PUPDR13_1 (0x2UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */ 2142 #define GPIO_PUPDR_PUPDR14_Pos (28U) 2143 #define GPIO_PUPDR_PUPDR14_Msk (0x3UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */ 2144 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk 2145 #define GPIO_PUPDR_PUPDR14_0 (0x1UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */ 2146 #define GPIO_PUPDR_PUPDR14_1 (0x2UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */ 2147 #define GPIO_PUPDR_PUPDR15_Pos (30U) 2148 #define GPIO_PUPDR_PUPDR15_Msk (0x3UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */ 2149 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk 2150 #define GPIO_PUPDR_PUPDR15_0 (0x1UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */ 2151 #define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ 2152 2153 /******************* Bit definition for GPIO_IDR register *******************/ 2154 #define GPIO_IDR_0 (0x00000001U) 2155 #define GPIO_IDR_1 (0x00000002U) 2156 #define GPIO_IDR_2 (0x00000004U) 2157 #define GPIO_IDR_3 (0x00000008U) 2158 #define GPIO_IDR_4 (0x00000010U) 2159 #define GPIO_IDR_5 (0x00000020U) 2160 #define GPIO_IDR_6 (0x00000040U) 2161 #define GPIO_IDR_7 (0x00000080U) 2162 #define GPIO_IDR_8 (0x00000100U) 2163 #define GPIO_IDR_9 (0x00000200U) 2164 #define GPIO_IDR_10 (0x00000400U) 2165 #define GPIO_IDR_11 (0x00000800U) 2166 #define GPIO_IDR_12 (0x00001000U) 2167 #define GPIO_IDR_13 (0x00002000U) 2168 #define GPIO_IDR_14 (0x00004000U) 2169 #define GPIO_IDR_15 (0x00008000U) 2170 2171 /****************** Bit definition for GPIO_ODR register ********************/ 2172 #define GPIO_ODR_0 (0x00000001U) 2173 #define GPIO_ODR_1 (0x00000002U) 2174 #define GPIO_ODR_2 (0x00000004U) 2175 #define GPIO_ODR_3 (0x00000008U) 2176 #define GPIO_ODR_4 (0x00000010U) 2177 #define GPIO_ODR_5 (0x00000020U) 2178 #define GPIO_ODR_6 (0x00000040U) 2179 #define GPIO_ODR_7 (0x00000080U) 2180 #define GPIO_ODR_8 (0x00000100U) 2181 #define GPIO_ODR_9 (0x00000200U) 2182 #define GPIO_ODR_10 (0x00000400U) 2183 #define GPIO_ODR_11 (0x00000800U) 2184 #define GPIO_ODR_12 (0x00001000U) 2185 #define GPIO_ODR_13 (0x00002000U) 2186 #define GPIO_ODR_14 (0x00004000U) 2187 #define GPIO_ODR_15 (0x00008000U) 2188 2189 /****************** Bit definition for GPIO_BSRR register ********************/ 2190 #define GPIO_BSRR_BS_0 (0x00000001U) 2191 #define GPIO_BSRR_BS_1 (0x00000002U) 2192 #define GPIO_BSRR_BS_2 (0x00000004U) 2193 #define GPIO_BSRR_BS_3 (0x00000008U) 2194 #define GPIO_BSRR_BS_4 (0x00000010U) 2195 #define GPIO_BSRR_BS_5 (0x00000020U) 2196 #define GPIO_BSRR_BS_6 (0x00000040U) 2197 #define GPIO_BSRR_BS_7 (0x00000080U) 2198 #define GPIO_BSRR_BS_8 (0x00000100U) 2199 #define GPIO_BSRR_BS_9 (0x00000200U) 2200 #define GPIO_BSRR_BS_10 (0x00000400U) 2201 #define GPIO_BSRR_BS_11 (0x00000800U) 2202 #define GPIO_BSRR_BS_12 (0x00001000U) 2203 #define GPIO_BSRR_BS_13 (0x00002000U) 2204 #define GPIO_BSRR_BS_14 (0x00004000U) 2205 #define GPIO_BSRR_BS_15 (0x00008000U) 2206 #define GPIO_BSRR_BR_0 (0x00010000U) 2207 #define GPIO_BSRR_BR_1 (0x00020000U) 2208 #define GPIO_BSRR_BR_2 (0x00040000U) 2209 #define GPIO_BSRR_BR_3 (0x00080000U) 2210 #define GPIO_BSRR_BR_4 (0x00100000U) 2211 #define GPIO_BSRR_BR_5 (0x00200000U) 2212 #define GPIO_BSRR_BR_6 (0x00400000U) 2213 #define GPIO_BSRR_BR_7 (0x00800000U) 2214 #define GPIO_BSRR_BR_8 (0x01000000U) 2215 #define GPIO_BSRR_BR_9 (0x02000000U) 2216 #define GPIO_BSRR_BR_10 (0x04000000U) 2217 #define GPIO_BSRR_BR_11 (0x08000000U) 2218 #define GPIO_BSRR_BR_12 (0x10000000U) 2219 #define GPIO_BSRR_BR_13 (0x20000000U) 2220 #define GPIO_BSRR_BR_14 (0x40000000U) 2221 #define GPIO_BSRR_BR_15 (0x80000000U) 2222 2223 /****************** Bit definition for GPIO_LCKR register ********************/ 2224 #define GPIO_LCKR_LCK0_Pos (0U) 2225 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ 2226 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk 2227 #define GPIO_LCKR_LCK1_Pos (1U) 2228 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ 2229 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk 2230 #define GPIO_LCKR_LCK2_Pos (2U) 2231 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ 2232 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk 2233 #define GPIO_LCKR_LCK3_Pos (3U) 2234 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ 2235 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk 2236 #define GPIO_LCKR_LCK4_Pos (4U) 2237 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ 2238 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk 2239 #define GPIO_LCKR_LCK5_Pos (5U) 2240 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ 2241 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk 2242 #define GPIO_LCKR_LCK6_Pos (6U) 2243 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ 2244 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk 2245 #define GPIO_LCKR_LCK7_Pos (7U) 2246 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ 2247 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk 2248 #define GPIO_LCKR_LCK8_Pos (8U) 2249 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ 2250 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk 2251 #define GPIO_LCKR_LCK9_Pos (9U) 2252 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ 2253 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk 2254 #define GPIO_LCKR_LCK10_Pos (10U) 2255 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ 2256 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk 2257 #define GPIO_LCKR_LCK11_Pos (11U) 2258 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ 2259 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk 2260 #define GPIO_LCKR_LCK12_Pos (12U) 2261 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ 2262 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk 2263 #define GPIO_LCKR_LCK13_Pos (13U) 2264 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ 2265 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk 2266 #define GPIO_LCKR_LCK14_Pos (14U) 2267 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ 2268 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk 2269 #define GPIO_LCKR_LCK15_Pos (15U) 2270 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ 2271 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk 2272 #define GPIO_LCKR_LCKK_Pos (16U) 2273 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ 2274 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk 2275 2276 /****************** Bit definition for GPIO_AFRL register ********************/ 2277 #define GPIO_AFRL_AFSEL0_Pos (0U) 2278 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ 2279 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk 2280 #define GPIO_AFRL_AFSEL1_Pos (4U) 2281 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ 2282 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk 2283 #define GPIO_AFRL_AFSEL2_Pos (8U) 2284 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ 2285 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk 2286 #define GPIO_AFRL_AFSEL3_Pos (12U) 2287 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ 2288 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk 2289 #define GPIO_AFRL_AFSEL4_Pos (16U) 2290 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ 2291 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk 2292 #define GPIO_AFRL_AFSEL5_Pos (20U) 2293 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ 2294 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk 2295 #define GPIO_AFRL_AFSEL6_Pos (24U) 2296 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ 2297 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk 2298 #define GPIO_AFRL_AFSEL7_Pos (28U) 2299 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ 2300 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk 2301 2302 /* Legacy aliases */ 2303 #define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos 2304 #define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk 2305 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 2306 #define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos 2307 #define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk 2308 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 2309 #define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos 2310 #define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk 2311 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 2312 #define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos 2313 #define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk 2314 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 2315 #define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos 2316 #define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk 2317 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 2318 #define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos 2319 #define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk 2320 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 2321 #define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos 2322 #define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk 2323 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 2324 #define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos 2325 #define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk 2326 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 2327 2328 /****************** Bit definition for GPIO_AFRH register ********************/ 2329 #define GPIO_AFRH_AFSEL8_Pos (0U) 2330 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ 2331 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk 2332 #define GPIO_AFRH_AFSEL9_Pos (4U) 2333 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ 2334 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk 2335 #define GPIO_AFRH_AFSEL10_Pos (8U) 2336 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ 2337 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk 2338 #define GPIO_AFRH_AFSEL11_Pos (12U) 2339 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ 2340 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk 2341 #define GPIO_AFRH_AFSEL12_Pos (16U) 2342 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ 2343 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk 2344 #define GPIO_AFRH_AFSEL13_Pos (20U) 2345 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ 2346 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk 2347 #define GPIO_AFRH_AFSEL14_Pos (24U) 2348 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ 2349 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk 2350 #define GPIO_AFRH_AFSEL15_Pos (28U) 2351 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ 2352 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk 2353 2354 /* Legacy aliases */ 2355 #define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos 2356 #define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk 2357 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 2358 #define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos 2359 #define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk 2360 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 2361 #define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos 2362 #define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk 2363 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 2364 #define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos 2365 #define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk 2366 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 2367 #define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos 2368 #define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk 2369 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 2370 #define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos 2371 #define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk 2372 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 2373 #define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos 2374 #define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk 2375 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 2376 #define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos 2377 #define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk 2378 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 2379 2380 /****************** Bit definition for GPIO_BRR register *********************/ 2381 #define GPIO_BRR_BR_0 (0x00000001U) 2382 #define GPIO_BRR_BR_1 (0x00000002U) 2383 #define GPIO_BRR_BR_2 (0x00000004U) 2384 #define GPIO_BRR_BR_3 (0x00000008U) 2385 #define GPIO_BRR_BR_4 (0x00000010U) 2386 #define GPIO_BRR_BR_5 (0x00000020U) 2387 #define GPIO_BRR_BR_6 (0x00000040U) 2388 #define GPIO_BRR_BR_7 (0x00000080U) 2389 #define GPIO_BRR_BR_8 (0x00000100U) 2390 #define GPIO_BRR_BR_9 (0x00000200U) 2391 #define GPIO_BRR_BR_10 (0x00000400U) 2392 #define GPIO_BRR_BR_11 (0x00000800U) 2393 #define GPIO_BRR_BR_12 (0x00001000U) 2394 #define GPIO_BRR_BR_13 (0x00002000U) 2395 #define GPIO_BRR_BR_14 (0x00004000U) 2396 #define GPIO_BRR_BR_15 (0x00008000U) 2397 2398 /******************************************************************************/ 2399 /* */ 2400 /* Inter-integrated Circuit Interface (I2C) */ 2401 /* */ 2402 /******************************************************************************/ 2403 2404 /******************* Bit definition for I2C_CR1 register *******************/ 2405 #define I2C_CR1_PE_Pos (0U) 2406 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ 2407 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ 2408 #define I2C_CR1_TXIE_Pos (1U) 2409 #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ 2410 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ 2411 #define I2C_CR1_RXIE_Pos (2U) 2412 #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ 2413 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ 2414 #define I2C_CR1_ADDRIE_Pos (3U) 2415 #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ 2416 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ 2417 #define I2C_CR1_NACKIE_Pos (4U) 2418 #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ 2419 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ 2420 #define I2C_CR1_STOPIE_Pos (5U) 2421 #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ 2422 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ 2423 #define I2C_CR1_TCIE_Pos (6U) 2424 #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ 2425 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ 2426 #define I2C_CR1_ERRIE_Pos (7U) 2427 #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ 2428 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ 2429 #define I2C_CR1_DNF_Pos (8U) 2430 #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ 2431 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ 2432 #define I2C_CR1_ANFOFF_Pos (12U) 2433 #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ 2434 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ 2435 #define I2C_CR1_SWRST_Pos (13U) 2436 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ 2437 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ 2438 #define I2C_CR1_TXDMAEN_Pos (14U) 2439 #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ 2440 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ 2441 #define I2C_CR1_RXDMAEN_Pos (15U) 2442 #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ 2443 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ 2444 #define I2C_CR1_SBC_Pos (16U) 2445 #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ 2446 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ 2447 #define I2C_CR1_NOSTRETCH_Pos (17U) 2448 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ 2449 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ 2450 #define I2C_CR1_GCEN_Pos (19U) 2451 #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ 2452 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ 2453 #define I2C_CR1_SMBHEN_Pos (20U) 2454 #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ 2455 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ 2456 #define I2C_CR1_SMBDEN_Pos (21U) 2457 #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ 2458 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ 2459 #define I2C_CR1_ALERTEN_Pos (22U) 2460 #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ 2461 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ 2462 #define I2C_CR1_PECEN_Pos (23U) 2463 #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ 2464 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ 2465 2466 /****************** Bit definition for I2C_CR2 register ********************/ 2467 #define I2C_CR2_SADD_Pos (0U) 2468 #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ 2469 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ 2470 #define I2C_CR2_RD_WRN_Pos (10U) 2471 #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ 2472 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ 2473 #define I2C_CR2_ADD10_Pos (11U) 2474 #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ 2475 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ 2476 #define I2C_CR2_HEAD10R_Pos (12U) 2477 #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ 2478 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ 2479 #define I2C_CR2_START_Pos (13U) 2480 #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ 2481 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ 2482 #define I2C_CR2_STOP_Pos (14U) 2483 #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ 2484 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ 2485 #define I2C_CR2_NACK_Pos (15U) 2486 #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ 2487 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ 2488 #define I2C_CR2_NBYTES_Pos (16U) 2489 #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ 2490 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ 2491 #define I2C_CR2_RELOAD_Pos (24U) 2492 #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ 2493 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ 2494 #define I2C_CR2_AUTOEND_Pos (25U) 2495 #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ 2496 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ 2497 #define I2C_CR2_PECBYTE_Pos (26U) 2498 #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ 2499 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ 2500 2501 /******************* Bit definition for I2C_OAR1 register ******************/ 2502 #define I2C_OAR1_OA1_Pos (0U) 2503 #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ 2504 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ 2505 #define I2C_OAR1_OA1MODE_Pos (10U) 2506 #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ 2507 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ 2508 #define I2C_OAR1_OA1EN_Pos (15U) 2509 #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ 2510 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ 2511 2512 /******************* Bit definition for I2C_OAR2 register ******************/ 2513 #define I2C_OAR2_OA2_Pos (1U) 2514 #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ 2515 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ 2516 #define I2C_OAR2_OA2MSK_Pos (8U) 2517 #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ 2518 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ 2519 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */ 2520 #define I2C_OAR2_OA2MASK01_Pos (8U) 2521 #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ 2522 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ 2523 #define I2C_OAR2_OA2MASK02_Pos (9U) 2524 #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ 2525 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ 2526 #define I2C_OAR2_OA2MASK03_Pos (8U) 2527 #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ 2528 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ 2529 #define I2C_OAR2_OA2MASK04_Pos (10U) 2530 #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ 2531 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ 2532 #define I2C_OAR2_OA2MASK05_Pos (8U) 2533 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ 2534 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ 2535 #define I2C_OAR2_OA2MASK06_Pos (9U) 2536 #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ 2537 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ 2538 #define I2C_OAR2_OA2MASK07_Pos (8U) 2539 #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ 2540 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ 2541 #define I2C_OAR2_OA2EN_Pos (15U) 2542 #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ 2543 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ 2544 2545 /******************* Bit definition for I2C_TIMINGR register ****************/ 2546 #define I2C_TIMINGR_SCLL_Pos (0U) 2547 #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ 2548 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ 2549 #define I2C_TIMINGR_SCLH_Pos (8U) 2550 #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ 2551 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ 2552 #define I2C_TIMINGR_SDADEL_Pos (16U) 2553 #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ 2554 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ 2555 #define I2C_TIMINGR_SCLDEL_Pos (20U) 2556 #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ 2557 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ 2558 #define I2C_TIMINGR_PRESC_Pos (28U) 2559 #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ 2560 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ 2561 2562 /******************* Bit definition for I2C_TIMEOUTR register ****************/ 2563 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) 2564 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ 2565 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ 2566 #define I2C_TIMEOUTR_TIDLE_Pos (12U) 2567 #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ 2568 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ 2569 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) 2570 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ 2571 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ 2572 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) 2573 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ 2574 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ 2575 #define I2C_TIMEOUTR_TEXTEN_Pos (31U) 2576 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ 2577 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ 2578 2579 /****************** Bit definition for I2C_ISR register ********************/ 2580 #define I2C_ISR_TXE_Pos (0U) 2581 #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ 2582 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ 2583 #define I2C_ISR_TXIS_Pos (1U) 2584 #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ 2585 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ 2586 #define I2C_ISR_RXNE_Pos (2U) 2587 #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ 2588 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ 2589 #define I2C_ISR_ADDR_Pos (3U) 2590 #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ 2591 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ 2592 #define I2C_ISR_NACKF_Pos (4U) 2593 #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ 2594 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ 2595 #define I2C_ISR_STOPF_Pos (5U) 2596 #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ 2597 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ 2598 #define I2C_ISR_TC_Pos (6U) 2599 #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ 2600 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ 2601 #define I2C_ISR_TCR_Pos (7U) 2602 #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ 2603 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ 2604 #define I2C_ISR_BERR_Pos (8U) 2605 #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ 2606 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ 2607 #define I2C_ISR_ARLO_Pos (9U) 2608 #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ 2609 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ 2610 #define I2C_ISR_OVR_Pos (10U) 2611 #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ 2612 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ 2613 #define I2C_ISR_PECERR_Pos (11U) 2614 #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ 2615 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ 2616 #define I2C_ISR_TIMEOUT_Pos (12U) 2617 #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ 2618 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ 2619 #define I2C_ISR_ALERT_Pos (13U) 2620 #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ 2621 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ 2622 #define I2C_ISR_BUSY_Pos (15U) 2623 #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ 2624 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ 2625 #define I2C_ISR_DIR_Pos (16U) 2626 #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ 2627 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ 2628 #define I2C_ISR_ADDCODE_Pos (17U) 2629 #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ 2630 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ 2631 2632 /****************** Bit definition for I2C_ICR register ********************/ 2633 #define I2C_ICR_ADDRCF_Pos (3U) 2634 #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ 2635 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ 2636 #define I2C_ICR_NACKCF_Pos (4U) 2637 #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ 2638 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ 2639 #define I2C_ICR_STOPCF_Pos (5U) 2640 #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ 2641 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ 2642 #define I2C_ICR_BERRCF_Pos (8U) 2643 #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ 2644 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ 2645 #define I2C_ICR_ARLOCF_Pos (9U) 2646 #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ 2647 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ 2648 #define I2C_ICR_OVRCF_Pos (10U) 2649 #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ 2650 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ 2651 #define I2C_ICR_PECCF_Pos (11U) 2652 #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ 2653 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ 2654 #define I2C_ICR_TIMOUTCF_Pos (12U) 2655 #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ 2656 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ 2657 #define I2C_ICR_ALERTCF_Pos (13U) 2658 #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ 2659 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ 2660 2661 /****************** Bit definition for I2C_PECR register *******************/ 2662 #define I2C_PECR_PEC_Pos (0U) 2663 #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ 2664 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ 2665 2666 /****************** Bit definition for I2C_RXDR register *********************/ 2667 #define I2C_RXDR_RXDATA_Pos (0U) 2668 #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ 2669 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ 2670 2671 /****************** Bit definition for I2C_TXDR register *******************/ 2672 #define I2C_TXDR_TXDATA_Pos (0U) 2673 #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ 2674 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ 2675 2676 /*****************************************************************************/ 2677 /* */ 2678 /* Independent WATCHDOG (IWDG) */ 2679 /* */ 2680 /*****************************************************************************/ 2681 /******************* Bit definition for IWDG_KR register *******************/ 2682 #define IWDG_KR_KEY_Pos (0U) 2683 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ 2684 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ 2685 2686 /******************* Bit definition for IWDG_PR register *******************/ 2687 #define IWDG_PR_PR_Pos (0U) 2688 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */ 2689 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ 2690 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x01 */ 2691 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x02 */ 2692 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x04 */ 2693 2694 /******************* Bit definition for IWDG_RLR register ******************/ 2695 #define IWDG_RLR_RL_Pos (0U) 2696 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ 2697 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ 2698 2699 /******************* Bit definition for IWDG_SR register *******************/ 2700 #define IWDG_SR_PVU_Pos (0U) 2701 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ 2702 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ 2703 #define IWDG_SR_RVU_Pos (1U) 2704 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ 2705 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ 2706 #define IWDG_SR_WVU_Pos (2U) 2707 #define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */ 2708 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */ 2709 2710 /******************* Bit definition for IWDG_KR register *******************/ 2711 #define IWDG_WINR_WIN_Pos (0U) 2712 #define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */ 2713 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */ 2714 2715 /*****************************************************************************/ 2716 /* */ 2717 /* Power Control (PWR) */ 2718 /* */ 2719 /*****************************************************************************/ 2720 2721 /* Note: No specific macro feature on this device */ 2722 2723 2724 /******************** Bit definition for PWR_CR register *******************/ 2725 #define PWR_CR_LPDS_Pos (0U) 2726 #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ 2727 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-power Deepsleep */ 2728 #define PWR_CR_PDDS_Pos (1U) 2729 #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ 2730 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ 2731 #define PWR_CR_CWUF_Pos (2U) 2732 #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ 2733 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ 2734 #define PWR_CR_CSBF_Pos (3U) 2735 #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ 2736 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ 2737 #define PWR_CR_DBP_Pos (8U) 2738 #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */ 2739 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ 2740 2741 /******************* Bit definition for PWR_CSR register *******************/ 2742 #define PWR_CSR_WUF_Pos (0U) 2743 #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ 2744 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ 2745 #define PWR_CSR_SBF_Pos (1U) 2746 #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ 2747 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ 2748 2749 #define PWR_CSR_EWUP1_Pos (8U) 2750 #define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */ 2751 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */ 2752 #define PWR_CSR_EWUP2_Pos (9U) 2753 #define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */ 2754 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */ 2755 2756 /*****************************************************************************/ 2757 /* */ 2758 /* Reset and Clock Control */ 2759 /* */ 2760 /*****************************************************************************/ 2761 /* 2762 * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) 2763 */ 2764 2765 /******************** Bit definition for RCC_CR register *******************/ 2766 #define RCC_CR_HSION_Pos (0U) 2767 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ 2768 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ 2769 #define RCC_CR_HSIRDY_Pos (1U) 2770 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ 2771 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ 2772 2773 #define RCC_CR_HSITRIM_Pos (3U) 2774 #define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ 2775 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ 2776 #define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */ 2777 #define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */ 2778 #define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */ 2779 #define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */ 2780 #define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */ 2781 2782 #define RCC_CR_HSICAL_Pos (8U) 2783 #define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ 2784 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ 2785 #define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */ 2786 #define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */ 2787 #define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */ 2788 #define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */ 2789 #define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */ 2790 #define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */ 2791 #define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */ 2792 #define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */ 2793 2794 #define RCC_CR_HSEON_Pos (16U) 2795 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ 2796 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ 2797 #define RCC_CR_HSERDY_Pos (17U) 2798 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ 2799 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ 2800 #define RCC_CR_HSEBYP_Pos (18U) 2801 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ 2802 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ 2803 #define RCC_CR_CSSON_Pos (19U) 2804 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ 2805 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ 2806 #define RCC_CR_PLLON_Pos (24U) 2807 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ 2808 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ 2809 #define RCC_CR_PLLRDY_Pos (25U) 2810 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ 2811 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ 2812 2813 /******************** Bit definition for RCC_CFGR register *****************/ 2814 /*!< SW configuration */ 2815 #define RCC_CFGR_SW_Pos (0U) 2816 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ 2817 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ 2818 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ 2819 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ 2820 2821 #define RCC_CFGR_SW_HSI (0x00000000U) /*!< HSI selected as system clock */ 2822 #define RCC_CFGR_SW_HSE (0x00000001U) /*!< HSE selected as system clock */ 2823 #define RCC_CFGR_SW_PLL (0x00000002U) /*!< PLL selected as system clock */ 2824 2825 /*!< SWS configuration */ 2826 #define RCC_CFGR_SWS_Pos (2U) 2827 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ 2828 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ 2829 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ 2830 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ 2831 2832 #define RCC_CFGR_SWS_HSI (0x00000000U) /*!< HSI oscillator used as system clock */ 2833 #define RCC_CFGR_SWS_HSE (0x00000004U) /*!< HSE oscillator used as system clock */ 2834 #define RCC_CFGR_SWS_PLL (0x00000008U) /*!< PLL used as system clock */ 2835 2836 /*!< HPRE configuration */ 2837 #define RCC_CFGR_HPRE_Pos (4U) 2838 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ 2839 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ 2840 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ 2841 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ 2842 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ 2843 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ 2844 2845 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */ 2846 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */ 2847 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */ 2848 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */ 2849 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */ 2850 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */ 2851 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */ 2852 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */ 2853 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */ 2854 2855 /*!< PPRE configuration */ 2856 #define RCC_CFGR_PPRE_Pos (8U) 2857 #define RCC_CFGR_PPRE_Msk (0x7UL << RCC_CFGR_PPRE_Pos) /*!< 0x00000700 */ 2858 #define RCC_CFGR_PPRE RCC_CFGR_PPRE_Msk /*!< PRE[2:0] bits (APB prescaler) */ 2859 #define RCC_CFGR_PPRE_0 (0x1UL << RCC_CFGR_PPRE_Pos) /*!< 0x00000100 */ 2860 #define RCC_CFGR_PPRE_1 (0x2UL << RCC_CFGR_PPRE_Pos) /*!< 0x00000200 */ 2861 #define RCC_CFGR_PPRE_2 (0x4UL << RCC_CFGR_PPRE_Pos) /*!< 0x00000400 */ 2862 2863 #define RCC_CFGR_PPRE_DIV1 (0x00000000U) /*!< HCLK not divided */ 2864 #define RCC_CFGR_PPRE_DIV2_Pos (10U) 2865 #define RCC_CFGR_PPRE_DIV2_Msk (0x1UL << RCC_CFGR_PPRE_DIV2_Pos) /*!< 0x00000400 */ 2866 #define RCC_CFGR_PPRE_DIV2 RCC_CFGR_PPRE_DIV2_Msk /*!< HCLK divided by 2 */ 2867 #define RCC_CFGR_PPRE_DIV4_Pos (8U) 2868 #define RCC_CFGR_PPRE_DIV4_Msk (0x5UL << RCC_CFGR_PPRE_DIV4_Pos) /*!< 0x00000500 */ 2869 #define RCC_CFGR_PPRE_DIV4 RCC_CFGR_PPRE_DIV4_Msk /*!< HCLK divided by 4 */ 2870 #define RCC_CFGR_PPRE_DIV8_Pos (9U) 2871 #define RCC_CFGR_PPRE_DIV8_Msk (0x3UL << RCC_CFGR_PPRE_DIV8_Pos) /*!< 0x00000600 */ 2872 #define RCC_CFGR_PPRE_DIV8 RCC_CFGR_PPRE_DIV8_Msk /*!< HCLK divided by 8 */ 2873 #define RCC_CFGR_PPRE_DIV16_Pos (8U) 2874 #define RCC_CFGR_PPRE_DIV16_Msk (0x7UL << RCC_CFGR_PPRE_DIV16_Pos) /*!< 0x00000700 */ 2875 #define RCC_CFGR_PPRE_DIV16 RCC_CFGR_PPRE_DIV16_Msk /*!< HCLK divided by 16 */ 2876 2877 /*!< ADCPPRE configuration */ 2878 #define RCC_CFGR_ADCPRE_Pos (14U) 2879 #define RCC_CFGR_ADCPRE_Msk (0x1UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */ 2880 #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE bit (ADC prescaler) */ 2881 2882 #define RCC_CFGR_ADCPRE_DIV2 (0x00000000U) /*!< PCLK divided by 2 */ 2883 #define RCC_CFGR_ADCPRE_DIV4 (0x00004000U) /*!< PCLK divided by 4 */ 2884 2885 #define RCC_CFGR_PLLSRC_Pos (16U) 2886 #define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ 2887 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ 2888 #define RCC_CFGR_PLLSRC_HSI_DIV2 (0x00000000U) /*!< HSI clock divided by 2 selected as PLL entry clock source */ 2889 #define RCC_CFGR_PLLSRC_HSE_PREDIV (0x00010000U) /*!< HSE/PREDIV clock selected as PLL entry clock source */ 2890 2891 #define RCC_CFGR_PLLXTPRE_Pos (17U) 2892 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ 2893 #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ 2894 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 (0x00000000U) /*!< HSE/PREDIV clock not divided for PLL entry */ 2895 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 (0x00020000U) /*!< HSE/PREDIV clock divided by 2 for PLL entry */ 2896 2897 /*!< PLLMUL configuration */ 2898 #define RCC_CFGR_PLLMUL_Pos (18U) 2899 #define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */ 2900 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ 2901 #define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */ 2902 #define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */ 2903 #define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */ 2904 #define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */ 2905 2906 #define RCC_CFGR_PLLMUL2 (0x00000000U) /*!< PLL input clock*2 */ 2907 #define RCC_CFGR_PLLMUL3 (0x00040000U) /*!< PLL input clock*3 */ 2908 #define RCC_CFGR_PLLMUL4 (0x00080000U) /*!< PLL input clock*4 */ 2909 #define RCC_CFGR_PLLMUL5 (0x000C0000U) /*!< PLL input clock*5 */ 2910 #define RCC_CFGR_PLLMUL6 (0x00100000U) /*!< PLL input clock*6 */ 2911 #define RCC_CFGR_PLLMUL7 (0x00140000U) /*!< PLL input clock*7 */ 2912 #define RCC_CFGR_PLLMUL8 (0x00180000U) /*!< PLL input clock*8 */ 2913 #define RCC_CFGR_PLLMUL9 (0x001C0000U) /*!< PLL input clock*9 */ 2914 #define RCC_CFGR_PLLMUL10 (0x00200000U) /*!< PLL input clock10 */ 2915 #define RCC_CFGR_PLLMUL11 (0x00240000U) /*!< PLL input clock*11 */ 2916 #define RCC_CFGR_PLLMUL12 (0x00280000U) /*!< PLL input clock*12 */ 2917 #define RCC_CFGR_PLLMUL13 (0x002C0000U) /*!< PLL input clock*13 */ 2918 #define RCC_CFGR_PLLMUL14 (0x00300000U) /*!< PLL input clock*14 */ 2919 #define RCC_CFGR_PLLMUL15 (0x00340000U) /*!< PLL input clock*15 */ 2920 #define RCC_CFGR_PLLMUL16 (0x00380000U) /*!< PLL input clock*16 */ 2921 2922 /*!< MCO configuration */ 2923 #define RCC_CFGR_MCO_Pos (24U) 2924 #define RCC_CFGR_MCO_Msk (0xFUL << RCC_CFGR_MCO_Pos) /*!< 0x0F000000 */ 2925 #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */ 2926 #define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ 2927 #define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ 2928 #define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ 2929 2930 #define RCC_CFGR_MCO_NOCLOCK (0x00000000U) /*!< No clock */ 2931 #define RCC_CFGR_MCO_HSI14 (0x01000000U) /*!< HSI14 clock selected as MCO source */ 2932 #define RCC_CFGR_MCO_LSI (0x02000000U) /*!< LSI clock selected as MCO source */ 2933 #define RCC_CFGR_MCO_LSE (0x03000000U) /*!< LSE clock selected as MCO source */ 2934 #define RCC_CFGR_MCO_SYSCLK (0x04000000U) /*!< System clock selected as MCO source */ 2935 #define RCC_CFGR_MCO_HSI (0x05000000U) /*!< HSI clock selected as MCO source */ 2936 #define RCC_CFGR_MCO_HSE (0x06000000U) /*!< HSE clock selected as MCO source */ 2937 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divided by 2 selected as MCO source */ 2938 2939 /* Reference defines */ 2940 #define RCC_CFGR_MCOSEL RCC_CFGR_MCO 2941 #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 2942 #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 2943 #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 2944 #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK 2945 #define RCC_CFGR_MCOSEL_HSI14 RCC_CFGR_MCO_HSI14 2946 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCO_LSI 2947 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCO_LSE 2948 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK 2949 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI 2950 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE 2951 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL 2952 2953 /*!<****************** Bit definition for RCC_CIR register *****************/ 2954 #define RCC_CIR_LSIRDYF_Pos (0U) 2955 #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ 2956 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ 2957 #define RCC_CIR_LSERDYF_Pos (1U) 2958 #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ 2959 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ 2960 #define RCC_CIR_HSIRDYF_Pos (2U) 2961 #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ 2962 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ 2963 #define RCC_CIR_HSERDYF_Pos (3U) 2964 #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ 2965 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ 2966 #define RCC_CIR_PLLRDYF_Pos (4U) 2967 #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ 2968 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ 2969 #define RCC_CIR_HSI14RDYF_Pos (5U) 2970 #define RCC_CIR_HSI14RDYF_Msk (0x1UL << RCC_CIR_HSI14RDYF_Pos) /*!< 0x00000020 */ 2971 #define RCC_CIR_HSI14RDYF RCC_CIR_HSI14RDYF_Msk /*!< HSI14 Ready Interrupt flag */ 2972 #define RCC_CIR_CSSF_Pos (7U) 2973 #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ 2974 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ 2975 #define RCC_CIR_LSIRDYIE_Pos (8U) 2976 #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ 2977 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ 2978 #define RCC_CIR_LSERDYIE_Pos (9U) 2979 #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ 2980 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ 2981 #define RCC_CIR_HSIRDYIE_Pos (10U) 2982 #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ 2983 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ 2984 #define RCC_CIR_HSERDYIE_Pos (11U) 2985 #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ 2986 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ 2987 #define RCC_CIR_PLLRDYIE_Pos (12U) 2988 #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ 2989 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ 2990 #define RCC_CIR_HSI14RDYIE_Pos (13U) 2991 #define RCC_CIR_HSI14RDYIE_Msk (0x1UL << RCC_CIR_HSI14RDYIE_Pos) /*!< 0x00002000 */ 2992 #define RCC_CIR_HSI14RDYIE RCC_CIR_HSI14RDYIE_Msk /*!< HSI14 Ready Interrupt Enable */ 2993 #define RCC_CIR_LSIRDYC_Pos (16U) 2994 #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ 2995 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ 2996 #define RCC_CIR_LSERDYC_Pos (17U) 2997 #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ 2998 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ 2999 #define RCC_CIR_HSIRDYC_Pos (18U) 3000 #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ 3001 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ 3002 #define RCC_CIR_HSERDYC_Pos (19U) 3003 #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ 3004 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ 3005 #define RCC_CIR_PLLRDYC_Pos (20U) 3006 #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ 3007 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ 3008 #define RCC_CIR_HSI14RDYC_Pos (21U) 3009 #define RCC_CIR_HSI14RDYC_Msk (0x1UL << RCC_CIR_HSI14RDYC_Pos) /*!< 0x00200000 */ 3010 #define RCC_CIR_HSI14RDYC RCC_CIR_HSI14RDYC_Msk /*!< HSI14 Ready Interrupt Clear */ 3011 #define RCC_CIR_CSSC_Pos (23U) 3012 #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ 3013 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ 3014 3015 /***************** Bit definition for RCC_APB2RSTR register ****************/ 3016 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) 3017 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ 3018 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */ 3019 #define RCC_APB2RSTR_ADCRST_Pos (9U) 3020 #define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ 3021 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */ 3022 #define RCC_APB2RSTR_TIM1RST_Pos (11U) 3023 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ 3024 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ 3025 #define RCC_APB2RSTR_SPI1RST_Pos (12U) 3026 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ 3027 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ 3028 #define RCC_APB2RSTR_USART1RST_Pos (14U) 3029 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ 3030 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ 3031 #define RCC_APB2RSTR_TIM15RST_Pos (16U) 3032 #define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ 3033 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ 3034 #define RCC_APB2RSTR_TIM16RST_Pos (17U) 3035 #define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ 3036 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ 3037 #define RCC_APB2RSTR_TIM17RST_Pos (18U) 3038 #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ 3039 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ 3040 #define RCC_APB2RSTR_DBGMCURST_Pos (22U) 3041 #define RCC_APB2RSTR_DBGMCURST_Msk (0x1UL << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */ 3042 #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */ 3043 3044 /*!< Old ADC1 reset bit definition maintained for legacy purpose */ 3045 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST 3046 3047 /***************** Bit definition for RCC_APB1RSTR register ****************/ 3048 #define RCC_APB1RSTR_TIM3RST_Pos (1U) 3049 #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ 3050 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ 3051 #define RCC_APB1RSTR_TIM6RST_Pos (4U) 3052 #define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ 3053 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ 3054 #define RCC_APB1RSTR_TIM14RST_Pos (8U) 3055 #define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ 3056 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */ 3057 #define RCC_APB1RSTR_WWDGRST_Pos (11U) 3058 #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ 3059 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ 3060 #define RCC_APB1RSTR_SPI2RST_Pos (14U) 3061 #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ 3062 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */ 3063 #define RCC_APB1RSTR_USART2RST_Pos (17U) 3064 #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ 3065 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ 3066 #define RCC_APB1RSTR_I2C1RST_Pos (21U) 3067 #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ 3068 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ 3069 #define RCC_APB1RSTR_I2C2RST_Pos (22U) 3070 #define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ 3071 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ 3072 #define RCC_APB1RSTR_PWRRST_Pos (28U) 3073 #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ 3074 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */ 3075 3076 /****************** Bit definition for RCC_AHBENR register *****************/ 3077 #define RCC_AHBENR_DMAEN_Pos (0U) 3078 #define RCC_AHBENR_DMAEN_Msk (0x1UL << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */ 3079 #define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */ 3080 #define RCC_AHBENR_SRAMEN_Pos (2U) 3081 #define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ 3082 #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ 3083 #define RCC_AHBENR_FLITFEN_Pos (4U) 3084 #define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ 3085 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ 3086 #define RCC_AHBENR_CRCEN_Pos (6U) 3087 #define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ 3088 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ 3089 #define RCC_AHBENR_GPIOAEN_Pos (17U) 3090 #define RCC_AHBENR_GPIOAEN_Msk (0x1UL << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00020000 */ 3091 #define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIOA clock enable */ 3092 #define RCC_AHBENR_GPIOBEN_Pos (18U) 3093 #define RCC_AHBENR_GPIOBEN_Msk (0x1UL << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00040000 */ 3094 #define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIOB clock enable */ 3095 #define RCC_AHBENR_GPIOCEN_Pos (19U) 3096 #define RCC_AHBENR_GPIOCEN_Msk (0x1UL << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00080000 */ 3097 #define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIOC clock enable */ 3098 #define RCC_AHBENR_GPIODEN_Pos (20U) 3099 #define RCC_AHBENR_GPIODEN_Msk (0x1UL << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00100000 */ 3100 #define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /*!< GPIOD clock enable */ 3101 #define RCC_AHBENR_GPIOFEN_Pos (22U) 3102 #define RCC_AHBENR_GPIOFEN_Msk (0x1UL << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00400000 */ 3103 #define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk /*!< GPIOF clock enable */ 3104 3105 /* Old Bit definition maintained for legacy purpose */ 3106 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */ 3107 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */ 3108 3109 /***************** Bit definition for RCC_APB2ENR register *****************/ 3110 #define RCC_APB2ENR_SYSCFGCOMPEN_Pos (0U) 3111 #define RCC_APB2ENR_SYSCFGCOMPEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGCOMPEN_Pos) /*!< 0x00000001 */ 3112 #define RCC_APB2ENR_SYSCFGCOMPEN RCC_APB2ENR_SYSCFGCOMPEN_Msk /*!< SYSCFG and comparator clock enable */ 3113 #define RCC_APB2ENR_ADCEN_Pos (9U) 3114 #define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */ 3115 #define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */ 3116 #define RCC_APB2ENR_TIM1EN_Pos (11U) 3117 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ 3118 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */ 3119 #define RCC_APB2ENR_SPI1EN_Pos (12U) 3120 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ 3121 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ 3122 #define RCC_APB2ENR_USART1EN_Pos (14U) 3123 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ 3124 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ 3125 #define RCC_APB2ENR_TIM15EN_Pos (16U) 3126 #define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ 3127 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 clock enable */ 3128 #define RCC_APB2ENR_TIM16EN_Pos (17U) 3129 #define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ 3130 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 clock enable */ 3131 #define RCC_APB2ENR_TIM17EN_Pos (18U) 3132 #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ 3133 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 clock enable */ 3134 #define RCC_APB2ENR_DBGMCUEN_Pos (22U) 3135 #define RCC_APB2ENR_DBGMCUEN_Msk (0x1UL << RCC_APB2ENR_DBGMCUEN_Pos) /*!< 0x00400000 */ 3136 #define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGMCUEN_Msk /*!< DBGMCU clock enable */ 3137 3138 /* Old Bit definition maintained for legacy purpose */ 3139 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */ 3140 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */ 3141 3142 /***************** Bit definition for RCC_APB1ENR register *****************/ 3143 #define RCC_APB1ENR_TIM3EN_Pos (1U) 3144 #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ 3145 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ 3146 #define RCC_APB1ENR_TIM6EN_Pos (4U) 3147 #define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ 3148 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */ 3149 #define RCC_APB1ENR_TIM14EN_Pos (8U) 3150 #define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */ 3151 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk /*!< Timer 14 clock enable */ 3152 #define RCC_APB1ENR_WWDGEN_Pos (11U) 3153 #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ 3154 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ 3155 #define RCC_APB1ENR_SPI2EN_Pos (14U) 3156 #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ 3157 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */ 3158 #define RCC_APB1ENR_USART2EN_Pos (17U) 3159 #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ 3160 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */ 3161 #define RCC_APB1ENR_I2C1EN_Pos (21U) 3162 #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ 3163 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */ 3164 #define RCC_APB1ENR_I2C2EN_Pos (22U) 3165 #define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ 3166 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enable */ 3167 #define RCC_APB1ENR_PWREN_Pos (28U) 3168 #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ 3169 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */ 3170 3171 /******************* Bit definition for RCC_BDCR register ******************/ 3172 #define RCC_BDCR_LSEON_Pos (0U) 3173 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ 3174 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ 3175 #define RCC_BDCR_LSERDY_Pos (1U) 3176 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ 3177 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ 3178 #define RCC_BDCR_LSEBYP_Pos (2U) 3179 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ 3180 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ 3181 3182 #define RCC_BDCR_LSEDRV_Pos (3U) 3183 #define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */ 3184 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */ 3185 #define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */ 3186 #define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ 3187 3188 #define RCC_BDCR_RTCSEL_Pos (8U) 3189 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ 3190 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ 3191 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ 3192 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ 3193 3194 /*!< RTC configuration */ 3195 #define RCC_BDCR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */ 3196 #define RCC_BDCR_RTCSEL_LSE (0x00000100U) /*!< LSE oscillator clock used as RTC clock */ 3197 #define RCC_BDCR_RTCSEL_LSI (0x00000200U) /*!< LSI oscillator clock used as RTC clock */ 3198 #define RCC_BDCR_RTCSEL_HSE (0x00000300U) /*!< HSE oscillator clock divided by 128 used as RTC clock */ 3199 3200 #define RCC_BDCR_RTCEN_Pos (15U) 3201 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ 3202 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ 3203 #define RCC_BDCR_BDRST_Pos (16U) 3204 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ 3205 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ 3206 3207 /******************* Bit definition for RCC_CSR register *******************/ 3208 #define RCC_CSR_LSION_Pos (0U) 3209 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ 3210 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ 3211 #define RCC_CSR_LSIRDY_Pos (1U) 3212 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ 3213 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ 3214 #define RCC_CSR_V18PWRRSTF_Pos (23U) 3215 #define RCC_CSR_V18PWRRSTF_Msk (0x1UL << RCC_CSR_V18PWRRSTF_Pos) /*!< 0x00800000 */ 3216 #define RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF_Msk /*!< V1.8 power domain reset flag */ 3217 #define RCC_CSR_RMVF_Pos (24U) 3218 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ 3219 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ 3220 #define RCC_CSR_OBLRSTF_Pos (25U) 3221 #define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ 3222 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */ 3223 #define RCC_CSR_PINRSTF_Pos (26U) 3224 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ 3225 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ 3226 #define RCC_CSR_PORRSTF_Pos (27U) 3227 #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ 3228 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ 3229 #define RCC_CSR_SFTRSTF_Pos (28U) 3230 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ 3231 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ 3232 #define RCC_CSR_IWDGRSTF_Pos (29U) 3233 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ 3234 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ 3235 #define RCC_CSR_WWDGRSTF_Pos (30U) 3236 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ 3237 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ 3238 #define RCC_CSR_LPWRRSTF_Pos (31U) 3239 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ 3240 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ 3241 3242 /* Old Bit definition maintained for legacy purpose */ 3243 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */ 3244 3245 /******************* Bit definition for RCC_AHBRSTR register ***************/ 3246 #define RCC_AHBRSTR_GPIOARST_Pos (17U) 3247 #define RCC_AHBRSTR_GPIOARST_Msk (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ 3248 #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */ 3249 #define RCC_AHBRSTR_GPIOBRST_Pos (18U) 3250 #define RCC_AHBRSTR_GPIOBRST_Msk (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ 3251 #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */ 3252 #define RCC_AHBRSTR_GPIOCRST_Pos (19U) 3253 #define RCC_AHBRSTR_GPIOCRST_Msk (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ 3254 #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */ 3255 #define RCC_AHBRSTR_GPIODRST_Pos (20U) 3256 #define RCC_AHBRSTR_GPIODRST_Msk (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */ 3257 #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD reset */ 3258 #define RCC_AHBRSTR_GPIOFRST_Pos (22U) 3259 #define RCC_AHBRSTR_GPIOFRST_Msk (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ 3260 #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */ 3261 3262 /******************* Bit definition for RCC_CFGR2 register *****************/ 3263 /*!< PREDIV configuration */ 3264 #define RCC_CFGR2_PREDIV_Pos (0U) 3265 #define RCC_CFGR2_PREDIV_Msk (0xFUL << RCC_CFGR2_PREDIV_Pos) /*!< 0x0000000F */ 3266 #define RCC_CFGR2_PREDIV RCC_CFGR2_PREDIV_Msk /*!< PREDIV[3:0] bits */ 3267 #define RCC_CFGR2_PREDIV_0 (0x1UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000001 */ 3268 #define RCC_CFGR2_PREDIV_1 (0x2UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000002 */ 3269 #define RCC_CFGR2_PREDIV_2 (0x4UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000004 */ 3270 #define RCC_CFGR2_PREDIV_3 (0x8UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000008 */ 3271 3272 #define RCC_CFGR2_PREDIV_DIV1 (0x00000000U) /*!< PREDIV input clock not divided */ 3273 #define RCC_CFGR2_PREDIV_DIV2 (0x00000001U) /*!< PREDIV input clock divided by 2 */ 3274 #define RCC_CFGR2_PREDIV_DIV3 (0x00000002U) /*!< PREDIV input clock divided by 3 */ 3275 #define RCC_CFGR2_PREDIV_DIV4 (0x00000003U) /*!< PREDIV input clock divided by 4 */ 3276 #define RCC_CFGR2_PREDIV_DIV5 (0x00000004U) /*!< PREDIV input clock divided by 5 */ 3277 #define RCC_CFGR2_PREDIV_DIV6 (0x00000005U) /*!< PREDIV input clock divided by 6 */ 3278 #define RCC_CFGR2_PREDIV_DIV7 (0x00000006U) /*!< PREDIV input clock divided by 7 */ 3279 #define RCC_CFGR2_PREDIV_DIV8 (0x00000007U) /*!< PREDIV input clock divided by 8 */ 3280 #define RCC_CFGR2_PREDIV_DIV9 (0x00000008U) /*!< PREDIV input clock divided by 9 */ 3281 #define RCC_CFGR2_PREDIV_DIV10 (0x00000009U) /*!< PREDIV input clock divided by 10 */ 3282 #define RCC_CFGR2_PREDIV_DIV11 (0x0000000AU) /*!< PREDIV input clock divided by 11 */ 3283 #define RCC_CFGR2_PREDIV_DIV12 (0x0000000BU) /*!< PREDIV input clock divided by 12 */ 3284 #define RCC_CFGR2_PREDIV_DIV13 (0x0000000CU) /*!< PREDIV input clock divided by 13 */ 3285 #define RCC_CFGR2_PREDIV_DIV14 (0x0000000DU) /*!< PREDIV input clock divided by 14 */ 3286 #define RCC_CFGR2_PREDIV_DIV15 (0x0000000EU) /*!< PREDIV input clock divided by 15 */ 3287 #define RCC_CFGR2_PREDIV_DIV16 (0x0000000FU) /*!< PREDIV input clock divided by 16 */ 3288 3289 /******************* Bit definition for RCC_CFGR3 register *****************/ 3290 /*!< USART1 Clock source selection */ 3291 #define RCC_CFGR3_USART1SW_Pos (0U) 3292 #define RCC_CFGR3_USART1SW_Msk (0x3UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000003 */ 3293 #define RCC_CFGR3_USART1SW RCC_CFGR3_USART1SW_Msk /*!< USART1SW[1:0] bits */ 3294 #define RCC_CFGR3_USART1SW_0 (0x1UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000001 */ 3295 #define RCC_CFGR3_USART1SW_1 (0x2UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000002 */ 3296 3297 #define RCC_CFGR3_USART1SW_PCLK (0x00000000U) /*!< PCLK clock used as USART1 clock source */ 3298 #define RCC_CFGR3_USART1SW_SYSCLK (0x00000001U) /*!< System clock selected as USART1 clock source */ 3299 #define RCC_CFGR3_USART1SW_LSE (0x00000002U) /*!< LSE oscillator clock used as USART1 clock source */ 3300 #define RCC_CFGR3_USART1SW_HSI (0x00000003U) /*!< HSI oscillator clock used as USART1 clock source */ 3301 3302 /*!< I2C1 Clock source selection */ 3303 #define RCC_CFGR3_I2C1SW_Pos (4U) 3304 #define RCC_CFGR3_I2C1SW_Msk (0x1UL << RCC_CFGR3_I2C1SW_Pos) /*!< 0x00000010 */ 3305 #define RCC_CFGR3_I2C1SW RCC_CFGR3_I2C1SW_Msk /*!< I2C1SW bits */ 3306 3307 #define RCC_CFGR3_I2C1SW_HSI (0x00000000U) /*!< HSI oscillator clock used as I2C1 clock source */ 3308 #define RCC_CFGR3_I2C1SW_SYSCLK_Pos (4U) 3309 #define RCC_CFGR3_I2C1SW_SYSCLK_Msk (0x1UL << RCC_CFGR3_I2C1SW_SYSCLK_Pos) /*!< 0x00000010 */ 3310 #define RCC_CFGR3_I2C1SW_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK_Msk /*!< System clock selected as I2C1 clock source */ 3311 3312 /******************* Bit definition for RCC_CR2 register *******************/ 3313 #define RCC_CR2_HSI14ON_Pos (0U) 3314 #define RCC_CR2_HSI14ON_Msk (0x1UL << RCC_CR2_HSI14ON_Pos) /*!< 0x00000001 */ 3315 #define RCC_CR2_HSI14ON RCC_CR2_HSI14ON_Msk /*!< Internal High Speed 14MHz clock enable */ 3316 #define RCC_CR2_HSI14RDY_Pos (1U) 3317 #define RCC_CR2_HSI14RDY_Msk (0x1UL << RCC_CR2_HSI14RDY_Pos) /*!< 0x00000002 */ 3318 #define RCC_CR2_HSI14RDY RCC_CR2_HSI14RDY_Msk /*!< Internal High Speed 14MHz clock ready flag */ 3319 #define RCC_CR2_HSI14DIS_Pos (2U) 3320 #define RCC_CR2_HSI14DIS_Msk (0x1UL << RCC_CR2_HSI14DIS_Pos) /*!< 0x00000004 */ 3321 #define RCC_CR2_HSI14DIS RCC_CR2_HSI14DIS_Msk /*!< Internal High Speed 14MHz clock disable */ 3322 #define RCC_CR2_HSI14TRIM_Pos (3U) 3323 #define RCC_CR2_HSI14TRIM_Msk (0x1FUL << RCC_CR2_HSI14TRIM_Pos) /*!< 0x000000F8 */ 3324 #define RCC_CR2_HSI14TRIM RCC_CR2_HSI14TRIM_Msk /*!< Internal High Speed 14MHz clock trimming */ 3325 #define RCC_CR2_HSI14CAL_Pos (8U) 3326 #define RCC_CR2_HSI14CAL_Msk (0xFFUL << RCC_CR2_HSI14CAL_Pos) /*!< 0x0000FF00 */ 3327 #define RCC_CR2_HSI14CAL RCC_CR2_HSI14CAL_Msk /*!< Internal High Speed 14MHz clock Calibration */ 3328 3329 /*****************************************************************************/ 3330 /* */ 3331 /* Real-Time Clock (RTC) */ 3332 /* */ 3333 /*****************************************************************************/ 3334 /* 3335 * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) 3336 */ 3337 #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ 3338 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ 3339 3340 /******************** Bits definition for RTC_TR register ******************/ 3341 #define RTC_TR_PM_Pos (22U) 3342 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ 3343 #define RTC_TR_PM RTC_TR_PM_Msk 3344 #define RTC_TR_HT_Pos (20U) 3345 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ 3346 #define RTC_TR_HT RTC_TR_HT_Msk 3347 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ 3348 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ 3349 #define RTC_TR_HU_Pos (16U) 3350 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ 3351 #define RTC_TR_HU RTC_TR_HU_Msk 3352 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ 3353 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ 3354 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ 3355 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ 3356 #define RTC_TR_MNT_Pos (12U) 3357 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ 3358 #define RTC_TR_MNT RTC_TR_MNT_Msk 3359 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ 3360 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ 3361 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ 3362 #define RTC_TR_MNU_Pos (8U) 3363 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ 3364 #define RTC_TR_MNU RTC_TR_MNU_Msk 3365 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ 3366 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ 3367 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ 3368 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ 3369 #define RTC_TR_ST_Pos (4U) 3370 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ 3371 #define RTC_TR_ST RTC_TR_ST_Msk 3372 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ 3373 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ 3374 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ 3375 #define RTC_TR_SU_Pos (0U) 3376 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ 3377 #define RTC_TR_SU RTC_TR_SU_Msk 3378 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ 3379 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ 3380 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ 3381 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ 3382 3383 /******************** Bits definition for RTC_DR register ******************/ 3384 #define RTC_DR_YT_Pos (20U) 3385 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ 3386 #define RTC_DR_YT RTC_DR_YT_Msk 3387 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ 3388 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ 3389 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ 3390 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ 3391 #define RTC_DR_YU_Pos (16U) 3392 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ 3393 #define RTC_DR_YU RTC_DR_YU_Msk 3394 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ 3395 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ 3396 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ 3397 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ 3398 #define RTC_DR_WDU_Pos (13U) 3399 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ 3400 #define RTC_DR_WDU RTC_DR_WDU_Msk 3401 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ 3402 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ 3403 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ 3404 #define RTC_DR_MT_Pos (12U) 3405 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ 3406 #define RTC_DR_MT RTC_DR_MT_Msk 3407 #define RTC_DR_MU_Pos (8U) 3408 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ 3409 #define RTC_DR_MU RTC_DR_MU_Msk 3410 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ 3411 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ 3412 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ 3413 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ 3414 #define RTC_DR_DT_Pos (4U) 3415 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ 3416 #define RTC_DR_DT RTC_DR_DT_Msk 3417 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ 3418 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ 3419 #define RTC_DR_DU_Pos (0U) 3420 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ 3421 #define RTC_DR_DU RTC_DR_DU_Msk 3422 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ 3423 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ 3424 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ 3425 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ 3426 3427 /******************** Bits definition for RTC_CR register ******************/ 3428 #define RTC_CR_COE_Pos (23U) 3429 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ 3430 #define RTC_CR_COE RTC_CR_COE_Msk 3431 #define RTC_CR_OSEL_Pos (21U) 3432 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ 3433 #define RTC_CR_OSEL RTC_CR_OSEL_Msk 3434 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ 3435 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ 3436 #define RTC_CR_POL_Pos (20U) 3437 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ 3438 #define RTC_CR_POL RTC_CR_POL_Msk 3439 #define RTC_CR_COSEL_Pos (19U) 3440 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ 3441 #define RTC_CR_COSEL RTC_CR_COSEL_Msk 3442 #define RTC_CR_BKP_Pos (18U) 3443 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ 3444 #define RTC_CR_BKP RTC_CR_BKP_Msk 3445 #define RTC_CR_SUB1H_Pos (17U) 3446 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ 3447 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk 3448 #define RTC_CR_ADD1H_Pos (16U) 3449 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ 3450 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk 3451 #define RTC_CR_TSIE_Pos (15U) 3452 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ 3453 #define RTC_CR_TSIE RTC_CR_TSIE_Msk 3454 #define RTC_CR_ALRAIE_Pos (12U) 3455 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ 3456 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk 3457 #define RTC_CR_TSE_Pos (11U) 3458 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ 3459 #define RTC_CR_TSE RTC_CR_TSE_Msk 3460 #define RTC_CR_ALRAE_Pos (8U) 3461 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ 3462 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk 3463 #define RTC_CR_FMT_Pos (6U) 3464 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ 3465 #define RTC_CR_FMT RTC_CR_FMT_Msk 3466 #define RTC_CR_BYPSHAD_Pos (5U) 3467 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ 3468 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk 3469 #define RTC_CR_REFCKON_Pos (4U) 3470 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ 3471 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk 3472 #define RTC_CR_TSEDGE_Pos (3U) 3473 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ 3474 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk 3475 3476 /* Legacy defines */ 3477 #define RTC_CR_BCK_Pos RTC_CR_BKP_Pos 3478 #define RTC_CR_BCK_Msk RTC_CR_BKP_Msk 3479 #define RTC_CR_BCK RTC_CR_BKP 3480 3481 /******************** Bits definition for RTC_ISR register *****************/ 3482 #define RTC_ISR_RECALPF_Pos (16U) 3483 #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ 3484 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk 3485 #define RTC_ISR_TAMP2F_Pos (14U) 3486 #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */ 3487 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk 3488 #define RTC_ISR_TAMP1F_Pos (13U) 3489 #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */ 3490 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk 3491 #define RTC_ISR_TSOVF_Pos (12U) 3492 #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ 3493 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk 3494 #define RTC_ISR_TSF_Pos (11U) 3495 #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ 3496 #define RTC_ISR_TSF RTC_ISR_TSF_Msk 3497 #define RTC_ISR_ALRAF_Pos (8U) 3498 #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ 3499 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk 3500 #define RTC_ISR_INIT_Pos (7U) 3501 #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ 3502 #define RTC_ISR_INIT RTC_ISR_INIT_Msk 3503 #define RTC_ISR_INITF_Pos (6U) 3504 #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ 3505 #define RTC_ISR_INITF RTC_ISR_INITF_Msk 3506 #define RTC_ISR_RSF_Pos (5U) 3507 #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ 3508 #define RTC_ISR_RSF RTC_ISR_RSF_Msk 3509 #define RTC_ISR_INITS_Pos (4U) 3510 #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ 3511 #define RTC_ISR_INITS RTC_ISR_INITS_Msk 3512 #define RTC_ISR_SHPF_Pos (3U) 3513 #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ 3514 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk 3515 #define RTC_ISR_ALRAWF_Pos (0U) 3516 #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ 3517 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk 3518 3519 /******************** Bits definition for RTC_PRER register ****************/ 3520 #define RTC_PRER_PREDIV_A_Pos (16U) 3521 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ 3522 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk 3523 #define RTC_PRER_PREDIV_S_Pos (0U) 3524 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ 3525 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk 3526 3527 /******************** Bits definition for RTC_ALRMAR register **************/ 3528 #define RTC_ALRMAR_MSK4_Pos (31U) 3529 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ 3530 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk 3531 #define RTC_ALRMAR_WDSEL_Pos (30U) 3532 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ 3533 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk 3534 #define RTC_ALRMAR_DT_Pos (28U) 3535 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ 3536 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk 3537 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ 3538 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ 3539 #define RTC_ALRMAR_DU_Pos (24U) 3540 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ 3541 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk 3542 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ 3543 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ 3544 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ 3545 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ 3546 #define RTC_ALRMAR_MSK3_Pos (23U) 3547 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ 3548 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk 3549 #define RTC_ALRMAR_PM_Pos (22U) 3550 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ 3551 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk 3552 #define RTC_ALRMAR_HT_Pos (20U) 3553 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ 3554 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk 3555 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ 3556 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ 3557 #define RTC_ALRMAR_HU_Pos (16U) 3558 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ 3559 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk 3560 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ 3561 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ 3562 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ 3563 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ 3564 #define RTC_ALRMAR_MSK2_Pos (15U) 3565 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ 3566 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk 3567 #define RTC_ALRMAR_MNT_Pos (12U) 3568 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ 3569 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk 3570 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ 3571 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ 3572 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ 3573 #define RTC_ALRMAR_MNU_Pos (8U) 3574 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ 3575 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk 3576 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ 3577 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ 3578 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ 3579 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ 3580 #define RTC_ALRMAR_MSK1_Pos (7U) 3581 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ 3582 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk 3583 #define RTC_ALRMAR_ST_Pos (4U) 3584 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ 3585 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk 3586 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ 3587 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ 3588 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ 3589 #define RTC_ALRMAR_SU_Pos (0U) 3590 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ 3591 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk 3592 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ 3593 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ 3594 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ 3595 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ 3596 3597 /******************** Bits definition for RTC_WPR register *****************/ 3598 #define RTC_WPR_KEY_Pos (0U) 3599 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ 3600 #define RTC_WPR_KEY RTC_WPR_KEY_Msk 3601 3602 /******************** Bits definition for RTC_SSR register *****************/ 3603 #define RTC_SSR_SS_Pos (0U) 3604 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ 3605 #define RTC_SSR_SS RTC_SSR_SS_Msk 3606 3607 /******************** Bits definition for RTC_SHIFTR register **************/ 3608 #define RTC_SHIFTR_SUBFS_Pos (0U) 3609 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ 3610 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk 3611 #define RTC_SHIFTR_ADD1S_Pos (31U) 3612 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ 3613 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk 3614 3615 /******************** Bits definition for RTC_TSTR register ****************/ 3616 #define RTC_TSTR_PM_Pos (22U) 3617 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ 3618 #define RTC_TSTR_PM RTC_TSTR_PM_Msk 3619 #define RTC_TSTR_HT_Pos (20U) 3620 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ 3621 #define RTC_TSTR_HT RTC_TSTR_HT_Msk 3622 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ 3623 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ 3624 #define RTC_TSTR_HU_Pos (16U) 3625 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ 3626 #define RTC_TSTR_HU RTC_TSTR_HU_Msk 3627 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ 3628 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ 3629 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ 3630 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ 3631 #define RTC_TSTR_MNT_Pos (12U) 3632 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ 3633 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk 3634 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ 3635 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ 3636 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ 3637 #define RTC_TSTR_MNU_Pos (8U) 3638 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ 3639 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk 3640 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ 3641 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ 3642 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ 3643 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ 3644 #define RTC_TSTR_ST_Pos (4U) 3645 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ 3646 #define RTC_TSTR_ST RTC_TSTR_ST_Msk 3647 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ 3648 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ 3649 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ 3650 #define RTC_TSTR_SU_Pos (0U) 3651 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ 3652 #define RTC_TSTR_SU RTC_TSTR_SU_Msk 3653 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ 3654 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ 3655 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ 3656 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ 3657 3658 /******************** Bits definition for RTC_TSDR register ****************/ 3659 #define RTC_TSDR_WDU_Pos (13U) 3660 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ 3661 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk 3662 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ 3663 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ 3664 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ 3665 #define RTC_TSDR_MT_Pos (12U) 3666 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ 3667 #define RTC_TSDR_MT RTC_TSDR_MT_Msk 3668 #define RTC_TSDR_MU_Pos (8U) 3669 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ 3670 #define RTC_TSDR_MU RTC_TSDR_MU_Msk 3671 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ 3672 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ 3673 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ 3674 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ 3675 #define RTC_TSDR_DT_Pos (4U) 3676 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ 3677 #define RTC_TSDR_DT RTC_TSDR_DT_Msk 3678 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ 3679 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ 3680 #define RTC_TSDR_DU_Pos (0U) 3681 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ 3682 #define RTC_TSDR_DU RTC_TSDR_DU_Msk 3683 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ 3684 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ 3685 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ 3686 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ 3687 3688 /******************** Bits definition for RTC_TSSSR register ***************/ 3689 #define RTC_TSSSR_SS_Pos (0U) 3690 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ 3691 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk 3692 3693 /******************** Bits definition for RTC_CALR register ****************/ 3694 #define RTC_CALR_CALP_Pos (15U) 3695 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ 3696 #define RTC_CALR_CALP RTC_CALR_CALP_Msk 3697 #define RTC_CALR_CALW8_Pos (14U) 3698 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ 3699 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk 3700 #define RTC_CALR_CALW16_Pos (13U) 3701 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ 3702 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk 3703 #define RTC_CALR_CALM_Pos (0U) 3704 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ 3705 #define RTC_CALR_CALM RTC_CALR_CALM_Msk 3706 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ 3707 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ 3708 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ 3709 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ 3710 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ 3711 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ 3712 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ 3713 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ 3714 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ 3715 3716 /******************** Bits definition for RTC_TAFCR register ***************/ 3717 #define RTC_TAFCR_PC15MODE_Pos (23U) 3718 #define RTC_TAFCR_PC15MODE_Msk (0x1UL << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */ 3719 #define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk 3720 #define RTC_TAFCR_PC15VALUE_Pos (22U) 3721 #define RTC_TAFCR_PC15VALUE_Msk (0x1UL << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */ 3722 #define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk 3723 #define RTC_TAFCR_PC14MODE_Pos (21U) 3724 #define RTC_TAFCR_PC14MODE_Msk (0x1UL << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */ 3725 #define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk 3726 #define RTC_TAFCR_PC14VALUE_Pos (20U) 3727 #define RTC_TAFCR_PC14VALUE_Msk (0x1UL << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */ 3728 #define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk 3729 #define RTC_TAFCR_PC13MODE_Pos (19U) 3730 #define RTC_TAFCR_PC13MODE_Msk (0x1UL << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */ 3731 #define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk 3732 #define RTC_TAFCR_PC13VALUE_Pos (18U) 3733 #define RTC_TAFCR_PC13VALUE_Msk (0x1UL << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */ 3734 #define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk 3735 #define RTC_TAFCR_TAMPPUDIS_Pos (15U) 3736 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ 3737 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk 3738 #define RTC_TAFCR_TAMPPRCH_Pos (13U) 3739 #define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ 3740 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk 3741 #define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ 3742 #define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ 3743 #define RTC_TAFCR_TAMPFLT_Pos (11U) 3744 #define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ 3745 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk 3746 #define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ 3747 #define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ 3748 #define RTC_TAFCR_TAMPFREQ_Pos (8U) 3749 #define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ 3750 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk 3751 #define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ 3752 #define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ 3753 #define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ 3754 #define RTC_TAFCR_TAMPTS_Pos (7U) 3755 #define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ 3756 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk 3757 #define RTC_TAFCR_TAMP2TRG_Pos (4U) 3758 #define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */ 3759 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk 3760 #define RTC_TAFCR_TAMP2E_Pos (3U) 3761 #define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */ 3762 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk 3763 #define RTC_TAFCR_TAMPIE_Pos (2U) 3764 #define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ 3765 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk 3766 #define RTC_TAFCR_TAMP1TRG_Pos (1U) 3767 #define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ 3768 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk 3769 #define RTC_TAFCR_TAMP1E_Pos (0U) 3770 #define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ 3771 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk 3772 3773 /* Reference defines */ 3774 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE 3775 3776 /******************** Bits definition for RTC_ALRMASSR register ************/ 3777 #define RTC_ALRMASSR_MASKSS_Pos (24U) 3778 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ 3779 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk 3780 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ 3781 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ 3782 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ 3783 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ 3784 #define RTC_ALRMASSR_SS_Pos (0U) 3785 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ 3786 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk 3787 3788 /*****************************************************************************/ 3789 /* */ 3790 /* Serial Peripheral Interface (SPI) */ 3791 /* */ 3792 /*****************************************************************************/ 3793 3794 /* 3795 * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) 3796 */ 3797 /* Note: No specific macro feature on this device */ 3798 3799 /******************* Bit definition for SPI_CR1 register *******************/ 3800 #define SPI_CR1_CPHA_Pos (0U) 3801 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ 3802 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ 3803 #define SPI_CR1_CPOL_Pos (1U) 3804 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ 3805 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ 3806 #define SPI_CR1_MSTR_Pos (2U) 3807 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ 3808 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ 3809 #define SPI_CR1_BR_Pos (3U) 3810 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */ 3811 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ 3812 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */ 3813 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */ 3814 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */ 3815 #define SPI_CR1_SPE_Pos (6U) 3816 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ 3817 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ 3818 #define SPI_CR1_LSBFIRST_Pos (7U) 3819 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ 3820 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ 3821 #define SPI_CR1_SSI_Pos (8U) 3822 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ 3823 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ 3824 #define SPI_CR1_SSM_Pos (9U) 3825 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ 3826 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ 3827 #define SPI_CR1_RXONLY_Pos (10U) 3828 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ 3829 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ 3830 #define SPI_CR1_CRCL_Pos (11U) 3831 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ 3832 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */ 3833 #define SPI_CR1_CRCNEXT_Pos (12U) 3834 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ 3835 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ 3836 #define SPI_CR1_CRCEN_Pos (13U) 3837 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ 3838 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ 3839 #define SPI_CR1_BIDIOE_Pos (14U) 3840 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ 3841 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ 3842 #define SPI_CR1_BIDIMODE_Pos (15U) 3843 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ 3844 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ 3845 3846 /******************* Bit definition for SPI_CR2 register *******************/ 3847 #define SPI_CR2_RXDMAEN_Pos (0U) 3848 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ 3849 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ 3850 #define SPI_CR2_TXDMAEN_Pos (1U) 3851 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ 3852 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ 3853 #define SPI_CR2_SSOE_Pos (2U) 3854 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ 3855 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ 3856 #define SPI_CR2_NSSP_Pos (3U) 3857 #define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */ 3858 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */ 3859 #define SPI_CR2_FRF_Pos (4U) 3860 #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ 3861 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */ 3862 #define SPI_CR2_ERRIE_Pos (5U) 3863 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ 3864 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ 3865 #define SPI_CR2_RXNEIE_Pos (6U) 3866 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ 3867 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ 3868 #define SPI_CR2_TXEIE_Pos (7U) 3869 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ 3870 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ 3871 #define SPI_CR2_DS_Pos (8U) 3872 #define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */ 3873 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */ 3874 #define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */ 3875 #define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */ 3876 #define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */ 3877 #define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */ 3878 #define SPI_CR2_FRXTH_Pos (12U) 3879 #define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */ 3880 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */ 3881 #define SPI_CR2_LDMARX_Pos (13U) 3882 #define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */ 3883 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */ 3884 #define SPI_CR2_LDMATX_Pos (14U) 3885 #define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */ 3886 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */ 3887 3888 /******************** Bit definition for SPI_SR register *******************/ 3889 #define SPI_SR_RXNE_Pos (0U) 3890 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ 3891 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ 3892 #define SPI_SR_TXE_Pos (1U) 3893 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */ 3894 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ 3895 #define SPI_SR_CRCERR_Pos (4U) 3896 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ 3897 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ 3898 #define SPI_SR_MODF_Pos (5U) 3899 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */ 3900 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ 3901 #define SPI_SR_OVR_Pos (6U) 3902 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */ 3903 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ 3904 #define SPI_SR_BSY_Pos (7U) 3905 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */ 3906 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ 3907 #define SPI_SR_FRE_Pos (8U) 3908 #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */ 3909 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */ 3910 #define SPI_SR_FRLVL_Pos (9U) 3911 #define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */ 3912 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */ 3913 #define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */ 3914 #define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */ 3915 #define SPI_SR_FTLVL_Pos (11U) 3916 #define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */ 3917 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */ 3918 #define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */ 3919 #define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */ 3920 3921 /******************** Bit definition for SPI_DR register *******************/ 3922 #define SPI_DR_DR_Pos (0U) 3923 #define SPI_DR_DR_Msk (0xFFFFFFFFUL << SPI_DR_DR_Pos) /*!< 0xFFFFFFFF */ 3924 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ 3925 3926 /******************* Bit definition for SPI_CRCPR register *****************/ 3927 #define SPI_CRCPR_CRCPOLY_Pos (0U) 3928 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0xFFFFFFFF */ 3929 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ 3930 3931 /****************** Bit definition for SPI_RXCRCR register *****************/ 3932 #define SPI_RXCRCR_RXCRC_Pos (0U) 3933 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0xFFFFFFFF */ 3934 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ 3935 3936 /****************** Bit definition for SPI_TXCRCR register *****************/ 3937 #define SPI_TXCRCR_TXCRC_Pos (0U) 3938 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0xFFFFFFFF */ 3939 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ 3940 3941 /****************** Bit definition for SPI_I2SCFGR register ****************/ 3942 #define SPI_I2SCFGR_I2SMOD_Pos (11U) 3943 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ 3944 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< Keep for compatibility */ 3945 3946 /*****************************************************************************/ 3947 /* */ 3948 /* System Configuration (SYSCFG) */ 3949 /* */ 3950 /*****************************************************************************/ 3951 /***************** Bit definition for SYSCFG_CFGR1 register ****************/ 3952 #define SYSCFG_CFGR1_MEM_MODE_Pos (0U) 3953 #define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */ 3954 #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ 3955 #define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */ 3956 #define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */ 3957 3958 #define SYSCFG_CFGR1_DMA_RMP_Pos (8U) 3959 #define SYSCFG_CFGR1_DMA_RMP_Msk (0x1FUL << SYSCFG_CFGR1_DMA_RMP_Pos) /*!< 0x00001F00 */ 3960 #define SYSCFG_CFGR1_DMA_RMP SYSCFG_CFGR1_DMA_RMP_Msk /*!< DMA remap mask */ 3961 #define SYSCFG_CFGR1_ADC_DMA_RMP_Pos (8U) 3962 #define SYSCFG_CFGR1_ADC_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_ADC_DMA_RMP_Pos) /*!< 0x00000100 */ 3963 #define SYSCFG_CFGR1_ADC_DMA_RMP SYSCFG_CFGR1_ADC_DMA_RMP_Msk /*!< ADC DMA remap */ 3964 #define SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos (9U) 3965 #define SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos) /*!< 0x00000200 */ 3966 #define SYSCFG_CFGR1_USART1TX_DMA_RMP SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk /*!< USART1 TX DMA remap */ 3967 #define SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos (10U) 3968 #define SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos) /*!< 0x00000400 */ 3969 #define SYSCFG_CFGR1_USART1RX_DMA_RMP SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk /*!< USART1 RX DMA remap */ 3970 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Pos (11U) 3971 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos) /*!< 0x00000800 */ 3972 #define SYSCFG_CFGR1_TIM16_DMA_RMP SYSCFG_CFGR1_TIM16_DMA_RMP_Msk /*!< Timer 16 DMA remap */ 3973 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Pos (12U) 3974 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos) /*!< 0x00001000 */ 3975 #define SYSCFG_CFGR1_TIM17_DMA_RMP SYSCFG_CFGR1_TIM17_DMA_RMP_Msk /*!< Timer 17 DMA remap */ 3976 3977 #define SYSCFG_CFGR1_I2C_FMP_PB6_Pos (16U) 3978 #define SYSCFG_CFGR1_I2C_FMP_PB6_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB6_Pos) /*!< 0x00010000 */ 3979 #define SYSCFG_CFGR1_I2C_FMP_PB6 SYSCFG_CFGR1_I2C_FMP_PB6_Msk /*!< I2C PB6 Fast mode plus */ 3980 #define SYSCFG_CFGR1_I2C_FMP_PB7_Pos (17U) 3981 #define SYSCFG_CFGR1_I2C_FMP_PB7_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB7_Pos) /*!< 0x00020000 */ 3982 #define SYSCFG_CFGR1_I2C_FMP_PB7 SYSCFG_CFGR1_I2C_FMP_PB7_Msk /*!< I2C PB7 Fast mode plus */ 3983 #define SYSCFG_CFGR1_I2C_FMP_PB8_Pos (18U) 3984 #define SYSCFG_CFGR1_I2C_FMP_PB8_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB8_Pos) /*!< 0x00040000 */ 3985 #define SYSCFG_CFGR1_I2C_FMP_PB8 SYSCFG_CFGR1_I2C_FMP_PB8_Msk /*!< I2C PB8 Fast mode plus */ 3986 #define SYSCFG_CFGR1_I2C_FMP_PB9_Pos (19U) 3987 #define SYSCFG_CFGR1_I2C_FMP_PB9_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB9_Pos) /*!< 0x00080000 */ 3988 #define SYSCFG_CFGR1_I2C_FMP_PB9 SYSCFG_CFGR1_I2C_FMP_PB9_Msk /*!< I2C PB9 Fast mode plus */ 3989 3990 /***************** Bit definition for SYSCFG_EXTICR1 register **************/ 3991 #define SYSCFG_EXTICR1_EXTI0_Pos (0U) 3992 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ 3993 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ 3994 #define SYSCFG_EXTICR1_EXTI1_Pos (4U) 3995 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ 3996 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ 3997 #define SYSCFG_EXTICR1_EXTI2_Pos (8U) 3998 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ 3999 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ 4000 #define SYSCFG_EXTICR1_EXTI3_Pos (12U) 4001 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ 4002 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ 4003 4004 /** 4005 * @brief EXTI0 configuration 4006 */ 4007 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */ 4008 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */ 4009 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */ 4010 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */ 4011 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!< PF[0] pin */ 4012 4013 /** 4014 * @brief EXTI1 configuration 4015 */ 4016 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */ 4017 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */ 4018 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */ 4019 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */ 4020 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!< PF[1] pin */ 4021 4022 /** 4023 * @brief EXTI2 configuration 4024 */ 4025 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */ 4026 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */ 4027 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */ 4028 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */ 4029 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!< PF[2] pin */ 4030 4031 /** 4032 * @brief EXTI3 configuration 4033 */ 4034 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */ 4035 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */ 4036 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */ 4037 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */ 4038 #define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!< PF[3] pin */ 4039 4040 /***************** Bit definition for SYSCFG_EXTICR2 register **************/ 4041 #define SYSCFG_EXTICR2_EXTI4_Pos (0U) 4042 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ 4043 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ 4044 #define SYSCFG_EXTICR2_EXTI5_Pos (4U) 4045 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ 4046 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ 4047 #define SYSCFG_EXTICR2_EXTI6_Pos (8U) 4048 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ 4049 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ 4050 #define SYSCFG_EXTICR2_EXTI7_Pos (12U) 4051 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ 4052 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ 4053 4054 /** 4055 * @brief EXTI4 configuration 4056 */ 4057 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */ 4058 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */ 4059 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */ 4060 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */ 4061 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!< PF[4] pin */ 4062 4063 /** 4064 * @brief EXTI5 configuration 4065 */ 4066 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */ 4067 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */ 4068 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */ 4069 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */ 4070 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!< PF[5] pin */ 4071 4072 /** 4073 * @brief EXTI6 configuration 4074 */ 4075 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */ 4076 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */ 4077 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */ 4078 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */ 4079 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!< PF[6] pin */ 4080 4081 /** 4082 * @brief EXTI7 configuration 4083 */ 4084 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */ 4085 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */ 4086 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */ 4087 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */ 4088 #define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!< PF[7] pin */ 4089 4090 /***************** Bit definition for SYSCFG_EXTICR3 register **************/ 4091 #define SYSCFG_EXTICR3_EXTI8_Pos (0U) 4092 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ 4093 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ 4094 #define SYSCFG_EXTICR3_EXTI9_Pos (4U) 4095 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ 4096 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ 4097 #define SYSCFG_EXTICR3_EXTI10_Pos (8U) 4098 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ 4099 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ 4100 #define SYSCFG_EXTICR3_EXTI11_Pos (12U) 4101 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ 4102 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ 4103 4104 /** 4105 * @brief EXTI8 configuration 4106 */ 4107 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */ 4108 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */ 4109 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */ 4110 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */ 4111 #define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!< PF[8] pin */ 4112 4113 4114 /** 4115 * @brief EXTI9 configuration 4116 */ 4117 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */ 4118 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */ 4119 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */ 4120 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */ 4121 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!< PF[9] pin */ 4122 4123 /** 4124 * @brief EXTI10 configuration 4125 */ 4126 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */ 4127 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */ 4128 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */ 4129 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */ 4130 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!< PF[10] pin */ 4131 4132 /** 4133 * @brief EXTI11 configuration 4134 */ 4135 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */ 4136 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */ 4137 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */ 4138 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */ 4139 #define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!< PF[11] pin */ 4140 4141 /***************** Bit definition for SYSCFG_EXTICR4 register **************/ 4142 #define SYSCFG_EXTICR4_EXTI12_Pos (0U) 4143 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ 4144 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ 4145 #define SYSCFG_EXTICR4_EXTI13_Pos (4U) 4146 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ 4147 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ 4148 #define SYSCFG_EXTICR4_EXTI14_Pos (8U) 4149 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ 4150 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ 4151 #define SYSCFG_EXTICR4_EXTI15_Pos (12U) 4152 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ 4153 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ 4154 4155 /** 4156 * @brief EXTI12 configuration 4157 */ 4158 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */ 4159 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */ 4160 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */ 4161 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */ 4162 #define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!< PF[12] pin */ 4163 4164 /** 4165 * @brief EXTI13 configuration 4166 */ 4167 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */ 4168 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */ 4169 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */ 4170 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */ 4171 #define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!< PF[13] pin */ 4172 4173 /** 4174 * @brief EXTI14 configuration 4175 */ 4176 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */ 4177 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */ 4178 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */ 4179 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */ 4180 #define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!< PF[14] pin */ 4181 4182 /** 4183 * @brief EXTI15 configuration 4184 */ 4185 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */ 4186 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */ 4187 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */ 4188 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */ 4189 #define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!< PF[15] pin */ 4190 4191 /***************** Bit definition for SYSCFG_CFGR2 register ****************/ 4192 #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U) 4193 #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1UL << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */ 4194 #define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */ 4195 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos (1U) 4196 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk (0x1UL << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos) /*!< 0x00000002 */ 4197 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */ 4198 #define SYSCFG_CFGR2_SRAM_PEF_Pos (8U) 4199 #define SYSCFG_CFGR2_SRAM_PEF_Msk (0x1UL << SYSCFG_CFGR2_SRAM_PEF_Pos) /*!< 0x00000100 */ 4200 #define SYSCFG_CFGR2_SRAM_PEF SYSCFG_CFGR2_SRAM_PEF_Msk /*!< SRAM Parity error flag */ 4201 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */ 4202 4203 /*****************************************************************************/ 4204 /* */ 4205 /* Timers (TIM) */ 4206 /* */ 4207 /*****************************************************************************/ 4208 /******************* Bit definition for TIM_CR1 register *******************/ 4209 #define TIM_CR1_CEN_Pos (0U) 4210 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ 4211 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ 4212 #define TIM_CR1_UDIS_Pos (1U) 4213 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ 4214 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ 4215 #define TIM_CR1_URS_Pos (2U) 4216 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */ 4217 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ 4218 #define TIM_CR1_OPM_Pos (3U) 4219 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ 4220 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ 4221 #define TIM_CR1_DIR_Pos (4U) 4222 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ 4223 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ 4224 4225 #define TIM_CR1_CMS_Pos (5U) 4226 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ 4227 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ 4228 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ 4229 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ 4230 4231 #define TIM_CR1_ARPE_Pos (7U) 4232 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ 4233 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ 4234 4235 #define TIM_CR1_CKD_Pos (8U) 4236 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ 4237 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ 4238 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ 4239 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ 4240 4241 /******************* Bit definition for TIM_CR2 register *******************/ 4242 #define TIM_CR2_CCPC_Pos (0U) 4243 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ 4244 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ 4245 #define TIM_CR2_CCUS_Pos (2U) 4246 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ 4247 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ 4248 #define TIM_CR2_CCDS_Pos (3U) 4249 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ 4250 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ 4251 4252 #define TIM_CR2_MMS_Pos (4U) 4253 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ 4254 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 4255 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ 4256 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ 4257 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ 4258 4259 #define TIM_CR2_TI1S_Pos (7U) 4260 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ 4261 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ 4262 #define TIM_CR2_OIS1_Pos (8U) 4263 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ 4264 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ 4265 #define TIM_CR2_OIS1N_Pos (9U) 4266 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ 4267 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ 4268 #define TIM_CR2_OIS2_Pos (10U) 4269 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ 4270 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ 4271 #define TIM_CR2_OIS2N_Pos (11U) 4272 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ 4273 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ 4274 #define TIM_CR2_OIS3_Pos (12U) 4275 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ 4276 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ 4277 #define TIM_CR2_OIS3N_Pos (13U) 4278 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ 4279 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ 4280 #define TIM_CR2_OIS4_Pos (14U) 4281 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ 4282 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ 4283 4284 /******************* Bit definition for TIM_SMCR register ******************/ 4285 #define TIM_SMCR_SMS_Pos (0U) 4286 #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */ 4287 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ 4288 #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ 4289 #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ 4290 #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ 4291 4292 #define TIM_SMCR_OCCS_Pos (3U) 4293 #define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ 4294 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ 4295 4296 #define TIM_SMCR_TS_Pos (4U) 4297 #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ 4298 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ 4299 #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ 4300 #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ 4301 #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ 4302 4303 #define TIM_SMCR_MSM_Pos (7U) 4304 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ 4305 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ 4306 4307 #define TIM_SMCR_ETF_Pos (8U) 4308 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ 4309 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ 4310 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ 4311 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ 4312 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ 4313 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ 4314 4315 #define TIM_SMCR_ETPS_Pos (12U) 4316 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ 4317 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ 4318 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ 4319 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ 4320 4321 #define TIM_SMCR_ECE_Pos (14U) 4322 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ 4323 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ 4324 #define TIM_SMCR_ETP_Pos (15U) 4325 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ 4326 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ 4327 4328 /******************* Bit definition for TIM_DIER register ******************/ 4329 #define TIM_DIER_UIE_Pos (0U) 4330 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ 4331 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ 4332 #define TIM_DIER_CC1IE_Pos (1U) 4333 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ 4334 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ 4335 #define TIM_DIER_CC2IE_Pos (2U) 4336 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ 4337 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ 4338 #define TIM_DIER_CC3IE_Pos (3U) 4339 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ 4340 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ 4341 #define TIM_DIER_CC4IE_Pos (4U) 4342 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ 4343 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ 4344 #define TIM_DIER_COMIE_Pos (5U) 4345 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ 4346 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ 4347 #define TIM_DIER_TIE_Pos (6U) 4348 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ 4349 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ 4350 #define TIM_DIER_BIE_Pos (7U) 4351 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ 4352 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ 4353 #define TIM_DIER_UDE_Pos (8U) 4354 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ 4355 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ 4356 #define TIM_DIER_CC1DE_Pos (9U) 4357 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ 4358 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ 4359 #define TIM_DIER_CC2DE_Pos (10U) 4360 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ 4361 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ 4362 #define TIM_DIER_CC3DE_Pos (11U) 4363 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ 4364 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ 4365 #define TIM_DIER_CC4DE_Pos (12U) 4366 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ 4367 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ 4368 #define TIM_DIER_COMDE_Pos (13U) 4369 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ 4370 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ 4371 #define TIM_DIER_TDE_Pos (14U) 4372 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ 4373 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ 4374 4375 /******************** Bit definition for TIM_SR register *******************/ 4376 #define TIM_SR_UIF_Pos (0U) 4377 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */ 4378 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ 4379 #define TIM_SR_CC1IF_Pos (1U) 4380 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ 4381 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ 4382 #define TIM_SR_CC2IF_Pos (2U) 4383 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ 4384 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ 4385 #define TIM_SR_CC3IF_Pos (3U) 4386 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ 4387 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ 4388 #define TIM_SR_CC4IF_Pos (4U) 4389 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ 4390 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ 4391 #define TIM_SR_COMIF_Pos (5U) 4392 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ 4393 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ 4394 #define TIM_SR_TIF_Pos (6U) 4395 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */ 4396 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ 4397 #define TIM_SR_BIF_Pos (7U) 4398 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */ 4399 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ 4400 #define TIM_SR_CC1OF_Pos (9U) 4401 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ 4402 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ 4403 #define TIM_SR_CC2OF_Pos (10U) 4404 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ 4405 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ 4406 #define TIM_SR_CC3OF_Pos (11U) 4407 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ 4408 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ 4409 #define TIM_SR_CC4OF_Pos (12U) 4410 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ 4411 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ 4412 4413 /******************* Bit definition for TIM_EGR register *******************/ 4414 #define TIM_EGR_UG_Pos (0U) 4415 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */ 4416 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ 4417 #define TIM_EGR_CC1G_Pos (1U) 4418 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ 4419 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ 4420 #define TIM_EGR_CC2G_Pos (2U) 4421 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ 4422 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ 4423 #define TIM_EGR_CC3G_Pos (3U) 4424 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ 4425 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ 4426 #define TIM_EGR_CC4G_Pos (4U) 4427 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ 4428 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ 4429 #define TIM_EGR_COMG_Pos (5U) 4430 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ 4431 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ 4432 #define TIM_EGR_TG_Pos (6U) 4433 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */ 4434 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ 4435 #define TIM_EGR_BG_Pos (7U) 4436 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */ 4437 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ 4438 4439 /****************** Bit definition for TIM_CCMR1 register ******************/ 4440 #define TIM_CCMR1_CC1S_Pos (0U) 4441 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ 4442 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ 4443 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ 4444 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ 4445 4446 #define TIM_CCMR1_OC1FE_Pos (2U) 4447 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ 4448 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ 4449 #define TIM_CCMR1_OC1PE_Pos (3U) 4450 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ 4451 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ 4452 4453 #define TIM_CCMR1_OC1M_Pos (4U) 4454 #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */ 4455 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ 4456 #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ 4457 #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ 4458 #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ 4459 4460 #define TIM_CCMR1_OC1CE_Pos (7U) 4461 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ 4462 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ 4463 4464 #define TIM_CCMR1_CC2S_Pos (8U) 4465 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ 4466 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ 4467 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ 4468 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ 4469 4470 #define TIM_CCMR1_OC2FE_Pos (10U) 4471 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ 4472 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ 4473 #define TIM_CCMR1_OC2PE_Pos (11U) 4474 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ 4475 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ 4476 4477 #define TIM_CCMR1_OC2M_Pos (12U) 4478 #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */ 4479 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ 4480 #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ 4481 #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ 4482 #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ 4483 4484 #define TIM_CCMR1_OC2CE_Pos (15U) 4485 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ 4486 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ 4487 4488 /*---------------------------------------------------------------------------*/ 4489 4490 #define TIM_CCMR1_IC1PSC_Pos (2U) 4491 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ 4492 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ 4493 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ 4494 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ 4495 4496 #define TIM_CCMR1_IC1F_Pos (4U) 4497 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ 4498 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ 4499 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ 4500 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ 4501 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ 4502 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ 4503 4504 #define TIM_CCMR1_IC2PSC_Pos (10U) 4505 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ 4506 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ 4507 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ 4508 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ 4509 4510 #define TIM_CCMR1_IC2F_Pos (12U) 4511 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ 4512 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ 4513 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ 4514 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ 4515 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ 4516 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ 4517 4518 /****************** Bit definition for TIM_CCMR2 register ******************/ 4519 #define TIM_CCMR2_CC3S_Pos (0U) 4520 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ 4521 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ 4522 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ 4523 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ 4524 4525 #define TIM_CCMR2_OC3FE_Pos (2U) 4526 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ 4527 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ 4528 #define TIM_CCMR2_OC3PE_Pos (3U) 4529 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ 4530 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ 4531 4532 #define TIM_CCMR2_OC3M_Pos (4U) 4533 #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */ 4534 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ 4535 #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ 4536 #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ 4537 #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ 4538 4539 #define TIM_CCMR2_OC3CE_Pos (7U) 4540 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ 4541 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ 4542 4543 #define TIM_CCMR2_CC4S_Pos (8U) 4544 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ 4545 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ 4546 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ 4547 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ 4548 4549 #define TIM_CCMR2_OC4FE_Pos (10U) 4550 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ 4551 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ 4552 #define TIM_CCMR2_OC4PE_Pos (11U) 4553 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ 4554 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ 4555 4556 #define TIM_CCMR2_OC4M_Pos (12U) 4557 #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */ 4558 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 4559 #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ 4560 #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ 4561 #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ 4562 4563 #define TIM_CCMR2_OC4CE_Pos (15U) 4564 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ 4565 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ 4566 4567 /*---------------------------------------------------------------------------*/ 4568 4569 #define TIM_CCMR2_IC3PSC_Pos (2U) 4570 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ 4571 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ 4572 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ 4573 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ 4574 4575 #define TIM_CCMR2_IC3F_Pos (4U) 4576 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ 4577 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ 4578 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ 4579 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ 4580 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ 4581 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ 4582 4583 #define TIM_CCMR2_IC4PSC_Pos (10U) 4584 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ 4585 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ 4586 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ 4587 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ 4588 4589 #define TIM_CCMR2_IC4F_Pos (12U) 4590 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ 4591 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ 4592 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ 4593 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ 4594 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ 4595 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ 4596 4597 /******************* Bit definition for TIM_CCER register ******************/ 4598 #define TIM_CCER_CC1E_Pos (0U) 4599 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ 4600 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ 4601 #define TIM_CCER_CC1P_Pos (1U) 4602 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ 4603 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ 4604 #define TIM_CCER_CC1NE_Pos (2U) 4605 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ 4606 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ 4607 #define TIM_CCER_CC1NP_Pos (3U) 4608 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ 4609 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ 4610 #define TIM_CCER_CC2E_Pos (4U) 4611 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ 4612 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ 4613 #define TIM_CCER_CC2P_Pos (5U) 4614 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ 4615 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ 4616 #define TIM_CCER_CC2NE_Pos (6U) 4617 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ 4618 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ 4619 #define TIM_CCER_CC2NP_Pos (7U) 4620 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ 4621 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ 4622 #define TIM_CCER_CC3E_Pos (8U) 4623 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ 4624 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ 4625 #define TIM_CCER_CC3P_Pos (9U) 4626 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ 4627 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ 4628 #define TIM_CCER_CC3NE_Pos (10U) 4629 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ 4630 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ 4631 #define TIM_CCER_CC3NP_Pos (11U) 4632 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ 4633 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ 4634 #define TIM_CCER_CC4E_Pos (12U) 4635 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ 4636 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ 4637 #define TIM_CCER_CC4P_Pos (13U) 4638 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ 4639 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ 4640 #define TIM_CCER_CC4NP_Pos (15U) 4641 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ 4642 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ 4643 4644 /******************* Bit definition for TIM_CNT register *******************/ 4645 #define TIM_CNT_CNT_Pos (0U) 4646 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ 4647 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ 4648 4649 /******************* Bit definition for TIM_PSC register *******************/ 4650 #define TIM_PSC_PSC_Pos (0U) 4651 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ 4652 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ 4653 4654 /******************* Bit definition for TIM_ARR register *******************/ 4655 #define TIM_ARR_ARR_Pos (0U) 4656 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ 4657 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ 4658 4659 /******************* Bit definition for TIM_RCR register *******************/ 4660 #define TIM_RCR_REP_Pos (0U) 4661 #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /*!< 0x000000FF */ 4662 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ 4663 4664 /******************* Bit definition for TIM_CCR1 register ******************/ 4665 #define TIM_CCR1_CCR1_Pos (0U) 4666 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ 4667 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ 4668 4669 /******************* Bit definition for TIM_CCR2 register ******************/ 4670 #define TIM_CCR2_CCR2_Pos (0U) 4671 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ 4672 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ 4673 4674 /******************* Bit definition for TIM_CCR3 register ******************/ 4675 #define TIM_CCR3_CCR3_Pos (0U) 4676 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ 4677 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ 4678 4679 /******************* Bit definition for TIM_CCR4 register ******************/ 4680 #define TIM_CCR4_CCR4_Pos (0U) 4681 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ 4682 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ 4683 4684 /******************* Bit definition for TIM_BDTR register ******************/ 4685 #define TIM_BDTR_DTG_Pos (0U) 4686 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ 4687 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ 4688 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ 4689 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */ 4690 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */ 4691 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */ 4692 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */ 4693 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */ 4694 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ 4695 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */ 4696 4697 #define TIM_BDTR_LOCK_Pos (8U) 4698 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ 4699 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ 4700 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ 4701 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */ 4702 4703 #define TIM_BDTR_OSSI_Pos (10U) 4704 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ 4705 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ 4706 #define TIM_BDTR_OSSR_Pos (11U) 4707 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ 4708 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ 4709 #define TIM_BDTR_BKE_Pos (12U) 4710 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ 4711 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */ 4712 #define TIM_BDTR_BKP_Pos (13U) 4713 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ 4714 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */ 4715 #define TIM_BDTR_AOE_Pos (14U) 4716 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ 4717 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ 4718 #define TIM_BDTR_MOE_Pos (15U) 4719 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ 4720 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ 4721 4722 /******************* Bit definition for TIM_DCR register *******************/ 4723 #define TIM_DCR_DBA_Pos (0U) 4724 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ 4725 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ 4726 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ 4727 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ 4728 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ 4729 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ 4730 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ 4731 4732 #define TIM_DCR_DBL_Pos (8U) 4733 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ 4734 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ 4735 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ 4736 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ 4737 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ 4738 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ 4739 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ 4740 4741 /******************* Bit definition for TIM_DMAR register ******************/ 4742 #define TIM_DMAR_DMAB_Pos (0U) 4743 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ 4744 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ 4745 4746 /******************* Bit definition for TIM14_OR register ********************/ 4747 #define TIM14_OR_TI1_RMP_Pos (0U) 4748 #define TIM14_OR_TI1_RMP_Msk (0x3UL << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000003 */ 4749 #define TIM14_OR_TI1_RMP TIM14_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */ 4750 #define TIM14_OR_TI1_RMP_0 (0x1UL << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000001 */ 4751 #define TIM14_OR_TI1_RMP_1 (0x2UL << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000002 */ 4752 4753 /******************************************************************************/ 4754 /* */ 4755 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ 4756 /* */ 4757 /******************************************************************************/ 4758 /****************** Bit definition for USART_CR1 register *******************/ 4759 #define USART_CR1_UE_Pos (0U) 4760 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */ 4761 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ 4762 #define USART_CR1_RE_Pos (2U) 4763 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */ 4764 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ 4765 #define USART_CR1_TE_Pos (3U) 4766 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */ 4767 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ 4768 #define USART_CR1_IDLEIE_Pos (4U) 4769 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ 4770 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ 4771 #define USART_CR1_RXNEIE_Pos (5U) 4772 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ 4773 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ 4774 #define USART_CR1_TCIE_Pos (6U) 4775 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ 4776 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ 4777 #define USART_CR1_TXEIE_Pos (7U) 4778 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ 4779 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */ 4780 #define USART_CR1_PEIE_Pos (8U) 4781 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ 4782 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ 4783 #define USART_CR1_PS_Pos (9U) 4784 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */ 4785 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ 4786 #define USART_CR1_PCE_Pos (10U) 4787 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */ 4788 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ 4789 #define USART_CR1_WAKE_Pos (11U) 4790 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ 4791 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */ 4792 #define USART_CR1_M_Pos (12U) 4793 #define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos) /*!< 0x00001000 */ 4794 #define USART_CR1_M USART_CR1_M_Msk /*!< Word Length */ 4795 #define USART_CR1_MME_Pos (13U) 4796 #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */ 4797 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */ 4798 #define USART_CR1_CMIE_Pos (14U) 4799 #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */ 4800 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */ 4801 #define USART_CR1_OVER8_Pos (15U) 4802 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ 4803 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */ 4804 #define USART_CR1_DEDT_Pos (16U) 4805 #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */ 4806 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */ 4807 #define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */ 4808 #define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */ 4809 #define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */ 4810 #define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */ 4811 #define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */ 4812 #define USART_CR1_DEAT_Pos (21U) 4813 #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */ 4814 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */ 4815 #define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */ 4816 #define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */ 4817 #define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */ 4818 #define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */ 4819 #define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */ 4820 #define USART_CR1_RTOIE_Pos (26U) 4821 #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */ 4822 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */ 4823 #define USART_CR1_EOBIE_Pos (27U) 4824 #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */ 4825 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */ 4826 4827 /****************** Bit definition for USART_CR2 register *******************/ 4828 #define USART_CR2_ADDM7_Pos (4U) 4829 #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */ 4830 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */ 4831 #define USART_CR2_LBCL_Pos (8U) 4832 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ 4833 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ 4834 #define USART_CR2_CPHA_Pos (9U) 4835 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ 4836 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ 4837 #define USART_CR2_CPOL_Pos (10U) 4838 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ 4839 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ 4840 #define USART_CR2_CLKEN_Pos (11U) 4841 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ 4842 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ 4843 #define USART_CR2_STOP_Pos (12U) 4844 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */ 4845 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ 4846 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */ 4847 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */ 4848 #define USART_CR2_SWAP_Pos (15U) 4849 #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */ 4850 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */ 4851 #define USART_CR2_RXINV_Pos (16U) 4852 #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */ 4853 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */ 4854 #define USART_CR2_TXINV_Pos (17U) 4855 #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */ 4856 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */ 4857 #define USART_CR2_DATAINV_Pos (18U) 4858 #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */ 4859 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */ 4860 #define USART_CR2_MSBFIRST_Pos (19U) 4861 #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */ 4862 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */ 4863 #define USART_CR2_ABREN_Pos (20U) 4864 #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */ 4865 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/ 4866 #define USART_CR2_ABRMODE_Pos (21U) 4867 #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */ 4868 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */ 4869 #define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */ 4870 #define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */ 4871 #define USART_CR2_RTOEN_Pos (23U) 4872 #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */ 4873 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */ 4874 #define USART_CR2_ADD_Pos (24U) 4875 #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */ 4876 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ 4877 4878 /****************** Bit definition for USART_CR3 register *******************/ 4879 #define USART_CR3_EIE_Pos (0U) 4880 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */ 4881 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ 4882 #define USART_CR3_HDSEL_Pos (3U) 4883 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ 4884 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ 4885 #define USART_CR3_DMAR_Pos (6U) 4886 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ 4887 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ 4888 #define USART_CR3_DMAT_Pos (7U) 4889 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ 4890 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ 4891 #define USART_CR3_RTSE_Pos (8U) 4892 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ 4893 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ 4894 #define USART_CR3_CTSE_Pos (9U) 4895 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ 4896 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ 4897 #define USART_CR3_CTSIE_Pos (10U) 4898 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ 4899 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ 4900 #define USART_CR3_ONEBIT_Pos (11U) 4901 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ 4902 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */ 4903 #define USART_CR3_OVRDIS_Pos (12U) 4904 #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */ 4905 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */ 4906 #define USART_CR3_DDRE_Pos (13U) 4907 #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */ 4908 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */ 4909 #define USART_CR3_DEM_Pos (14U) 4910 #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */ 4911 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */ 4912 #define USART_CR3_DEP_Pos (15U) 4913 #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */ 4914 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */ 4915 4916 /****************** Bit definition for USART_BRR register *******************/ 4917 #define USART_BRR_DIV_FRACTION_Pos (0U) 4918 #define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */ 4919 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */ 4920 #define USART_BRR_DIV_MANTISSA_Pos (4U) 4921 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */ 4922 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */ 4923 4924 /****************** Bit definition for USART_GTPR register ******************/ 4925 #define USART_GTPR_PSC_Pos (0U) 4926 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ 4927 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ 4928 #define USART_GTPR_GT_Pos (8U) 4929 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ 4930 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */ 4931 4932 4933 /******************* Bit definition for USART_RTOR register *****************/ 4934 #define USART_RTOR_RTO_Pos (0U) 4935 #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */ 4936 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */ 4937 #define USART_RTOR_BLEN_Pos (24U) 4938 #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */ 4939 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */ 4940 4941 /******************* Bit definition for USART_RQR register ******************/ 4942 #define USART_RQR_ABRRQ_Pos (0U) 4943 #define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */ 4944 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */ 4945 #define USART_RQR_SBKRQ_Pos (1U) 4946 #define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */ 4947 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */ 4948 #define USART_RQR_MMRQ_Pos (2U) 4949 #define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */ 4950 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */ 4951 #define USART_RQR_RXFRQ_Pos (3U) 4952 #define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */ 4953 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */ 4954 4955 /******************* Bit definition for USART_ISR register ******************/ 4956 #define USART_ISR_PE_Pos (0U) 4957 #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */ 4958 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */ 4959 #define USART_ISR_FE_Pos (1U) 4960 #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */ 4961 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */ 4962 #define USART_ISR_NE_Pos (2U) 4963 #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */ 4964 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */ 4965 #define USART_ISR_ORE_Pos (3U) 4966 #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */ 4967 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */ 4968 #define USART_ISR_IDLE_Pos (4U) 4969 #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */ 4970 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */ 4971 #define USART_ISR_RXNE_Pos (5U) 4972 #define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */ 4973 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */ 4974 #define USART_ISR_TC_Pos (6U) 4975 #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */ 4976 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */ 4977 #define USART_ISR_TXE_Pos (7U) 4978 #define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */ 4979 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */ 4980 #define USART_ISR_CTSIF_Pos (9U) 4981 #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */ 4982 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */ 4983 #define USART_ISR_CTS_Pos (10U) 4984 #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */ 4985 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */ 4986 #define USART_ISR_RTOF_Pos (11U) 4987 #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */ 4988 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */ 4989 #define USART_ISR_ABRE_Pos (14U) 4990 #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */ 4991 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */ 4992 #define USART_ISR_ABRF_Pos (15U) 4993 #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */ 4994 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */ 4995 #define USART_ISR_BUSY_Pos (16U) 4996 #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */ 4997 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */ 4998 #define USART_ISR_CMF_Pos (17U) 4999 #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */ 5000 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */ 5001 #define USART_ISR_SBKF_Pos (18U) 5002 #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */ 5003 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */ 5004 #define USART_ISR_RWU_Pos (19U) 5005 #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */ 5006 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */ 5007 #define USART_ISR_TEACK_Pos (21U) 5008 #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */ 5009 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */ 5010 #define USART_ISR_REACK_Pos (22U) 5011 #define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */ 5012 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */ 5013 5014 /******************* Bit definition for USART_ICR register ******************/ 5015 #define USART_ICR_PECF_Pos (0U) 5016 #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */ 5017 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */ 5018 #define USART_ICR_FECF_Pos (1U) 5019 #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */ 5020 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */ 5021 #define USART_ICR_NCF_Pos (2U) 5022 #define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */ 5023 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */ 5024 #define USART_ICR_ORECF_Pos (3U) 5025 #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */ 5026 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */ 5027 #define USART_ICR_IDLECF_Pos (4U) 5028 #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */ 5029 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */ 5030 #define USART_ICR_TCCF_Pos (6U) 5031 #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */ 5032 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */ 5033 #define USART_ICR_CTSCF_Pos (9U) 5034 #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */ 5035 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */ 5036 #define USART_ICR_RTOCF_Pos (11U) 5037 #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */ 5038 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */ 5039 #define USART_ICR_CMCF_Pos (17U) 5040 #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */ 5041 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */ 5042 5043 /******************* Bit definition for USART_RDR register ******************/ 5044 #define USART_RDR_RDR ((uint16_t)0x01FFU) /*!< RDR[8:0] bits (Receive Data value) */ 5045 5046 /******************* Bit definition for USART_TDR register ******************/ 5047 #define USART_TDR_TDR ((uint16_t)0x01FFU) /*!< TDR[8:0] bits (Transmit Data value) */ 5048 5049 /******************************************************************************/ 5050 /* */ 5051 /* Window WATCHDOG (WWDG) */ 5052 /* */ 5053 /******************************************************************************/ 5054 5055 /******************* Bit definition for WWDG_CR register ********************/ 5056 #define WWDG_CR_T_Pos (0U) 5057 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */ 5058 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ 5059 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */ 5060 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */ 5061 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */ 5062 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */ 5063 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */ 5064 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */ 5065 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */ 5066 5067 /* Legacy defines */ 5068 #define WWDG_CR_T0 WWDG_CR_T_0 5069 #define WWDG_CR_T1 WWDG_CR_T_1 5070 #define WWDG_CR_T2 WWDG_CR_T_2 5071 #define WWDG_CR_T3 WWDG_CR_T_3 5072 #define WWDG_CR_T4 WWDG_CR_T_4 5073 #define WWDG_CR_T5 WWDG_CR_T_5 5074 #define WWDG_CR_T6 WWDG_CR_T_6 5075 5076 #define WWDG_CR_WDGA_Pos (7U) 5077 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ 5078 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */ 5079 5080 /******************* Bit definition for WWDG_CFR register *******************/ 5081 #define WWDG_CFR_W_Pos (0U) 5082 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */ 5083 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */ 5084 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */ 5085 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */ 5086 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */ 5087 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */ 5088 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */ 5089 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */ 5090 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */ 5091 5092 /* Legacy defines */ 5093 #define WWDG_CFR_W0 WWDG_CFR_W_0 5094 #define WWDG_CFR_W1 WWDG_CFR_W_1 5095 #define WWDG_CFR_W2 WWDG_CFR_W_2 5096 #define WWDG_CFR_W3 WWDG_CFR_W_3 5097 #define WWDG_CFR_W4 WWDG_CFR_W_4 5098 #define WWDG_CFR_W5 WWDG_CFR_W_5 5099 #define WWDG_CFR_W6 WWDG_CFR_W_6 5100 5101 #define WWDG_CFR_WDGTB_Pos (7U) 5102 #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ 5103 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */ 5104 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ 5105 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ 5106 5107 /* Legacy defines */ 5108 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 5109 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 5110 5111 #define WWDG_CFR_EWI_Pos (9U) 5112 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ 5113 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */ 5114 5115 /******************* Bit definition for WWDG_SR register ********************/ 5116 #define WWDG_SR_EWIF_Pos (0U) 5117 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ 5118 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ 5119 5120 /** 5121 * @} 5122 */ 5123 5124 /** 5125 * @} 5126 */ 5127 5128 5129 /** @addtogroup Exported_macro 5130 * @{ 5131 */ 5132 5133 /****************************** ADC Instances *********************************/ 5134 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) 5135 5136 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC) 5137 5138 /****************************** CRC Instances *********************************/ 5139 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) 5140 5141 /******************************* DMA Instances ********************************/ 5142 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ 5143 ((INSTANCE) == DMA1_Channel2) || \ 5144 ((INSTANCE) == DMA1_Channel3) || \ 5145 ((INSTANCE) == DMA1_Channel4) || \ 5146 ((INSTANCE) == DMA1_Channel5)) 5147 5148 /****************************** GPIO Instances ********************************/ 5149 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 5150 ((INSTANCE) == GPIOB) || \ 5151 ((INSTANCE) == GPIOC) || \ 5152 ((INSTANCE) == GPIOD) || \ 5153 ((INSTANCE) == GPIOF)) 5154 5155 /**************************** GPIO Alternate Function Instances ***************/ 5156 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 5157 ((INSTANCE) == GPIOB) || \ 5158 ((INSTANCE) == GPIOF)) 5159 5160 /****************************** GPIO Lock Instances ***************************/ 5161 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 5162 ((INSTANCE) == GPIOB)) 5163 5164 /****************************** I2C Instances *********************************/ 5165 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ 5166 ((INSTANCE) == I2C2)) 5167 5168 5169 /****************************** IWDG Instances ********************************/ 5170 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) 5171 5172 /****************************** RTC Instances *********************************/ 5173 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) 5174 5175 /****************************** SMBUS Instances *********************************/ 5176 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1) 5177 5178 /****************************** SPI Instances *********************************/ 5179 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ 5180 ((INSTANCE) == SPI2)) 5181 5182 /****************************** TIM Instances *********************************/ 5183 #define IS_TIM_INSTANCE(INSTANCE)\ 5184 (((INSTANCE) == TIM1) || \ 5185 ((INSTANCE) == TIM3) || \ 5186 ((INSTANCE) == TIM6) || \ 5187 ((INSTANCE) == TIM14) || \ 5188 ((INSTANCE) == TIM15) || \ 5189 ((INSTANCE) == TIM16) || \ 5190 ((INSTANCE) == TIM17)) 5191 5192 #define IS_TIM_CC1_INSTANCE(INSTANCE)\ 5193 (((INSTANCE) == TIM1) || \ 5194 ((INSTANCE) == TIM3) || \ 5195 ((INSTANCE) == TIM14) || \ 5196 ((INSTANCE) == TIM15) || \ 5197 ((INSTANCE) == TIM16) || \ 5198 ((INSTANCE) == TIM17)) 5199 5200 #define IS_TIM_CC2_INSTANCE(INSTANCE)\ 5201 (((INSTANCE) == TIM1) || \ 5202 ((INSTANCE) == TIM3) || \ 5203 ((INSTANCE) == TIM15)) 5204 5205 #define IS_TIM_CC3_INSTANCE(INSTANCE)\ 5206 (((INSTANCE) == TIM1) || \ 5207 ((INSTANCE) == TIM3)) 5208 5209 #define IS_TIM_CC4_INSTANCE(INSTANCE)\ 5210 (((INSTANCE) == TIM1) || \ 5211 ((INSTANCE) == TIM3)) 5212 5213 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\ 5214 (((INSTANCE) == TIM1) || \ 5215 ((INSTANCE) == TIM3)) 5216 5217 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\ 5218 (((INSTANCE) == TIM1) || \ 5219 ((INSTANCE) == TIM3)) 5220 5221 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\ 5222 (((INSTANCE) == TIM1) || \ 5223 ((INSTANCE) == TIM3) || \ 5224 ((INSTANCE) == TIM15)) 5225 5226 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\ 5227 (((INSTANCE) == TIM1) || \ 5228 ((INSTANCE) == TIM3) || \ 5229 ((INSTANCE) == TIM15)) 5230 5231 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\ 5232 (((INSTANCE) == TIM1) || \ 5233 ((INSTANCE) == TIM3)) 5234 5235 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ 5236 (((INSTANCE) == TIM1) || \ 5237 ((INSTANCE) == TIM3)) 5238 5239 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\ 5240 (((INSTANCE) == TIM1)) 5241 5242 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\ 5243 (((INSTANCE) == TIM1)) 5244 5245 #define IS_TIM_XOR_INSTANCE(INSTANCE)\ 5246 (((INSTANCE) == TIM1) || \ 5247 ((INSTANCE) == TIM3)) 5248 5249 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\ 5250 (((INSTANCE) == TIM1) || \ 5251 ((INSTANCE) == TIM3) || \ 5252 ((INSTANCE) == TIM15)) 5253 5254 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\ 5255 (((INSTANCE) == TIM1) || \ 5256 ((INSTANCE) == TIM3) || \ 5257 ((INSTANCE) == TIM15)) 5258 5259 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (0) 5260 5261 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ 5262 (((INSTANCE) == TIM1) || \ 5263 ((INSTANCE) == TIM3) || \ 5264 ((INSTANCE) == TIM15) || \ 5265 ((INSTANCE) == TIM16) || \ 5266 ((INSTANCE) == TIM17)) 5267 5268 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\ 5269 (((INSTANCE) == TIM1) || \ 5270 ((INSTANCE) == TIM15) || \ 5271 ((INSTANCE) == TIM16) || \ 5272 ((INSTANCE) == TIM17)) 5273 5274 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ 5275 ((((INSTANCE) == TIM1) && \ 5276 (((CHANNEL) == TIM_CHANNEL_1) || \ 5277 ((CHANNEL) == TIM_CHANNEL_2) || \ 5278 ((CHANNEL) == TIM_CHANNEL_3) || \ 5279 ((CHANNEL) == TIM_CHANNEL_4))) \ 5280 || \ 5281 (((INSTANCE) == TIM3) && \ 5282 (((CHANNEL) == TIM_CHANNEL_1) || \ 5283 ((CHANNEL) == TIM_CHANNEL_2) || \ 5284 ((CHANNEL) == TIM_CHANNEL_3) || \ 5285 ((CHANNEL) == TIM_CHANNEL_4))) \ 5286 || \ 5287 (((INSTANCE) == TIM14) && \ 5288 (((CHANNEL) == TIM_CHANNEL_1))) \ 5289 || \ 5290 (((INSTANCE) == TIM15) && \ 5291 (((CHANNEL) == TIM_CHANNEL_1) || \ 5292 ((CHANNEL) == TIM_CHANNEL_2))) \ 5293 || \ 5294 (((INSTANCE) == TIM16) && \ 5295 (((CHANNEL) == TIM_CHANNEL_1))) \ 5296 || \ 5297 (((INSTANCE) == TIM17) && \ 5298 (((CHANNEL) == TIM_CHANNEL_1)))) 5299 5300 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ 5301 ((((INSTANCE) == TIM1) && \ 5302 (((CHANNEL) == TIM_CHANNEL_1) || \ 5303 ((CHANNEL) == TIM_CHANNEL_2) || \ 5304 ((CHANNEL) == TIM_CHANNEL_3))) \ 5305 || \ 5306 (((INSTANCE) == TIM15) && \ 5307 ((CHANNEL) == TIM_CHANNEL_1)) \ 5308 || \ 5309 (((INSTANCE) == TIM16) && \ 5310 ((CHANNEL) == TIM_CHANNEL_1)) \ 5311 || \ 5312 (((INSTANCE) == TIM17) && \ 5313 ((CHANNEL) == TIM_CHANNEL_1))) 5314 5315 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ 5316 (((INSTANCE) == TIM1) || \ 5317 ((INSTANCE) == TIM3)) 5318 5319 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\ 5320 (((INSTANCE) == TIM1) || \ 5321 ((INSTANCE) == TIM15) || \ 5322 ((INSTANCE) == TIM16) || \ 5323 ((INSTANCE) == TIM17)) 5324 5325 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\ 5326 (((INSTANCE) == TIM1) || \ 5327 ((INSTANCE) == TIM3) || \ 5328 ((INSTANCE) == TIM14) || \ 5329 ((INSTANCE) == TIM15) || \ 5330 ((INSTANCE) == TIM16) || \ 5331 ((INSTANCE) == TIM17)) 5332 5333 #define IS_TIM_DMA_INSTANCE(INSTANCE)\ 5334 (((INSTANCE) == TIM1) || \ 5335 ((INSTANCE) == TIM3) || \ 5336 ((INSTANCE) == TIM6) || \ 5337 ((INSTANCE) == TIM15) || \ 5338 ((INSTANCE) == TIM16) || \ 5339 ((INSTANCE) == TIM17)) 5340 5341 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\ 5342 (((INSTANCE) == TIM1) || \ 5343 ((INSTANCE) == TIM3) || \ 5344 ((INSTANCE) == TIM15) || \ 5345 ((INSTANCE) == TIM16) || \ 5346 ((INSTANCE) == TIM17)) 5347 5348 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\ 5349 (((INSTANCE) == TIM1) || \ 5350 ((INSTANCE) == TIM15) || \ 5351 ((INSTANCE) == TIM16) || \ 5352 ((INSTANCE) == TIM17)) 5353 5354 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\ 5355 ((INSTANCE) == TIM14) 5356 5357 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\ 5358 ((INSTANCE) == TIM1) 5359 5360 /******************** USART Instances : Synchronous mode **********************/ 5361 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5362 ((INSTANCE) == USART2)) 5363 5364 /******************** USART Instances : auto Baud rate detection **************/ 5365 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 5366 5367 /******************** UART Instances : Asynchronous mode **********************/ 5368 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5369 ((INSTANCE) == USART2)) 5370 5371 /******************** UART Instances : Half-Duplex mode **********************/ 5372 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5373 ((INSTANCE) == USART2)) 5374 5375 /****************** UART Instances : Hardware Flow control ********************/ 5376 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5377 ((INSTANCE) == USART2)) 5378 5379 /****************** UART Instances : Driver enable detection ********************/ 5380 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5381 ((INSTANCE) == USART2)) 5382 5383 /****************************** WWDG Instances ********************************/ 5384 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) 5385 5386 /** 5387 * @} 5388 */ 5389 5390 5391 /******************************************************************************/ 5392 /* For a painless codes migration between the STM32F0xx device product */ 5393 /* lines, the aliases defined below are put in place to overcome the */ 5394 /* differences in the interrupt handlers and IRQn definitions. */ 5395 /* No need to update developed interrupt code when moving across */ 5396 /* product lines within the same STM32F0 Family */ 5397 /******************************************************************************/ 5398 5399 /* Aliases for __IRQn */ 5400 #define ADC1_COMP_IRQn ADC1_IRQn 5401 #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn 5402 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn 5403 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn 5404 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn 5405 #define RCC_CRS_IRQn RCC_IRQn 5406 #define TIM6_DAC_IRQn TIM6_IRQn 5407 5408 #define SVC_IRQn SVCall_IRQn 5409 5410 /* Aliases for __IRQHandler */ 5411 #define ADC1_COMP_IRQHandler ADC1_IRQHandler 5412 #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler 5413 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler 5414 #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler 5415 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler 5416 #define RCC_CRS_IRQHandler RCC_IRQHandler 5417 #define TIM6_DAC_IRQHandler TIM6_IRQHandler 5418 5419 5420 #ifdef __cplusplus 5421 } 5422 #endif /* __cplusplus */ 5423 5424 #endif /* __STM32F030x8_H */ 5425 5426 /** 5427 * @} 5428 */ 5429 5430 /** 5431 * @} 5432 */ 5433 5434
