1 /** 2 ****************************************************************************** 3 * @file stm32_hal_legacy.h 4 * @author MCD Application Team 5 * @brief This file contains aliases definition for the STM32Cube HAL constants 6 * macros and functions maintained for legacy purpose. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32_HAL_LEGACY 22 #define STM32_HAL_LEGACY 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 /* Exported types ------------------------------------------------------------*/ 30 /* Exported constants --------------------------------------------------------*/ 31 32 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose 33 * @{ 34 */ 35 #define AES_FLAG_RDERR CRYP_FLAG_RDERR 36 #define AES_FLAG_WRERR CRYP_FLAG_WRERR 37 #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF 38 #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR 39 #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR 40 #if defined(STM32H7) || defined(STM32MP1) 41 #define CRYP_DATATYPE_32B CRYP_NO_SWAP 42 #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP 43 #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP 44 #define CRYP_DATATYPE_1B CRYP_BIT_SWAP 45 #endif /* STM32H7 || STM32MP1 */ 46 /** 47 * @} 48 */ 49 50 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose 51 * @{ 52 */ 53 #define ADC_RESOLUTION12b ADC_RESOLUTION_12B 54 #define ADC_RESOLUTION10b ADC_RESOLUTION_10B 55 #define ADC_RESOLUTION8b ADC_RESOLUTION_8B 56 #define ADC_RESOLUTION6b ADC_RESOLUTION_6B 57 #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN 58 #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED 59 #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV 60 #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV 61 #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV 62 #define REGULAR_GROUP ADC_REGULAR_GROUP 63 #define INJECTED_GROUP ADC_INJECTED_GROUP 64 #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP 65 #define AWD_EVENT ADC_AWD_EVENT 66 #define AWD1_EVENT ADC_AWD1_EVENT 67 #define AWD2_EVENT ADC_AWD2_EVENT 68 #define AWD3_EVENT ADC_AWD3_EVENT 69 #define OVR_EVENT ADC_OVR_EVENT 70 #define JQOVF_EVENT ADC_JQOVF_EVENT 71 #define ALL_CHANNELS ADC_ALL_CHANNELS 72 #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS 73 #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS 74 #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR 75 #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT 76 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 77 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 78 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 79 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 80 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 81 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO 82 #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 83 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO 84 #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 85 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO 86 #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 87 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 88 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE 89 #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING 90 #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING 91 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING 92 #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 93 94 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY 95 #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY 96 #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC 97 #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC 98 #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL 99 #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL 100 #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 101 102 #if defined(STM32H7) 103 #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT 104 #endif /* STM32H7 */ 105 106 #if defined(STM32U5) 107 #define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES 108 #define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES 109 #define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 110 #endif /* STM32U5 */ 111 112 #if defined(STM32H5) 113 #define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE 114 #endif /* STM32H5 */ 115 /** 116 * @} 117 */ 118 119 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose 120 * @{ 121 */ 122 123 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG 124 125 /** 126 * @} 127 */ 128 129 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose 130 * @{ 131 */ 132 #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE 133 #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE 134 #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 135 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 136 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 137 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 138 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 139 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 140 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 141 #if defined(STM32L0) 142 #define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM 143 input 1 for COMP1, LPTIM input 2 for COMP2 */ 144 #endif 145 #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR 146 #if defined(STM32F373xC) || defined(STM32F378xx) 147 #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 148 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR 149 #endif /* STM32F373xC || STM32F378xx */ 150 151 #if defined(STM32L0) || defined(STM32L4) 152 #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON 153 154 #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 155 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 156 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 157 #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 158 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 159 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 160 161 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT 162 #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT 163 #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT 164 #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT 165 #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 166 #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 167 #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 168 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 169 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 170 #if defined(STM32L0) 171 /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ 172 /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ 173 /* to the second dedicated IO (only for COMP2). */ 174 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 175 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 176 #else 177 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 178 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 179 #endif 180 #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 181 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 182 183 #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW 184 #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH 185 186 /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ 187 /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ 188 #if defined(COMP_CSR_LOCK) 189 #define COMP_FLAG_LOCK COMP_CSR_LOCK 190 #elif defined(COMP_CSR_COMP1LOCK) 191 #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK 192 #elif defined(COMP_CSR_COMPxLOCK) 193 #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK 194 #endif 195 196 #if defined(STM32L4) 197 #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 198 #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 199 #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 200 #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 201 #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 202 #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 203 #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE 204 #endif 205 206 #if defined(STM32L0) 207 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED 208 #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER 209 #else 210 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED 211 #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED 212 #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER 213 #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER 214 #endif 215 216 #endif 217 218 #if defined(STM32U5) 219 #define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG 220 #endif 221 222 /** 223 * @} 224 */ 225 226 /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose 227 * @{ 228 */ 229 #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig 230 #if defined(STM32U5) 231 #define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE 232 #define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE 233 #define MPU_DEVICE_nGRE MPU_DEVICE_NGRE 234 #endif /* STM32U5 */ 235 /** 236 * @} 237 */ 238 239 /** @defgroup CRC_Aliases CRC API aliases 240 * @{ 241 */ 242 #if defined(STM32H5) || defined(STM32C0) 243 #else 244 #define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for 245 inter STM32 series compatibility */ 246 #define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for 247 inter STM32 series compatibility */ 248 #endif 249 /** 250 * @} 251 */ 252 253 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose 254 * @{ 255 */ 256 257 #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE 258 #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE 259 260 /** 261 * @} 262 */ 263 264 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose 265 * @{ 266 */ 267 268 #define DAC1_CHANNEL_1 DAC_CHANNEL_1 269 #define DAC1_CHANNEL_2 DAC_CHANNEL_2 270 #define DAC2_CHANNEL_1 DAC_CHANNEL_1 271 #define DAC_WAVE_NONE 0x00000000U 272 #define DAC_WAVE_NOISE DAC_CR_WAVE1_0 273 #define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 274 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE 275 #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE 276 #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE 277 278 #if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) 279 #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL 280 #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL 281 #endif 282 283 #if defined(STM32U5) 284 #define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 285 #define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 286 #define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 287 #define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 288 #endif 289 290 #if defined(STM32H5) 291 #define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 292 #define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1 293 #endif 294 295 #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \ 296 defined(STM32F4) || defined(STM32G4) 297 #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID 298 #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID 299 #endif 300 301 /** 302 * @} 303 */ 304 305 /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose 306 * @{ 307 */ 308 #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 309 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 310 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 311 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 312 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 313 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 314 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 315 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 316 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 317 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 318 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 319 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 320 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 321 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 322 323 #define IS_HAL_REMAPDMA IS_DMA_REMAP 324 #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE 325 #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE 326 327 #if defined(STM32L4) 328 329 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 330 #define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 331 #define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 332 #define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 333 #define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 334 #define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 335 #define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 336 #define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 337 #define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 338 #define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 339 #define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 340 #define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 341 #define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 342 #define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 343 #define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 344 #define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 345 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 346 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 347 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 348 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 349 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 350 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 351 #define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE 352 #define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT 353 #define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT 354 #define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT 355 356 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT 357 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING 358 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING 359 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING 360 361 #if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ 362 defined(STM32L4S7xx) || defined(STM32L4S9xx) 363 #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI 364 #endif 365 366 #endif /* STM32L4 */ 367 368 #if defined(STM32G0) 369 #define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 370 #define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 371 #define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM 372 #define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM 373 374 #define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM 375 #define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM 376 #endif 377 378 #if defined(STM32H7) 379 380 #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 381 #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 382 383 #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX 384 #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX 385 386 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 387 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 388 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 389 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 390 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 391 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 392 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 393 #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 394 395 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 396 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 397 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 398 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 399 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 400 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 401 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 402 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 403 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 404 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 405 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 406 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 407 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 408 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 409 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 410 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 411 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP 412 #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT 413 #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT 414 #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP 415 #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 416 #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 417 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 418 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT 419 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 420 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 421 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT 422 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 423 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 424 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 425 426 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT 427 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING 428 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING 429 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING 430 431 #define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT 432 #define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT 433 #define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT 434 435 #define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT 436 #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT 437 438 #endif /* STM32H7 */ 439 440 #if defined(STM32U5) 441 #define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI 442 #endif /* STM32U5 */ 443 /** 444 * @} 445 */ 446 447 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose 448 * @{ 449 */ 450 451 #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE 452 #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD 453 #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD 454 #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD 455 #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS 456 #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES 457 #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES 458 #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE 459 #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE 460 #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE 461 #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE 462 #define OBEX_PCROP OPTIONBYTE_PCROP 463 #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG 464 #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE 465 #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE 466 #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE 467 #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD 468 #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD 469 #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE 470 #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD 471 #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD 472 #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE 473 #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD 474 #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD 475 #if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) 476 /* #define PAGESIZE FLASH_PAGE_SIZE */ 477 #endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ 478 #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE 479 #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD 480 #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD 481 #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 482 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 483 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 484 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 485 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST 486 #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST 487 #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA 488 #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB 489 #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA 490 #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB 491 #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE 492 #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN 493 #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE 494 #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN 495 #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE 496 #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD 497 #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG 498 #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS 499 #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP 500 #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV 501 #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR 502 #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG 503 #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION 504 #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA 505 #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE 506 #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE 507 #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS 508 #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS 509 #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST 510 #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR 511 #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO 512 #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION 513 #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS 514 #define OB_WDG_SW OB_IWDG_SW 515 #define OB_WDG_HW OB_IWDG_HW 516 #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET 517 #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET 518 #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET 519 #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET 520 #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR 521 #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 522 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 523 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 524 #if defined(STM32G0) || defined(STM32C0) 525 #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE 526 #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH 527 #else 528 #define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE 529 #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE 530 #endif 531 #if defined(STM32H7) 532 #define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 533 #define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 534 #define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 535 #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 536 #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 537 #define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 538 #define FLASH_FLAG_WDW FLASH_FLAG_WBNE 539 #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL 540 #endif /* STM32H7 */ 541 #if defined(STM32U5) 542 #define OB_USER_nRST_STOP OB_USER_NRST_STOP 543 #define OB_USER_nRST_STDBY OB_USER_NRST_STDBY 544 #define OB_USER_nRST_SHDW OB_USER_NRST_SHDW 545 #define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 546 #define OB_USER_nBOOT0 OB_USER_NBOOT0 547 #define OB_nBOOT0_RESET OB_NBOOT0_RESET 548 #define OB_nBOOT0_SET OB_NBOOT0_SET 549 #define OB_USER_SRAM134_RST OB_USER_SRAM_RST 550 #define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE 551 #define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE 552 #endif /* STM32U5 */ 553 #if defined(STM32U0) 554 #define OB_USER_nRST_STOP OB_USER_NRST_STOP 555 #define OB_USER_nRST_STDBY OB_USER_NRST_STDBY 556 #define OB_USER_nRST_SHDW OB_USER_NRST_SHDW 557 #define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL 558 #define OB_USER_nBOOT0 OB_USER_NBOOT0 559 #define OB_USER_nBOOT1 OB_USER_NBOOT1 560 #define OB_nBOOT0_RESET OB_NBOOT0_RESET 561 #define OB_nBOOT0_SET OB_NBOOT0_SET 562 #endif /* STM32U0 */ 563 564 /** 565 * @} 566 */ 567 568 /** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose 569 * @{ 570 */ 571 572 #if defined(STM32H7) 573 #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE 574 #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE 575 #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET 576 #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET 577 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE 578 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE 579 #endif /* STM32H7 */ 580 581 /** 582 * @} 583 */ 584 585 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose 586 * @{ 587 */ 588 589 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 590 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 591 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 592 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 593 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 594 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 595 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 596 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 597 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 598 #if defined(STM32G4) 599 600 #define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster 601 #define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster 602 #define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD 603 #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD 604 #endif /* STM32G4 */ 605 606 #if defined(STM32U5) 607 608 #define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster 609 #define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster 610 #define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection 611 #define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection 612 613 #endif /* STM32U5 */ 614 615 #if defined(STM32H5) 616 #define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC 617 #define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC 618 #define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC 619 #define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC 620 #define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC 621 #define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC 622 623 #define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC 624 #define SYSCFG_BREAK_PVD SBS_BREAK_PVD 625 #define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC 626 #define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP 627 628 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0 629 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1 630 #define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2 631 #define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3 632 633 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE 634 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE 635 636 #define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6 637 #define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7 638 #define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8 639 #define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9 640 641 #define SYSCFG_ETH_MII SBS_ETH_MII 642 #define SYSCFG_ETH_RMII SBS_ETH_RMII 643 #define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG 644 645 #define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE 646 #define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR 647 #define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG 648 649 #define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG 650 651 #define SYSCFG_MPU_NSEC SBS_MPU_NSEC 652 #define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC 653 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 654 #define SYSCFG_SAU SBS_SAU 655 #define SYSCFG_MPU_SEC SBS_MPU_SEC 656 #define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC 657 #define SYSCFG_LOCK_ALL SBS_LOCK_ALL 658 #else 659 #define SYSCFG_LOCK_ALL SBS_LOCK_ALL 660 #endif /* __ARM_FEATURE_CMSE */ 661 662 #define SYSCFG_CLK SBS_CLK 663 #define SYSCFG_CLASSB SBS_CLASSB 664 #define SYSCFG_FPU SBS_FPU 665 #define SYSCFG_ALL SBS_ALL 666 667 #define SYSCFG_SEC SBS_SEC 668 #define SYSCFG_NSEC SBS_NSEC 669 670 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE 671 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE 672 673 #define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK 674 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK 675 #define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK 676 #define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK 677 678 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE 679 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE 680 681 #define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS 682 #define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS 683 684 #define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT 685 #define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG 686 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE 687 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE 688 #define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING 689 #define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS 690 #define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES 691 #define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES 692 #define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS 693 694 #define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig 695 #define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig 696 #define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig 697 #define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF 698 #define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF 699 700 #define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster 701 #define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster 702 #define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect 703 704 #define HAL_SYSCFG_Lock HAL_SBS_Lock 705 #define HAL_SYSCFG_GetLock HAL_SBS_GetLock 706 707 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 708 #define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes 709 #define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes 710 #endif /* __ARM_FEATURE_CMSE */ 711 712 #endif /* STM32H5 */ 713 714 715 /** 716 * @} 717 */ 718 719 720 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose 721 * @{ 722 */ 723 #if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) 724 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE 725 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE 726 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 727 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 728 #elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) 729 #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE 730 #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE 731 #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 732 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 733 #endif 734 /** 735 * @} 736 */ 737 738 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose 739 * @{ 740 */ 741 742 #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef 743 #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef 744 /** 745 * @} 746 */ 747 748 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose 749 * @{ 750 */ 751 #define GET_GPIO_SOURCE GPIO_GET_INDEX 752 #define GET_GPIO_INDEX GPIO_GET_INDEX 753 754 #if defined(STM32F4) 755 #define GPIO_AF12_SDMMC GPIO_AF12_SDIO 756 #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO 757 #endif 758 759 #if defined(STM32F7) 760 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 761 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 762 #endif 763 764 #if defined(STM32L4) 765 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 766 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 767 #endif 768 769 #if defined(STM32H7) 770 #define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 771 #define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 772 #define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 773 #define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 774 #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 775 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 776 777 #if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ 778 defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) 779 #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS 780 #define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS 781 #define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS 782 #endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \ 783 STM32H757xx */ 784 #endif /* STM32H7 */ 785 786 #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 787 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 788 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 789 790 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \ 791 defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) 792 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 793 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 794 #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH 795 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 796 #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ 797 798 #if defined(STM32L1) 799 #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW 800 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM 801 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH 802 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 803 #endif /* STM32L1 */ 804 805 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) 806 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 807 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 808 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH 809 #endif /* STM32F0 || STM32F3 || STM32F1 */ 810 811 #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 812 813 #if defined(STM32U5) || defined(STM32H5) 814 #define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ 815 #endif /* STM32U5 || STM32H5 */ 816 #if defined(STM32U5) 817 #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP 818 #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 819 #endif /* STM32U5 */ 820 821 #if defined(STM32WBA) 822 #define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF 823 #define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF 824 #define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF 825 #define GPIO_AF11_RF_IO1 GPIO_AF11_RF 826 #define GPIO_AF11_RF_IO2 GPIO_AF11_RF 827 #define GPIO_AF11_RF_IO3 GPIO_AF11_RF 828 #define GPIO_AF11_RF_IO4 GPIO_AF11_RF 829 #define GPIO_AF11_RF_IO5 GPIO_AF11_RF 830 #define GPIO_AF11_RF_IO6 GPIO_AF11_RF 831 #define GPIO_AF11_RF_IO7 GPIO_AF11_RF 832 #define GPIO_AF11_RF_IO8 GPIO_AF11_RF 833 #define GPIO_AF11_RF_IO9 GPIO_AF11_RF 834 #endif /* STM32WBA */ 835 /** 836 * @} 837 */ 838 839 /** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose 840 * @{ 841 */ 842 #if defined(STM32U5) 843 #define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI 844 #define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB 845 #endif /* STM32U5 */ 846 #if defined(STM32H5) 847 #define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1 848 #define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC 849 #define GTZC_PERIPH_USBFS GTZC_PERIPH_USB 850 #endif /* STM32H5 */ 851 #if defined(STM32H5) || defined(STM32U5) 852 #define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX 853 #define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX 854 #define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED 855 #define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED 856 #define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC 857 #define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC 858 #define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV 859 #define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV 860 #define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF 861 #define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON 862 #endif /* STM32H5 || STM32U5 */ 863 /** 864 * @} 865 */ 866 867 /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose 868 * @{ 869 */ 870 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED 871 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 872 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 873 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 874 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 875 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 876 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 877 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 878 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 879 880 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER 881 #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER 882 #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD 883 #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD 884 #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER 885 #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER 886 #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE 887 #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE 888 889 #if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) 890 #define HRTIMInterruptResquests HRTIMInterruptRequests 891 #endif /* STM32F3 || STM32G4 || STM32H7 */ 892 893 #if defined(STM32G4) 894 #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig 895 #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable 896 #define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable 897 #define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset 898 #define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A 899 #define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B 900 #define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL 901 #define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL 902 #endif /* STM32G4 */ 903 904 #if defined(STM32H7) 905 #define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 906 #define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 907 #define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 908 #define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 909 #define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 910 #define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 911 #define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 912 #define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 913 #define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 914 #define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 915 #define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 916 #define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 917 #define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 918 #define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 919 #define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 920 #define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 921 #define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 922 #define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 923 #define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 924 #define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 925 #define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 926 #define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 927 #define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 928 #define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 929 #define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 930 #define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 931 #define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 932 #define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 933 #define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 934 #define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 935 #define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 936 #define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 937 #define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 938 #define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 939 #define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 940 #define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 941 #define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 942 #define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 943 #define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 944 #define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 945 #define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 946 #define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 947 #define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 948 #define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 949 #define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 950 #define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 951 #define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 952 #define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 953 #define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 954 #define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 955 #define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 956 #define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 957 #define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 958 #define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 959 960 #define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 961 #define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 962 #define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 963 #define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 964 #define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 965 #define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 966 #define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 967 #define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 968 #define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 969 #define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 970 #define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 971 #define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 972 #define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 973 #define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 974 #define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 975 #define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 976 #define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 977 #define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 978 #define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 979 #define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 980 #define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 981 #define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 982 #define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 983 #define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 984 #define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 985 #define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 986 #define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 987 #define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 988 #define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 989 #define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 990 #define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 991 #define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 992 #define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 993 #define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 994 #define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 995 #define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 996 #define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 997 #define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 998 #define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 999 #define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 1000 #define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 1001 #define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 1002 #define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 1003 #define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 1004 #define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 1005 #define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 1006 #define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 1007 #define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 1008 #define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 1009 #define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 1010 #define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 1011 #define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 1012 #define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 1013 #define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 1014 #endif /* STM32H7 */ 1015 1016 #if defined(STM32F3) 1017 /** @brief Constants defining available sources associated to external events. 1018 */ 1019 #define HRTIM_EVENTSRC_1 (0x00000000U) 1020 #define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) 1021 #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) 1022 #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) 1023 1024 /** @brief Constants defining the DLL calibration periods (in micro seconds) 1025 */ 1026 #define HRTIM_CALIBRATIONRATE_7300 0x00000000U 1027 #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) 1028 #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) 1029 #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) 1030 #endif /* STM32F3 */ 1031 1032 /** 1033 * @} 1034 */ 1035 1036 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose 1037 * @{ 1038 */ 1039 #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE 1040 #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE 1041 #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE 1042 #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE 1043 #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE 1044 #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE 1045 #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE 1046 #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE 1047 #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \ 1048 defined(STM32L1) || defined(STM32F7) 1049 #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX 1050 #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX 1051 #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX 1052 #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX 1053 #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX 1054 #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX 1055 #endif 1056 /** 1057 * @} 1058 */ 1059 1060 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose 1061 * @{ 1062 */ 1063 #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE 1064 #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE 1065 1066 /** 1067 * @} 1068 */ 1069 1070 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose 1071 * @{ 1072 */ 1073 #define KR_KEY_RELOAD IWDG_KEY_RELOAD 1074 #define KR_KEY_ENABLE IWDG_KEY_ENABLE 1075 #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE 1076 #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE 1077 /** 1078 * @} 1079 */ 1080 1081 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose 1082 * @{ 1083 */ 1084 1085 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 1086 #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS 1087 #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS 1088 #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS 1089 1090 #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING 1091 #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING 1092 #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING 1093 1094 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 1095 #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS 1096 #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS 1097 #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS 1098 1099 /* The following 3 definition have also been present in a temporary version of lptim.h */ 1100 /* They need to be renamed also to the right name, just in case */ 1101 #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS 1102 #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS 1103 #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS 1104 1105 1106 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose 1107 * @{ 1108 */ 1109 #define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue 1110 /** 1111 * @} 1112 */ 1113 1114 #if defined(STM32U5) 1115 #define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF 1116 #define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF 1117 #define LPTIM_CHANNEL_ALL 0x00000000U 1118 #endif /* STM32U5 */ 1119 /** 1120 * @} 1121 */ 1122 1123 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose 1124 * @{ 1125 */ 1126 #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b 1127 #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b 1128 #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b 1129 #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b 1130 1131 #define NAND_AddressTypedef NAND_AddressTypeDef 1132 1133 #define __ARRAY_ADDRESS ARRAY_ADDRESS 1134 #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE 1135 #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE 1136 #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE 1137 #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE 1138 /** 1139 * @} 1140 */ 1141 1142 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose 1143 * @{ 1144 */ 1145 #define NOR_StatusTypedef HAL_NOR_StatusTypeDef 1146 #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS 1147 #define NOR_ONGOING HAL_NOR_STATUS_ONGOING 1148 #define NOR_ERROR HAL_NOR_STATUS_ERROR 1149 #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT 1150 1151 #define __NOR_WRITE NOR_WRITE 1152 #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT 1153 /** 1154 * @} 1155 */ 1156 1157 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose 1158 * @{ 1159 */ 1160 1161 #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 1162 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 1163 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 1164 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 1165 1166 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 1167 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 1168 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 1169 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 1170 1171 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 1172 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 1173 1174 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 1175 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 1176 1177 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 1178 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 1179 1180 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 1181 1182 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO 1183 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 1184 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 1185 1186 #if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5) 1187 #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID 1188 #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID 1189 #endif 1190 1191 #if defined(STM32L4) || defined(STM32L5) 1192 #define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER 1193 #elif defined(STM32G4) 1194 #define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED 1195 #endif 1196 1197 /** 1198 * @} 1199 */ 1200 1201 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose 1202 * @{ 1203 */ 1204 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS 1205 1206 #if defined(STM32H7) 1207 #define I2S_IT_TXE I2S_IT_TXP 1208 #define I2S_IT_RXNE I2S_IT_RXP 1209 1210 #define I2S_FLAG_TXE I2S_FLAG_TXP 1211 #define I2S_FLAG_RXNE I2S_FLAG_RXP 1212 #endif 1213 1214 #if defined(STM32F7) 1215 #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL 1216 #endif 1217 /** 1218 * @} 1219 */ 1220 1221 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose 1222 * @{ 1223 */ 1224 1225 /* Compact Flash-ATA registers description */ 1226 #define CF_DATA ATA_DATA 1227 #define CF_SECTOR_COUNT ATA_SECTOR_COUNT 1228 #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER 1229 #define CF_CYLINDER_LOW ATA_CYLINDER_LOW 1230 #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH 1231 #define CF_CARD_HEAD ATA_CARD_HEAD 1232 #define CF_STATUS_CMD ATA_STATUS_CMD 1233 #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE 1234 #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA 1235 1236 /* Compact Flash-ATA commands */ 1237 #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD 1238 #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD 1239 #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD 1240 #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD 1241 1242 #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef 1243 #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS 1244 #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING 1245 #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR 1246 #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT 1247 /** 1248 * @} 1249 */ 1250 1251 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose 1252 * @{ 1253 */ 1254 1255 #define FORMAT_BIN RTC_FORMAT_BIN 1256 #define FORMAT_BCD RTC_FORMAT_BCD 1257 1258 #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE 1259 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE 1260 #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 1261 #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 1262 1263 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 1264 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 1265 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE 1266 #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 1267 #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 1268 1269 #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT 1270 #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 1271 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 1272 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 1273 1274 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE 1275 #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 1276 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 1277 1278 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT 1279 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 1280 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 1281 1282 #if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) 1283 #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE 1284 #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM 1285 #endif /* STM32H5 || STM32H7RS || STM32N6 */ 1286 1287 #if defined(STM32WBA) 1288 #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE 1289 #define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2 1290 #define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK 1291 #define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE 1292 #define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH 1293 #define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM 1294 #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL 1295 #endif /* STM32WBA */ 1296 1297 #if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) 1298 #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE 1299 #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL 1300 #endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ 1301 1302 #if defined(STM32F7) 1303 #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK 1304 #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK 1305 #endif /* STM32F7 */ 1306 1307 #if defined(STM32H7) 1308 #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X 1309 #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT 1310 #endif /* STM32H7 */ 1311 1312 #if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) 1313 #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 1314 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 1315 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 1316 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP 1317 #endif /* STM32F7 || STM32H7 || STM32L0 */ 1318 1319 /** 1320 * @} 1321 */ 1322 1323 1324 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose 1325 * @{ 1326 */ 1327 #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE 1328 #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE 1329 1330 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE 1331 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE 1332 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE 1333 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE 1334 1335 #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE 1336 #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE 1337 1338 #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE 1339 #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE 1340 /** 1341 * @} 1342 */ 1343 1344 1345 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose 1346 * @{ 1347 */ 1348 #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE 1349 #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE 1350 #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE 1351 #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE 1352 #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE 1353 #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE 1354 #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE 1355 #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE 1356 #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE 1357 #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE 1358 #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN 1359 /** 1360 * @} 1361 */ 1362 1363 /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose 1364 * @{ 1365 */ 1366 #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE 1367 #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE 1368 1369 #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE 1370 #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE 1371 1372 #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE 1373 #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE 1374 1375 #if defined(STM32H7) 1376 1377 #define SPI_FLAG_TXE SPI_FLAG_TXP 1378 #define SPI_FLAG_RXNE SPI_FLAG_RXP 1379 1380 #define SPI_IT_TXE SPI_IT_TXP 1381 #define SPI_IT_RXNE SPI_IT_RXP 1382 1383 #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET 1384 #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET 1385 #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET 1386 #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET 1387 1388 #endif /* STM32H7 */ 1389 1390 /** 1391 * @} 1392 */ 1393 1394 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose 1395 * @{ 1396 */ 1397 #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK 1398 #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK 1399 1400 #define TIM_DMABase_CR1 TIM_DMABASE_CR1 1401 #define TIM_DMABase_CR2 TIM_DMABASE_CR2 1402 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR 1403 #define TIM_DMABase_DIER TIM_DMABASE_DIER 1404 #define TIM_DMABase_SR TIM_DMABASE_SR 1405 #define TIM_DMABase_EGR TIM_DMABASE_EGR 1406 #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 1407 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 1408 #define TIM_DMABase_CCER TIM_DMABASE_CCER 1409 #define TIM_DMABase_CNT TIM_DMABASE_CNT 1410 #define TIM_DMABase_PSC TIM_DMABASE_PSC 1411 #define TIM_DMABase_ARR TIM_DMABASE_ARR 1412 #define TIM_DMABase_RCR TIM_DMABASE_RCR 1413 #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 1414 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 1415 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 1416 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 1417 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR 1418 #define TIM_DMABase_DCR TIM_DMABASE_DCR 1419 #define TIM_DMABase_DMAR TIM_DMABASE_DMAR 1420 #define TIM_DMABase_OR1 TIM_DMABASE_OR1 1421 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 1422 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 1423 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 1424 #define TIM_DMABase_OR2 TIM_DMABASE_OR2 1425 #define TIM_DMABase_OR3 TIM_DMABASE_OR3 1426 #define TIM_DMABase_OR TIM_DMABASE_OR 1427 1428 #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE 1429 #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 1430 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 1431 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 1432 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 1433 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM 1434 #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER 1435 #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK 1436 #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 1437 1438 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER 1439 #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS 1440 #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS 1441 #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS 1442 #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS 1443 #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS 1444 #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS 1445 #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS 1446 #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS 1447 #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS 1448 #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS 1449 #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS 1450 #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS 1451 #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS 1452 #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS 1453 #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS 1454 #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS 1455 #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS 1456 1457 #if defined(STM32L0) 1458 #define TIM22_TI1_GPIO1 TIM22_TI1_GPIO 1459 #define TIM22_TI1_GPIO2 TIM22_TI1_GPIO 1460 #endif 1461 1462 #if defined(STM32F3) 1463 #define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE 1464 #endif 1465 1466 #if defined(STM32H7) 1467 #define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 1468 #define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 1469 #define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 1470 #define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 1471 #define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 1472 #define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 1473 #define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 1474 #define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 1475 #define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 1476 #define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 1477 #define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 1478 #define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 1479 #define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 1480 #define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 1481 #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 1482 #endif 1483 1484 #if defined(STM32U5) 1485 #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS 1486 #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK 1487 #endif 1488 /** 1489 * @} 1490 */ 1491 1492 /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose 1493 * @{ 1494 */ 1495 #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING 1496 #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING 1497 /** 1498 * @} 1499 */ 1500 1501 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose 1502 * @{ 1503 */ 1504 #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 1505 #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 1506 #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 1507 #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 1508 1509 #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE 1510 #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE 1511 1512 #define __DIV_SAMPLING16 UART_DIV_SAMPLING16 1513 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 1514 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 1515 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 1516 1517 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8 1518 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 1519 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 1520 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 1521 1522 #define __DIV_LPUART UART_DIV_LPUART 1523 1524 #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE 1525 #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK 1526 1527 /** 1528 * @} 1529 */ 1530 1531 1532 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose 1533 * @{ 1534 */ 1535 1536 #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE 1537 #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE 1538 1539 #define USARTNACK_ENABLED USART_NACK_ENABLE 1540 #define USARTNACK_DISABLED USART_NACK_DISABLE 1541 /** 1542 * @} 1543 */ 1544 1545 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose 1546 * @{ 1547 */ 1548 #define CFR_BASE WWDG_CFR_BASE 1549 1550 /** 1551 * @} 1552 */ 1553 1554 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose 1555 * @{ 1556 */ 1557 #define CAN_FilterFIFO0 CAN_FILTER_FIFO0 1558 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1 1559 #define CAN_IT_RQCP0 CAN_IT_TME 1560 #define CAN_IT_RQCP1 CAN_IT_TME 1561 #define CAN_IT_RQCP2 CAN_IT_TME 1562 #define INAK_TIMEOUT CAN_TIMEOUT_VALUE 1563 #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE 1564 #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) 1565 #define CAN_TXSTATUS_OK ((uint8_t)0x01U) 1566 #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) 1567 1568 /** 1569 * @} 1570 */ 1571 1572 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose 1573 * @{ 1574 */ 1575 1576 #define VLAN_TAG ETH_VLAN_TAG 1577 #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD 1578 #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD 1579 #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD 1580 #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK 1581 #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK 1582 #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK 1583 #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK 1584 1585 #define ETH_MMCCR 0x00000100U 1586 #define ETH_MMCRIR 0x00000104U 1587 #define ETH_MMCTIR 0x00000108U 1588 #define ETH_MMCRIMR 0x0000010CU 1589 #define ETH_MMCTIMR 0x00000110U 1590 #define ETH_MMCTGFSCCR 0x0000014CU 1591 #define ETH_MMCTGFMSCCR 0x00000150U 1592 #define ETH_MMCTGFCR 0x00000168U 1593 #define ETH_MMCRFCECR 0x00000194U 1594 #define ETH_MMCRFAECR 0x00000198U 1595 #define ETH_MMCRGUFCR 0x000001C4U 1596 1597 #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ 1598 #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ 1599 #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ 1600 #define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ 1601 #define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to 1602 the MAC transmitter) */ 1603 #define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from 1604 MAC transmitter */ 1605 #define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus 1606 or flushing the TxFIFO */ 1607 #define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ 1608 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ 1609 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status 1610 of previous frame or IFG/backoff period to be over */ 1611 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and 1612 transmitting a Pause control frame (in full duplex mode) */ 1613 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input 1614 frame for transmission */ 1615 #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ 1616 #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ 1617 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control 1618 de-activate threshold */ 1619 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control 1620 activate threshold */ 1621 #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ 1622 #if defined(STM32F1) 1623 #else 1624 #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ 1625 #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ 1626 #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status 1627 (or time-stamp) */ 1628 #endif 1629 #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and 1630 status */ 1631 #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ 1632 #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ 1633 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ 1634 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ 1635 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ 1636 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ 1637 1638 #define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */ 1639 1640 /** 1641 * @} 1642 */ 1643 1644 /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose 1645 * @{ 1646 */ 1647 #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR 1648 #define DCMI_IT_OVF DCMI_IT_OVR 1649 #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI 1650 #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI 1651 1652 #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop 1653 #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop 1654 #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop 1655 1656 /** 1657 * @} 1658 */ 1659 1660 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ 1661 || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ 1662 || defined(STM32H7) 1663 /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose 1664 * @{ 1665 */ 1666 #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 1667 #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 1668 #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 1669 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 1670 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 1671 1672 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 1673 #define CM_RGB888 DMA2D_INPUT_RGB888 1674 #define CM_RGB565 DMA2D_INPUT_RGB565 1675 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 1676 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 1677 #define CM_L8 DMA2D_INPUT_L8 1678 #define CM_AL44 DMA2D_INPUT_AL44 1679 #define CM_AL88 DMA2D_INPUT_AL88 1680 #define CM_L4 DMA2D_INPUT_L4 1681 #define CM_A8 DMA2D_INPUT_A8 1682 #define CM_A4 DMA2D_INPUT_A4 1683 /** 1684 * @} 1685 */ 1686 #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ 1687 1688 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ 1689 || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ 1690 || defined(STM32H7) || defined(STM32U5) 1691 /** @defgroup DMA2D_Aliases DMA2D API Aliases 1692 * @{ 1693 */ 1694 #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort 1695 for compatibility with legacy code */ 1696 /** 1697 * @} 1698 */ 1699 1700 #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ 1701 1702 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose 1703 * @{ 1704 */ 1705 1706 /** 1707 * @} 1708 */ 1709 1710 /* Exported functions --------------------------------------------------------*/ 1711 1712 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose 1713 * @{ 1714 */ 1715 #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback 1716 /** 1717 * @} 1718 */ 1719 1720 /** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose 1721 * @{ 1722 */ 1723 1724 #if defined(STM32U5) 1725 #define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr 1726 #define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT 1727 #endif /* STM32U5 */ 1728 1729 /** 1730 * @} 1731 */ 1732 1733 #if !defined(STM32F2) 1734 /** @defgroup HASH_alias HASH API alias 1735 * @{ 1736 */ 1737 #define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ 1738 /** 1739 * 1740 * @} 1741 */ 1742 #endif /* STM32F2 */ 1743 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose 1744 * @{ 1745 */ 1746 #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef 1747 #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef 1748 #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish 1749 #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish 1750 #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish 1751 #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish 1752 1753 /*HASH Algorithm Selection*/ 1754 1755 #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 1756 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 1757 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 1758 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 1759 1760 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH 1761 #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC 1762 1763 #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY 1764 #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY 1765 1766 #if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) 1767 1768 #define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt 1769 #define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End 1770 #define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT 1771 #define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT 1772 1773 #define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt 1774 #define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End 1775 #define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT 1776 #define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT 1777 1778 #define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt 1779 #define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End 1780 #define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT 1781 #define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT 1782 1783 #define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt 1784 #define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End 1785 #define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT 1786 #define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT 1787 1788 #endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ 1789 /** 1790 * @} 1791 */ 1792 1793 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose 1794 * @{ 1795 */ 1796 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode 1797 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode 1798 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode 1799 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode 1800 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode 1801 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode 1802 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ 1803 )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \ 1804 HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) 1805 #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect 1806 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) 1807 #if defined(STM32L0) 1808 #else 1809 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) 1810 #endif 1811 #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) 1812 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ 1813 )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \ 1814 HAL_ADCEx_DisableVREFINTTempSensor()) 1815 #if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \ 1816 defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) 1817 #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode 1818 #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode 1819 #define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode 1820 #define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode 1821 #endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ 1822 1823 /** 1824 * @} 1825 */ 1826 1827 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose 1828 * @{ 1829 */ 1830 #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram 1831 #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown 1832 #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown 1833 #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock 1834 #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock 1835 #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase 1836 #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program 1837 1838 /** 1839 * @} 1840 */ 1841 1842 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose 1843 * @{ 1844 */ 1845 #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter 1846 #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter 1847 #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter 1848 #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter 1849 1850 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ 1851 HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ 1852 HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) 1853 1854 #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \ 1855 defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \ 1856 defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) 1857 #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT 1858 #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT 1859 #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT 1860 #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT 1861 #endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || 1862 STM32L4 || STM32L5 || STM32G4 || STM32L1 */ 1863 #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \ 1864 defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) 1865 #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA 1866 #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA 1867 #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA 1868 #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA 1869 #endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ 1870 1871 #if defined(STM32F4) 1872 #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT 1873 #define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT 1874 #define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT 1875 #define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT 1876 #define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA 1877 #define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA 1878 #define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA 1879 #define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA 1880 #endif /* STM32F4 */ 1881 /** 1882 * @} 1883 */ 1884 1885 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose 1886 * @{ 1887 */ 1888 1889 #if defined(STM32G0) 1890 #define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD 1891 #define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD 1892 #define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD 1893 #define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler 1894 #endif 1895 #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD 1896 #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg 1897 #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown 1898 #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor 1899 #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg 1900 #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown 1901 #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor 1902 #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler 1903 #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD 1904 #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler 1905 #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback 1906 #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive 1907 #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive 1908 #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC 1909 #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC 1910 #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM 1911 1912 #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL 1913 #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING 1914 #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING 1915 #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING 1916 #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING 1917 #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING 1918 #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING 1919 1920 #define CR_OFFSET_BB PWR_CR_OFFSET_BB 1921 #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB 1922 #define PMODE_BIT_NUMBER VOS_BIT_NUMBER 1923 #define CR_PMODE_BB CR_VOS_BB 1924 1925 #define DBP_BitNumber DBP_BIT_NUMBER 1926 #define PVDE_BitNumber PVDE_BIT_NUMBER 1927 #define PMODE_BitNumber PMODE_BIT_NUMBER 1928 #define EWUP_BitNumber EWUP_BIT_NUMBER 1929 #define FPDS_BitNumber FPDS_BIT_NUMBER 1930 #define ODEN_BitNumber ODEN_BIT_NUMBER 1931 #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER 1932 #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER 1933 #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER 1934 #define BRE_BitNumber BRE_BIT_NUMBER 1935 1936 #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL 1937 1938 #if defined (STM32U5) 1939 #define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP 1940 #define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP 1941 #define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP 1942 #define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP 1943 #define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP 1944 #define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP 1945 #define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP 1946 #define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP 1947 #define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP 1948 #define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP 1949 #define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP 1950 #define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP 1951 #define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP 1952 1953 #define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP 1954 #define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP 1955 #define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP 1956 1957 #define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP 1958 #define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP 1959 #define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP 1960 #define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP 1961 #define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP 1962 #define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP 1963 #define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP 1964 #define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP 1965 #define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP 1966 #define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP 1967 #define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP 1968 #define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP 1969 #define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP 1970 #define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP 1971 1972 #define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP 1973 1974 #define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP 1975 #define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP 1976 #define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP 1977 #define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP 1978 #define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP 1979 #define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP 1980 #define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP 1981 #define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP 1982 #define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP 1983 #define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP 1984 #define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP 1985 #define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP 1986 #define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP 1987 #define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP 1988 1989 #define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP 1990 #define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP 1991 #define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP 1992 #define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP 1993 #define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP 1994 #define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP 1995 #define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP 1996 #define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP 1997 #define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP 1998 1999 2000 #define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP 2001 #define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP 2002 #define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP 2003 #define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP 2004 #define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP 2005 #define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP 2006 #define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP 2007 #define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP 2008 #define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP 2009 2010 2011 #define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY 2012 #define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY 2013 #define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY 2014 2015 #define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN 2016 #define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN 2017 #define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN 2018 #define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN 2019 #define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN 2020 #define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN 2021 2022 #define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK 2023 #endif 2024 2025 /** 2026 * @} 2027 */ 2028 2029 /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose 2030 * @{ 2031 */ 2032 #if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) 2033 #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey 2034 #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock 2035 #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock 2036 #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets 2037 #endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ 2038 2039 /** 2040 * @} 2041 */ 2042 2043 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose 2044 * @{ 2045 */ 2046 #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT 2047 #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback 2048 #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback 2049 /** 2050 * @} 2051 */ 2052 2053 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose 2054 * @{ 2055 */ 2056 #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo 2057 /** 2058 * @} 2059 */ 2060 2061 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose 2062 * @{ 2063 */ 2064 #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt 2065 #define HAL_TIM_DMAError TIM_DMAError 2066 #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt 2067 #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt 2068 #if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \ 2069 defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) 2070 #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro 2071 #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT 2072 #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback 2073 #define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent 2074 #define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT 2075 #define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA 2076 #endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ 2077 /** 2078 * @} 2079 */ 2080 2081 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose 2082 * @{ 2083 */ 2084 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback 2085 /** 2086 * @} 2087 */ 2088 2089 /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose 2090 * @{ 2091 */ 2092 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback 2093 #define HAL_LTDC_Relaod HAL_LTDC_Reload 2094 #define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig 2095 #define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig 2096 /** 2097 * @} 2098 */ 2099 2100 2101 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose 2102 * @{ 2103 */ 2104 2105 /** 2106 * @} 2107 */ 2108 2109 /* Exported macros ------------------------------------------------------------*/ 2110 2111 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose 2112 * @{ 2113 */ 2114 #define AES_IT_CC CRYP_IT_CC 2115 #define AES_IT_ERR CRYP_IT_ERR 2116 #define AES_FLAG_CCF CRYP_FLAG_CCF 2117 /** 2118 * @} 2119 */ 2120 2121 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose 2122 * @{ 2123 */ 2124 #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE 2125 #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH 2126 #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH 2127 #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM 2128 #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC 2129 #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM 2130 #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC 2131 #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI 2132 #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK 2133 #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG 2134 #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG 2135 #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE 2136 #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE 2137 #define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE 2138 2139 #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY 2140 #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 2141 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS 2142 #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER 2143 #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER 2144 2145 /** 2146 * @} 2147 */ 2148 2149 2150 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose 2151 * @{ 2152 */ 2153 #define __ADC_ENABLE __HAL_ADC_ENABLE 2154 #define __ADC_DISABLE __HAL_ADC_DISABLE 2155 #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS 2156 #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS 2157 #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE 2158 #define __ADC_IS_ENABLED ADC_IS_ENABLE 2159 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR 2160 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED 2161 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED 2162 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR 2163 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED 2164 #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING 2165 #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE 2166 2167 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION 2168 #define __HAL_ADC_JSQR_RK ADC_JSQR_RK 2169 #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT 2170 #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR 2171 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION 2172 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE 2173 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS 2174 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS 2175 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM 2176 #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT 2177 #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS 2178 #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN 2179 #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ 2180 #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET 2181 #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET 2182 #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL 2183 #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL 2184 #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET 2185 #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET 2186 #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD 2187 2188 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION 2189 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION 2190 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION 2191 #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER 2192 #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI 2193 #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 2194 #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 2195 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER 2196 #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER 2197 #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE 2198 2199 #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT 2200 #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT 2201 #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL 2202 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM 2203 #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET 2204 #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE 2205 #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE 2206 #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER 2207 2208 #define __HAL_ADC_SQR1 ADC_SQR1 2209 #define __HAL_ADC_SMPR1 ADC_SMPR1 2210 #define __HAL_ADC_SMPR2 ADC_SMPR2 2211 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK 2212 #define __HAL_ADC_SQR2_RK ADC_SQR2_RK 2213 #define __HAL_ADC_SQR1_RK ADC_SQR1_RK 2214 #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS 2215 #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS 2216 #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV 2217 #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection 2218 #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq 2219 #define __HAL_ADC_JSQR ADC_JSQR 2220 2221 #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL 2222 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS 2223 #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF 2224 #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT 2225 #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS 2226 #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN 2227 #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR 2228 #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ 2229 2230 /** 2231 * @} 2232 */ 2233 2234 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose 2235 * @{ 2236 */ 2237 #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT 2238 #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT 2239 #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT 2240 #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE 2241 2242 /** 2243 * @} 2244 */ 2245 2246 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose 2247 * @{ 2248 */ 2249 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 2250 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 2251 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 2252 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 2253 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 2254 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 2255 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 2256 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 2257 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 2258 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 2259 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 2260 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 2261 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 2262 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 2263 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 2264 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 2265 2266 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 2267 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 2268 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 2269 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 2270 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 2271 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 2272 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 2273 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 2274 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 2275 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 2276 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 2277 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 2278 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 2279 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 2280 2281 2282 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 2283 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 2284 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 2285 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 2286 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 2287 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 2288 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC 2289 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC 2290 #if defined(STM32H7) 2291 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 2292 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 2293 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 2294 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 2295 #else 2296 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG 2297 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG 2298 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG 2299 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG 2300 #endif /* STM32H7 */ 2301 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT 2302 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT 2303 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT 2304 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT 2305 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT 2306 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT 2307 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 2308 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 2309 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 2310 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 2311 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 2312 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 2313 2314 /** 2315 * @} 2316 */ 2317 2318 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose 2319 * @{ 2320 */ 2321 #if defined(STM32F3) 2322 #define COMP_START __HAL_COMP_ENABLE 2323 #define COMP_STOP __HAL_COMP_DISABLE 2324 #define COMP_LOCK __HAL_COMP_LOCK 2325 2326 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \ 2327 defined(STM32F334x8) || defined(STM32F328xx) 2328 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 2329 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 2330 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 2331 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 2332 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 2333 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 2334 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 2335 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 2336 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 2337 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 2338 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 2339 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 2340 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2341 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2342 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 2343 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2344 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2345 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 2346 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2347 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2348 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 2349 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2350 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2351 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 2352 #endif 2353 #if defined(STM32F302xE) || defined(STM32F302xC) 2354 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2355 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 2356 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 2357 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 2358 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2359 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 2360 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 2361 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 2362 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2363 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 2364 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 2365 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 2366 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2367 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 2368 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 2369 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 2370 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2371 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2372 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2373 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 2374 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2375 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2376 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2377 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 2378 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2379 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2380 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2381 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 2382 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2383 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2384 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2385 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 2386 #endif 2387 #if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) 2388 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2389 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 2390 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ 2391 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 2392 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ 2393 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ 2394 __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) 2395 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2396 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 2397 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ 2398 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 2399 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ 2400 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ 2401 __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) 2402 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2403 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 2404 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ 2405 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 2406 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ 2407 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ 2408 __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) 2409 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2410 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 2411 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ 2412 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 2413 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ 2414 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ 2415 __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) 2416 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2417 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2418 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ 2419 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2420 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ 2421 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ 2422 __HAL_COMP_COMP7_EXTI_ENABLE_IT()) 2423 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2424 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2425 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ 2426 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2427 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ 2428 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ 2429 __HAL_COMP_COMP7_EXTI_DISABLE_IT()) 2430 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2431 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2432 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ 2433 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2434 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ 2435 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ 2436 __HAL_COMP_COMP7_EXTI_GET_FLAG()) 2437 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2438 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2439 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ 2440 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2441 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ 2442 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ 2443 __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) 2444 #endif 2445 #if defined(STM32F373xC) ||defined(STM32F378xx) 2446 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2447 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 2448 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2449 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 2450 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2451 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 2452 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2453 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 2454 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2455 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 2456 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2457 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 2458 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2459 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 2460 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2461 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 2462 #endif 2463 #else 2464 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2465 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 2466 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2467 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 2468 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2469 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 2470 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2471 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 2472 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2473 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 2474 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2475 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 2476 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2477 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 2478 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2479 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 2480 #endif 2481 2482 #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE 2483 2484 #if defined(STM32L0) || defined(STM32L4) 2485 /* Note: On these STM32 families, the only argument of this macro */ 2486 /* is COMP_FLAG_LOCK. */ 2487 /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ 2488 /* argument. */ 2489 #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) 2490 #endif 2491 /** 2492 * @} 2493 */ 2494 2495 #if defined(STM32L0) || defined(STM32L4) 2496 /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose 2497 * @{ 2498 */ 2499 #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is 2500 done into HAL_COMP_Init() */ 2501 #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is 2502 done into HAL_COMP_Init() */ 2503 /** 2504 * @} 2505 */ 2506 #endif 2507 2508 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose 2509 * @{ 2510 */ 2511 2512 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ 2513 ((WAVE) == DAC_WAVE_NOISE)|| \ 2514 ((WAVE) == DAC_WAVE_TRIANGLE)) 2515 2516 /** 2517 * @} 2518 */ 2519 2520 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose 2521 * @{ 2522 */ 2523 2524 #define IS_WRPAREA IS_OB_WRPAREA 2525 #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM 2526 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM 2527 #define IS_TYPEERASE IS_FLASH_TYPEERASE 2528 #define IS_NBSECTORS IS_FLASH_NBSECTORS 2529 #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE 2530 2531 /** 2532 * @} 2533 */ 2534 2535 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose 2536 * @{ 2537 */ 2538 2539 #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 2540 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START 2541 #if defined(STM32F1) 2542 #define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE 2543 #else 2544 #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE 2545 #endif /* STM32F1 */ 2546 #define __HAL_I2C_RISE_TIME I2C_RISE_TIME 2547 #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD 2548 #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST 2549 #define __HAL_I2C_SPEED I2C_SPEED 2550 #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE 2551 #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ 2552 #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS 2553 #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE 2554 #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ 2555 #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB 2556 #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB 2557 #define __HAL_I2C_FREQRANGE I2C_FREQRANGE 2558 /** 2559 * @} 2560 */ 2561 2562 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose 2563 * @{ 2564 */ 2565 2566 #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE 2567 #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT 2568 2569 #if defined(STM32H7) 2570 #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG 2571 #endif 2572 2573 /** 2574 * @} 2575 */ 2576 2577 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose 2578 * @{ 2579 */ 2580 2581 #define __IRDA_DISABLE __HAL_IRDA_DISABLE 2582 #define __IRDA_ENABLE __HAL_IRDA_ENABLE 2583 2584 #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 2585 #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 2586 #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 2587 #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 2588 2589 #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE 2590 2591 2592 /** 2593 * @} 2594 */ 2595 2596 2597 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose 2598 * @{ 2599 */ 2600 #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS 2601 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS 2602 /** 2603 * @} 2604 */ 2605 2606 2607 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose 2608 * @{ 2609 */ 2610 2611 #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT 2612 #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT 2613 #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE 2614 2615 /** 2616 * @} 2617 */ 2618 2619 2620 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose 2621 * @{ 2622 */ 2623 #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD 2624 #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX 2625 #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX 2626 #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX 2627 #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX 2628 #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L 2629 #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H 2630 #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM 2631 #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES 2632 #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX 2633 #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT 2634 #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION 2635 #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET 2636 2637 /** 2638 * @} 2639 */ 2640 2641 2642 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose 2643 * @{ 2644 */ 2645 #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 2646 #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 2647 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 2648 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2649 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 2650 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2651 #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE 2652 #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE 2653 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE 2654 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE 2655 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE 2656 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE 2657 #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine 2658 #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine 2659 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig 2660 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig 2661 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ 2662 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ 2663 } while(0) 2664 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 2665 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 2666 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 2667 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2668 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 2669 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2670 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2671 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2672 #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \ 2673 HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \ 2674 } while(0) 2675 #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \ 2676 HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \ 2677 } while(0) 2678 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention 2679 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention 2680 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 2681 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 2682 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE 2683 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE 2684 #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB 2685 #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB 2686 2687 #if defined (STM32F4) 2688 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() 2689 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() 2690 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() 2691 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() 2692 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() 2693 #else 2694 #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG 2695 #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT 2696 #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT 2697 #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT 2698 #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG 2699 #endif /* STM32F4 */ 2700 /** 2701 * @} 2702 */ 2703 2704 2705 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose 2706 * @{ 2707 */ 2708 2709 #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI 2710 #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI 2711 2712 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback 2713 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \ 2714 HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) 2715 2716 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE 2717 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE 2718 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE 2719 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE 2720 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET 2721 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET 2722 #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE 2723 #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE 2724 #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET 2725 #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET 2726 #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE 2727 #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE 2728 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE 2729 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE 2730 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET 2731 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET 2732 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE 2733 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE 2734 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET 2735 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET 2736 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE 2737 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE 2738 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE 2739 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE 2740 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET 2741 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET 2742 #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE 2743 #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE 2744 #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE 2745 #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE 2746 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET 2747 #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET 2748 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE 2749 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE 2750 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET 2751 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET 2752 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET 2753 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET 2754 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET 2755 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET 2756 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET 2757 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET 2758 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET 2759 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET 2760 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET 2761 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET 2762 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET 2763 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET 2764 #if defined(STM32C0) 2765 #define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET 2766 #define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET 2767 #define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET 2768 #define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET 2769 #endif /* STM32C0 */ 2770 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE 2771 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE 2772 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET 2773 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET 2774 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 2775 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 2776 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE 2777 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE 2778 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 2779 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 2780 #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 2781 #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 2782 #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 2783 #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 2784 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE 2785 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE 2786 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET 2787 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET 2788 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE 2789 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE 2790 #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE 2791 #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE 2792 #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET 2793 #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET 2794 #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE 2795 #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE 2796 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET 2797 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET 2798 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE 2799 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE 2800 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE 2801 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE 2802 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET 2803 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET 2804 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE 2805 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE 2806 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET 2807 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET 2808 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE 2809 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE 2810 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE 2811 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE 2812 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET 2813 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET 2814 #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE 2815 #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE 2816 #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET 2817 #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET 2818 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE 2819 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE 2820 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE 2821 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE 2822 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET 2823 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET 2824 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE 2825 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE 2826 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE 2827 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE 2828 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET 2829 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET 2830 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE 2831 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE 2832 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE 2833 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE 2834 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET 2835 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET 2836 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE 2837 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE 2838 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET 2839 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET 2840 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE 2841 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE 2842 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE 2843 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE 2844 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE 2845 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE 2846 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE 2847 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE 2848 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE 2849 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE 2850 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET 2851 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET 2852 #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE 2853 #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE 2854 #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET 2855 #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET 2856 #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE 2857 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE 2858 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE 2859 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE 2860 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE 2861 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE 2862 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET 2863 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET 2864 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE 2865 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE 2866 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE 2867 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE 2868 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE 2869 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE 2870 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET 2871 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET 2872 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE 2873 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE 2874 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE 2875 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE 2876 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET 2877 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET 2878 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE 2879 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE 2880 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE 2881 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE 2882 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET 2883 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET 2884 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE 2885 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE 2886 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE 2887 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE 2888 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET 2889 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET 2890 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE 2891 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE 2892 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE 2893 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE 2894 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET 2895 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET 2896 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE 2897 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE 2898 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE 2899 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE 2900 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET 2901 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET 2902 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE 2903 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE 2904 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE 2905 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE 2906 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET 2907 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET 2908 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE 2909 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE 2910 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE 2911 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE 2912 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET 2913 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET 2914 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE 2915 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE 2916 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE 2917 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE 2918 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET 2919 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET 2920 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE 2921 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE 2922 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE 2923 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE 2924 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET 2925 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET 2926 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE 2927 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE 2928 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE 2929 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE 2930 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET 2931 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET 2932 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE 2933 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE 2934 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE 2935 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE 2936 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET 2937 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET 2938 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE 2939 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE 2940 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE 2941 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE 2942 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET 2943 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET 2944 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE 2945 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE 2946 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE 2947 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE 2948 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET 2949 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET 2950 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE 2951 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE 2952 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE 2953 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE 2954 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET 2955 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET 2956 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE 2957 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE 2958 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE 2959 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE 2960 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET 2961 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET 2962 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE 2963 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE 2964 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE 2965 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE 2966 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET 2967 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET 2968 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE 2969 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE 2970 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE 2971 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE 2972 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET 2973 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET 2974 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE 2975 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE 2976 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE 2977 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE 2978 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET 2979 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET 2980 2981 #if defined(STM32WB) 2982 #define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE 2983 #define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE 2984 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE 2985 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE 2986 #define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET 2987 #define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET 2988 #define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED 2989 #define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED 2990 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED 2991 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED 2992 #define QSPI_IRQHandler QUADSPI_IRQHandler 2993 #endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ 2994 2995 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE 2996 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE 2997 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE 2998 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE 2999 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET 3000 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET 3001 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE 3002 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE 3003 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE 3004 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE 3005 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET 3006 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET 3007 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE 3008 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE 3009 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE 3010 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE 3011 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET 3012 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET 3013 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 3014 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 3015 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE 3016 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE 3017 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE 3018 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE 3019 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET 3020 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET 3021 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE 3022 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE 3023 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE 3024 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE 3025 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET 3026 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET 3027 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE 3028 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE 3029 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE 3030 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE 3031 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET 3032 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET 3033 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE 3034 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE 3035 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE 3036 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE 3037 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET 3038 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET 3039 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE 3040 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE 3041 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE 3042 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE 3043 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE 3044 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE 3045 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE 3046 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE 3047 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE 3048 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE 3049 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET 3050 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET 3051 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE 3052 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE 3053 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE 3054 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE 3055 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET 3056 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET 3057 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE 3058 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE 3059 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE 3060 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE 3061 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET 3062 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET 3063 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE 3064 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE 3065 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET 3066 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET 3067 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE 3068 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE 3069 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET 3070 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET 3071 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE 3072 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE 3073 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET 3074 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET 3075 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE 3076 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE 3077 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET 3078 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET 3079 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE 3080 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE 3081 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET 3082 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET 3083 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE 3084 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE 3085 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE 3086 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE 3087 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET 3088 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET 3089 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE 3090 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE 3091 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE 3092 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE 3093 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET 3094 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET 3095 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE 3096 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE 3097 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE 3098 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE 3099 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET 3100 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET 3101 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE 3102 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE 3103 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE 3104 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE 3105 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET 3106 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET 3107 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE 3108 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE 3109 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE 3110 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE 3111 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET 3112 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET 3113 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE 3114 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE 3115 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE 3116 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE 3117 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET 3118 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET 3119 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE 3120 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE 3121 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE 3122 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE 3123 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET 3124 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET 3125 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE 3126 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE 3127 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE 3128 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE 3129 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET 3130 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET 3131 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE 3132 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE 3133 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE 3134 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE 3135 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET 3136 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET 3137 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE 3138 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE 3139 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE 3140 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE 3141 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET 3142 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET 3143 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE 3144 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE 3145 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET 3146 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET 3147 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE 3148 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE 3149 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE 3150 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE 3151 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET 3152 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET 3153 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE 3154 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE 3155 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE 3156 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE 3157 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET 3158 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET 3159 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE 3160 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE 3161 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE 3162 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE 3163 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET 3164 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET 3165 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE 3166 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE 3167 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE 3168 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE 3169 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET 3170 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET 3171 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE 3172 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE 3173 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE 3174 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE 3175 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET 3176 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET 3177 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE 3178 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE 3179 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE 3180 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE 3181 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET 3182 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET 3183 #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE 3184 #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE 3185 #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE 3186 #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE 3187 #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET 3188 #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET 3189 #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE 3190 #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE 3191 #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE 3192 #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE 3193 #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET 3194 #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET 3195 #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE 3196 #define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE 3197 #define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET 3198 #define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET 3199 #define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE 3200 #define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE 3201 #define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET 3202 #define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET 3203 #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE 3204 #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE 3205 #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET 3206 #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE 3207 #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE 3208 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE 3209 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE 3210 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET 3211 3212 #if defined(STM32H7) 3213 #define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE 3214 #define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE 3215 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE 3216 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE 3217 3218 #define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ 3219 #define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ 3220 3221 3222 #define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED 3223 #define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED 3224 #define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 3225 #define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 3226 #define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 3227 #define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 3228 #define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 3229 #endif 3230 3231 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE 3232 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE 3233 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE 3234 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE 3235 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET 3236 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET 3237 3238 #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE 3239 #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE 3240 #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET 3241 #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET 3242 #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE 3243 #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE 3244 #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE 3245 #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE 3246 #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET 3247 #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET 3248 #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE 3249 #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE 3250 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE 3251 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE 3252 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE 3253 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE 3254 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET 3255 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET 3256 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE 3257 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE 3258 3259 #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 3260 #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 3261 #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE 3262 #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE 3263 #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE 3264 #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE 3265 #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE 3266 #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE 3267 #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE 3268 #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE 3269 #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE 3270 #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE 3271 #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE 3272 #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE 3273 #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE 3274 #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE 3275 #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE 3276 #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE 3277 #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE 3278 #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET 3279 #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET 3280 #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE 3281 #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE 3282 #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE 3283 #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE 3284 #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE 3285 #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET 3286 #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET 3287 #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE 3288 #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE 3289 #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE 3290 #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE 3291 #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET 3292 #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET 3293 #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE 3294 #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE 3295 #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE 3296 #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE 3297 #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET 3298 #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET 3299 #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE 3300 #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE 3301 #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE 3302 #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE 3303 #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE 3304 #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE 3305 #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE 3306 #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE 3307 #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE 3308 #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE 3309 #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE 3310 #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE 3311 #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE 3312 #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE 3313 #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE 3314 #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE 3315 #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE 3316 #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE 3317 #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE 3318 #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE 3319 #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE 3320 #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET 3321 #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET 3322 #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE 3323 #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE 3324 #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE 3325 #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE 3326 #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET 3327 #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET 3328 #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE 3329 #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE 3330 #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE 3331 #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE 3332 #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET 3333 #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET 3334 #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE 3335 #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE 3336 #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE 3337 #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE 3338 #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET 3339 #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET 3340 #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE 3341 #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE 3342 #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE 3343 #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE 3344 #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET 3345 #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE 3346 #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE 3347 #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE 3348 #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE 3349 #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE 3350 #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE 3351 #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET 3352 #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET 3353 #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE 3354 #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE 3355 #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE 3356 #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE 3357 #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET 3358 #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET 3359 #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE 3360 #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE 3361 #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE 3362 #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE 3363 #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET 3364 #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET 3365 #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE 3366 #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE 3367 #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 3368 #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 3369 #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 3370 #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 3371 #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 3372 #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 3373 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 3374 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 3375 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED 3376 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED 3377 #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 3378 #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 3379 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 3380 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 3381 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED 3382 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED 3383 #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE 3384 #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE 3385 #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE 3386 #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE 3387 #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE 3388 #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE 3389 #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE 3390 #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE 3391 #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE 3392 #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET 3393 #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET 3394 #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE 3395 #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE 3396 #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 3397 #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 3398 #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 3399 #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 3400 #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE 3401 #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE 3402 #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET 3403 #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET 3404 #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE 3405 #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE 3406 3407 /* alias define maintained for legacy */ 3408 #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 3409 #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 3410 3411 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE 3412 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE 3413 #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE 3414 #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE 3415 #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE 3416 #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE 3417 #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE 3418 #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE 3419 #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE 3420 #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE 3421 #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE 3422 #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE 3423 #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE 3424 #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE 3425 #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE 3426 #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE 3427 #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE 3428 #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE 3429 #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE 3430 #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE 3431 3432 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET 3433 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET 3434 #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET 3435 #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET 3436 #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET 3437 #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET 3438 #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET 3439 #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET 3440 #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET 3441 #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET 3442 #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET 3443 #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET 3444 #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET 3445 #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET 3446 #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET 3447 #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET 3448 #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET 3449 #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET 3450 #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET 3451 #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET 3452 3453 #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED 3454 #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED 3455 #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED 3456 #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED 3457 #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED 3458 #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED 3459 #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED 3460 #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED 3461 #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED 3462 #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED 3463 #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED 3464 #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED 3465 #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED 3466 #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED 3467 #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED 3468 #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED 3469 #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED 3470 #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED 3471 #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED 3472 #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED 3473 #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED 3474 #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED 3475 #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED 3476 #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED 3477 #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED 3478 #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED 3479 #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED 3480 #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED 3481 #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED 3482 #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED 3483 #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED 3484 #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED 3485 #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED 3486 #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED 3487 #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED 3488 #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED 3489 #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED 3490 #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED 3491 #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED 3492 #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED 3493 #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED 3494 #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED 3495 #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED 3496 #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED 3497 #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED 3498 #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED 3499 #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED 3500 #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED 3501 #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED 3502 #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED 3503 #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED 3504 #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED 3505 #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED 3506 #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED 3507 #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED 3508 #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED 3509 #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED 3510 #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED 3511 #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED 3512 #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED 3513 #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED 3514 #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED 3515 #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED 3516 #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED 3517 #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED 3518 #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED 3519 #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED 3520 #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED 3521 #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED 3522 #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED 3523 #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED 3524 #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED 3525 #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED 3526 #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED 3527 #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED 3528 #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED 3529 #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED 3530 #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED 3531 #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED 3532 #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED 3533 #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED 3534 #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED 3535 #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED 3536 #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED 3537 #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED 3538 #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED 3539 #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED 3540 #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED 3541 #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED 3542 #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED 3543 #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED 3544 #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED 3545 #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED 3546 #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED 3547 #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED 3548 #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED 3549 #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED 3550 #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED 3551 #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED 3552 #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED 3553 #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED 3554 #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED 3555 #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED 3556 #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED 3557 #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED 3558 #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED 3559 #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED 3560 #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED 3561 #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED 3562 #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED 3563 #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED 3564 #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED 3565 #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED 3566 #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED 3567 #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED 3568 #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED 3569 3570 #if defined(STM32L1) 3571 #define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE 3572 #define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE 3573 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE 3574 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE 3575 #define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET 3576 #define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET 3577 #endif /* STM32L1 */ 3578 3579 #if defined(STM32F4) 3580 #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 3581 #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 3582 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 3583 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 3584 #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 3585 #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 3586 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED 3587 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED 3588 #define Sdmmc1ClockSelection SdioClockSelection 3589 #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO 3590 #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 3591 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK 3592 #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG 3593 #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE 3594 #endif 3595 3596 #if defined(STM32F7) || defined(STM32L4) 3597 #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET 3598 #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET 3599 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE 3600 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE 3601 #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE 3602 #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE 3603 #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED 3604 #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED 3605 #define SdioClockSelection Sdmmc1ClockSelection 3606 #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 3607 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG 3608 #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE 3609 #endif 3610 3611 #if defined(STM32F7) 3612 #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 3613 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK 3614 #endif 3615 3616 #if defined(STM32H7) 3617 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() 3618 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() 3619 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() 3620 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() 3621 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() 3622 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() 3623 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() 3624 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() 3625 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() 3626 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() 3627 3628 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() 3629 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() 3630 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() 3631 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() 3632 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() 3633 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() 3634 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() 3635 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() 3636 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() 3637 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() 3638 #endif 3639 3640 #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG 3641 #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG 3642 3643 #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE 3644 3645 #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE 3646 #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE 3647 #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK 3648 #define IS_RCC_HCLK_DIV IS_RCC_PCLK 3649 #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK 3650 3651 #define RCC_IT_HSI14 RCC_IT_HSI14RDY 3652 3653 #define RCC_IT_CSSLSE RCC_IT_LSECSS 3654 #define RCC_IT_CSSHSE RCC_IT_CSS 3655 3656 #define RCC_PLLMUL_3 RCC_PLL_MUL3 3657 #define RCC_PLLMUL_4 RCC_PLL_MUL4 3658 #define RCC_PLLMUL_6 RCC_PLL_MUL6 3659 #define RCC_PLLMUL_8 RCC_PLL_MUL8 3660 #define RCC_PLLMUL_12 RCC_PLL_MUL12 3661 #define RCC_PLLMUL_16 RCC_PLL_MUL16 3662 #define RCC_PLLMUL_24 RCC_PLL_MUL24 3663 #define RCC_PLLMUL_32 RCC_PLL_MUL32 3664 #define RCC_PLLMUL_48 RCC_PLL_MUL48 3665 3666 #define RCC_PLLDIV_2 RCC_PLL_DIV2 3667 #define RCC_PLLDIV_3 RCC_PLL_DIV3 3668 #define RCC_PLLDIV_4 RCC_PLL_DIV4 3669 3670 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE 3671 #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG 3672 #define RCC_MCO_NODIV RCC_MCODIV_1 3673 #define RCC_MCO_DIV1 RCC_MCODIV_1 3674 #define RCC_MCO_DIV2 RCC_MCODIV_2 3675 #define RCC_MCO_DIV4 RCC_MCODIV_4 3676 #define RCC_MCO_DIV8 RCC_MCODIV_8 3677 #define RCC_MCO_DIV16 RCC_MCODIV_16 3678 #define RCC_MCO_DIV32 RCC_MCODIV_32 3679 #define RCC_MCO_DIV64 RCC_MCODIV_64 3680 #define RCC_MCO_DIV128 RCC_MCODIV_128 3681 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK 3682 #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI 3683 #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE 3684 #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK 3685 #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI 3686 #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 3687 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 3688 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE 3689 #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK 3690 #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK 3691 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 3692 3693 #if defined(STM32U0) 3694 #define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK 3695 #endif 3696 3697 #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ 3698 defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) 3699 #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE 3700 #else 3701 #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK 3702 #endif 3703 3704 #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 3705 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL 3706 #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI 3707 #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL 3708 #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL 3709 #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 3710 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 3711 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 3712 3713 #define HSION_BitNumber RCC_HSION_BIT_NUMBER 3714 #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER 3715 #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER 3716 #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER 3717 #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER 3718 #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER 3719 #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER 3720 #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER 3721 #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER 3722 #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER 3723 #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER 3724 #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER 3725 #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER 3726 #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER 3727 #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER 3728 #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER 3729 #define LSION_BitNumber RCC_LSION_BIT_NUMBER 3730 #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER 3731 #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER 3732 #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER 3733 #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER 3734 #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER 3735 #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER 3736 #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER 3737 #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER 3738 #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER 3739 #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS 3740 #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS 3741 #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS 3742 #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS 3743 #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE 3744 #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE 3745 3746 #define CR_HSION_BB RCC_CR_HSION_BB 3747 #define CR_CSSON_BB RCC_CR_CSSON_BB 3748 #define CR_PLLON_BB RCC_CR_PLLON_BB 3749 #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB 3750 #define CR_MSION_BB RCC_CR_MSION_BB 3751 #define CSR_LSION_BB RCC_CSR_LSION_BB 3752 #define CSR_LSEON_BB RCC_CSR_LSEON_BB 3753 #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB 3754 #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB 3755 #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB 3756 #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB 3757 #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB 3758 #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB 3759 #define CR_HSEON_BB RCC_CR_HSEON_BB 3760 #define CSR_RMVF_BB RCC_CSR_RMVF_BB 3761 #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB 3762 #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB 3763 3764 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE 3765 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE 3766 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE 3767 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE 3768 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE 3769 3770 #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT 3771 3772 #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN 3773 #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF 3774 3775 #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 3776 #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ 3777 #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP 3778 #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ 3779 #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE 3780 #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 3781 3782 #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE 3783 #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE 3784 #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED 3785 #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED 3786 #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET 3787 #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET 3788 #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE 3789 #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE 3790 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED 3791 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED 3792 #define DfsdmClockSelection Dfsdm1ClockSelection 3793 #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 3794 #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 3795 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK 3796 #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG 3797 #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE 3798 #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 3799 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 3800 #if !defined(STM32U0) 3801 #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 3802 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 3803 #endif 3804 3805 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 3806 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 3807 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 3808 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 3809 #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 3810 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 3811 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 3812 #if defined(STM32U5) 3813 #define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL 3814 #define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL 3815 #define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE 3816 #define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE 3817 #define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE 3818 #define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE 3819 #define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE 3820 #define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE 3821 #define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE 3822 #define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE 3823 #define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE 3824 #define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT 3825 #define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK 3826 #define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 3827 #define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 3828 #define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 3829 #define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK 3830 #define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE 3831 #define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE 3832 #define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED 3833 #define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED 3834 #define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET 3835 #define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET 3836 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE 3837 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE 3838 #define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE 3839 #define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE 3840 #define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE 3841 #define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG 3842 #define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE 3843 #endif /* STM32U5 */ 3844 3845 #if defined(STM32H5) 3846 #define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE 3847 #define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE 3848 #define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG 3849 #define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE 3850 3851 #define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE 3852 #define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI 3853 #define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI 3854 #define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE 3855 #define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0 3856 #define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1 3857 #define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2 3858 #define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3 3859 #define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE 3860 #define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM 3861 3862 #define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE 3863 #define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE 3864 #define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE 3865 #define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE 3866 #define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE 3867 #define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE 3868 #define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE 3869 #define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE 3870 #define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE 3871 #define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE 3872 3873 #define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE 3874 #define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE 3875 #define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE 3876 #define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE 3877 #define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG 3878 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG 3879 #define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG 3880 #define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG 3881 #define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE 3882 #define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE 3883 #define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE 3884 #define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE 3885 #define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE 3886 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG 3887 3888 #define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE 3889 #define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE 3890 #define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE 3891 #define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE 3892 #define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG 3893 #define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG 3894 3895 #define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE 3896 #define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE 3897 #define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE 3898 #define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE 3899 #define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG 3900 #define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG 3901 3902 #define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0 3903 #define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1 3904 #define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2 3905 #define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3 3906 3907 #define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE 3908 #define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM 3909 3910 #define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE 3911 #define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI 3912 #define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI 3913 #define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE 3914 3915 #define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0 3916 #define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1 3917 #define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2 3918 #define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3 3919 3920 #define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE 3921 #define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM 3922 3923 #define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE 3924 #define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI 3925 #define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI 3926 #define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE 3927 3928 3929 #endif /* STM32H5 */ 3930 3931 /** 3932 * @} 3933 */ 3934 3935 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose 3936 * @{ 3937 */ 3938 #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) 3939 3940 /** 3941 * @} 3942 */ 3943 3944 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose 3945 * @{ 3946 */ 3947 #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ 3948 defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ 3949 defined (STM32WBA) || defined (STM32V7) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \ 3950 defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) 3951 #else 3952 #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG 3953 #endif 3954 #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT 3955 #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT 3956 3957 #if defined (STM32F1) 3958 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() 3959 3960 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() 3961 3962 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() 3963 3964 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() 3965 3966 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() 3967 #else 3968 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ 3969 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ 3970 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) 3971 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ 3972 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ 3973 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) 3974 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ 3975 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ 3976 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) 3977 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ 3978 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ 3979 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) 3980 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ 3981 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ 3982 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) 3983 #endif /* STM32F1 */ 3984 3985 #if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ 3986 defined (STM32H7) || \ 3987 defined (STM32L0) || defined (STM32L1) || \ 3988 defined (STM32WB) 3989 #define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG 3990 #endif 3991 3992 #define IS_ALARM IS_RTC_ALARM 3993 #define IS_ALARM_MASK IS_RTC_ALARM_MASK 3994 #define IS_TAMPER IS_RTC_TAMPER 3995 #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE 3996 #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER 3997 #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT 3998 #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE 3999 #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION 4000 #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE 4001 #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ 4002 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION 4003 #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER 4004 #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK 4005 #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER 4006 4007 #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE 4008 #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE 4009 4010 #if defined (STM32H5) 4011 #define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE 4012 #define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE 4013 #endif /* STM32H5 */ 4014 4015 /** 4016 * @} 4017 */ 4018 4019 /** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose 4020 * @{ 4021 */ 4022 4023 #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE 4024 #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS 4025 4026 #if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) 4027 #define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE 4028 #define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE 4029 #define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE 4030 4031 #define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV 4032 #define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV 4033 #endif 4034 4035 #if defined(STM32F4) || defined(STM32F2) 4036 #define SD_SDMMC_DISABLED SD_SDIO_DISABLED 4037 #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY 4038 #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED 4039 #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION 4040 #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND 4041 #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT 4042 #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED 4043 #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE 4044 #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE 4045 #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE 4046 #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL 4047 #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT 4048 #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT 4049 #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG 4050 #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG 4051 #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT 4052 #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT 4053 #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS 4054 #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT 4055 #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND 4056 /* alias CMSIS */ 4057 #define SDMMC1_IRQn SDIO_IRQn 4058 #define SDMMC1_IRQHandler SDIO_IRQHandler 4059 #endif 4060 4061 #if defined(STM32F7) || defined(STM32L4) 4062 #define SD_SDIO_DISABLED SD_SDMMC_DISABLED 4063 #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY 4064 #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED 4065 #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION 4066 #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND 4067 #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT 4068 #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED 4069 #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE 4070 #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE 4071 #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE 4072 #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE 4073 #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT 4074 #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT 4075 #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG 4076 #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG 4077 #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT 4078 #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT 4079 #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS 4080 #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT 4081 #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND 4082 /* alias CMSIS for compatibilities */ 4083 #define SDIO_IRQn SDMMC1_IRQn 4084 #define SDIO_IRQHandler SDMMC1_IRQHandler 4085 #endif 4086 4087 #if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) 4088 #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef 4089 #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef 4090 #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef 4091 #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef 4092 #endif 4093 4094 #if defined(STM32H7) || defined(STM32L5) 4095 #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback 4096 #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback 4097 #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback 4098 #define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback 4099 #define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback 4100 #define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback 4101 #define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback 4102 #define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback 4103 #define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback 4104 #endif 4105 /** 4106 * @} 4107 */ 4108 4109 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose 4110 * @{ 4111 */ 4112 4113 #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT 4114 #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT 4115 #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE 4116 #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE 4117 #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE 4118 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE 4119 4120 #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 4121 #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 4122 4123 #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE 4124 4125 /** 4126 * @} 4127 */ 4128 4129 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose 4130 * @{ 4131 */ 4132 #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 4133 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 4134 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START 4135 #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH 4136 #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR 4137 #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE 4138 #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE 4139 #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED 4140 /** 4141 * @} 4142 */ 4143 4144 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose 4145 * @{ 4146 */ 4147 4148 #define __HAL_SPI_1LINE_TX SPI_1LINE_TX 4149 #define __HAL_SPI_1LINE_RX SPI_1LINE_RX 4150 #define __HAL_SPI_RESET_CRC SPI_RESET_CRC 4151 4152 /** 4153 * @} 4154 */ 4155 4156 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose 4157 * @{ 4158 */ 4159 4160 #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 4161 #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION 4162 #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 4163 #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION 4164 4165 #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD 4166 4167 #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE 4168 #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE 4169 4170 /** 4171 * @} 4172 */ 4173 4174 4175 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose 4176 * @{ 4177 */ 4178 4179 #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT 4180 #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT 4181 #define __USART_ENABLE __HAL_USART_ENABLE 4182 #define __USART_DISABLE __HAL_USART_DISABLE 4183 4184 #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 4185 #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 4186 4187 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) 4188 #define USART_OVERSAMPLING_16 0x00000000U 4189 #define USART_OVERSAMPLING_8 USART_CR1_OVER8 4190 4191 #define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ 4192 ((__SAMPLING__) == USART_OVERSAMPLING_8)) 4193 #endif /* STM32F0 || STM32F3 || STM32F7 */ 4194 /** 4195 * @} 4196 */ 4197 4198 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose 4199 * @{ 4200 */ 4201 #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE 4202 4203 #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 4204 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 4205 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 4206 #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE 4207 4208 #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 4209 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 4210 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 4211 #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE 4212 4213 #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT 4214 #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT 4215 #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG 4216 #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG 4217 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE 4218 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE 4219 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 4220 4221 #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT 4222 #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT 4223 #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG 4224 #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG 4225 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE 4226 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 4227 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 4228 #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT 4229 4230 #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT 4231 #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT 4232 #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG 4233 #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG 4234 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE 4235 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 4236 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 4237 #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT 4238 4239 #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup 4240 #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup 4241 4242 #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo 4243 #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo 4244 #if defined(STM32U5) 4245 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD 4246 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK 4247 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC 4248 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST 4249 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF 4250 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT 4251 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM 4252 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM 4253 #define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK 4254 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ 4255 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT 4256 #define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 4257 #define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 4258 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM 4259 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG 4260 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM 4261 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM 4262 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT 4263 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM 4264 #define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM 4265 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID 4266 #define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 4267 #define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 4268 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK 4269 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK 4270 #endif 4271 /** 4272 * @} 4273 */ 4274 4275 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose 4276 * @{ 4277 */ 4278 #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE 4279 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE 4280 4281 #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 4282 #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT 4283 4284 #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 4285 4286 #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN 4287 #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER 4288 #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER 4289 #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER 4290 #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD 4291 #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD 4292 #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION 4293 #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION 4294 #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER 4295 #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER 4296 #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE 4297 #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE 4298 4299 #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 4300 4301 #define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 4302 #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 4303 /** 4304 * @} 4305 */ 4306 4307 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose 4308 * @{ 4309 */ 4310 4311 #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT 4312 #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT 4313 #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG 4314 #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG 4315 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER 4316 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER 4317 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER 4318 4319 #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE 4320 #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE 4321 #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE 4322 /** 4323 * @} 4324 */ 4325 4326 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose 4327 * @{ 4328 */ 4329 #define __HAL_LTDC_LAYER LTDC_LAYER 4330 #define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG 4331 /** 4332 * @} 4333 */ 4334 4335 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose 4336 * @{ 4337 */ 4338 #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE 4339 #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE 4340 #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE 4341 #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE 4342 #define SAI_STREOMODE SAI_STEREOMODE 4343 #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY 4344 #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL 4345 #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL 4346 #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL 4347 #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL 4348 #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL 4349 #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE 4350 #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 4351 #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE 4352 /** 4353 * @} 4354 */ 4355 4356 /** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose 4357 * @{ 4358 */ 4359 #if defined(STM32H7) 4360 #define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow 4361 #define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT 4362 #define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA 4363 #endif 4364 /** 4365 * @} 4366 */ 4367 4368 /** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose 4369 * @{ 4370 */ 4371 #if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) 4372 #define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT 4373 #define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA 4374 #define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart 4375 #define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT 4376 #define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA 4377 #define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop 4378 #endif 4379 /** 4380 * @} 4381 */ 4382 4383 /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose 4384 * @{ 4385 */ 4386 #if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) 4387 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE 4388 #endif /* STM32L4 || STM32F4 || STM32F7 */ 4389 /** 4390 * @} 4391 */ 4392 4393 /** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose 4394 * @{ 4395 */ 4396 #if defined (STM32F7) 4397 #define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE 4398 #endif /* STM32F7 */ 4399 /** 4400 * @} 4401 */ 4402 4403 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose 4404 * @{ 4405 */ 4406 4407 /** 4408 * @} 4409 */ 4410 4411 #ifdef __cplusplus 4412 } 4413 #endif 4414 4415 #endif /* STM32_HAL_LEGACY */ 4416 4417 4418
