1 /**
2 ******************************************************************************
3 * @file stm32c0xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32C0xx_LL_TIM_H
21 #define __STM32C0xx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32c0xx.h"
29
30 /** @addtogroup STM32C0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM14) || defined (TIM16) || defined (TIM17)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U, /* 6: TIMx_CH4 */
54 0x3CU, /* 7: TIMx_CH5 */
55 0x3CU /* 8: TIMx_CH6 */
56 };
57
58 static const uint8_t SHIFT_TAB_OCxx[] =
59 {
60 0U, /* 0: OC1M, OC1FE, OC1PE */
61 0U, /* 1: - NA */
62 8U, /* 2: OC2M, OC2FE, OC2PE */
63 0U, /* 3: - NA */
64 0U, /* 4: OC3M, OC3FE, OC3PE */
65 0U, /* 5: - NA */
66 8U, /* 6: OC4M, OC4FE, OC4PE */
67 0U, /* 7: OC5M, OC5FE, OC5PE */
68 8U /* 8: OC6M, OC6FE, OC6PE */
69 };
70
71 static const uint8_t SHIFT_TAB_ICxx[] =
72 {
73 0U, /* 0: CC1S, IC1PSC, IC1F */
74 0U, /* 1: - NA */
75 8U, /* 2: CC2S, IC2PSC, IC2F */
76 0U, /* 3: - NA */
77 0U, /* 4: CC3S, IC3PSC, IC3F */
78 0U, /* 5: - NA */
79 8U, /* 6: CC4S, IC4PSC, IC4F */
80 0U, /* 7: - NA */
81 0U /* 8: - NA */
82 };
83
84 static const uint8_t SHIFT_TAB_CCxP[] =
85 {
86 0U, /* 0: CC1P */
87 2U, /* 1: CC1NP */
88 4U, /* 2: CC2P */
89 6U, /* 3: CC2NP */
90 8U, /* 4: CC3P */
91 10U, /* 5: CC3NP */
92 12U, /* 6: CC4P */
93 16U, /* 7: CC5P */
94 20U /* 8: CC6P */
95 };
96
97 static const uint8_t SHIFT_TAB_OISx[] =
98 {
99 0U, /* 0: OIS1 */
100 1U, /* 1: OIS1N */
101 2U, /* 2: OIS2 */
102 3U, /* 3: OIS2N */
103 4U, /* 4: OIS3 */
104 5U, /* 5: OIS3N */
105 6U, /* 6: OIS4 */
106 8U, /* 7: OIS5 */
107 10U /* 8: OIS6 */
108 };
109 /**
110 * @}
111 */
112
113 /* Private constants ---------------------------------------------------------*/
114 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
115 * @{
116 */
117
118 /* Defines used for the bit position in the register and perform offsets */
119 #define TIM_POSITION_BRK_SOURCE ((Source >> 1U) & 0x1FUL)
120
121 /* Generic bit definitions for TIMx_AF1 register */
122 #define TIMx_AF1_BKINP TIM_AF1_BKINP /*!< BRK BKIN input polarity */
123 #define TIMx_AF1_ETRSEL TIM_AF1_ETRSEL /*!< TIMx ETR source selection */
124
125
126 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
127 #define DT_DELAY_1 ((uint8_t)0x7F)
128 #define DT_DELAY_2 ((uint8_t)0x3F)
129 #define DT_DELAY_3 ((uint8_t)0x1F)
130 #define DT_DELAY_4 ((uint8_t)0x1F)
131
132 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
133 #define DT_RANGE_1 ((uint8_t)0x00)
134 #define DT_RANGE_2 ((uint8_t)0x80)
135 #define DT_RANGE_3 ((uint8_t)0xC0)
136 #define DT_RANGE_4 ((uint8_t)0xE0)
137
138 /** Legacy definitions for compatibility purpose
139 @cond 0
140 */
141 /**
142 @endcond
143 */
144
145 #define OCREF_CLEAR_SELECT_POS (16U)
146 #define OCREF_CLEAR_SELECT_MSK (0x1U << OCREF_CLEAR_SELECT_POS) /*!< 0x00010000 */
147 /**
148 * @}
149 */
150
151 /* Private macros ------------------------------------------------------------*/
152 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
153 * @{
154 */
155 /** @brief Convert channel id into channel index.
156 * @param __CHANNEL__ This parameter can be one of the following values:
157 * @arg @ref LL_TIM_CHANNEL_CH1
158 * @arg @ref LL_TIM_CHANNEL_CH1N
159 * @arg @ref LL_TIM_CHANNEL_CH2
160 * @arg @ref LL_TIM_CHANNEL_CH2N
161 * @arg @ref LL_TIM_CHANNEL_CH3
162 * @arg @ref LL_TIM_CHANNEL_CH3N
163 * @arg @ref LL_TIM_CHANNEL_CH4
164 * @arg @ref LL_TIM_CHANNEL_CH5
165 * @arg @ref LL_TIM_CHANNEL_CH6
166 * @retval none
167 */
168 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
169 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
170 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
171 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
172 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
173 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
174 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
175 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
176 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
177
178 /** @brief Calculate the deadtime sampling period(in ps).
179 * @param __TIMCLK__ timer input clock frequency (in Hz).
180 * @param __CKD__ This parameter can be one of the following values:
181 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
182 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
183 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
184 * @retval none
185 */
186 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
187 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
188 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
189 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
190 /**
191 * @}
192 */
193
194
195 /* Exported types ------------------------------------------------------------*/
196 #if defined(USE_FULL_LL_DRIVER)
197 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
198 * @{
199 */
200
201 /**
202 * @brief TIM Time Base configuration structure definition.
203 */
204 typedef struct
205 {
206 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
207 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
208
209 This feature can be modified afterwards using unitary function
210 @ref LL_TIM_SetPrescaler().*/
211
212 uint32_t CounterMode; /*!< Specifies the counter mode.
213 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
214
215 This feature can be modified afterwards using unitary function
216 @ref LL_TIM_SetCounterMode().*/
217
218 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
219 Auto-Reload Register at the next update event.
220 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
221 Some timer instances may support 32 bits counters. In that case this parameter must
222 be a number between 0x0000 and 0xFFFFFFFF.
223
224 This feature can be modified afterwards using unitary function
225 @ref LL_TIM_SetAutoReload().*/
226
227 uint32_t ClockDivision; /*!< Specifies the clock division.
228 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
229
230 This feature can be modified afterwards using unitary function
231 @ref LL_TIM_SetClockDivision().*/
232
233 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
234 reaches zero, an update event is generated and counting restarts
235 from the RCR value (N).
236 This means in PWM mode that (N+1) corresponds to:
237 - the number of PWM periods in edge-aligned mode
238 - the number of half PWM period in center-aligned mode
239 GP timers: this parameter must be a number between Min_Data = 0x00 and
240 Max_Data = 0xFF.
241 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
242 Max_Data = 0xFFFF.
243
244 This feature can be modified afterwards using unitary function
245 @ref LL_TIM_SetRepetitionCounter().*/
246 } LL_TIM_InitTypeDef;
247
248 /**
249 * @brief TIM Output Compare configuration structure definition.
250 */
251 typedef struct
252 {
253 uint32_t OCMode; /*!< Specifies the output mode.
254 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
255
256 This feature can be modified afterwards using unitary function
257 @ref LL_TIM_OC_SetMode().*/
258
259 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
260 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
261
262 This feature can be modified afterwards using unitary functions
263 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
264
265 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
266 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
267
268 This feature can be modified afterwards using unitary functions
269 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
270
271 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
272 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
273
274 This feature can be modified afterwards using unitary function
275 LL_TIM_OC_SetCompareCHx (x=1..6).*/
276
277 uint32_t OCPolarity; /*!< Specifies the output polarity.
278 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
279
280 This feature can be modified afterwards using unitary function
281 @ref LL_TIM_OC_SetPolarity().*/
282
283 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
284 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
285
286 This feature can be modified afterwards using unitary function
287 @ref LL_TIM_OC_SetPolarity().*/
288
289
290 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
291 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
292
293 This feature can be modified afterwards using unitary function
294 @ref LL_TIM_OC_SetIdleState().*/
295
296 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
297 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
298
299 This feature can be modified afterwards using unitary function
300 @ref LL_TIM_OC_SetIdleState().*/
301 } LL_TIM_OC_InitTypeDef;
302
303 /**
304 * @brief TIM Input Capture configuration structure definition.
305 */
306
307 typedef struct
308 {
309
310 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
311 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
312
313 This feature can be modified afterwards using unitary function
314 @ref LL_TIM_IC_SetPolarity().*/
315
316 uint32_t ICActiveInput; /*!< Specifies the input.
317 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
318
319 This feature can be modified afterwards using unitary function
320 @ref LL_TIM_IC_SetActiveInput().*/
321
322 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
323 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
324
325 This feature can be modified afterwards using unitary function
326 @ref LL_TIM_IC_SetPrescaler().*/
327
328 uint32_t ICFilter; /*!< Specifies the input capture filter.
329 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
330
331 This feature can be modified afterwards using unitary function
332 @ref LL_TIM_IC_SetFilter().*/
333 } LL_TIM_IC_InitTypeDef;
334
335
336 /**
337 * @brief TIM Encoder interface configuration structure definition.
338 */
339 typedef struct
340 {
341 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
342 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
343
344 This feature can be modified afterwards using unitary function
345 @ref LL_TIM_SetEncoderMode().*/
346
347 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
348 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
349
350 This feature can be modified afterwards using unitary function
351 @ref LL_TIM_IC_SetPolarity().*/
352
353 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
354 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
355
356 This feature can be modified afterwards using unitary function
357 @ref LL_TIM_IC_SetActiveInput().*/
358
359 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
360 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
361
362 This feature can be modified afterwards using unitary function
363 @ref LL_TIM_IC_SetPrescaler().*/
364
365 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
366 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
367
368 This feature can be modified afterwards using unitary function
369 @ref LL_TIM_IC_SetFilter().*/
370
371 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
372 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
373
374 This feature can be modified afterwards using unitary function
375 @ref LL_TIM_IC_SetPolarity().*/
376
377 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
378 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
379
380 This feature can be modified afterwards using unitary function
381 @ref LL_TIM_IC_SetActiveInput().*/
382
383 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
384 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
385
386 This feature can be modified afterwards using unitary function
387 @ref LL_TIM_IC_SetPrescaler().*/
388
389 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
390 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
391
392 This feature can be modified afterwards using unitary function
393 @ref LL_TIM_IC_SetFilter().*/
394
395 } LL_TIM_ENCODER_InitTypeDef;
396
397 /**
398 * @brief TIM Hall sensor interface configuration structure definition.
399 */
400 typedef struct
401 {
402
403 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
404 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
405
406 This feature can be modified afterwards using unitary function
407 @ref LL_TIM_IC_SetPolarity().*/
408
409 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
410 Prescaler must be set to get a maximum counter period longer than the
411 time interval between 2 consecutive changes on the Hall inputs.
412 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
413
414 This feature can be modified afterwards using unitary function
415 @ref LL_TIM_IC_SetPrescaler().*/
416
417 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
418 This parameter can be a value of
419 @ref TIM_LL_EC_IC_FILTER.
420
421 This feature can be modified afterwards using unitary function
422 @ref LL_TIM_IC_SetFilter().*/
423
424 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
425 A positive pulse (TRGO event) is generated with a programmable delay every time
426 a change occurs on the Hall inputs.
427 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
428
429 This feature can be modified afterwards using unitary function
430 @ref LL_TIM_OC_SetCompareCH2().*/
431 } LL_TIM_HALLSENSOR_InitTypeDef;
432
433 /**
434 * @brief BDTR (Break and Dead Time) structure definition
435 */
436 typedef struct
437 {
438 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
439 This parameter can be a value of @ref TIM_LL_EC_OSSR
440
441 This feature can be modified afterwards using unitary function
442 @ref LL_TIM_SetOffStates()
443
444 @note This bit-field cannot be modified as long as LOCK level 2 has been
445 programmed. */
446
447 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
448 This parameter can be a value of @ref TIM_LL_EC_OSSI
449
450 This feature can be modified afterwards using unitary function
451 @ref LL_TIM_SetOffStates()
452
453 @note This bit-field cannot be modified as long as LOCK level 2 has been
454 programmed. */
455
456 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
457 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
458
459 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
460 register has been written, their content is frozen until the next reset.*/
461
462 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
463 switching-on of the outputs.
464 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
465
466 This feature can be modified afterwards using unitary function
467 @ref LL_TIM_OC_SetDeadTime()
468
469 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
470 programmed. */
471
472 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
473 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
474
475 This feature can be modified afterwards using unitary functions
476 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
477
478 @note This bit-field can not be modified as long as LOCK level 1 has been
479 programmed. */
480
481 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
482 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
483
484 This feature can be modified afterwards using unitary function
485 @ref LL_TIM_ConfigBRK()
486
487 @note This bit-field can not be modified as long as LOCK level 1 has been
488 programmed. */
489
490 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
491 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
492
493 This feature can be modified afterwards using unitary function
494 @ref LL_TIM_ConfigBRK()
495
496 @note This bit-field can not be modified as long as LOCK level 1 has been
497 programmed. */
498
499 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
500 This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
501
502 This feature can be modified afterwards using unitary functions
503 @ref LL_TIM_ConfigBRK()
504
505 @note Bidirectional break input is only supported by advanced timers instances.
506
507 @note This bit-field can not be modified as long as LOCK level 1 has been
508 programmed. */
509
510 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
511 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
512
513 This feature can be modified afterwards using unitary functions
514 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
515
516 @note This bit-field can not be modified as long as LOCK level 1 has been
517 programmed. */
518
519 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
520 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
521
522 This feature can be modified afterwards using unitary function
523 @ref LL_TIM_ConfigBRK2()
524
525 @note This bit-field can not be modified as long as LOCK level 1 has been
526 programmed. */
527
528 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
529 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
530
531 This feature can be modified afterwards using unitary function
532 @ref LL_TIM_ConfigBRK2()
533
534 @note This bit-field can not be modified as long as LOCK level 1 has been
535 programmed. */
536
537 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
538 This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
539
540 This feature can be modified afterwards using unitary functions
541 @ref LL_TIM_ConfigBRK2()
542
543 @note Bidirectional break input is only supported by advanced timers instances.
544
545 @note This bit-field can not be modified as long as LOCK level 1 has been
546 programmed. */
547
548 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
549 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
550
551 This feature can be modified afterwards using unitary functions
552 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
553
554 @note This bit-field can not be modified as long as LOCK level 1 has been
555 programmed. */
556 } LL_TIM_BDTR_InitTypeDef;
557
558 /**
559 * @}
560 */
561 #endif /* USE_FULL_LL_DRIVER */
562
563 /* Exported constants --------------------------------------------------------*/
564 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
565 * @{
566 */
567
568 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
569 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
570 * @{
571 */
572 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
573 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
574 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
575 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
576 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
577 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
578 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
579 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
580 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
581 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
582 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
583 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
584 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
585 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
586 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
587 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
588 /**
589 * @}
590 */
591
592 #if defined(USE_FULL_LL_DRIVER)
593 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
594 * @{
595 */
596 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
597 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
598 /**
599 * @}
600 */
601
602 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
603 * @{
604 */
605 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
606 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
607 /**
608 * @}
609 */
610
611 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
612 * @{
613 */
614 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
615 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
616 /**
617 * @}
618 */
619 #endif /* USE_FULL_LL_DRIVER */
620
621 /** @defgroup TIM_LL_EC_IT IT Defines
622 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
623 * @{
624 */
625 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
626 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
627 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
628 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
629 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
630 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
631 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
632 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
633 /**
634 * @}
635 */
636
637 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
638 * @{
639 */
640 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
641 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
642 /**
643 * @}
644 */
645
646 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
647 * @{
648 */
649 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
650 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
651 /**
652 * @}
653 */
654
655 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
656 * @{
657 */
658 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
659 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
660 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
661 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
662 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
663 /**
664 * @}
665 */
666
667 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
668 * @{
669 */
670 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
671 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
672 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
673 /**
674 * @}
675 */
676
677 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
678 * @{
679 */
680 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
681 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
682 /**
683 * @}
684 */
685
686 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
687 * @{
688 */
689 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
690 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
691 /**
692 * @}
693 */
694
695 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
696 * @{
697 */
698 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
699 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
700 /**
701 * @}
702 */
703
704 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
705 * @{
706 */
707 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
708 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
709 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
710 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
711 /**
712 * @}
713 */
714
715 /** @defgroup TIM_LL_EC_CHANNEL Channel
716 * @{
717 */
718 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
719 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
720 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
721 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
722 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
723 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
724 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
725 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
726 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
727 /**
728 * @}
729 */
730
731 #if defined(USE_FULL_LL_DRIVER)
732 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
733 * @{
734 */
735 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
736 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
737 /**
738 * @}
739 */
740 #endif /* USE_FULL_LL_DRIVER */
741
742 /** Legacy definitions for compatibility purpose
743 @cond 0
744 */
745 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
746 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
747 /**
748 @endcond
749 */
750
751 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
752 * @{
753 */
754 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
755 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
756 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
757 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
758 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
759 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
760 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
761 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
762 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
763 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
764 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
765 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
766 #define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
767 #define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
768 /**
769 * @}
770 */
771
772 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
773 * @{
774 */
775 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
776 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
777 /**
778 * @}
779 */
780
781 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
782 * @{
783 */
784 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
785 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
786 /**
787 * @}
788 */
789
790 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
791 * @{
792 */
793 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
794 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
795 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
796 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
797 /**
798 * @}
799 */
800
801 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
802 * @{
803 */
804 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
805 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
806 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
807 /**
808 * @}
809 */
810
811 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
812 * @{
813 */
814 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
815 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
816 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
817 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
818 /**
819 * @}
820 */
821
822 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
823 * @{
824 */
825 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
826 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
827 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
828 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
829 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
830 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
831 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
832 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
833 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
834 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
835 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
836 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
837 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
838 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
839 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
840 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
841 /**
842 * @}
843 */
844
845 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
846 * @{
847 */
848 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
849 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
850 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
851 /**
852 * @}
853 */
854
855 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
856 * @{
857 */
858 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
859 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
860 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
861 /**
862 * @}
863 */
864
865 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
866 * @{
867 */
868 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
869 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
870 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
871 /**
872 * @}
873 */
874
875 /** @defgroup TIM_LL_EC_TRGO Trigger Output
876 * @{
877 */
878 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
879 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
880 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
881 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
882 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
883 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
884 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
885 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
886 /**
887 * @}
888 */
889
890 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
891 * @{
892 */
893 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
894 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
895 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
896 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
897 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
898 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
899 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
900 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
901 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
902 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
903 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
904 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
905 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
906 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
907 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
908 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
909 /**
910 * @}
911 */
912
913 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
914 * @{
915 */
916 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
917 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
918 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
919 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
920 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
921 /**
922 * @}
923 */
924
925 /** @defgroup TIM_LL_EC_TS Trigger Selection
926 * @{
927 */
928 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
929 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
930 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
931 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
932 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
933 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
934 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
935 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
936 /**
937 * @}
938 */
939
940 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
941 * @{
942 */
943 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
944 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
945 /**
946 * @}
947 */
948
949 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
950 * @{
951 */
952 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
953 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
954 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
955 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
956 /**
957 * @}
958 */
959
960 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
961 * @{
962 */
963 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
964 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
965 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
966 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
967 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
968 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
969 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
970 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
971 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
972 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
973 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
974 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
975 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
976 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
977 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
978 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
979 /**
980 * @}
981 */
982
983 /** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source
984 * @{
985 */
986 #define LL_TIM_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
987 #define LL_TIM_ETRSOURCE_ADC1_AWD1 (TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 1 */
988 #define LL_TIM_ETRSOURCE_ADC1_AWD2 TIM_AF1_ETRSEL_2 /*!< ETR input is connected to ADC1 analog watchdog 2 */
989 #define LL_TIM_ETRSOURCE_ADC1_AWD3 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 3 */
990 #if defined(TIM2)
991 #define LL_TIM_ETRSOURCE_LSE (TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */
992 #define LL_TIM_ETRSOURCE_MCO TIM_AF1_ETRSEL_2 /*!< ETR input is connected to MCO */
993 #define LL_TIM_ETRSOURCE_MCO2 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< ETR input is connected to MCO2 */
994 #endif /* TIM2 */
995 /**
996 * @}
997 */
998
999 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
1000 * @{
1001 */
1002 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
1003 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
1004 /**
1005 * @}
1006 */
1007
1008 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
1009 * @{
1010 */
1011 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1012 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
1013 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
1014 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
1015 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
1016 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
1017 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
1018 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
1019 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
1020 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
1021 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
1022 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
1023 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
1024 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
1025 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
1026 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
1027 /**
1028 * @}
1029 */
1030
1031 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
1032 * @{
1033 */
1034 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
1035 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
1036 /**
1037 * @}
1038 */
1039
1040 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1041 * @{
1042 */
1043 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1044 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1045 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1046 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1047 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1048 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1049 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1050 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1051 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1052 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1053 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1054 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1055 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1056 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1057 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1058 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1059 /**
1060 * @}
1061 */
1062
1063 /** @defgroup TIM_LL_EC_OSSI OSSI
1064 * @{
1065 */
1066 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1067 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1068 /**
1069 * @}
1070 */
1071
1072 /** @defgroup TIM_LL_EC_OSSR OSSR
1073 * @{
1074 */
1075 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1076 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1077 /**
1078 * @}
1079 */
1080
1081 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1082 * @{
1083 */
1084 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1085 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1086 /**
1087 * @}
1088 */
1089
1090 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1091 * @{
1092 */
1093 #define LL_TIM_BKIN_SOURCE_BKIN TIM_AF1_BKINE /*!< BKIN input from AF controller */
1094 /**
1095 * @}
1096 */
1097
1098 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1099 * @{
1100 */
1101 #define LL_TIM_BKIN_POLARITY_LOW TIM_AF1_BKINP /*!< BRK BKIN input is active low */
1102 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1103 /**
1104 * @}
1105 */
1106
1107 /** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
1108 * @{
1109 */
1110 #define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
1111 #define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
1112 /**
1113 * @}
1114 */
1115
1116 /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
1117 * @{
1118 */
1119 #define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
1120 #define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
1121 /**
1122 * @}
1123 */
1124
1125 /** Legacy definitions for compatibility purpose
1126 @cond 0
1127 */
1128 #define LL_TIM_ReArmBRK(_PARAM_)
1129 #define LL_TIM_ReArmBRK2(_PARAM_)
1130 /**
1131 @endcond
1132 */
1133
1134 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1135 * @{
1136 */
1137 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1138 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1139 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1140 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1141 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1142 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1143 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1144 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1145 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1146 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1147 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1148 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1149 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1150 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1151 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1152 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1153 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1154 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1155 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1156 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1157 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1158 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1159 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1160 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_TISEL register is the DMA base address for DMA burst */
1161 /**
1162 * @}
1163 */
1164
1165 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1166 * @{
1167 */
1168 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1169 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1170 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1171 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1172 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1173 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1174 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1175 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1176 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1177 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1178 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1179 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1180 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1181 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1182 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1183 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1184 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1185 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1186 /**
1187 * @}
1188 */
1189
1190 /** @defgroup TIM_LL_EC_TIM14_TI1_RMP TIM14 Timer Input Ch1 Remap
1191 * @{
1192 */
1193 #define LL_TIM_TIM14_TI1_RMP_GPIO 0x00000000U /*!< TIM14 input 1 is connected to GPIO */
1194 #define LL_TIM_TIM14_TI1_RMP_RTC_CLK TIM_TISEL_TI1SEL_0 /*!< TIM14 input 1 is connected to RTC clock */
1195 #define LL_TIM_TIM14_TI1_RMP_HSE_32 TIM_TISEL_TI1SEL_1 /*!< TIM14 input 1 is connected to HSE/32 clock */
1196 #define LL_TIM_TIM14_TI1_RMP_MCO (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM14 input 1 is connected to MCO */
1197 #define LL_TIM_TIM14_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2 /*!< TIM14 input 1 is connected to MCO2 */
1198 /**
1199 * @}
1200 */
1201
1202 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 Timer Input Ch1 Remap
1203 * @{
1204 */
1205 #define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /*!< TIM16 input 1 is connected to GPIO */
1206 #define LL_TIM_TIM16_TI1_RMP_LSI TIM_TISEL_TI1SEL_0 /*!< TIM16 input 1 is connected to LSI */
1207 #define LL_TIM_TIM16_TI1_RMP_LSE TIM_TISEL_TI1SEL_1 /*!< TIM16 input 1 is connected to LSE */
1208 #define LL_TIM_TIM16_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2 /*!< TIM16 input 1 is connected to MCO2 */
1209 /**
1210 * @}
1211 */
1212
1213 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap
1214 * @{
1215 */
1216 #define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U /*!< TIM17 input 1 is connected to GPIO */
1217 #define LL_TIM_TIM17_TI1_RMP_HSE_32 TIM_TISEL_TI1SEL_1 /*!< TIM17 input 1 is connected to HSE/32 clock */
1218 #define LL_TIM_TIM17_TI1_RMP_MCO (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM17 input 1 is connected to MCO */
1219 #define LL_TIM_TIM17_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2 /*!< TIM17 input 1 is connected to MCO2 */
1220 /**
1221 * @}
1222 */
1223
1224 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
1225 * @{
1226 */
1227 #define LL_TIM_OCREF_CLR_INT_ETR OCREF_CLEAR_SELECT_MSK /*!< OCREF_CLR_INT is connected to ETRF */
1228 /**
1229 * @}
1230 */
1231
1232 /** Legacy definitions for compatibility purpose
1233 @cond 0
1234 */
1235 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1236 /**
1237 @endcond
1238 */
1239
1240 /**
1241 * @}
1242 */
1243
1244 /* Exported macro ------------------------------------------------------------*/
1245 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1246 * @{
1247 */
1248
1249 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1250 * @{
1251 */
1252 /**
1253 * @brief Write a value in TIM register.
1254 * @param __INSTANCE__ TIM Instance
1255 * @param __REG__ Register to be written
1256 * @param __VALUE__ Value to be written in the register
1257 * @retval None
1258 */
1259 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1260
1261 /**
1262 * @brief Read a value in TIM register.
1263 * @param __INSTANCE__ TIM Instance
1264 * @param __REG__ Register to be read
1265 * @retval Register value
1266 */
1267 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1268 /**
1269 * @}
1270 */
1271
1272 /**
1273 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1274 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1275 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1276 * to TIMx_CNT register bit 31)
1277 * @param __CNT__ Counter value
1278 * @retval UIF status bit
1279 */
1280 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1281 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1282
1283 /**
1284 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1285 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1286 * @param __TIMCLK__ timer input clock frequency (in Hz)
1287 * @param __CKD__ This parameter can be one of the following values:
1288 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1289 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1290 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1291 * @param __DT__ deadtime duration (in ns)
1292 * @retval DTG[0:7]
1293 */
1294 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1295 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1296 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1297 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1298 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1299 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1300 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1301 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1302 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1303 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1304 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1305 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1306 0U)
1307
1308 /**
1309 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1310 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1311 * @param __TIMCLK__ timer input clock frequency (in Hz)
1312 * @param __CNTCLK__ counter clock frequency (in Hz)
1313 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1314 */
1315 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1316 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1317
1318 /**
1319 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1320 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1321 * @param __TIMCLK__ timer input clock frequency (in Hz)
1322 * @param __PSC__ prescaler
1323 * @param __FREQ__ output signal frequency (in Hz)
1324 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1325 */
1326 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1327 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1328
1329 /**
1330 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1331 * active/inactive delay.
1332 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1333 * @param __TIMCLK__ timer input clock frequency (in Hz)
1334 * @param __PSC__ prescaler
1335 * @param __DELAY__ timer output compare active/inactive delay (in us)
1336 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1337 */
1338 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1339 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1340 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1341
1342 /**
1343 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1344 * (when the timer operates in one pulse mode).
1345 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1346 * @param __TIMCLK__ timer input clock frequency (in Hz)
1347 * @param __PSC__ prescaler
1348 * @param __DELAY__ timer output compare active/inactive delay (in us)
1349 * @param __PULSE__ pulse duration (in us)
1350 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1351 */
1352 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1353 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1354 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1355
1356 /**
1357 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1358 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1359 * @param __ICPSC__ This parameter can be one of the following values:
1360 * @arg @ref LL_TIM_ICPSC_DIV1
1361 * @arg @ref LL_TIM_ICPSC_DIV2
1362 * @arg @ref LL_TIM_ICPSC_DIV4
1363 * @arg @ref LL_TIM_ICPSC_DIV8
1364 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1365 */
1366 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1367 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1368
1369
1370 /**
1371 * @}
1372 */
1373
1374 /* Exported functions --------------------------------------------------------*/
1375 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1376 * @{
1377 */
1378
1379 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1380 * @{
1381 */
1382 /**
1383 * @brief Enable timer counter.
1384 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1385 * @param TIMx Timer instance
1386 * @retval None
1387 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1388 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1389 {
1390 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1391 }
1392
1393 /**
1394 * @brief Disable timer counter.
1395 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1396 * @param TIMx Timer instance
1397 * @retval None
1398 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1399 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1400 {
1401 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1402 }
1403
1404 /**
1405 * @brief Indicates whether the timer counter is enabled.
1406 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1407 * @param TIMx Timer instance
1408 * @retval State of bit (1 or 0).
1409 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1410 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1411 {
1412 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1413 }
1414
1415 /**
1416 * @brief Enable update event generation.
1417 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1418 * @param TIMx Timer instance
1419 * @retval None
1420 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1421 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1422 {
1423 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1424 }
1425
1426 /**
1427 * @brief Disable update event generation.
1428 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1429 * @param TIMx Timer instance
1430 * @retval None
1431 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1432 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1433 {
1434 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1435 }
1436
1437 /**
1438 * @brief Indicates whether update event generation is enabled.
1439 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1440 * @param TIMx Timer instance
1441 * @retval Inverted state of bit (0 or 1).
1442 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1443 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1444 {
1445 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1446 }
1447
1448 /**
1449 * @brief Set update event source
1450 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1451 * generate an update interrupt or DMA request if enabled:
1452 * - Counter overflow/underflow
1453 * - Setting the UG bit
1454 * - Update generation through the slave mode controller
1455 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1456 * overflow/underflow generates an update interrupt or DMA request if enabled.
1457 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1458 * @param TIMx Timer instance
1459 * @param UpdateSource This parameter can be one of the following values:
1460 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1461 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1462 * @retval None
1463 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1464 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1465 {
1466 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1467 }
1468
1469 /**
1470 * @brief Get actual event update source
1471 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1472 * @param TIMx Timer instance
1473 * @retval Returned value can be one of the following values:
1474 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1475 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1476 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1477 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1478 {
1479 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1480 }
1481
1482 /**
1483 * @brief Set one pulse mode (one shot v.s. repetitive).
1484 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1485 * @param TIMx Timer instance
1486 * @param OnePulseMode This parameter can be one of the following values:
1487 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1488 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1489 * @retval None
1490 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1491 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1492 {
1493 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1494 }
1495
1496 /**
1497 * @brief Get actual one pulse mode.
1498 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1499 * @param TIMx Timer instance
1500 * @retval Returned value can be one of the following values:
1501 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1502 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1503 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1504 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1505 {
1506 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1507 }
1508
1509 /**
1510 * @brief Set the timer counter counting mode.
1511 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1512 * check whether or not the counter mode selection feature is supported
1513 * by a timer instance.
1514 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1515 * requires a timer reset to avoid unexpected direction
1516 * due to DIR bit readonly in center aligned mode.
1517 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1518 * CR1 CMS LL_TIM_SetCounterMode
1519 * @param TIMx Timer instance
1520 * @param CounterMode This parameter can be one of the following values:
1521 * @arg @ref LL_TIM_COUNTERMODE_UP
1522 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1523 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1524 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1525 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1526 * @retval None
1527 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1528 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1529 {
1530 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1531 }
1532
1533 /**
1534 * @brief Get actual counter mode.
1535 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1536 * check whether or not the counter mode selection feature is supported
1537 * by a timer instance.
1538 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1539 * CR1 CMS LL_TIM_GetCounterMode
1540 * @param TIMx Timer instance
1541 * @retval Returned value can be one of the following values:
1542 * @arg @ref LL_TIM_COUNTERMODE_UP
1543 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1544 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1545 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1546 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1547 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1548 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1549 {
1550 uint32_t counter_mode;
1551
1552 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1553
1554 if (counter_mode == 0U)
1555 {
1556 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1557 }
1558
1559 return counter_mode;
1560 }
1561
1562 /**
1563 * @brief Enable auto-reload (ARR) preload.
1564 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1565 * @param TIMx Timer instance
1566 * @retval None
1567 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1568 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1569 {
1570 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1571 }
1572
1573 /**
1574 * @brief Disable auto-reload (ARR) preload.
1575 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1576 * @param TIMx Timer instance
1577 * @retval None
1578 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1579 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1580 {
1581 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1582 }
1583
1584 /**
1585 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1586 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1587 * @param TIMx Timer instance
1588 * @retval State of bit (1 or 0).
1589 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1590 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1591 {
1592 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1593 }
1594
1595 /**
1596 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1597 * (when supported) and the digital filters.
1598 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1599 * whether or not the clock division feature is supported by the timer
1600 * instance.
1601 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1602 * @param TIMx Timer instance
1603 * @param ClockDivision This parameter can be one of the following values:
1604 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1605 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1606 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1607 * @retval None
1608 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1609 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1610 {
1611 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1612 }
1613
1614 /**
1615 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1616 * generators (when supported) and the digital filters.
1617 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1618 * whether or not the clock division feature is supported by the timer
1619 * instance.
1620 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1621 * @param TIMx Timer instance
1622 * @retval Returned value can be one of the following values:
1623 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1624 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1625 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1626 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1627 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1628 {
1629 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1630 }
1631
1632 /**
1633 * @brief Set the counter value.
1634 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1635 * whether or not a timer instance supports a 32 bits counter.
1636 * @rmtoll CNT CNT LL_TIM_SetCounter
1637 * @param TIMx Timer instance
1638 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1639 * @retval None
1640 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1641 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1642 {
1643 WRITE_REG(TIMx->CNT, Counter);
1644 }
1645
1646 /**
1647 * @brief Get the counter value.
1648 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1649 * whether or not a timer instance supports a 32 bits counter.
1650 * @rmtoll CNT CNT LL_TIM_GetCounter
1651 * @param TIMx Timer instance
1652 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1653 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)1654 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
1655 {
1656 return (uint32_t)(READ_REG(TIMx->CNT));
1657 }
1658
1659 /**
1660 * @brief Get the current direction of the counter
1661 * @rmtoll CR1 DIR LL_TIM_GetDirection
1662 * @param TIMx Timer instance
1663 * @retval Returned value can be one of the following values:
1664 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1665 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1666 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)1667 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
1668 {
1669 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1670 }
1671
1672 /**
1673 * @brief Set the prescaler value.
1674 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1675 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1676 * prescaler ratio is taken into account at the next update event.
1677 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1678 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1679 * @param TIMx Timer instance
1680 * @param Prescaler between Min_Data=0 and Max_Data=65535
1681 * @retval None
1682 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1683 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1684 {
1685 WRITE_REG(TIMx->PSC, Prescaler);
1686 }
1687
1688 /**
1689 * @brief Get the prescaler value.
1690 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1691 * @param TIMx Timer instance
1692 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1693 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)1694 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
1695 {
1696 return (uint32_t)(READ_REG(TIMx->PSC));
1697 }
1698
1699 /**
1700 * @brief Set the auto-reload value.
1701 * @note The counter is blocked while the auto-reload value is null.
1702 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1703 * whether or not a timer instance supports a 32 bits counter.
1704 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1705 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1706 * @param TIMx Timer instance
1707 * @param AutoReload between Min_Data=0 and Max_Data=65535
1708 * @retval None
1709 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1710 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1711 {
1712 WRITE_REG(TIMx->ARR, AutoReload);
1713 }
1714
1715 /**
1716 * @brief Get the auto-reload value.
1717 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1718 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1719 * whether or not a timer instance supports a 32 bits counter.
1720 * @param TIMx Timer instance
1721 * @retval Auto-reload value
1722 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)1723 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
1724 {
1725 return (uint32_t)(READ_REG(TIMx->ARR));
1726 }
1727
1728 /**
1729 * @brief Set the repetition counter value.
1730 * @note For advanced timer instances RepetitionCounter can be up to 65535.
1731 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1732 * whether or not a timer instance supports a repetition counter.
1733 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1734 * @param TIMx Timer instance
1735 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1736 * @retval None
1737 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1738 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1739 {
1740 WRITE_REG(TIMx->RCR, RepetitionCounter);
1741 }
1742
1743 /**
1744 * @brief Get the repetition counter value.
1745 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1746 * whether or not a timer instance supports a repetition counter.
1747 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1748 * @param TIMx Timer instance
1749 * @retval Repetition counter value
1750 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)1751 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
1752 {
1753 return (uint32_t)(READ_REG(TIMx->RCR));
1754 }
1755
1756 /**
1757 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1758 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
1759 * in an atomic way.
1760 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
1761 * @param TIMx Timer instance
1762 * @retval None
1763 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)1764 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
1765 {
1766 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1767 }
1768
1769 /**
1770 * @brief Disable update interrupt flag (UIF) remapping.
1771 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
1772 * @param TIMx Timer instance
1773 * @retval None
1774 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)1775 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
1776 {
1777 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1778 }
1779
1780 /**
1781 * @brief Indicate whether update interrupt flag (UIF) copy is set.
1782 * @param Counter Counter value
1783 * @retval State of bit (1 or 0).
1784 */
LL_TIM_IsActiveUIFCPY(const uint32_t Counter)1785 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
1786 {
1787 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
1788 }
1789
1790 /**
1791 * @}
1792 */
1793
1794 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1795 * @{
1796 */
1797 /**
1798 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1799 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1800 * they are updated only when a commutation event (COM) occurs.
1801 * @note Only on channels that have a complementary output.
1802 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1803 * whether or not a timer instance is able to generate a commutation event.
1804 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1805 * @param TIMx Timer instance
1806 * @retval None
1807 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)1808 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1809 {
1810 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1811 }
1812
1813 /**
1814 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1815 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1816 * whether or not a timer instance is able to generate a commutation event.
1817 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1818 * @param TIMx Timer instance
1819 * @retval None
1820 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)1821 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1822 {
1823 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1824 }
1825
1826 /**
1827 * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
1828 * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
1829 * @param TIMx Timer instance
1830 * @retval State of bit (1 or 0).
1831 */
LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef * TIMx)1832 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
1833 {
1834 return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
1835 }
1836
1837 /**
1838 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1839 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1840 * whether or not a timer instance is able to generate a commutation event.
1841 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1842 * @param TIMx Timer instance
1843 * @param CCUpdateSource This parameter can be one of the following values:
1844 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1845 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1846 * @retval None
1847 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)1848 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1849 {
1850 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1851 }
1852
1853 /**
1854 * @brief Set the trigger of the capture/compare DMA request.
1855 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1856 * @param TIMx Timer instance
1857 * @param DMAReqTrigger This parameter can be one of the following values:
1858 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1859 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1860 * @retval None
1861 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1862 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1863 {
1864 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1865 }
1866
1867 /**
1868 * @brief Get actual trigger of the capture/compare DMA request.
1869 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1870 * @param TIMx Timer instance
1871 * @retval Returned value can be one of the following values:
1872 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1873 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1874 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)1875 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
1876 {
1877 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1878 }
1879
1880 /**
1881 * @brief Set the lock level to freeze the
1882 * configuration of several capture/compare parameters.
1883 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1884 * the lock mechanism is supported by a timer instance.
1885 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1886 * @param TIMx Timer instance
1887 * @param LockLevel This parameter can be one of the following values:
1888 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1889 * @arg @ref LL_TIM_LOCKLEVEL_1
1890 * @arg @ref LL_TIM_LOCKLEVEL_2
1891 * @arg @ref LL_TIM_LOCKLEVEL_3
1892 * @retval None
1893 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)1894 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1895 {
1896 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1897 }
1898
1899 /**
1900 * @brief Enable capture/compare channels.
1901 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1902 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1903 * CCER CC2E LL_TIM_CC_EnableChannel\n
1904 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1905 * CCER CC3E LL_TIM_CC_EnableChannel\n
1906 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1907 * CCER CC4E LL_TIM_CC_EnableChannel\n
1908 * CCER CC5E LL_TIM_CC_EnableChannel\n
1909 * CCER CC6E LL_TIM_CC_EnableChannel
1910 * @param TIMx Timer instance
1911 * @param Channels This parameter can be a combination of the following values:
1912 * @arg @ref LL_TIM_CHANNEL_CH1
1913 * @arg @ref LL_TIM_CHANNEL_CH1N
1914 * @arg @ref LL_TIM_CHANNEL_CH2
1915 * @arg @ref LL_TIM_CHANNEL_CH2N
1916 * @arg @ref LL_TIM_CHANNEL_CH3
1917 * @arg @ref LL_TIM_CHANNEL_CH3N
1918 * @arg @ref LL_TIM_CHANNEL_CH4
1919 * @arg @ref LL_TIM_CHANNEL_CH5
1920 * @arg @ref LL_TIM_CHANNEL_CH6
1921 * @retval None
1922 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1923 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1924 {
1925 SET_BIT(TIMx->CCER, Channels);
1926 }
1927
1928 /**
1929 * @brief Disable capture/compare channels.
1930 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1931 * CCER CC1NE LL_TIM_CC_DisableChannel\n
1932 * CCER CC2E LL_TIM_CC_DisableChannel\n
1933 * CCER CC2NE LL_TIM_CC_DisableChannel\n
1934 * CCER CC3E LL_TIM_CC_DisableChannel\n
1935 * CCER CC3NE LL_TIM_CC_DisableChannel\n
1936 * CCER CC4E LL_TIM_CC_DisableChannel\n
1937 * CCER CC5E LL_TIM_CC_DisableChannel\n
1938 * CCER CC6E LL_TIM_CC_DisableChannel
1939 * @param TIMx Timer instance
1940 * @param Channels This parameter can be a combination of the following values:
1941 * @arg @ref LL_TIM_CHANNEL_CH1
1942 * @arg @ref LL_TIM_CHANNEL_CH1N
1943 * @arg @ref LL_TIM_CHANNEL_CH2
1944 * @arg @ref LL_TIM_CHANNEL_CH2N
1945 * @arg @ref LL_TIM_CHANNEL_CH3
1946 * @arg @ref LL_TIM_CHANNEL_CH3N
1947 * @arg @ref LL_TIM_CHANNEL_CH4
1948 * @arg @ref LL_TIM_CHANNEL_CH5
1949 * @arg @ref LL_TIM_CHANNEL_CH6
1950 * @retval None
1951 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1952 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1953 {
1954 CLEAR_BIT(TIMx->CCER, Channels);
1955 }
1956
1957 /**
1958 * @brief Indicate whether channel(s) is(are) enabled.
1959 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
1960 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
1961 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
1962 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
1963 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
1964 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
1965 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
1966 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
1967 * CCER CC6E LL_TIM_CC_IsEnabledChannel
1968 * @param TIMx Timer instance
1969 * @param Channels This parameter can be a combination of the following values:
1970 * @arg @ref LL_TIM_CHANNEL_CH1
1971 * @arg @ref LL_TIM_CHANNEL_CH1N
1972 * @arg @ref LL_TIM_CHANNEL_CH2
1973 * @arg @ref LL_TIM_CHANNEL_CH2N
1974 * @arg @ref LL_TIM_CHANNEL_CH3
1975 * @arg @ref LL_TIM_CHANNEL_CH3N
1976 * @arg @ref LL_TIM_CHANNEL_CH4
1977 * @arg @ref LL_TIM_CHANNEL_CH5
1978 * @arg @ref LL_TIM_CHANNEL_CH6
1979 * @retval State of bit (1 or 0).
1980 */
LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef * TIMx,uint32_t Channels)1981 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
1982 {
1983 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
1984 }
1985
1986 /**
1987 * @}
1988 */
1989
1990 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
1991 * @{
1992 */
1993 /**
1994 * @brief Configure an output channel.
1995 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
1996 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
1997 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
1998 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
1999 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2000 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2001 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2002 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2003 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2004 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2005 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2006 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2007 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2008 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2009 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2010 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2011 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2012 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2013 * @param TIMx Timer instance
2014 * @param Channel This parameter can be one of the following values:
2015 * @arg @ref LL_TIM_CHANNEL_CH1
2016 * @arg @ref LL_TIM_CHANNEL_CH2
2017 * @arg @ref LL_TIM_CHANNEL_CH3
2018 * @arg @ref LL_TIM_CHANNEL_CH4
2019 * @arg @ref LL_TIM_CHANNEL_CH5
2020 * @arg @ref LL_TIM_CHANNEL_CH6
2021 * @param Configuration This parameter must be a combination of all the following values:
2022 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2023 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2024 * @retval None
2025 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2026 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2027 {
2028 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2029 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2030 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2031 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2032 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2033 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2034 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2035 }
2036
2037 /**
2038 * @brief Define the behavior of the output reference signal OCxREF from which
2039 * OCx and OCxN (when relevant) are derived.
2040 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2041 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2042 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2043 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2044 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2045 * CCMR3 OC6M LL_TIM_OC_SetMode
2046 * @param TIMx Timer instance
2047 * @param Channel This parameter can be one of the following values:
2048 * @arg @ref LL_TIM_CHANNEL_CH1
2049 * @arg @ref LL_TIM_CHANNEL_CH2
2050 * @arg @ref LL_TIM_CHANNEL_CH3
2051 * @arg @ref LL_TIM_CHANNEL_CH4
2052 * @arg @ref LL_TIM_CHANNEL_CH5
2053 * @arg @ref LL_TIM_CHANNEL_CH6
2054 * @param Mode This parameter can be one of the following values:
2055 * @arg @ref LL_TIM_OCMODE_FROZEN
2056 * @arg @ref LL_TIM_OCMODE_ACTIVE
2057 * @arg @ref LL_TIM_OCMODE_INACTIVE
2058 * @arg @ref LL_TIM_OCMODE_TOGGLE
2059 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2060 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2061 * @arg @ref LL_TIM_OCMODE_PWM1
2062 * @arg @ref LL_TIM_OCMODE_PWM2
2063 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2064 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2065 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2066 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2067 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2068 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2069 * @retval None
2070 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)2071 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2072 {
2073 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2074 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2075 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2076 }
2077
2078 /**
2079 * @brief Get the output compare mode of an output channel.
2080 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2081 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2082 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2083 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2084 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2085 * CCMR3 OC6M LL_TIM_OC_GetMode
2086 * @param TIMx Timer instance
2087 * @param Channel This parameter can be one of the following values:
2088 * @arg @ref LL_TIM_CHANNEL_CH1
2089 * @arg @ref LL_TIM_CHANNEL_CH2
2090 * @arg @ref LL_TIM_CHANNEL_CH3
2091 * @arg @ref LL_TIM_CHANNEL_CH4
2092 * @arg @ref LL_TIM_CHANNEL_CH5
2093 * @arg @ref LL_TIM_CHANNEL_CH6
2094 * @retval Returned value can be one of the following values:
2095 * @arg @ref LL_TIM_OCMODE_FROZEN
2096 * @arg @ref LL_TIM_OCMODE_ACTIVE
2097 * @arg @ref LL_TIM_OCMODE_INACTIVE
2098 * @arg @ref LL_TIM_OCMODE_TOGGLE
2099 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2100 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2101 * @arg @ref LL_TIM_OCMODE_PWM1
2102 * @arg @ref LL_TIM_OCMODE_PWM2
2103 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2104 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2105 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2106 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2107 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2108 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2109 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)2110 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
2111 {
2112 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2113 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2114 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2115 }
2116
2117 /**
2118 * @brief Set the polarity of an output channel.
2119 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2120 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2121 * CCER CC2P LL_TIM_OC_SetPolarity\n
2122 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2123 * CCER CC3P LL_TIM_OC_SetPolarity\n
2124 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2125 * CCER CC4P LL_TIM_OC_SetPolarity\n
2126 * CCER CC5P LL_TIM_OC_SetPolarity\n
2127 * CCER CC6P LL_TIM_OC_SetPolarity
2128 * @param TIMx Timer instance
2129 * @param Channel This parameter can be one of the following values:
2130 * @arg @ref LL_TIM_CHANNEL_CH1
2131 * @arg @ref LL_TIM_CHANNEL_CH1N
2132 * @arg @ref LL_TIM_CHANNEL_CH2
2133 * @arg @ref LL_TIM_CHANNEL_CH2N
2134 * @arg @ref LL_TIM_CHANNEL_CH3
2135 * @arg @ref LL_TIM_CHANNEL_CH3N
2136 * @arg @ref LL_TIM_CHANNEL_CH4
2137 * @arg @ref LL_TIM_CHANNEL_CH5
2138 * @arg @ref LL_TIM_CHANNEL_CH6
2139 * @param Polarity This parameter can be one of the following values:
2140 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2141 * @arg @ref LL_TIM_OCPOLARITY_LOW
2142 * @retval None
2143 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2144 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2145 {
2146 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2147 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2148 }
2149
2150 /**
2151 * @brief Get the polarity of an output channel.
2152 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2153 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2154 * CCER CC2P LL_TIM_OC_GetPolarity\n
2155 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2156 * CCER CC3P LL_TIM_OC_GetPolarity\n
2157 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2158 * CCER CC4P LL_TIM_OC_GetPolarity\n
2159 * CCER CC5P LL_TIM_OC_GetPolarity\n
2160 * CCER CC6P LL_TIM_OC_GetPolarity
2161 * @param TIMx Timer instance
2162 * @param Channel This parameter can be one of the following values:
2163 * @arg @ref LL_TIM_CHANNEL_CH1
2164 * @arg @ref LL_TIM_CHANNEL_CH1N
2165 * @arg @ref LL_TIM_CHANNEL_CH2
2166 * @arg @ref LL_TIM_CHANNEL_CH2N
2167 * @arg @ref LL_TIM_CHANNEL_CH3
2168 * @arg @ref LL_TIM_CHANNEL_CH3N
2169 * @arg @ref LL_TIM_CHANNEL_CH4
2170 * @arg @ref LL_TIM_CHANNEL_CH5
2171 * @arg @ref LL_TIM_CHANNEL_CH6
2172 * @retval Returned value can be one of the following values:
2173 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2174 * @arg @ref LL_TIM_OCPOLARITY_LOW
2175 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2176 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2177 {
2178 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2179 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2180 }
2181
2182 /**
2183 * @brief Set the IDLE state of an output channel
2184 * @note This function is significant only for the timer instances
2185 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2186 * can be used to check whether or not a timer instance provides
2187 * a break input.
2188 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2189 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2190 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2191 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2192 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2193 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2194 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2195 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2196 * CR2 OIS6 LL_TIM_OC_SetIdleState
2197 * @param TIMx Timer instance
2198 * @param Channel This parameter can be one of the following values:
2199 * @arg @ref LL_TIM_CHANNEL_CH1
2200 * @arg @ref LL_TIM_CHANNEL_CH1N
2201 * @arg @ref LL_TIM_CHANNEL_CH2
2202 * @arg @ref LL_TIM_CHANNEL_CH2N
2203 * @arg @ref LL_TIM_CHANNEL_CH3
2204 * @arg @ref LL_TIM_CHANNEL_CH3N
2205 * @arg @ref LL_TIM_CHANNEL_CH4
2206 * @arg @ref LL_TIM_CHANNEL_CH5
2207 * @arg @ref LL_TIM_CHANNEL_CH6
2208 * @param IdleState This parameter can be one of the following values:
2209 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2210 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2211 * @retval None
2212 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2213 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2214 {
2215 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2216 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2217 }
2218
2219 /**
2220 * @brief Get the IDLE state of an output channel
2221 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2222 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2223 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2224 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2225 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2226 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2227 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2228 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2229 * CR2 OIS6 LL_TIM_OC_GetIdleState
2230 * @param TIMx Timer instance
2231 * @param Channel This parameter can be one of the following values:
2232 * @arg @ref LL_TIM_CHANNEL_CH1
2233 * @arg @ref LL_TIM_CHANNEL_CH1N
2234 * @arg @ref LL_TIM_CHANNEL_CH2
2235 * @arg @ref LL_TIM_CHANNEL_CH2N
2236 * @arg @ref LL_TIM_CHANNEL_CH3
2237 * @arg @ref LL_TIM_CHANNEL_CH3N
2238 * @arg @ref LL_TIM_CHANNEL_CH4
2239 * @arg @ref LL_TIM_CHANNEL_CH5
2240 * @arg @ref LL_TIM_CHANNEL_CH6
2241 * @retval Returned value can be one of the following values:
2242 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2243 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2244 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)2245 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
2246 {
2247 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2248 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2249 }
2250
2251 /**
2252 * @brief Enable fast mode for the output channel.
2253 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2254 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2255 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2256 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2257 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2258 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2259 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2260 * @param TIMx Timer instance
2261 * @param Channel This parameter can be one of the following values:
2262 * @arg @ref LL_TIM_CHANNEL_CH1
2263 * @arg @ref LL_TIM_CHANNEL_CH2
2264 * @arg @ref LL_TIM_CHANNEL_CH3
2265 * @arg @ref LL_TIM_CHANNEL_CH4
2266 * @arg @ref LL_TIM_CHANNEL_CH5
2267 * @arg @ref LL_TIM_CHANNEL_CH6
2268 * @retval None
2269 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2270 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2271 {
2272 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2273 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2274 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2275
2276 }
2277
2278 /**
2279 * @brief Disable fast mode for the output channel.
2280 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2281 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2282 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2283 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2284 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2285 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2286 * @param TIMx Timer instance
2287 * @param Channel This parameter can be one of the following values:
2288 * @arg @ref LL_TIM_CHANNEL_CH1
2289 * @arg @ref LL_TIM_CHANNEL_CH2
2290 * @arg @ref LL_TIM_CHANNEL_CH3
2291 * @arg @ref LL_TIM_CHANNEL_CH4
2292 * @arg @ref LL_TIM_CHANNEL_CH5
2293 * @arg @ref LL_TIM_CHANNEL_CH6
2294 * @retval None
2295 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2296 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2297 {
2298 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2299 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2300 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2301
2302 }
2303
2304 /**
2305 * @brief Indicates whether fast mode is enabled for the output channel.
2306 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2307 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2308 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2309 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2310 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2311 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2312 * @param TIMx Timer instance
2313 * @param Channel This parameter can be one of the following values:
2314 * @arg @ref LL_TIM_CHANNEL_CH1
2315 * @arg @ref LL_TIM_CHANNEL_CH2
2316 * @arg @ref LL_TIM_CHANNEL_CH3
2317 * @arg @ref LL_TIM_CHANNEL_CH4
2318 * @arg @ref LL_TIM_CHANNEL_CH5
2319 * @arg @ref LL_TIM_CHANNEL_CH6
2320 * @retval State of bit (1 or 0).
2321 */
LL_TIM_OC_IsEnabledFast(const TIM_TypeDef * TIMx,uint32_t Channel)2322 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
2323 {
2324 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2325 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2326 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2327 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2328 }
2329
2330 /**
2331 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2332 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2333 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2334 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2335 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2336 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2337 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2338 * @param TIMx Timer instance
2339 * @param Channel This parameter can be one of the following values:
2340 * @arg @ref LL_TIM_CHANNEL_CH1
2341 * @arg @ref LL_TIM_CHANNEL_CH2
2342 * @arg @ref LL_TIM_CHANNEL_CH3
2343 * @arg @ref LL_TIM_CHANNEL_CH4
2344 * @arg @ref LL_TIM_CHANNEL_CH5
2345 * @arg @ref LL_TIM_CHANNEL_CH6
2346 * @retval None
2347 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2348 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2349 {
2350 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2351 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2352 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2353 }
2354
2355 /**
2356 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2357 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2358 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2359 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2360 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2361 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2362 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2363 * @param TIMx Timer instance
2364 * @param Channel This parameter can be one of the following values:
2365 * @arg @ref LL_TIM_CHANNEL_CH1
2366 * @arg @ref LL_TIM_CHANNEL_CH2
2367 * @arg @ref LL_TIM_CHANNEL_CH3
2368 * @arg @ref LL_TIM_CHANNEL_CH4
2369 * @arg @ref LL_TIM_CHANNEL_CH5
2370 * @arg @ref LL_TIM_CHANNEL_CH6
2371 * @retval None
2372 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2373 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2374 {
2375 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2376 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2377 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2378 }
2379
2380 /**
2381 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2382 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2383 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2384 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2385 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2386 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2387 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2388 * @param TIMx Timer instance
2389 * @param Channel This parameter can be one of the following values:
2390 * @arg @ref LL_TIM_CHANNEL_CH1
2391 * @arg @ref LL_TIM_CHANNEL_CH2
2392 * @arg @ref LL_TIM_CHANNEL_CH3
2393 * @arg @ref LL_TIM_CHANNEL_CH4
2394 * @arg @ref LL_TIM_CHANNEL_CH5
2395 * @arg @ref LL_TIM_CHANNEL_CH6
2396 * @retval State of bit (1 or 0).
2397 */
LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef * TIMx,uint32_t Channel)2398 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
2399 {
2400 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2401 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2402 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2403 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2404 }
2405
2406 /**
2407 * @brief Enable clearing the output channel on an external event.
2408 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2409 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2410 * or not a timer instance can clear the OCxREF signal on an external event.
2411 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2412 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2413 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2414 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2415 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2416 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2417 * @param TIMx Timer instance
2418 * @param Channel This parameter can be one of the following values:
2419 * @arg @ref LL_TIM_CHANNEL_CH1
2420 * @arg @ref LL_TIM_CHANNEL_CH2
2421 * @arg @ref LL_TIM_CHANNEL_CH3
2422 * @arg @ref LL_TIM_CHANNEL_CH4
2423 * @arg @ref LL_TIM_CHANNEL_CH5
2424 * @arg @ref LL_TIM_CHANNEL_CH6
2425 * @retval None
2426 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2427 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2428 {
2429 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2430 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2431 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2432 }
2433
2434 /**
2435 * @brief Disable clearing the output channel on an external event.
2436 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2437 * or not a timer instance can clear the OCxREF signal on an external event.
2438 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2439 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2440 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2441 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2442 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2443 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2444 * @param TIMx Timer instance
2445 * @param Channel This parameter can be one of the following values:
2446 * @arg @ref LL_TIM_CHANNEL_CH1
2447 * @arg @ref LL_TIM_CHANNEL_CH2
2448 * @arg @ref LL_TIM_CHANNEL_CH3
2449 * @arg @ref LL_TIM_CHANNEL_CH4
2450 * @arg @ref LL_TIM_CHANNEL_CH5
2451 * @arg @ref LL_TIM_CHANNEL_CH6
2452 * @retval None
2453 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2454 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2455 {
2456 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2457 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2458 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2459 }
2460
2461 /**
2462 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2463 * @note This function enables clearing the output channel on an external event.
2464 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2465 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2466 * or not a timer instance can clear the OCxREF signal on an external event.
2467 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2468 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2469 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2470 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2471 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2472 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2473 * @param TIMx Timer instance
2474 * @param Channel This parameter can be one of the following values:
2475 * @arg @ref LL_TIM_CHANNEL_CH1
2476 * @arg @ref LL_TIM_CHANNEL_CH2
2477 * @arg @ref LL_TIM_CHANNEL_CH3
2478 * @arg @ref LL_TIM_CHANNEL_CH4
2479 * @arg @ref LL_TIM_CHANNEL_CH5
2480 * @arg @ref LL_TIM_CHANNEL_CH6
2481 * @retval State of bit (1 or 0).
2482 */
LL_TIM_OC_IsEnabledClear(const TIM_TypeDef * TIMx,uint32_t Channel)2483 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
2484 {
2485 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2486 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2487 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2488 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2489 }
2490
2491 /**
2492 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2493 * the Ocx and OCxN signals).
2494 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2495 * dead-time insertion feature is supported by a timer instance.
2496 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2497 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2498 * @param TIMx Timer instance
2499 * @param DeadTime between Min_Data=0 and Max_Data=255
2500 * @retval None
2501 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2502 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2503 {
2504 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2505 }
2506
2507 /**
2508 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2509 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2510 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2511 * whether or not a timer instance supports a 32 bits counter.
2512 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2513 * output channel 1 is supported by a timer instance.
2514 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2515 * @param TIMx Timer instance
2516 * @param CompareValue between Min_Data=0 and Max_Data=65535
2517 * @retval None
2518 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2519 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2520 {
2521 WRITE_REG(TIMx->CCR1, CompareValue);
2522 }
2523
2524 /**
2525 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2526 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2527 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2528 * whether or not a timer instance supports a 32 bits counter.
2529 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2530 * output channel 2 is supported by a timer instance.
2531 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2532 * @param TIMx Timer instance
2533 * @param CompareValue between Min_Data=0 and Max_Data=65535
2534 * @retval None
2535 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2536 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2537 {
2538 WRITE_REG(TIMx->CCR2, CompareValue);
2539 }
2540
2541 /**
2542 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2543 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2544 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2545 * whether or not a timer instance supports a 32 bits counter.
2546 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2547 * output channel is supported by a timer instance.
2548 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2549 * @param TIMx Timer instance
2550 * @param CompareValue between Min_Data=0 and Max_Data=65535
2551 * @retval None
2552 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2553 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2554 {
2555 WRITE_REG(TIMx->CCR3, CompareValue);
2556 }
2557
2558 /**
2559 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2560 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2561 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2562 * whether or not a timer instance supports a 32 bits counter.
2563 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2564 * output channel 4 is supported by a timer instance.
2565 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2566 * @param TIMx Timer instance
2567 * @param CompareValue between Min_Data=0 and Max_Data=65535
2568 * @retval None
2569 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2570 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2571 {
2572 WRITE_REG(TIMx->CCR4, CompareValue);
2573 }
2574
2575 /**
2576 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2577 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2578 * output channel 5 is supported by a timer instance.
2579 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2580 * @param TIMx Timer instance
2581 * @param CompareValue between Min_Data=0 and Max_Data=65535
2582 * @retval None
2583 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)2584 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2585 {
2586 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
2587 }
2588
2589 /**
2590 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2591 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2592 * output channel 6 is supported by a timer instance.
2593 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2594 * @param TIMx Timer instance
2595 * @param CompareValue between Min_Data=0 and Max_Data=65535
2596 * @retval None
2597 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)2598 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2599 {
2600 WRITE_REG(TIMx->CCR6, CompareValue);
2601 }
2602
2603 /**
2604 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2605 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2606 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2607 * whether or not a timer instance supports a 32 bits counter.
2608 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2609 * output channel 1 is supported by a timer instance.
2610 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2611 * @param TIMx Timer instance
2612 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2613 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)2614 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
2615 {
2616 return (uint32_t)(READ_REG(TIMx->CCR1));
2617 }
2618
2619 /**
2620 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2621 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2622 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2623 * whether or not a timer instance supports a 32 bits counter.
2624 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2625 * output channel 2 is supported by a timer instance.
2626 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2627 * @param TIMx Timer instance
2628 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2629 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)2630 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
2631 {
2632 return (uint32_t)(READ_REG(TIMx->CCR2));
2633 }
2634
2635 /**
2636 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2637 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2638 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2639 * whether or not a timer instance supports a 32 bits counter.
2640 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2641 * output channel 3 is supported by a timer instance.
2642 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2643 * @param TIMx Timer instance
2644 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2645 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)2646 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
2647 {
2648 return (uint32_t)(READ_REG(TIMx->CCR3));
2649 }
2650
2651 /**
2652 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2653 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2654 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2655 * whether or not a timer instance supports a 32 bits counter.
2656 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2657 * output channel 4 is supported by a timer instance.
2658 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2659 * @param TIMx Timer instance
2660 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2661 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)2662 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
2663 {
2664 return (uint32_t)(READ_REG(TIMx->CCR4));
2665 }
2666
2667 /**
2668 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
2669 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2670 * output channel 5 is supported by a timer instance.
2671 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2672 * @param TIMx Timer instance
2673 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2674 */
LL_TIM_OC_GetCompareCH5(const TIM_TypeDef * TIMx)2675 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
2676 {
2677 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
2678 }
2679
2680 /**
2681 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
2682 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2683 * output channel 6 is supported by a timer instance.
2684 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2685 * @param TIMx Timer instance
2686 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2687 */
LL_TIM_OC_GetCompareCH6(const TIM_TypeDef * TIMx)2688 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
2689 {
2690 return (uint32_t)(READ_REG(TIMx->CCR6));
2691 }
2692
2693 /**
2694 * @brief Select on which reference signal the OC5REF is combined to.
2695 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
2696 * whether or not a timer instance supports the combined 3-phase PWM mode.
2697 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2698 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2699 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2700 * @param TIMx Timer instance
2701 * @param GroupCH5 This parameter can be a combination of the following values:
2702 * @arg @ref LL_TIM_GROUPCH5_NONE
2703 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
2704 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
2705 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
2706 * @retval None
2707 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)2708 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
2709 {
2710 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
2711 }
2712
2713 /**
2714 * @}
2715 */
2716
2717 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2718 * @{
2719 */
2720 /**
2721 * @brief Configure input channel.
2722 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2723 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2724 * CCMR1 IC1F LL_TIM_IC_Config\n
2725 * CCMR1 CC2S LL_TIM_IC_Config\n
2726 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2727 * CCMR1 IC2F LL_TIM_IC_Config\n
2728 * CCMR2 CC3S LL_TIM_IC_Config\n
2729 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2730 * CCMR2 IC3F LL_TIM_IC_Config\n
2731 * CCMR2 CC4S LL_TIM_IC_Config\n
2732 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2733 * CCMR2 IC4F LL_TIM_IC_Config\n
2734 * CCER CC1P LL_TIM_IC_Config\n
2735 * CCER CC1NP LL_TIM_IC_Config\n
2736 * CCER CC2P LL_TIM_IC_Config\n
2737 * CCER CC2NP LL_TIM_IC_Config\n
2738 * CCER CC3P LL_TIM_IC_Config\n
2739 * CCER CC3NP LL_TIM_IC_Config\n
2740 * CCER CC4P LL_TIM_IC_Config\n
2741 * CCER CC4NP LL_TIM_IC_Config
2742 * @param TIMx Timer instance
2743 * @param Channel This parameter can be one of the following values:
2744 * @arg @ref LL_TIM_CHANNEL_CH1
2745 * @arg @ref LL_TIM_CHANNEL_CH2
2746 * @arg @ref LL_TIM_CHANNEL_CH3
2747 * @arg @ref LL_TIM_CHANNEL_CH4
2748 * @param Configuration This parameter must be a combination of all the following values:
2749 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2750 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2751 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2752 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2753 * @retval None
2754 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2755 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2756 {
2757 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2758 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2759 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2760 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
2761 << SHIFT_TAB_ICxx[iChannel]);
2762 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2763 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2764 }
2765
2766 /**
2767 * @brief Set the active input.
2768 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2769 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2770 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2771 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2772 * @param TIMx Timer instance
2773 * @param Channel This parameter can be one of the following values:
2774 * @arg @ref LL_TIM_CHANNEL_CH1
2775 * @arg @ref LL_TIM_CHANNEL_CH2
2776 * @arg @ref LL_TIM_CHANNEL_CH3
2777 * @arg @ref LL_TIM_CHANNEL_CH4
2778 * @param ICActiveInput This parameter can be one of the following values:
2779 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2780 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2781 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2782 * @retval None
2783 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)2784 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2785 {
2786 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2787 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2788 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2789 }
2790
2791 /**
2792 * @brief Get the current active input.
2793 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2794 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2795 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2796 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2797 * @param TIMx Timer instance
2798 * @param Channel This parameter can be one of the following values:
2799 * @arg @ref LL_TIM_CHANNEL_CH1
2800 * @arg @ref LL_TIM_CHANNEL_CH2
2801 * @arg @ref LL_TIM_CHANNEL_CH3
2802 * @arg @ref LL_TIM_CHANNEL_CH4
2803 * @retval Returned value can be one of the following values:
2804 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2805 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2806 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2807 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)2808 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
2809 {
2810 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2811 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2812 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2813 }
2814
2815 /**
2816 * @brief Set the prescaler of input channel.
2817 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2818 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2819 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2820 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2821 * @param TIMx Timer instance
2822 * @param Channel This parameter can be one of the following values:
2823 * @arg @ref LL_TIM_CHANNEL_CH1
2824 * @arg @ref LL_TIM_CHANNEL_CH2
2825 * @arg @ref LL_TIM_CHANNEL_CH3
2826 * @arg @ref LL_TIM_CHANNEL_CH4
2827 * @param ICPrescaler This parameter can be one of the following values:
2828 * @arg @ref LL_TIM_ICPSC_DIV1
2829 * @arg @ref LL_TIM_ICPSC_DIV2
2830 * @arg @ref LL_TIM_ICPSC_DIV4
2831 * @arg @ref LL_TIM_ICPSC_DIV8
2832 * @retval None
2833 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)2834 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2835 {
2836 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2837 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2838 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2839 }
2840
2841 /**
2842 * @brief Get the current prescaler value acting on an input channel.
2843 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2844 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2845 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2846 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2847 * @param TIMx Timer instance
2848 * @param Channel This parameter can be one of the following values:
2849 * @arg @ref LL_TIM_CHANNEL_CH1
2850 * @arg @ref LL_TIM_CHANNEL_CH2
2851 * @arg @ref LL_TIM_CHANNEL_CH3
2852 * @arg @ref LL_TIM_CHANNEL_CH4
2853 * @retval Returned value can be one of the following values:
2854 * @arg @ref LL_TIM_ICPSC_DIV1
2855 * @arg @ref LL_TIM_ICPSC_DIV2
2856 * @arg @ref LL_TIM_ICPSC_DIV4
2857 * @arg @ref LL_TIM_ICPSC_DIV8
2858 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)2859 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
2860 {
2861 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2862 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2863 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2864 }
2865
2866 /**
2867 * @brief Set the input filter duration.
2868 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2869 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
2870 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
2871 * CCMR2 IC4F LL_TIM_IC_SetFilter
2872 * @param TIMx Timer instance
2873 * @param Channel This parameter can be one of the following values:
2874 * @arg @ref LL_TIM_CHANNEL_CH1
2875 * @arg @ref LL_TIM_CHANNEL_CH2
2876 * @arg @ref LL_TIM_CHANNEL_CH3
2877 * @arg @ref LL_TIM_CHANNEL_CH4
2878 * @param ICFilter This parameter can be one of the following values:
2879 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2880 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2881 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2882 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2883 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2884 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2885 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2886 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2887 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2888 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2889 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2890 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2891 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2892 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2893 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2894 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2895 * @retval None
2896 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)2897 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2898 {
2899 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2900 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2901 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2902 }
2903
2904 /**
2905 * @brief Get the input filter duration.
2906 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2907 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
2908 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
2909 * CCMR2 IC4F LL_TIM_IC_GetFilter
2910 * @param TIMx Timer instance
2911 * @param Channel This parameter can be one of the following values:
2912 * @arg @ref LL_TIM_CHANNEL_CH1
2913 * @arg @ref LL_TIM_CHANNEL_CH2
2914 * @arg @ref LL_TIM_CHANNEL_CH3
2915 * @arg @ref LL_TIM_CHANNEL_CH4
2916 * @retval Returned value can be one of the following values:
2917 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2918 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2919 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2920 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2921 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2922 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2923 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2924 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2925 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2926 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2927 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2928 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2929 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2930 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2931 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2932 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2933 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)2934 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
2935 {
2936 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2937 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2938 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2939 }
2940
2941 /**
2942 * @brief Set the input channel polarity.
2943 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
2944 * CCER CC1NP LL_TIM_IC_SetPolarity\n
2945 * CCER CC2P LL_TIM_IC_SetPolarity\n
2946 * CCER CC2NP LL_TIM_IC_SetPolarity\n
2947 * CCER CC3P LL_TIM_IC_SetPolarity\n
2948 * CCER CC3NP LL_TIM_IC_SetPolarity\n
2949 * CCER CC4P LL_TIM_IC_SetPolarity\n
2950 * CCER CC4NP LL_TIM_IC_SetPolarity
2951 * @param TIMx Timer instance
2952 * @param Channel This parameter can be one of the following values:
2953 * @arg @ref LL_TIM_CHANNEL_CH1
2954 * @arg @ref LL_TIM_CHANNEL_CH2
2955 * @arg @ref LL_TIM_CHANNEL_CH3
2956 * @arg @ref LL_TIM_CHANNEL_CH4
2957 * @param ICPolarity This parameter can be one of the following values:
2958 * @arg @ref LL_TIM_IC_POLARITY_RISING
2959 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2960 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2961 * @retval None
2962 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)2963 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
2964 {
2965 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2966 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2967 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
2968 }
2969
2970 /**
2971 * @brief Get the current input channel polarity.
2972 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
2973 * CCER CC1NP LL_TIM_IC_GetPolarity\n
2974 * CCER CC2P LL_TIM_IC_GetPolarity\n
2975 * CCER CC2NP LL_TIM_IC_GetPolarity\n
2976 * CCER CC3P LL_TIM_IC_GetPolarity\n
2977 * CCER CC3NP LL_TIM_IC_GetPolarity\n
2978 * CCER CC4P LL_TIM_IC_GetPolarity\n
2979 * CCER CC4NP LL_TIM_IC_GetPolarity
2980 * @param TIMx Timer instance
2981 * @param Channel This parameter can be one of the following values:
2982 * @arg @ref LL_TIM_CHANNEL_CH1
2983 * @arg @ref LL_TIM_CHANNEL_CH2
2984 * @arg @ref LL_TIM_CHANNEL_CH3
2985 * @arg @ref LL_TIM_CHANNEL_CH4
2986 * @retval Returned value can be one of the following values:
2987 * @arg @ref LL_TIM_IC_POLARITY_RISING
2988 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2989 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2990 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2991 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2992 {
2993 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2994 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
2995 SHIFT_TAB_CCxP[iChannel]);
2996 }
2997
2998 /**
2999 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3000 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3001 * a timer instance provides an XOR input.
3002 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3003 * @param TIMx Timer instance
3004 * @retval None
3005 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)3006 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3007 {
3008 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3009 }
3010
3011 /**
3012 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3013 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3014 * a timer instance provides an XOR input.
3015 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3016 * @param TIMx Timer instance
3017 * @retval None
3018 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)3019 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3020 {
3021 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3022 }
3023
3024 /**
3025 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3026 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3027 * a timer instance provides an XOR input.
3028 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3029 * @param TIMx Timer instance
3030 * @retval State of bit (1 or 0).
3031 */
LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef * TIMx)3032 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
3033 {
3034 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3035 }
3036
3037 /**
3038 * @brief Get captured value for input channel 1.
3039 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3040 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3041 * whether or not a timer instance supports a 32 bits counter.
3042 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3043 * input channel 1 is supported by a timer instance.
3044 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3045 * @param TIMx Timer instance
3046 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3047 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)3048 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
3049 {
3050 return (uint32_t)(READ_REG(TIMx->CCR1));
3051 }
3052
3053 /**
3054 * @brief Get captured value for input channel 2.
3055 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3056 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3057 * whether or not a timer instance supports a 32 bits counter.
3058 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3059 * input channel 2 is supported by a timer instance.
3060 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3061 * @param TIMx Timer instance
3062 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3063 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)3064 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
3065 {
3066 return (uint32_t)(READ_REG(TIMx->CCR2));
3067 }
3068
3069 /**
3070 * @brief Get captured value for input channel 3.
3071 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3072 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3073 * whether or not a timer instance supports a 32 bits counter.
3074 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3075 * input channel 3 is supported by a timer instance.
3076 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3077 * @param TIMx Timer instance
3078 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3079 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)3080 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
3081 {
3082 return (uint32_t)(READ_REG(TIMx->CCR3));
3083 }
3084
3085 /**
3086 * @brief Get captured value for input channel 4.
3087 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3088 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3089 * whether or not a timer instance supports a 32 bits counter.
3090 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3091 * input channel 4 is supported by a timer instance.
3092 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3093 * @param TIMx Timer instance
3094 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3095 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)3096 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
3097 {
3098 return (uint32_t)(READ_REG(TIMx->CCR4));
3099 }
3100
3101 /**
3102 * @}
3103 */
3104
3105 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3106 * @{
3107 */
3108 /**
3109 * @brief Enable external clock mode 2.
3110 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3111 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3112 * whether or not a timer instance supports external clock mode2.
3113 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3114 * @param TIMx Timer instance
3115 * @retval None
3116 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3117 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3118 {
3119 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3120 }
3121
3122 /**
3123 * @brief Disable external clock mode 2.
3124 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3125 * whether or not a timer instance supports external clock mode2.
3126 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3127 * @param TIMx Timer instance
3128 * @retval None
3129 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3130 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3131 {
3132 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3133 }
3134
3135 /**
3136 * @brief Indicate whether external clock mode 2 is enabled.
3137 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3138 * whether or not a timer instance supports external clock mode2.
3139 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3140 * @param TIMx Timer instance
3141 * @retval State of bit (1 or 0).
3142 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)3143 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
3144 {
3145 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3146 }
3147
3148 /**
3149 * @brief Set the clock source of the counter clock.
3150 * @note when selected clock source is external clock mode 1, the timer input
3151 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3152 * function. This timer input must be configured by calling
3153 * the @ref LL_TIM_IC_Config() function.
3154 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3155 * whether or not a timer instance supports external clock mode1.
3156 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3157 * whether or not a timer instance supports external clock mode2.
3158 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3159 * SMCR ECE LL_TIM_SetClockSource
3160 * @param TIMx Timer instance
3161 * @param ClockSource This parameter can be one of the following values:
3162 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3163 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3164 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3165 * @retval None
3166 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3167 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3168 {
3169 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3170 }
3171
3172 /**
3173 * @brief Set the encoder interface mode.
3174 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3175 * whether or not a timer instance supports the encoder mode.
3176 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3177 * @param TIMx Timer instance
3178 * @param EncoderMode This parameter can be one of the following values:
3179 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3180 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3181 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3182 * @retval None
3183 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3184 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3185 {
3186 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3187 }
3188
3189 /**
3190 * @}
3191 */
3192
3193 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3194 * @{
3195 */
3196 /**
3197 * @brief Set the trigger output (TRGO) used for timer synchronization .
3198 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3199 * whether or not a timer instance can operate as a master timer.
3200 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3201 * @param TIMx Timer instance
3202 * @param TimerSynchronization This parameter can be one of the following values:
3203 * @arg @ref LL_TIM_TRGO_RESET
3204 * @arg @ref LL_TIM_TRGO_ENABLE
3205 * @arg @ref LL_TIM_TRGO_UPDATE
3206 * @arg @ref LL_TIM_TRGO_CC1IF
3207 * @arg @ref LL_TIM_TRGO_OC1REF
3208 * @arg @ref LL_TIM_TRGO_OC2REF
3209 * @arg @ref LL_TIM_TRGO_OC3REF
3210 * @arg @ref LL_TIM_TRGO_OC4REF
3211 * @retval None
3212 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3213 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3214 {
3215 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3216 }
3217
3218 /**
3219 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3220 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3221 * whether or not a timer instance can be used for ADC synchronization.
3222 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3223 * @param TIMx Timer Instance
3224 * @param ADCSynchronization This parameter can be one of the following values:
3225 * @arg @ref LL_TIM_TRGO2_RESET
3226 * @arg @ref LL_TIM_TRGO2_ENABLE
3227 * @arg @ref LL_TIM_TRGO2_UPDATE
3228 * @arg @ref LL_TIM_TRGO2_CC1F
3229 * @arg @ref LL_TIM_TRGO2_OC1
3230 * @arg @ref LL_TIM_TRGO2_OC2
3231 * @arg @ref LL_TIM_TRGO2_OC3
3232 * @arg @ref LL_TIM_TRGO2_OC4
3233 * @arg @ref LL_TIM_TRGO2_OC5
3234 * @arg @ref LL_TIM_TRGO2_OC6
3235 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3236 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3237 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3238 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3239 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3240 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3241 * @retval None
3242 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)3243 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3244 {
3245 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3246 }
3247
3248 /**
3249 * @brief Set the synchronization mode of a slave timer.
3250 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3251 * a timer instance can operate as a slave timer.
3252 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3253 * @param TIMx Timer instance
3254 * @param SlaveMode This parameter can be one of the following values:
3255 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3256 * @arg @ref LL_TIM_SLAVEMODE_RESET
3257 * @arg @ref LL_TIM_SLAVEMODE_GATED
3258 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3259 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3260 * @retval None
3261 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3262 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3263 {
3264 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3265 }
3266
3267 /**
3268 * @brief Set the selects the trigger input to be used to synchronize the counter.
3269 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3270 * a timer instance can operate as a slave timer.
3271 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3272 * @param TIMx Timer instance
3273 * @param TriggerInput This parameter can be one of the following values:
3274 * @arg @ref LL_TIM_TS_ITR0
3275 * @arg @ref LL_TIM_TS_ITR1
3276 * @arg @ref LL_TIM_TS_ITR2
3277 * @arg @ref LL_TIM_TS_ITR3
3278 * @arg @ref LL_TIM_TS_ITR7 (*)
3279 * @arg @ref LL_TIM_TS_TI1F_ED
3280 * @arg @ref LL_TIM_TS_TI1FP1
3281 * @arg @ref LL_TIM_TS_TI2FP2
3282 * @arg @ref LL_TIM_TS_ETRF
3283 *
3284 * (*) Value not defined in all devices.
3285 * @retval None
3286 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)3287 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3288 {
3289 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3290 }
3291
3292 /**
3293 * @brief Enable the Master/Slave mode.
3294 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3295 * a timer instance can operate as a slave timer.
3296 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3297 * @param TIMx Timer instance
3298 * @retval None
3299 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)3300 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3301 {
3302 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3303 }
3304
3305 /**
3306 * @brief Disable the Master/Slave mode.
3307 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3308 * a timer instance can operate as a slave timer.
3309 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3310 * @param TIMx Timer instance
3311 * @retval None
3312 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)3313 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3314 {
3315 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3316 }
3317
3318 /**
3319 * @brief Indicates whether the Master/Slave mode is enabled.
3320 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3321 * a timer instance can operate as a slave timer.
3322 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3323 * @param TIMx Timer instance
3324 * @retval State of bit (1 or 0).
3325 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)3326 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
3327 {
3328 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3329 }
3330
3331 /**
3332 * @brief Configure the external trigger (ETR) input.
3333 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3334 * a timer instance provides an external trigger input.
3335 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3336 * SMCR ETPS LL_TIM_ConfigETR\n
3337 * SMCR ETF LL_TIM_ConfigETR
3338 * @param TIMx Timer instance
3339 * @param ETRPolarity This parameter can be one of the following values:
3340 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3341 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3342 * @param ETRPrescaler This parameter can be one of the following values:
3343 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3344 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3345 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3346 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3347 * @param ETRFilter This parameter can be one of the following values:
3348 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3349 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3350 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3351 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3352 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3353 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3354 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3355 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3356 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3357 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3358 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3359 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3360 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3361 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3362 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3363 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3364 * @retval None
3365 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)3366 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3367 uint32_t ETRFilter)
3368 {
3369 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3370 }
3371
3372 /**
3373 * @brief Select the external trigger (ETR) input source.
3374 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
3375 * not a timer instance supports ETR source selection.
3376 * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
3377 * @param TIMx Timer instance
3378 * @param ETRSource This parameter can be one of the following values:
3379 * TIM1
3380 *
3381 * @arg @ref LL_TIM_ETRSOURCE_GPIO
3382 * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD1
3383 * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD2
3384 * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD3
3385 *
3386 * TIM2 (*)
3387 *
3388 * @arg @ref LL_TIM_ETRSOURCE_GPIO
3389 * @arg @ref LL_TIM_ETRSOURCE_LSE
3390 * @arg @ref LL_TIM_ETRSOURCE_MCO
3391 * @arg @ref LL_TIM_ETRSOURCE_MCO2
3392 *
3393 * (*) Timer instance not available on all devices \n
3394 * @retval None
3395 */
LL_TIM_SetETRSource(TIM_TypeDef * TIMx,uint32_t ETRSource)3396 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
3397 {
3398 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
3399 }
3400
3401 /**
3402 * @}
3403 */
3404
3405 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
3406 * @{
3407 */
3408 /**
3409 * @brief Enable the break function.
3410 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3411 * a timer instance provides a break input.
3412 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3413 * @param TIMx Timer instance
3414 * @retval None
3415 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)3416 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3417 {
3418 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3419 }
3420
3421 /**
3422 * @brief Disable the break function.
3423 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3424 * @param TIMx Timer instance
3425 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3426 * a timer instance provides a break input.
3427 * @retval None
3428 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)3429 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3430 {
3431 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3432 }
3433
3434 /**
3435 * @brief Configure the break input.
3436 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3437 * a timer instance provides a break input.
3438 * @note Bidirectional mode is only supported by advanced timer instances.
3439 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3440 * a timer instance is an advanced-control timer.
3441 * @note In bidirectional mode (BKBID bit set), the Break input is configured both
3442 * in input mode and in open drain output mode. Any active Break event will
3443 * assert a low logic level on the Break input to indicate an internal break
3444 * event to external devices.
3445 * @note When bidirectional mode isn't supported, BreakAFMode must be set to
3446 * LL_TIM_BREAK_AFMODE_INPUT.
3447 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3448 * BDTR BKF LL_TIM_ConfigBRK\n
3449 * BDTR BKBID LL_TIM_ConfigBRK
3450 * @param TIMx Timer instance
3451 * @param BreakPolarity This parameter can be one of the following values:
3452 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3453 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3454 * @param BreakFilter This parameter can be one of the following values:
3455 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3456 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3457 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3458 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3459 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3460 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3461 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3462 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3463 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3464 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3465 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3466 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3467 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3468 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3469 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3470 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3471 * @param BreakAFMode This parameter can be one of the following values:
3472 * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
3473 * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
3474 * @retval None
3475 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter,uint32_t BreakAFMode)3476 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
3477 uint32_t BreakAFMode)
3478 {
3479 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
3480 }
3481
3482 /**
3483 * @brief Disarm the break input (when it operates in bidirectional mode).
3484 * @note The break input can be disarmed only when it is configured in
3485 * bidirectional mode and when when MOE is reset.
3486 * @note Purpose is to be able to have the input voltage back to high-state,
3487 * whatever the time constant on the output .
3488 * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
3489 * @param TIMx Timer instance
3490 * @retval None
3491 */
LL_TIM_DisarmBRK(TIM_TypeDef * TIMx)3492 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
3493 {
3494 SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
3495 }
3496
3497 /**
3498 * @brief Enable the break 2 function.
3499 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3500 * a timer instance provides a second break input.
3501 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
3502 * @param TIMx Timer instance
3503 * @retval None
3504 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)3505 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
3506 {
3507 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3508 }
3509
3510 /**
3511 * @brief Disable the break 2 function.
3512 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3513 * a timer instance provides a second break input.
3514 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
3515 * @param TIMx Timer instance
3516 * @retval None
3517 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)3518 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
3519 {
3520 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3521 }
3522
3523 /**
3524 * @brief Configure the break 2 input.
3525 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3526 * a timer instance provides a second break input.
3527 * @note Bidirectional mode is only supported by advanced timer instances.
3528 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3529 * a timer instance is an advanced-control timer.
3530 * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
3531 * in input mode and in open drain output mode. Any active Break event will
3532 * assert a low logic level on the Break 2 input to indicate an internal break
3533 * event to external devices.
3534 * @note When bidirectional mode isn't supported, Break2AFMode must be set to
3535 * LL_TIM_BREAK2_AFMODE_INPUT.
3536 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3537 * BDTR BK2F LL_TIM_ConfigBRK2\n
3538 * BDTR BK2BID LL_TIM_ConfigBRK2
3539 * @param TIMx Timer instance
3540 * @param Break2Polarity This parameter can be one of the following values:
3541 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3542 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3543 * @param Break2Filter This parameter can be one of the following values:
3544 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3545 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3546 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3547 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3548 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3549 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3550 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3551 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3552 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3553 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3554 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3555 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3556 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3557 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3558 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3559 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3560 * @param Break2AFMode This parameter can be one of the following values:
3561 * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
3562 * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
3563 * @retval None
3564 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter,uint32_t Break2AFMode)3565 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
3566 uint32_t Break2AFMode)
3567 {
3568 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
3569 }
3570
3571 /**
3572 * @brief Disarm the break 2 input (when it operates in bidirectional mode).
3573 * @note The break 2 input can be disarmed only when it is configured in
3574 * bidirectional mode and when when MOE is reset.
3575 * @note Purpose is to be able to have the input voltage back to high-state,
3576 * whatever the time constant on the output.
3577 * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
3578 * @param TIMx Timer instance
3579 * @retval None
3580 */
LL_TIM_DisarmBRK2(TIM_TypeDef * TIMx)3581 __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
3582 {
3583 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
3584 }
3585
3586 /**
3587 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
3588 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3589 * a timer instance provides a break input.
3590 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
3591 * BDTR OSSR LL_TIM_SetOffStates
3592 * @param TIMx Timer instance
3593 * @param OffStateIdle This parameter can be one of the following values:
3594 * @arg @ref LL_TIM_OSSI_DISABLE
3595 * @arg @ref LL_TIM_OSSI_ENABLE
3596 * @param OffStateRun This parameter can be one of the following values:
3597 * @arg @ref LL_TIM_OSSR_DISABLE
3598 * @arg @ref LL_TIM_OSSR_ENABLE
3599 * @retval None
3600 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)3601 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
3602 {
3603 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
3604 }
3605
3606 /**
3607 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
3608 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3609 * a timer instance provides a break input.
3610 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
3611 * @param TIMx Timer instance
3612 * @retval None
3613 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)3614 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
3615 {
3616 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3617 }
3618
3619 /**
3620 * @brief Disable automatic output (MOE can be set only by software).
3621 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3622 * a timer instance provides a break input.
3623 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
3624 * @param TIMx Timer instance
3625 * @retval None
3626 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)3627 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
3628 {
3629 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3630 }
3631
3632 /**
3633 * @brief Indicate whether automatic output is enabled.
3634 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3635 * a timer instance provides a break input.
3636 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
3637 * @param TIMx Timer instance
3638 * @retval State of bit (1 or 0).
3639 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)3640 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
3641 {
3642 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
3643 }
3644
3645 /**
3646 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
3647 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3648 * software and is reset in case of break or break2 event
3649 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3650 * a timer instance provides a break input.
3651 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
3652 * @param TIMx Timer instance
3653 * @retval None
3654 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)3655 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
3656 {
3657 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3658 }
3659
3660 /**
3661 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3662 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3663 * software and is reset in case of break or break2 event.
3664 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3665 * a timer instance provides a break input.
3666 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3667 * @param TIMx Timer instance
3668 * @retval None
3669 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)3670 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3671 {
3672 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3673 }
3674
3675 /**
3676 * @brief Indicates whether outputs are enabled.
3677 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3678 * a timer instance provides a break input.
3679 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3680 * @param TIMx Timer instance
3681 * @retval State of bit (1 or 0).
3682 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)3683 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
3684 {
3685 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3686 }
3687
3688 /**
3689 * @brief Enable the signals connected to the designated timer break input.
3690 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3691 * or not a timer instance allows for break input selection.
3692 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
3693 * AF2 BK2INE LL_TIM_EnableBreakInputSource\n
3694 * @param TIMx Timer instance
3695 * @param BreakInput This parameter can be one of the following values:
3696 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3697 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3698 * @param Source This parameter can be one of the following values:
3699 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3700 *
3701 * @retval None
3702 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3703 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3704 {
3705 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3706 SET_BIT(*pReg, Source);
3707 }
3708
3709 /**
3710 * @brief Disable the signals connected to the designated timer break input.
3711 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3712 * or not a timer instance allows for break input selection.
3713 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
3714 * AF2 BK2INE LL_TIM_DisableBreakInputSource\n
3715 * @param TIMx Timer instance
3716 * @param BreakInput This parameter can be one of the following values:
3717 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3718 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3719 * @param Source This parameter can be one of the following values:
3720 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3721 *
3722 * @retval None
3723 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3724 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3725 {
3726 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3727 CLEAR_BIT(*pReg, Source);
3728 }
3729
3730 /**
3731 * @brief Set the polarity of the break signal for the timer break input.
3732 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3733 * or not a timer instance allows for break input selection.
3734 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
3735 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
3736 * @param TIMx Timer instance
3737 * @param BreakInput This parameter can be one of the following values:
3738 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3739 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3740 * @param Source This parameter can be one of the following values:
3741 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3742 * @param Polarity This parameter can be one of the following values:
3743 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
3744 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
3745 * @retval None
3746 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)3747 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
3748 uint32_t Polarity)
3749 {
3750 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3751 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
3752 }
3753 /**
3754 * @}
3755 */
3756
3757 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
3758 * @{
3759 */
3760 /**
3761 * @brief Configures the timer DMA burst feature.
3762 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
3763 * not a timer instance supports the DMA burst mode.
3764 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
3765 * DCR DBA LL_TIM_ConfigDMABurst
3766 * @param TIMx Timer instance
3767 * @param DMABurstBaseAddress This parameter can be one of the following values:
3768 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3769 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3770 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3771 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3772 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3773 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3774 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3775 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3776 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3777 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3778 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3779 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3780 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3781 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3782 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3783 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3784 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3785 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3786 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
3787 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
3788 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
3789 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
3790 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
3791 * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
3792 * @param DMABurstLength This parameter can be one of the following values:
3793 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3794 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3795 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3796 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3797 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3798 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3799 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3800 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3801 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3802 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3803 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3804 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3805 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3806 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3807 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3808 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3809 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3810 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3811 * @retval None
3812 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)3813 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3814 {
3815 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
3816 }
3817
3818 /**
3819 * @}
3820 */
3821
3822 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3823 * @{
3824 */
3825 /**
3826 * @brief Remap TIM inputs (input channel, internal/external triggers).
3827 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3828 * a some timer inputs can be remapped.
3829 * @rmtoll TIM1_TISEL TI1SEL LL_TIM_SetRemap\n
3830 * TIM1_TISEL TI2SEL LL_TIM_SetRemap\n
3831 * TIM1_TISEL TI3SEL LL_TIM_SetRemap\n
3832 * TIM1_TISEL TI4SEL LL_TIM_SetRemap\n
3833 * TIM2_TISEL TI1SEL LL_TIM_SetRemap\n
3834 * TIM2_TISEL TI2SEL LL_TIM_SetRemap\n
3835 * TIM2_TISEL TI3SEL LL_TIM_SetRemap\n
3836 * TIM2_TISEL TI4SEL LL_TIM_SetRemap\n
3837 * TIM3_TISEL TI1SEL LL_TIM_SetRemap\n
3838 * TIM3_TISEL TI2SEL LL_TIM_SetRemap\n
3839 * TIM3_TISEL TI3SEL LL_TIM_SetRemap\n
3840 * TIM3_TISEL TI4SEL LL_TIM_SetRemap\n
3841 * TIM14_TISEL TI1SEL LL_TIM_SetRemap\n
3842 * TIM16_TISEL TI1SEL LL_TIM_SetRemap\n
3843 * TIM17_TISEL TI1SEL LL_TIM_SetRemap
3844 * @param TIMx Timer instance
3845 * @param Remap Remap param depends on the TIMx. Description available only
3846 * in CHM version of the User Manual (not in .pdf).
3847 * Otherwise see Reference Manual description of TISEL registers.
3848 *
3849 * Below description summarizes "Timer Instance" and "Remap" param combinations:
3850 *
3851 * TIM14: one of the following values
3852 *
3853 * @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO
3854 * @arg @ref LL_TIM_TIM14_TI1_RMP_RTC_CLK
3855 * @arg @ref LL_TIM_TIM14_TI1_RMP_HSE_32
3856 * @arg @ref LL_TIM_TIM14_TI1_RMP_MCO
3857 * @arg @ref LL_TIM_TIM14_TI1_RMP_MCO2
3858 *
3859 * TIM16: one of the following values
3860 *
3861 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
3862 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
3863 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
3864 * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO2
3865 *
3866 * TIM17: one of the following values
3867 *
3868 * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
3869 * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
3870 * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
3871 * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO2
3872 * @retval None
3873 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)3874 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
3875 {
3876 MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
3877 }
3878
3879 /**
3880 * @}
3881 */
3882
3883 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
3884 * @{
3885 */
3886 /**
3887 * @brief Set the OCREF clear input source
3888 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
3889 * @note This function can only be used in Output compare and PWM modes.
3890 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
3891 * @param TIMx Timer instance
3892 * @param OCRefClearInputSource This parameter can be one of the following values:
3893 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
3894 * @retval None
3895 */
LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx,uint32_t OCRefClearInputSource)3896 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
3897 {
3898 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS,
3899 ((OCRefClearInputSource & OCREF_CLEAR_SELECT_MSK) >> OCREF_CLEAR_SELECT_POS) << TIM_SMCR_OCCS_Pos);
3900 }
3901 /**
3902 * @}
3903 */
3904
3905 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
3906 * @{
3907 */
3908 /**
3909 * @brief Clear the update interrupt flag (UIF).
3910 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
3911 * @param TIMx Timer instance
3912 * @retval None
3913 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)3914 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
3915 {
3916 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
3917 }
3918
3919 /**
3920 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
3921 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
3922 * @param TIMx Timer instance
3923 * @retval State of bit (1 or 0).
3924 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)3925 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
3926 {
3927 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
3928 }
3929
3930 /**
3931 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
3932 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
3933 * @param TIMx Timer instance
3934 * @retval None
3935 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)3936 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
3937 {
3938 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
3939 }
3940
3941 /**
3942 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
3943 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
3944 * @param TIMx Timer instance
3945 * @retval State of bit (1 or 0).
3946 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)3947 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
3948 {
3949 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
3950 }
3951
3952 /**
3953 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
3954 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
3955 * @param TIMx Timer instance
3956 * @retval None
3957 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)3958 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
3959 {
3960 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
3961 }
3962
3963 /**
3964 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
3965 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
3966 * @param TIMx Timer instance
3967 * @retval State of bit (1 or 0).
3968 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)3969 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
3970 {
3971 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
3972 }
3973
3974 /**
3975 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
3976 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
3977 * @param TIMx Timer instance
3978 * @retval None
3979 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)3980 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
3981 {
3982 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
3983 }
3984
3985 /**
3986 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
3987 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
3988 * @param TIMx Timer instance
3989 * @retval State of bit (1 or 0).
3990 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)3991 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
3992 {
3993 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
3994 }
3995
3996 /**
3997 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
3998 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
3999 * @param TIMx Timer instance
4000 * @retval None
4001 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)4002 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
4003 {
4004 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
4005 }
4006
4007 /**
4008 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
4009 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
4010 * @param TIMx Timer instance
4011 * @retval State of bit (1 or 0).
4012 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)4013 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
4014 {
4015 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
4016 }
4017
4018 /**
4019 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
4020 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
4021 * @param TIMx Timer instance
4022 * @retval None
4023 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)4024 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
4025 {
4026 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
4027 }
4028
4029 /**
4030 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
4031 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
4032 * @param TIMx Timer instance
4033 * @retval State of bit (1 or 0).
4034 */
LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef * TIMx)4035 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
4036 {
4037 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
4038 }
4039
4040 /**
4041 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
4042 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
4043 * @param TIMx Timer instance
4044 * @retval None
4045 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)4046 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
4047 {
4048 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
4049 }
4050
4051 /**
4052 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
4053 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
4054 * @param TIMx Timer instance
4055 * @retval State of bit (1 or 0).
4056 */
LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef * TIMx)4057 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
4058 {
4059 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
4060 }
4061
4062 /**
4063 * @brief Clear the commutation interrupt flag (COMIF).
4064 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
4065 * @param TIMx Timer instance
4066 * @retval None
4067 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)4068 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
4069 {
4070 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
4071 }
4072
4073 /**
4074 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
4075 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
4076 * @param TIMx Timer instance
4077 * @retval State of bit (1 or 0).
4078 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)4079 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
4080 {
4081 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
4082 }
4083
4084 /**
4085 * @brief Clear the trigger interrupt flag (TIF).
4086 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
4087 * @param TIMx Timer instance
4088 * @retval None
4089 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)4090 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
4091 {
4092 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
4093 }
4094
4095 /**
4096 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
4097 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
4098 * @param TIMx Timer instance
4099 * @retval State of bit (1 or 0).
4100 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)4101 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
4102 {
4103 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
4104 }
4105
4106 /**
4107 * @brief Clear the break interrupt flag (BIF).
4108 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
4109 * @param TIMx Timer instance
4110 * @retval None
4111 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)4112 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
4113 {
4114 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
4115 }
4116
4117 /**
4118 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
4119 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
4120 * @param TIMx Timer instance
4121 * @retval State of bit (1 or 0).
4122 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)4123 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
4124 {
4125 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
4126 }
4127
4128 /**
4129 * @brief Clear the break 2 interrupt flag (B2IF).
4130 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
4131 * @param TIMx Timer instance
4132 * @retval None
4133 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)4134 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
4135 {
4136 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
4137 }
4138
4139 /**
4140 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
4141 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
4142 * @param TIMx Timer instance
4143 * @retval State of bit (1 or 0).
4144 */
LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef * TIMx)4145 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
4146 {
4147 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
4148 }
4149
4150 /**
4151 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
4152 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
4153 * @param TIMx Timer instance
4154 * @retval None
4155 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)4156 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
4157 {
4158 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
4159 }
4160
4161 /**
4162 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
4163 * (Capture/Compare 1 interrupt is pending).
4164 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
4165 * @param TIMx Timer instance
4166 * @retval State of bit (1 or 0).
4167 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)4168 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
4169 {
4170 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
4171 }
4172
4173 /**
4174 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
4175 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
4176 * @param TIMx Timer instance
4177 * @retval None
4178 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)4179 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
4180 {
4181 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
4182 }
4183
4184 /**
4185 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
4186 * (Capture/Compare 2 over-capture interrupt is pending).
4187 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
4188 * @param TIMx Timer instance
4189 * @retval State of bit (1 or 0).
4190 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)4191 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
4192 {
4193 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
4194 }
4195
4196 /**
4197 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
4198 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
4199 * @param TIMx Timer instance
4200 * @retval None
4201 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)4202 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
4203 {
4204 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
4205 }
4206
4207 /**
4208 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
4209 * (Capture/Compare 3 over-capture interrupt is pending).
4210 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
4211 * @param TIMx Timer instance
4212 * @retval State of bit (1 or 0).
4213 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)4214 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
4215 {
4216 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
4217 }
4218
4219 /**
4220 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
4221 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
4222 * @param TIMx Timer instance
4223 * @retval None
4224 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)4225 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
4226 {
4227 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
4228 }
4229
4230 /**
4231 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
4232 * (Capture/Compare 4 over-capture interrupt is pending).
4233 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
4234 * @param TIMx Timer instance
4235 * @retval State of bit (1 or 0).
4236 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)4237 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
4238 {
4239 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
4240 }
4241
4242 /**
4243 * @brief Clear the system break interrupt flag (SBIF).
4244 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
4245 * @param TIMx Timer instance
4246 * @retval None
4247 */
LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)4248 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
4249 {
4250 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
4251 }
4252
4253 /**
4254 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
4255 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
4256 * @param TIMx Timer instance
4257 * @retval State of bit (1 or 0).
4258 */
LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef * TIMx)4259 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
4260 {
4261 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
4262 }
4263
4264 /**
4265 * @}
4266 */
4267
4268 /** @defgroup TIM_LL_EF_IT_Management IT-Management
4269 * @{
4270 */
4271 /**
4272 * @brief Enable update interrupt (UIE).
4273 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
4274 * @param TIMx Timer instance
4275 * @retval None
4276 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)4277 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
4278 {
4279 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
4280 }
4281
4282 /**
4283 * @brief Disable update interrupt (UIE).
4284 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
4285 * @param TIMx Timer instance
4286 * @retval None
4287 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)4288 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
4289 {
4290 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
4291 }
4292
4293 /**
4294 * @brief Indicates whether the update interrupt (UIE) is enabled.
4295 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
4296 * @param TIMx Timer instance
4297 * @retval State of bit (1 or 0).
4298 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)4299 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
4300 {
4301 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
4302 }
4303
4304 /**
4305 * @brief Enable capture/compare 1 interrupt (CC1IE).
4306 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
4307 * @param TIMx Timer instance
4308 * @retval None
4309 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)4310 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
4311 {
4312 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4313 }
4314
4315 /**
4316 * @brief Disable capture/compare 1 interrupt (CC1IE).
4317 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
4318 * @param TIMx Timer instance
4319 * @retval None
4320 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)4321 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
4322 {
4323 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4324 }
4325
4326 /**
4327 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
4328 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
4329 * @param TIMx Timer instance
4330 * @retval State of bit (1 or 0).
4331 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)4332 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
4333 {
4334 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
4335 }
4336
4337 /**
4338 * @brief Enable capture/compare 2 interrupt (CC2IE).
4339 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
4340 * @param TIMx Timer instance
4341 * @retval None
4342 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)4343 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
4344 {
4345 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4346 }
4347
4348 /**
4349 * @brief Disable capture/compare 2 interrupt (CC2IE).
4350 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
4351 * @param TIMx Timer instance
4352 * @retval None
4353 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)4354 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
4355 {
4356 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4357 }
4358
4359 /**
4360 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
4361 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
4362 * @param TIMx Timer instance
4363 * @retval State of bit (1 or 0).
4364 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)4365 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
4366 {
4367 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
4368 }
4369
4370 /**
4371 * @brief Enable capture/compare 3 interrupt (CC3IE).
4372 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
4373 * @param TIMx Timer instance
4374 * @retval None
4375 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)4376 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
4377 {
4378 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4379 }
4380
4381 /**
4382 * @brief Disable capture/compare 3 interrupt (CC3IE).
4383 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
4384 * @param TIMx Timer instance
4385 * @retval None
4386 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)4387 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
4388 {
4389 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4390 }
4391
4392 /**
4393 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
4394 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
4395 * @param TIMx Timer instance
4396 * @retval State of bit (1 or 0).
4397 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)4398 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
4399 {
4400 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
4401 }
4402
4403 /**
4404 * @brief Enable capture/compare 4 interrupt (CC4IE).
4405 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
4406 * @param TIMx Timer instance
4407 * @retval None
4408 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)4409 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
4410 {
4411 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4412 }
4413
4414 /**
4415 * @brief Disable capture/compare 4 interrupt (CC4IE).
4416 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
4417 * @param TIMx Timer instance
4418 * @retval None
4419 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)4420 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
4421 {
4422 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4423 }
4424
4425 /**
4426 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
4427 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
4428 * @param TIMx Timer instance
4429 * @retval State of bit (1 or 0).
4430 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)4431 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
4432 {
4433 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
4434 }
4435
4436 /**
4437 * @brief Enable commutation interrupt (COMIE).
4438 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
4439 * @param TIMx Timer instance
4440 * @retval None
4441 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)4442 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
4443 {
4444 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
4445 }
4446
4447 /**
4448 * @brief Disable commutation interrupt (COMIE).
4449 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
4450 * @param TIMx Timer instance
4451 * @retval None
4452 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)4453 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
4454 {
4455 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
4456 }
4457
4458 /**
4459 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
4460 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
4461 * @param TIMx Timer instance
4462 * @retval State of bit (1 or 0).
4463 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)4464 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
4465 {
4466 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
4467 }
4468
4469 /**
4470 * @brief Enable trigger interrupt (TIE).
4471 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
4472 * @param TIMx Timer instance
4473 * @retval None
4474 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)4475 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
4476 {
4477 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
4478 }
4479
4480 /**
4481 * @brief Disable trigger interrupt (TIE).
4482 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
4483 * @param TIMx Timer instance
4484 * @retval None
4485 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)4486 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
4487 {
4488 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
4489 }
4490
4491 /**
4492 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
4493 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
4494 * @param TIMx Timer instance
4495 * @retval State of bit (1 or 0).
4496 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)4497 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
4498 {
4499 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
4500 }
4501
4502 /**
4503 * @brief Enable break interrupt (BIE).
4504 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
4505 * @param TIMx Timer instance
4506 * @retval None
4507 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)4508 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
4509 {
4510 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
4511 }
4512
4513 /**
4514 * @brief Disable break interrupt (BIE).
4515 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
4516 * @param TIMx Timer instance
4517 * @retval None
4518 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)4519 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
4520 {
4521 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
4522 }
4523
4524 /**
4525 * @brief Indicates whether the break interrupt (BIE) is enabled.
4526 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
4527 * @param TIMx Timer instance
4528 * @retval State of bit (1 or 0).
4529 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)4530 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
4531 {
4532 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
4533 }
4534
4535 /**
4536 * @}
4537 */
4538
4539 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
4540 * @{
4541 */
4542 /**
4543 * @brief Enable update DMA request (UDE).
4544 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
4545 * @param TIMx Timer instance
4546 * @retval None
4547 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)4548 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4549 {
4550 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
4551 }
4552
4553 /**
4554 * @brief Disable update DMA request (UDE).
4555 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
4556 * @param TIMx Timer instance
4557 * @retval None
4558 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)4559 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4560 {
4561 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
4562 }
4563
4564 /**
4565 * @brief Indicates whether the update DMA request (UDE) is enabled.
4566 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
4567 * @param TIMx Timer instance
4568 * @retval State of bit (1 or 0).
4569 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)4570 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
4571 {
4572 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
4573 }
4574
4575 /**
4576 * @brief Enable capture/compare 1 DMA request (CC1DE).
4577 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
4578 * @param TIMx Timer instance
4579 * @retval None
4580 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)4581 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
4582 {
4583 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4584 }
4585
4586 /**
4587 * @brief Disable capture/compare 1 DMA request (CC1DE).
4588 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
4589 * @param TIMx Timer instance
4590 * @retval None
4591 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)4592 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
4593 {
4594 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4595 }
4596
4597 /**
4598 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
4599 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
4600 * @param TIMx Timer instance
4601 * @retval State of bit (1 or 0).
4602 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)4603 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
4604 {
4605 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
4606 }
4607
4608 /**
4609 * @brief Enable capture/compare 2 DMA request (CC2DE).
4610 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
4611 * @param TIMx Timer instance
4612 * @retval None
4613 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)4614 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
4615 {
4616 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4617 }
4618
4619 /**
4620 * @brief Disable capture/compare 2 DMA request (CC2DE).
4621 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
4622 * @param TIMx Timer instance
4623 * @retval None
4624 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)4625 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
4626 {
4627 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4628 }
4629
4630 /**
4631 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
4632 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
4633 * @param TIMx Timer instance
4634 * @retval State of bit (1 or 0).
4635 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)4636 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
4637 {
4638 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
4639 }
4640
4641 /**
4642 * @brief Enable capture/compare 3 DMA request (CC3DE).
4643 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
4644 * @param TIMx Timer instance
4645 * @retval None
4646 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)4647 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
4648 {
4649 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4650 }
4651
4652 /**
4653 * @brief Disable capture/compare 3 DMA request (CC3DE).
4654 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
4655 * @param TIMx Timer instance
4656 * @retval None
4657 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)4658 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
4659 {
4660 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4661 }
4662
4663 /**
4664 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
4665 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
4666 * @param TIMx Timer instance
4667 * @retval State of bit (1 or 0).
4668 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)4669 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
4670 {
4671 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
4672 }
4673
4674 /**
4675 * @brief Enable capture/compare 4 DMA request (CC4DE).
4676 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
4677 * @param TIMx Timer instance
4678 * @retval None
4679 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)4680 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
4681 {
4682 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4683 }
4684
4685 /**
4686 * @brief Disable capture/compare 4 DMA request (CC4DE).
4687 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
4688 * @param TIMx Timer instance
4689 * @retval None
4690 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)4691 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
4692 {
4693 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4694 }
4695
4696 /**
4697 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
4698 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
4699 * @param TIMx Timer instance
4700 * @retval State of bit (1 or 0).
4701 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)4702 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
4703 {
4704 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
4705 }
4706
4707 /**
4708 * @brief Enable commutation DMA request (COMDE).
4709 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
4710 * @param TIMx Timer instance
4711 * @retval None
4712 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)4713 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
4714 {
4715 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
4716 }
4717
4718 /**
4719 * @brief Disable commutation DMA request (COMDE).
4720 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
4721 * @param TIMx Timer instance
4722 * @retval None
4723 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)4724 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
4725 {
4726 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
4727 }
4728
4729 /**
4730 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
4731 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
4732 * @param TIMx Timer instance
4733 * @retval State of bit (1 or 0).
4734 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)4735 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
4736 {
4737 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
4738 }
4739
4740 /**
4741 * @brief Enable trigger interrupt (TDE).
4742 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
4743 * @param TIMx Timer instance
4744 * @retval None
4745 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)4746 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
4747 {
4748 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
4749 }
4750
4751 /**
4752 * @brief Disable trigger interrupt (TDE).
4753 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
4754 * @param TIMx Timer instance
4755 * @retval None
4756 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)4757 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
4758 {
4759 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
4760 }
4761
4762 /**
4763 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
4764 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
4765 * @param TIMx Timer instance
4766 * @retval State of bit (1 or 0).
4767 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)4768 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
4769 {
4770 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
4771 }
4772
4773 /**
4774 * @}
4775 */
4776
4777 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
4778 * @{
4779 */
4780 /**
4781 * @brief Generate an update event.
4782 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
4783 * @param TIMx Timer instance
4784 * @retval None
4785 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)4786 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
4787 {
4788 SET_BIT(TIMx->EGR, TIM_EGR_UG);
4789 }
4790
4791 /**
4792 * @brief Generate Capture/Compare 1 event.
4793 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
4794 * @param TIMx Timer instance
4795 * @retval None
4796 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)4797 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
4798 {
4799 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
4800 }
4801
4802 /**
4803 * @brief Generate Capture/Compare 2 event.
4804 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
4805 * @param TIMx Timer instance
4806 * @retval None
4807 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)4808 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
4809 {
4810 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
4811 }
4812
4813 /**
4814 * @brief Generate Capture/Compare 3 event.
4815 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
4816 * @param TIMx Timer instance
4817 * @retval None
4818 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)4819 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
4820 {
4821 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
4822 }
4823
4824 /**
4825 * @brief Generate Capture/Compare 4 event.
4826 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
4827 * @param TIMx Timer instance
4828 * @retval None
4829 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)4830 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
4831 {
4832 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
4833 }
4834
4835 /**
4836 * @brief Generate commutation event.
4837 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
4838 * @param TIMx Timer instance
4839 * @retval None
4840 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)4841 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
4842 {
4843 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
4844 }
4845
4846 /**
4847 * @brief Generate trigger event.
4848 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
4849 * @param TIMx Timer instance
4850 * @retval None
4851 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)4852 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
4853 {
4854 SET_BIT(TIMx->EGR, TIM_EGR_TG);
4855 }
4856
4857 /**
4858 * @brief Generate break event.
4859 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
4860 * @param TIMx Timer instance
4861 * @retval None
4862 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)4863 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
4864 {
4865 SET_BIT(TIMx->EGR, TIM_EGR_BG);
4866 }
4867
4868 /**
4869 * @brief Generate break 2 event.
4870 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
4871 * @param TIMx Timer instance
4872 * @retval None
4873 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)4874 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
4875 {
4876 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
4877 }
4878
4879 /**
4880 * @}
4881 */
4882
4883 #if defined(USE_FULL_LL_DRIVER)
4884 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
4885 * @{
4886 */
4887
4888 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
4889 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
4890 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
4891 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4892 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4893 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
4894 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
4895 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4896 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4897 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4898 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4899 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4900 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4901 /**
4902 * @}
4903 */
4904 #endif /* USE_FULL_LL_DRIVER */
4905
4906 /**
4907 * @}
4908 */
4909
4910 /**
4911 * @}
4912 */
4913
4914 #endif /* TIM1 || TIM2 || TIM3 || TIM14 || TIM16 || TIM17 */
4915
4916 /**
4917 * @}
4918 */
4919
4920 #ifdef __cplusplus
4921 }
4922 #endif
4923
4924 #endif /* __STM32C0xx_LL_TIM_H */
4925
