1 /**
2 ******************************************************************************
3 * @file stm32c0xx_hal_i2c.c
4 * @author MCD Application Team
5 * @brief I2C HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Inter Integrated Circuit (I2C) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State and Errors functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2022 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 ==============================================================================
25 ##### How to use this driver #####
26 ==============================================================================
27 [..]
28 The I2C HAL driver can be used as follows:
29
30 (#) Declare a I2C_HandleTypeDef handle structure, for example:
31 I2C_HandleTypeDef hi2c;
32
33 (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
34 (##) Enable the I2Cx interface clock
35 (##) I2C pins configuration
36 (+++) Enable the clock for the I2C GPIOs
37 (+++) Configure I2C pins as alternate function open-drain
38 (##) NVIC configuration if you need to use interrupt process
39 (+++) Configure the I2Cx interrupt priority
40 (+++) Enable the NVIC I2C IRQ Channel
41 (##) DMA Configuration if you need to use DMA process
42 (+++) Declare a DMA_HandleTypeDef handle structure for
43 the transmit or receive channel
44 (+++) Enable the DMAx interface clock using
45 (+++) Configure the DMA handle parameters
46 (+++) Configure the DMA Tx or Rx channel
47 (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
48 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
49 the DMA Tx or Rx channel
50
51 (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
52 Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
53
54 (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
55 (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
56
57 (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
58
59 (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
60
61 *** Polling mode IO operation ***
62 =================================
63 [..]
64 (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
65 (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
66 (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
67 (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
68
69 *** Polling mode IO MEM operation ***
70 =====================================
71 [..]
72 (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
73 (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
74
75
76 *** Interrupt mode IO operation ***
77 ===================================
78 [..]
79 (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
80 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
81 add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
82 (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
83 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
84 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
85 (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
86 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
87 add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
88 (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
89 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
90 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
91 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
92 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
93 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
94 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
95 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
96 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
97 This action will inform Master to generate a Stop condition to discard the communication.
98
99
100 *** Interrupt mode or DMA mode IO sequential operation ***
101 ==========================================================
102 [..]
103 (@) These interfaces allow to manage a sequential transfer with a repeated start condition
104 when a direction change during transfer
105 [..]
106 (+) A specific option field manage the different steps of a sequential transfer
107 (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
108 (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in
109 no sequential mode
110 (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
111 and data to transfer without a final stop condition
112 (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with
113 start condition, address and data to transfer without a final stop condition,
114 an then permit a call the same master sequential interface several times
115 (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
116 or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
117 (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
118 and with new data to transfer if the direction change or manage only the new data to
119 transfer
120 if no direction change and without a final stop condition in both cases
121 (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
122 and with new data to transfer if the direction change or manage only the new data to
123 transfer
124 if no direction change and with a final stop condition in both cases
125 (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
126 after several call of the same master sequential interface several times
127 (link with option I2C_FIRST_AND_NEXT_FRAME).
128 Usage can, transfer several bytes one by one using
129 HAL_I2C_Master_Seq_Transmit_IT
130 or HAL_I2C_Master_Seq_Receive_IT
131 or HAL_I2C_Master_Seq_Transmit_DMA
132 or HAL_I2C_Master_Seq_Receive_DMA
133 with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
134 Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or
135 Receive sequence permit to call the opposite interface Receive or Transmit
136 without stopping the communication and so generate a restart condition.
137 (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
138 each call of the same master sequential
139 interface.
140 Usage can, transfer several bytes one by one with a restart with slave address between
141 each bytes using
142 HAL_I2C_Master_Seq_Transmit_IT
143 or HAL_I2C_Master_Seq_Receive_IT
144 or HAL_I2C_Master_Seq_Transmit_DMA
145 or HAL_I2C_Master_Seq_Receive_DMA
146 with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
147 Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
148 generation of STOP condition.
149
150 (+) Different sequential I2C interfaces are listed below:
151 (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
152 HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
153 (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and
154 users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
155 (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
156 HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
157 (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
158 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
159 (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
160 (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
161 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
162 (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
163 HAL_I2C_DisableListen_IT()
164 (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
165 add their own code to check the Address Match Code and the transmission direction request by master
166 (Write/Read).
167 (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
168 add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
169 (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
170 HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
171 (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and
172 users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
173 (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
174 HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
175 (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
176 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
177 (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
178 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
179 (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
180 This action will inform Master to generate a Stop condition to discard the communication.
181
182 *** Interrupt mode IO MEM operation ***
183 =======================================
184 [..]
185 (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
186 HAL_I2C_Mem_Write_IT()
187 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
188 add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
189 (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
190 HAL_I2C_Mem_Read_IT()
191 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
192 add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
193 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
194 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
195
196 *** DMA mode IO operation ***
197 ==============================
198 [..]
199 (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
200 HAL_I2C_Master_Transmit_DMA()
201 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
202 add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
203 (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
204 HAL_I2C_Master_Receive_DMA()
205 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
206 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
207 (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
208 HAL_I2C_Slave_Transmit_DMA()
209 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
210 add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
211 (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
212 HAL_I2C_Slave_Receive_DMA()
213 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
214 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
215 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
216 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
217 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
218 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
219 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
220 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
221 This action will inform Master to generate a Stop condition to discard the communication.
222
223 *** DMA mode IO MEM operation ***
224 =================================
225 [..]
226 (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
227 HAL_I2C_Mem_Write_DMA()
228 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
229 add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
230 (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
231 HAL_I2C_Mem_Read_DMA()
232 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
233 add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
234 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
235 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
236
237
238 *** I2C HAL driver macros list ***
239 ==================================
240 [..]
241 Below the list of most used macros in I2C HAL driver.
242
243 (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
244 (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
245 (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
246 (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
247 (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
248 (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
249 (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
250
251 *** Callback registration ***
252 =============================================
253 [..]
254 The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
255 allows the user to configure dynamically the driver callbacks.
256 Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
257 to register an interrupt callback.
258 [..]
259 Function HAL_I2C_RegisterCallback() allows to register following callbacks:
260 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
261 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
262 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
263 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
264 (+) ListenCpltCallback : callback for end of listen mode.
265 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
266 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
267 (+) ErrorCallback : callback for error detection.
268 (+) AbortCpltCallback : callback for abort completion process.
269 (+) MspInitCallback : callback for Msp Init.
270 (+) MspDeInitCallback : callback for Msp DeInit.
271 This function takes as parameters the HAL peripheral handle, the Callback ID
272 and a pointer to the user callback function.
273 [..]
274 For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
275 [..]
276 Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
277 weak function.
278 HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
279 and the Callback ID.
280 This function allows to reset following callbacks:
281 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
282 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
283 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
284 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
285 (+) ListenCpltCallback : callback for end of listen mode.
286 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
287 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
288 (+) ErrorCallback : callback for error detection.
289 (+) AbortCpltCallback : callback for abort completion process.
290 (+) MspInitCallback : callback for Msp Init.
291 (+) MspDeInitCallback : callback for Msp DeInit.
292 [..]
293 For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
294 [..]
295 By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
296 all callbacks are set to the corresponding weak functions:
297 examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
298 Exception done for MspInit and MspDeInit functions that are
299 reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
300 these callbacks are null (not registered beforehand).
301 If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
302 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
303 [..]
304 Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
305 Exception done MspInit/MspDeInit functions that can be registered/unregistered
306 in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
307 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
308 Then, the user first registers the MspInit/MspDeInit user callbacks
309 using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
310 or HAL_I2C_Init() function.
311 [..]
312 When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
313 not defined, the callback registration feature is not available and all callbacks
314 are set to the corresponding weak functions.
315
316 [..]
317 (@) You can refer to the I2C HAL driver header file for more useful macros
318
319 @endverbatim
320 */
321
322 /* Includes ------------------------------------------------------------------*/
323 #include "stm32c0xx_hal.h"
324
325 /** @addtogroup STM32C0xx_HAL_Driver
326 * @{
327 */
328
329 /** @defgroup I2C I2C
330 * @brief I2C HAL module driver
331 * @{
332 */
333
334 #ifdef HAL_I2C_MODULE_ENABLED
335
336 /* Private typedef -----------------------------------------------------------*/
337 /* Private define ------------------------------------------------------------*/
338
339 /** @defgroup I2C_Private_Define I2C Private Define
340 * @{
341 */
342 #define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */
343 #define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */
344 #define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */
345 #define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */
346 #define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */
347 #define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */
348 #define I2C_TIMEOUT_TC (25U) /*!< 25 ms */
349 #define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */
350 #define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */
351 #define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */
352
353 #define MAX_NBYTE_SIZE 255U
354 #define SLAVE_ADDR_SHIFT 7U
355 #define SLAVE_ADDR_MSK 0x06U
356
357 /* Private define for @ref PreviousState usage */
358 #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
359 (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
360 (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
361 /*!< Mask State define, keep only RX and TX bits */
362 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
363 /*!< Default Value */
364 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
365 (uint32_t)HAL_I2C_MODE_MASTER))
366 /*!< Master Busy TX, combinaison of State LSB and Mode enum */
367 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
368 (uint32_t)HAL_I2C_MODE_MASTER))
369 /*!< Master Busy RX, combinaison of State LSB and Mode enum */
370 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
371 (uint32_t)HAL_I2C_MODE_SLAVE))
372 /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
373 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
374 (uint32_t)HAL_I2C_MODE_SLAVE))
375 /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
376 #define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
377 (uint32_t)HAL_I2C_MODE_MEM))
378 /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
379 #define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
380 (uint32_t)HAL_I2C_MODE_MEM))
381 /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
382
383
384 /* Private define to centralize the enable/disable of Interrupts */
385 #define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with
386 @ref I2C_XFER_LISTEN_IT */
387 #define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with
388 @ref I2C_XFER_LISTEN_IT */
389 #define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT
390 and @ref I2C_XFER_RX_IT */
391
392 #define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error
393 and NACK treatment */
394 #define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */
395 #define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */
396
397 /* Private define Sequential Transfer Options default/reset value */
398 #define I2C_NO_OPTION_FRAME (0xFFFF0000U)
399 /**
400 * @}
401 */
402
403 /* Private macros ------------------------------------------------------------*/
404 /** @addtogroup I2C_Private_Macro
405 * @{
406 */
407 #if defined(HAL_DMA_MODULE_ENABLED)
408 /* Macro to get remaining data to transfer on DMA side */
409 #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)
410 #endif /* HAL_DMA_MODULE_ENABLED */
411 /**
412 * @}
413 */
414
415 /* Private variables ---------------------------------------------------------*/
416 /* Private function prototypes -----------------------------------------------*/
417
418 /** @defgroup I2C_Private_Functions I2C Private Functions
419 * @{
420 */
421 #if defined(HAL_DMA_MODULE_ENABLED)
422 /* Private functions to handle DMA transfer */
423 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
424 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
425 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
426 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
427 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
428 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
429
430 #endif /* HAL_DMA_MODULE_ENABLED */
431
432 /* Private functions to handle IT transfer */
433 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
434 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
435 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
436 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
437 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
438 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
439 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
440
441 /* Private functions to handle IT transfer */
442 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
443 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
444 uint32_t Tickstart);
445 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
446 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
447 uint32_t Tickstart);
448
449 /* Private functions for I2C transfer IRQ handler */
450 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
451 uint32_t ITSources);
452 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
453 uint32_t ITSources);
454 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
455 uint32_t ITSources);
456 #if defined(HAL_DMA_MODULE_ENABLED)
457 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
458 uint32_t ITSources);
459 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
460 uint32_t ITSources);
461 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
462 uint32_t ITSources);
463 #endif /* HAL_DMA_MODULE_ENABLED */
464
465 /* Private functions to handle flags during polling transfer */
466 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
467 uint32_t Timeout, uint32_t Tickstart);
468 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
469 uint32_t Tickstart);
470 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
471 uint32_t Tickstart);
472 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
473 uint32_t Tickstart);
474 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
475 uint32_t Tickstart);
476
477 /* Private functions to centralize the enable/disable of Interrupts */
478 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
479 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
480
481 /* Private function to treat different error callback */
482 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
483
484 /* Private function to flush TXDR register */
485 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
486
487 /* Private function to handle start, restart or stop a transfer */
488 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
489 uint32_t Request);
490
491 /* Private function to Convert Specific options */
492 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
493 /**
494 * @}
495 */
496
497 /* Exported functions --------------------------------------------------------*/
498
499 /** @defgroup I2C_Exported_Functions I2C Exported Functions
500 * @{
501 */
502
503 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
504 * @brief Initialization and Configuration functions
505 *
506 @verbatim
507 ===============================================================================
508 ##### Initialization and de-initialization functions #####
509 ===============================================================================
510 [..] This subsection provides a set of functions allowing to initialize and
511 deinitialize the I2Cx peripheral:
512
513 (+) User must Implement HAL_I2C_MspInit() function in which he configures
514 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
515
516 (+) Call the function HAL_I2C_Init() to configure the selected device with
517 the selected configuration:
518 (++) Clock Timing
519 (++) Own Address 1
520 (++) Addressing mode (Master, Slave)
521 (++) Dual Addressing mode
522 (++) Own Address 2
523 (++) Own Address 2 Mask
524 (++) General call mode
525 (++) Nostretch mode
526
527 (+) Call the function HAL_I2C_DeInit() to restore the default configuration
528 of the selected I2Cx peripheral.
529
530 @endverbatim
531 * @{
532 */
533
534 /**
535 * @brief Initializes the I2C according to the specified parameters
536 * in the I2C_InitTypeDef and initialize the associated handle.
537 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
538 * the configuration information for the specified I2C.
539 * @retval HAL status
540 */
HAL_I2C_Init(I2C_HandleTypeDef * hi2c)541 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
542 {
543 /* Check the I2C handle allocation */
544 if (hi2c == NULL)
545 {
546 return HAL_ERROR;
547 }
548
549 /* Check the parameters */
550 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
551 assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
552 assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
553 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
554 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
555 assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
556 assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
557 assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
558
559 if (hi2c->State == HAL_I2C_STATE_RESET)
560 {
561 /* Allocate lock resource and initialize it */
562 hi2c->Lock = HAL_UNLOCKED;
563
564 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
565 /* Init the I2C Callback settings */
566 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
567 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
568 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
569 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
570 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
571 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
572 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
573 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
574 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
575 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
576
577 if (hi2c->MspInitCallback == NULL)
578 {
579 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
580 }
581
582 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
583 hi2c->MspInitCallback(hi2c);
584 #else
585 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
586 HAL_I2C_MspInit(hi2c);
587 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
588 }
589
590 hi2c->State = HAL_I2C_STATE_BUSY;
591
592 /* Disable the selected I2C peripheral */
593 __HAL_I2C_DISABLE(hi2c);
594
595 /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
596 /* Configure I2Cx: Frequency range */
597 hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
598
599 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
600 /* Disable Own Address1 before set the Own Address1 configuration */
601 hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
602
603 /* Configure I2Cx: Own Address1 and ack own address1 mode */
604 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
605 {
606 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
607 }
608 else /* I2C_ADDRESSINGMODE_10BIT */
609 {
610 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
611 }
612
613 /*---------------------------- I2Cx CR2 Configuration ----------------------*/
614 /* Configure I2Cx: Addressing Master mode */
615 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
616 {
617 SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
618 }
619 else
620 {
621 /* Clear the I2C ADD10 bit */
622 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
623 }
624 /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
625 hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
626
627 /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
628 /* Disable Own Address2 before set the Own Address2 configuration */
629 hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
630
631 /* Configure I2Cx: Dual mode and Own Address2 */
632 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
633 (hi2c->Init.OwnAddress2Masks << 8));
634
635 /*---------------------------- I2Cx CR1 Configuration ----------------------*/
636 /* Configure I2Cx: Generalcall and NoStretch mode */
637 hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
638
639 /* Enable the selected I2C peripheral */
640 __HAL_I2C_ENABLE(hi2c);
641
642 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
643 hi2c->State = HAL_I2C_STATE_READY;
644 hi2c->PreviousState = I2C_STATE_NONE;
645 hi2c->Mode = HAL_I2C_MODE_NONE;
646
647 return HAL_OK;
648 }
649
650 /**
651 * @brief DeInitialize the I2C peripheral.
652 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
653 * the configuration information for the specified I2C.
654 * @retval HAL status
655 */
HAL_I2C_DeInit(I2C_HandleTypeDef * hi2c)656 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
657 {
658 /* Check the I2C handle allocation */
659 if (hi2c == NULL)
660 {
661 return HAL_ERROR;
662 }
663
664 /* Check the parameters */
665 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
666
667 hi2c->State = HAL_I2C_STATE_BUSY;
668
669 /* Disable the I2C Peripheral Clock */
670 __HAL_I2C_DISABLE(hi2c);
671
672 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
673 if (hi2c->MspDeInitCallback == NULL)
674 {
675 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
676 }
677
678 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
679 hi2c->MspDeInitCallback(hi2c);
680 #else
681 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
682 HAL_I2C_MspDeInit(hi2c);
683 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
684
685 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
686 hi2c->State = HAL_I2C_STATE_RESET;
687 hi2c->PreviousState = I2C_STATE_NONE;
688 hi2c->Mode = HAL_I2C_MODE_NONE;
689
690 /* Release Lock */
691 __HAL_UNLOCK(hi2c);
692
693 return HAL_OK;
694 }
695
696 /**
697 * @brief Initialize the I2C MSP.
698 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
699 * the configuration information for the specified I2C.
700 * @retval None
701 */
HAL_I2C_MspInit(I2C_HandleTypeDef * hi2c)702 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
703 {
704 /* Prevent unused argument(s) compilation warning */
705 UNUSED(hi2c);
706
707 /* NOTE : This function should not be modified, when the callback is needed,
708 the HAL_I2C_MspInit could be implemented in the user file
709 */
710 }
711
712 /**
713 * @brief DeInitialize the I2C MSP.
714 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
715 * the configuration information for the specified I2C.
716 * @retval None
717 */
HAL_I2C_MspDeInit(I2C_HandleTypeDef * hi2c)718 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
719 {
720 /* Prevent unused argument(s) compilation warning */
721 UNUSED(hi2c);
722
723 /* NOTE : This function should not be modified, when the callback is needed,
724 the HAL_I2C_MspDeInit could be implemented in the user file
725 */
726 }
727
728 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
729 /**
730 * @brief Register a User I2C Callback
731 * To be used instead of the weak predefined callback
732 * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
733 * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
734 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
735 * the configuration information for the specified I2C.
736 * @param CallbackID ID of the callback to be registered
737 * This parameter can be one of the following values:
738 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
739 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
740 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
741 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
742 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
743 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
744 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
745 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
746 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
747 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
748 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
749 * @param pCallback pointer to the Callback function
750 * @retval HAL status
751 */
HAL_I2C_RegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID,pI2C_CallbackTypeDef pCallback)752 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
753 pI2C_CallbackTypeDef pCallback)
754 {
755 HAL_StatusTypeDef status = HAL_OK;
756
757 if (pCallback == NULL)
758 {
759 /* Update the error code */
760 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
761
762 return HAL_ERROR;
763 }
764
765 if (HAL_I2C_STATE_READY == hi2c->State)
766 {
767 switch (CallbackID)
768 {
769 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
770 hi2c->MasterTxCpltCallback = pCallback;
771 break;
772
773 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
774 hi2c->MasterRxCpltCallback = pCallback;
775 break;
776
777 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
778 hi2c->SlaveTxCpltCallback = pCallback;
779 break;
780
781 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
782 hi2c->SlaveRxCpltCallback = pCallback;
783 break;
784
785 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
786 hi2c->ListenCpltCallback = pCallback;
787 break;
788
789 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
790 hi2c->MemTxCpltCallback = pCallback;
791 break;
792
793 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
794 hi2c->MemRxCpltCallback = pCallback;
795 break;
796
797 case HAL_I2C_ERROR_CB_ID :
798 hi2c->ErrorCallback = pCallback;
799 break;
800
801 case HAL_I2C_ABORT_CB_ID :
802 hi2c->AbortCpltCallback = pCallback;
803 break;
804
805 case HAL_I2C_MSPINIT_CB_ID :
806 hi2c->MspInitCallback = pCallback;
807 break;
808
809 case HAL_I2C_MSPDEINIT_CB_ID :
810 hi2c->MspDeInitCallback = pCallback;
811 break;
812
813 default :
814 /* Update the error code */
815 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
816
817 /* Return error status */
818 status = HAL_ERROR;
819 break;
820 }
821 }
822 else if (HAL_I2C_STATE_RESET == hi2c->State)
823 {
824 switch (CallbackID)
825 {
826 case HAL_I2C_MSPINIT_CB_ID :
827 hi2c->MspInitCallback = pCallback;
828 break;
829
830 case HAL_I2C_MSPDEINIT_CB_ID :
831 hi2c->MspDeInitCallback = pCallback;
832 break;
833
834 default :
835 /* Update the error code */
836 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
837
838 /* Return error status */
839 status = HAL_ERROR;
840 break;
841 }
842 }
843 else
844 {
845 /* Update the error code */
846 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
847
848 /* Return error status */
849 status = HAL_ERROR;
850 }
851
852 return status;
853 }
854
855 /**
856 * @brief Unregister an I2C Callback
857 * I2C callback is redirected to the weak predefined callback
858 * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
859 * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
860 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
861 * the configuration information for the specified I2C.
862 * @param CallbackID ID of the callback to be unregistered
863 * This parameter can be one of the following values:
864 * This parameter can be one of the following values:
865 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
866 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
867 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
868 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
869 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
870 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
871 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
872 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
873 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
874 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
875 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
876 * @retval HAL status
877 */
HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID)878 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
879 {
880 HAL_StatusTypeDef status = HAL_OK;
881
882 if (HAL_I2C_STATE_READY == hi2c->State)
883 {
884 switch (CallbackID)
885 {
886 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
887 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
888 break;
889
890 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
891 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
892 break;
893
894 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
895 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
896 break;
897
898 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
899 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
900 break;
901
902 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
903 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
904 break;
905
906 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
907 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
908 break;
909
910 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
911 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
912 break;
913
914 case HAL_I2C_ERROR_CB_ID :
915 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
916 break;
917
918 case HAL_I2C_ABORT_CB_ID :
919 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
920 break;
921
922 case HAL_I2C_MSPINIT_CB_ID :
923 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
924 break;
925
926 case HAL_I2C_MSPDEINIT_CB_ID :
927 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
928 break;
929
930 default :
931 /* Update the error code */
932 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
933
934 /* Return error status */
935 status = HAL_ERROR;
936 break;
937 }
938 }
939 else if (HAL_I2C_STATE_RESET == hi2c->State)
940 {
941 switch (CallbackID)
942 {
943 case HAL_I2C_MSPINIT_CB_ID :
944 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
945 break;
946
947 case HAL_I2C_MSPDEINIT_CB_ID :
948 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
949 break;
950
951 default :
952 /* Update the error code */
953 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
954
955 /* Return error status */
956 status = HAL_ERROR;
957 break;
958 }
959 }
960 else
961 {
962 /* Update the error code */
963 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
964
965 /* Return error status */
966 status = HAL_ERROR;
967 }
968
969 return status;
970 }
971
972 /**
973 * @brief Register the Slave Address Match I2C Callback
974 * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
975 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
976 * the configuration information for the specified I2C.
977 * @param pCallback pointer to the Address Match Callback function
978 * @retval HAL status
979 */
HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef * hi2c,pI2C_AddrCallbackTypeDef pCallback)980 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
981 {
982 HAL_StatusTypeDef status = HAL_OK;
983
984 if (pCallback == NULL)
985 {
986 /* Update the error code */
987 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
988
989 return HAL_ERROR;
990 }
991
992 if (HAL_I2C_STATE_READY == hi2c->State)
993 {
994 hi2c->AddrCallback = pCallback;
995 }
996 else
997 {
998 /* Update the error code */
999 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
1000
1001 /* Return error status */
1002 status = HAL_ERROR;
1003 }
1004
1005 return status;
1006 }
1007
1008 /**
1009 * @brief UnRegister the Slave Address Match I2C Callback
1010 * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
1011 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1012 * the configuration information for the specified I2C.
1013 * @retval HAL status
1014 */
HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef * hi2c)1015 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
1016 {
1017 HAL_StatusTypeDef status = HAL_OK;
1018
1019 if (HAL_I2C_STATE_READY == hi2c->State)
1020 {
1021 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
1022 }
1023 else
1024 {
1025 /* Update the error code */
1026 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
1027
1028 /* Return error status */
1029 status = HAL_ERROR;
1030 }
1031
1032 return status;
1033 }
1034
1035 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
1036
1037 /**
1038 * @}
1039 */
1040
1041 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
1042 * @brief Data transfers functions
1043 *
1044 @verbatim
1045 ===============================================================================
1046 ##### IO operation functions #####
1047 ===============================================================================
1048 [..]
1049 This subsection provides a set of functions allowing to manage the I2C data
1050 transfers.
1051
1052 (#) There are two modes of transfer:
1053 (++) Blocking mode : The communication is performed in the polling mode.
1054 The status of all data processing is returned by the same function
1055 after finishing transfer.
1056 (++) No-Blocking mode : The communication is performed using Interrupts
1057 or DMA. These functions return the status of the transfer startup.
1058 The end of the data processing will be indicated through the
1059 dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
1060 using DMA mode.
1061
1062 (#) Blocking mode functions are :
1063 (++) HAL_I2C_Master_Transmit()
1064 (++) HAL_I2C_Master_Receive()
1065 (++) HAL_I2C_Slave_Transmit()
1066 (++) HAL_I2C_Slave_Receive()
1067 (++) HAL_I2C_Mem_Write()
1068 (++) HAL_I2C_Mem_Read()
1069 (++) HAL_I2C_IsDeviceReady()
1070
1071 (#) No-Blocking mode functions with Interrupt are :
1072 (++) HAL_I2C_Master_Transmit_IT()
1073 (++) HAL_I2C_Master_Receive_IT()
1074 (++) HAL_I2C_Slave_Transmit_IT()
1075 (++) HAL_I2C_Slave_Receive_IT()
1076 (++) HAL_I2C_Mem_Write_IT()
1077 (++) HAL_I2C_Mem_Read_IT()
1078 (++) HAL_I2C_Master_Seq_Transmit_IT()
1079 (++) HAL_I2C_Master_Seq_Receive_IT()
1080 (++) HAL_I2C_Slave_Seq_Transmit_IT()
1081 (++) HAL_I2C_Slave_Seq_Receive_IT()
1082 (++) HAL_I2C_EnableListen_IT()
1083 (++) HAL_I2C_DisableListen_IT()
1084 (++) HAL_I2C_Master_Abort_IT()
1085
1086 (#) No-Blocking mode functions with DMA are :
1087 (++) HAL_I2C_Master_Transmit_DMA()
1088 (++) HAL_I2C_Master_Receive_DMA()
1089 (++) HAL_I2C_Slave_Transmit_DMA()
1090 (++) HAL_I2C_Slave_Receive_DMA()
1091 (++) HAL_I2C_Mem_Write_DMA()
1092 (++) HAL_I2C_Mem_Read_DMA()
1093 (++) HAL_I2C_Master_Seq_Transmit_DMA()
1094 (++) HAL_I2C_Master_Seq_Receive_DMA()
1095 (++) HAL_I2C_Slave_Seq_Transmit_DMA()
1096 (++) HAL_I2C_Slave_Seq_Receive_DMA()
1097
1098 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
1099 (++) HAL_I2C_MasterTxCpltCallback()
1100 (++) HAL_I2C_MasterRxCpltCallback()
1101 (++) HAL_I2C_SlaveTxCpltCallback()
1102 (++) HAL_I2C_SlaveRxCpltCallback()
1103 (++) HAL_I2C_MemTxCpltCallback()
1104 (++) HAL_I2C_MemRxCpltCallback()
1105 (++) HAL_I2C_AddrCallback()
1106 (++) HAL_I2C_ListenCpltCallback()
1107 (++) HAL_I2C_ErrorCallback()
1108 (++) HAL_I2C_AbortCpltCallback()
1109
1110 @endverbatim
1111 * @{
1112 */
1113
1114 /**
1115 * @brief Transmits in master mode an amount of data in blocking mode.
1116 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1117 * the configuration information for the specified I2C.
1118 * @param DevAddress Target device address: The device 7 bits address value
1119 * in datasheet must be shifted to the left before calling the interface
1120 * @param pData Pointer to data buffer
1121 * @param Size Amount of data to be sent
1122 * @param Timeout Timeout duration
1123 * @retval HAL status
1124 */
HAL_I2C_Master_Transmit(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1125 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1126 uint16_t Size, uint32_t Timeout)
1127 {
1128 uint32_t tickstart;
1129 uint32_t xfermode;
1130
1131 if (hi2c->State == HAL_I2C_STATE_READY)
1132 {
1133 /* Process Locked */
1134 __HAL_LOCK(hi2c);
1135
1136 /* Init tickstart for timeout management*/
1137 tickstart = HAL_GetTick();
1138
1139 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1140 {
1141 return HAL_ERROR;
1142 }
1143
1144 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1145 hi2c->Mode = HAL_I2C_MODE_MASTER;
1146 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1147
1148 /* Prepare transfer parameters */
1149 hi2c->pBuffPtr = pData;
1150 hi2c->XferCount = Size;
1151 hi2c->XferISR = NULL;
1152
1153 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1154 {
1155 hi2c->XferSize = MAX_NBYTE_SIZE;
1156 xfermode = I2C_RELOAD_MODE;
1157 }
1158 else
1159 {
1160 hi2c->XferSize = hi2c->XferCount;
1161 xfermode = I2C_AUTOEND_MODE;
1162 }
1163
1164 if (hi2c->XferSize > 0U)
1165 {
1166 /* Preload TX register */
1167 /* Write data to TXDR */
1168 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1169
1170 /* Increment Buffer pointer */
1171 hi2c->pBuffPtr++;
1172
1173 hi2c->XferCount--;
1174 hi2c->XferSize--;
1175
1176 /* Send Slave Address */
1177 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1178 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode,
1179 I2C_GENERATE_START_WRITE);
1180 }
1181 else
1182 {
1183 /* Send Slave Address */
1184 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1185 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
1186 I2C_GENERATE_START_WRITE);
1187 }
1188
1189 while (hi2c->XferCount > 0U)
1190 {
1191 /* Wait until TXIS flag is set */
1192 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1193 {
1194 return HAL_ERROR;
1195 }
1196 /* Write data to TXDR */
1197 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1198
1199 /* Increment Buffer pointer */
1200 hi2c->pBuffPtr++;
1201
1202 hi2c->XferCount--;
1203 hi2c->XferSize--;
1204
1205 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1206 {
1207 /* Wait until TCR flag is set */
1208 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1209 {
1210 return HAL_ERROR;
1211 }
1212
1213 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1214 {
1215 hi2c->XferSize = MAX_NBYTE_SIZE;
1216 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1217 I2C_NO_STARTSTOP);
1218 }
1219 else
1220 {
1221 hi2c->XferSize = hi2c->XferCount;
1222 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1223 I2C_NO_STARTSTOP);
1224 }
1225 }
1226 }
1227
1228 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1229 /* Wait until STOPF flag is set */
1230 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1231 {
1232 return HAL_ERROR;
1233 }
1234
1235 /* Clear STOP Flag */
1236 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1237
1238 /* Clear Configuration Register 2 */
1239 I2C_RESET_CR2(hi2c);
1240
1241 hi2c->State = HAL_I2C_STATE_READY;
1242 hi2c->Mode = HAL_I2C_MODE_NONE;
1243
1244 /* Process Unlocked */
1245 __HAL_UNLOCK(hi2c);
1246
1247 return HAL_OK;
1248 }
1249 else
1250 {
1251 return HAL_BUSY;
1252 }
1253 }
1254
1255 /**
1256 * @brief Receives in master mode an amount of data in blocking mode.
1257 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1258 * the configuration information for the specified I2C.
1259 * @param DevAddress Target device address: The device 7 bits address value
1260 * in datasheet must be shifted to the left before calling the interface
1261 * @param pData Pointer to data buffer
1262 * @param Size Amount of data to be sent
1263 * @param Timeout Timeout duration
1264 * @retval HAL status
1265 */
HAL_I2C_Master_Receive(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1266 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1267 uint16_t Size, uint32_t Timeout)
1268 {
1269 uint32_t tickstart;
1270
1271 if (hi2c->State == HAL_I2C_STATE_READY)
1272 {
1273 /* Process Locked */
1274 __HAL_LOCK(hi2c);
1275
1276 /* Init tickstart for timeout management*/
1277 tickstart = HAL_GetTick();
1278
1279 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1280 {
1281 return HAL_ERROR;
1282 }
1283
1284 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1285 hi2c->Mode = HAL_I2C_MODE_MASTER;
1286 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1287
1288 /* Prepare transfer parameters */
1289 hi2c->pBuffPtr = pData;
1290 hi2c->XferCount = Size;
1291 hi2c->XferISR = NULL;
1292
1293 /* Send Slave Address */
1294 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1295 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1296 {
1297 hi2c->XferSize = MAX_NBYTE_SIZE;
1298 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1299 I2C_GENERATE_START_READ);
1300 }
1301 else
1302 {
1303 hi2c->XferSize = hi2c->XferCount;
1304 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1305 I2C_GENERATE_START_READ);
1306 }
1307
1308 while (hi2c->XferCount > 0U)
1309 {
1310 /* Wait until RXNE flag is set */
1311 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1312 {
1313 return HAL_ERROR;
1314 }
1315
1316 /* Read data from RXDR */
1317 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1318
1319 /* Increment Buffer pointer */
1320 hi2c->pBuffPtr++;
1321
1322 hi2c->XferSize--;
1323 hi2c->XferCount--;
1324
1325 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1326 {
1327 /* Wait until TCR flag is set */
1328 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1329 {
1330 return HAL_ERROR;
1331 }
1332
1333 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1334 {
1335 hi2c->XferSize = MAX_NBYTE_SIZE;
1336 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1337 I2C_NO_STARTSTOP);
1338 }
1339 else
1340 {
1341 hi2c->XferSize = hi2c->XferCount;
1342 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1343 I2C_NO_STARTSTOP);
1344 }
1345 }
1346 }
1347
1348 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1349 /* Wait until STOPF flag is set */
1350 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1351 {
1352 return HAL_ERROR;
1353 }
1354
1355 /* Clear STOP Flag */
1356 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1357
1358 /* Clear Configuration Register 2 */
1359 I2C_RESET_CR2(hi2c);
1360
1361 hi2c->State = HAL_I2C_STATE_READY;
1362 hi2c->Mode = HAL_I2C_MODE_NONE;
1363
1364 /* Process Unlocked */
1365 __HAL_UNLOCK(hi2c);
1366
1367 return HAL_OK;
1368 }
1369 else
1370 {
1371 return HAL_BUSY;
1372 }
1373 }
1374
1375 /**
1376 * @brief Transmits in slave mode an amount of data in blocking mode.
1377 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1378 * the configuration information for the specified I2C.
1379 * @param pData Pointer to data buffer
1380 * @param Size Amount of data to be sent
1381 * @param Timeout Timeout duration
1382 * @retval HAL status
1383 */
HAL_I2C_Slave_Transmit(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1384 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
1385 uint32_t Timeout)
1386 {
1387 uint32_t tickstart;
1388
1389 if (hi2c->State == HAL_I2C_STATE_READY)
1390 {
1391 if ((pData == NULL) || (Size == 0U))
1392 {
1393 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1394 return HAL_ERROR;
1395 }
1396 /* Process Locked */
1397 __HAL_LOCK(hi2c);
1398
1399 /* Init tickstart for timeout management*/
1400 tickstart = HAL_GetTick();
1401
1402 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1403 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1404 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1405
1406 /* Prepare transfer parameters */
1407 hi2c->pBuffPtr = pData;
1408 hi2c->XferCount = Size;
1409 hi2c->XferISR = NULL;
1410
1411 /* Enable Address Acknowledge */
1412 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1413
1414 /* Wait until ADDR flag is set */
1415 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1416 {
1417 /* Disable Address Acknowledge */
1418 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1419 return HAL_ERROR;
1420 }
1421
1422 /* Preload TX data if no stretch enable */
1423 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
1424 {
1425 /* Preload TX register */
1426 /* Write data to TXDR */
1427 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1428
1429 /* Increment Buffer pointer */
1430 hi2c->pBuffPtr++;
1431
1432 hi2c->XferCount--;
1433 }
1434
1435 /* Clear ADDR flag */
1436 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1437
1438 /* If 10bit addressing mode is selected */
1439 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
1440 {
1441 /* Wait until ADDR flag is set */
1442 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1443 {
1444 /* Disable Address Acknowledge */
1445 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1446 return HAL_ERROR;
1447 }
1448
1449 /* Clear ADDR flag */
1450 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1451 }
1452
1453 /* Wait until DIR flag is set Transmitter mode */
1454 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
1455 {
1456 /* Disable Address Acknowledge */
1457 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1458 return HAL_ERROR;
1459 }
1460
1461 while (hi2c->XferCount > 0U)
1462 {
1463 /* Wait until TXIS flag is set */
1464 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1465 {
1466 /* Disable Address Acknowledge */
1467 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1468 return HAL_ERROR;
1469 }
1470
1471 /* Write data to TXDR */
1472 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1473
1474 /* Increment Buffer pointer */
1475 hi2c->pBuffPtr++;
1476
1477 hi2c->XferCount--;
1478 }
1479
1480 /* Wait until AF flag is set */
1481 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
1482 {
1483 /* Disable Address Acknowledge */
1484 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1485 return HAL_ERROR;
1486 }
1487
1488 /* Flush TX register */
1489 I2C_Flush_TXDR(hi2c);
1490
1491 /* Clear AF flag */
1492 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
1493
1494 /* Wait until STOP flag is set */
1495 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1496 {
1497 /* Disable Address Acknowledge */
1498 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1499
1500 return HAL_ERROR;
1501 }
1502
1503 /* Clear STOP flag */
1504 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1505
1506 /* Wait until BUSY flag is reset */
1507 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1508 {
1509 /* Disable Address Acknowledge */
1510 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1511 return HAL_ERROR;
1512 }
1513
1514 /* Disable Address Acknowledge */
1515 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1516
1517 hi2c->State = HAL_I2C_STATE_READY;
1518 hi2c->Mode = HAL_I2C_MODE_NONE;
1519
1520 /* Process Unlocked */
1521 __HAL_UNLOCK(hi2c);
1522
1523 return HAL_OK;
1524 }
1525 else
1526 {
1527 return HAL_BUSY;
1528 }
1529 }
1530
1531 /**
1532 * @brief Receive in slave mode an amount of data in blocking mode
1533 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1534 * the configuration information for the specified I2C.
1535 * @param pData Pointer to data buffer
1536 * @param Size Amount of data to be sent
1537 * @param Timeout Timeout duration
1538 * @retval HAL status
1539 */
HAL_I2C_Slave_Receive(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1540 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
1541 uint32_t Timeout)
1542 {
1543 uint32_t tickstart;
1544
1545 if (hi2c->State == HAL_I2C_STATE_READY)
1546 {
1547 if ((pData == NULL) || (Size == 0U))
1548 {
1549 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1550 return HAL_ERROR;
1551 }
1552 /* Process Locked */
1553 __HAL_LOCK(hi2c);
1554
1555 /* Init tickstart for timeout management*/
1556 tickstart = HAL_GetTick();
1557
1558 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1559 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1560 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1561
1562 /* Prepare transfer parameters */
1563 hi2c->pBuffPtr = pData;
1564 hi2c->XferCount = Size;
1565 hi2c->XferSize = hi2c->XferCount;
1566 hi2c->XferISR = NULL;
1567
1568 /* Enable Address Acknowledge */
1569 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1570
1571 /* Wait until ADDR flag is set */
1572 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1573 {
1574 /* Disable Address Acknowledge */
1575 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1576 return HAL_ERROR;
1577 }
1578
1579 /* Clear ADDR flag */
1580 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1581
1582 /* Wait until DIR flag is reset Receiver mode */
1583 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
1584 {
1585 /* Disable Address Acknowledge */
1586 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1587 return HAL_ERROR;
1588 }
1589
1590 while (hi2c->XferCount > 0U)
1591 {
1592 /* Wait until RXNE flag is set */
1593 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1594 {
1595 /* Disable Address Acknowledge */
1596 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1597
1598 /* Store Last receive data if any */
1599 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
1600 {
1601 /* Read data from RXDR */
1602 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1603
1604 /* Increment Buffer pointer */
1605 hi2c->pBuffPtr++;
1606
1607 hi2c->XferCount--;
1608 hi2c->XferSize--;
1609 }
1610
1611 return HAL_ERROR;
1612 }
1613
1614 /* Read data from RXDR */
1615 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1616
1617 /* Increment Buffer pointer */
1618 hi2c->pBuffPtr++;
1619
1620 hi2c->XferCount--;
1621 hi2c->XferSize--;
1622 }
1623
1624 /* Wait until STOP flag is set */
1625 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1626 {
1627 /* Disable Address Acknowledge */
1628 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1629 return HAL_ERROR;
1630 }
1631
1632 /* Clear STOP flag */
1633 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1634
1635 /* Wait until BUSY flag is reset */
1636 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1637 {
1638 /* Disable Address Acknowledge */
1639 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1640 return HAL_ERROR;
1641 }
1642
1643 /* Disable Address Acknowledge */
1644 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1645
1646 hi2c->State = HAL_I2C_STATE_READY;
1647 hi2c->Mode = HAL_I2C_MODE_NONE;
1648
1649 /* Process Unlocked */
1650 __HAL_UNLOCK(hi2c);
1651
1652 return HAL_OK;
1653 }
1654 else
1655 {
1656 return HAL_BUSY;
1657 }
1658 }
1659
1660 /**
1661 * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
1662 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1663 * the configuration information for the specified I2C.
1664 * @param DevAddress Target device address: The device 7 bits address value
1665 * in datasheet must be shifted to the left before calling the interface
1666 * @param pData Pointer to data buffer
1667 * @param Size Amount of data to be sent
1668 * @retval HAL status
1669 */
HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1670 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1671 uint16_t Size)
1672 {
1673 uint32_t xfermode;
1674
1675 if (hi2c->State == HAL_I2C_STATE_READY)
1676 {
1677 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1678 {
1679 return HAL_BUSY;
1680 }
1681
1682 /* Process Locked */
1683 __HAL_LOCK(hi2c);
1684
1685 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1686 hi2c->Mode = HAL_I2C_MODE_MASTER;
1687 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1688
1689 /* Prepare transfer parameters */
1690 hi2c->pBuffPtr = pData;
1691 hi2c->XferCount = Size;
1692 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1693 hi2c->XferISR = I2C_Master_ISR_IT;
1694
1695 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1696 {
1697 hi2c->XferSize = MAX_NBYTE_SIZE;
1698 xfermode = I2C_RELOAD_MODE;
1699 }
1700 else
1701 {
1702 hi2c->XferSize = hi2c->XferCount;
1703 xfermode = I2C_AUTOEND_MODE;
1704 }
1705
1706 /* Send Slave Address */
1707 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1708 if (hi2c->XferSize > 0U)
1709 {
1710 /* Preload TX register */
1711 /* Write data to TXDR */
1712 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1713
1714 /* Increment Buffer pointer */
1715 hi2c->pBuffPtr++;
1716
1717 hi2c->XferCount--;
1718 hi2c->XferSize--;
1719
1720 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode,
1721 I2C_GENERATE_START_WRITE);
1722 }
1723 else
1724 {
1725 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
1726 I2C_GENERATE_START_WRITE);
1727 }
1728
1729 /* Process Unlocked */
1730 __HAL_UNLOCK(hi2c);
1731
1732 /* Note : The I2C interrupts must be enabled after unlocking current process
1733 to avoid the risk of I2C interrupt handle execution before current
1734 process unlock */
1735
1736 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1737 /* possible to enable all of these */
1738 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1739 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1740 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
1741
1742 return HAL_OK;
1743 }
1744 else
1745 {
1746 return HAL_BUSY;
1747 }
1748 }
1749
1750 /**
1751 * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
1752 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1753 * the configuration information for the specified I2C.
1754 * @param DevAddress Target device address: The device 7 bits address value
1755 * in datasheet must be shifted to the left before calling the interface
1756 * @param pData Pointer to data buffer
1757 * @param Size Amount of data to be sent
1758 * @retval HAL status
1759 */
HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1760 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1761 uint16_t Size)
1762 {
1763 uint32_t xfermode;
1764
1765 if (hi2c->State == HAL_I2C_STATE_READY)
1766 {
1767 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1768 {
1769 return HAL_BUSY;
1770 }
1771
1772 /* Process Locked */
1773 __HAL_LOCK(hi2c);
1774
1775 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1776 hi2c->Mode = HAL_I2C_MODE_MASTER;
1777 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1778
1779 /* Prepare transfer parameters */
1780 hi2c->pBuffPtr = pData;
1781 hi2c->XferCount = Size;
1782 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1783 hi2c->XferISR = I2C_Master_ISR_IT;
1784
1785 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1786 {
1787 hi2c->XferSize = MAX_NBYTE_SIZE;
1788 xfermode = I2C_RELOAD_MODE;
1789 }
1790 else
1791 {
1792 hi2c->XferSize = hi2c->XferCount;
1793 xfermode = I2C_AUTOEND_MODE;
1794 }
1795
1796 /* Send Slave Address */
1797 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1798 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
1799
1800 /* Process Unlocked */
1801 __HAL_UNLOCK(hi2c);
1802
1803 /* Note : The I2C interrupts must be enabled after unlocking current process
1804 to avoid the risk of I2C interrupt handle execution before current
1805 process unlock */
1806
1807 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1808 /* possible to enable all of these */
1809 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1810 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1811 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
1812
1813 return HAL_OK;
1814 }
1815 else
1816 {
1817 return HAL_BUSY;
1818 }
1819 }
1820
1821 /**
1822 * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
1823 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1824 * the configuration information for the specified I2C.
1825 * @param pData Pointer to data buffer
1826 * @param Size Amount of data to be sent
1827 * @retval HAL status
1828 */
HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1829 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1830 {
1831 if (hi2c->State == HAL_I2C_STATE_READY)
1832 {
1833 /* Process Locked */
1834 __HAL_LOCK(hi2c);
1835
1836 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1837 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1838 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1839
1840 /* Enable Address Acknowledge */
1841 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1842
1843 /* Prepare transfer parameters */
1844 hi2c->pBuffPtr = pData;
1845 hi2c->XferCount = Size;
1846 hi2c->XferSize = hi2c->XferCount;
1847 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1848 hi2c->XferISR = I2C_Slave_ISR_IT;
1849
1850 /* Preload TX data if no stretch enable */
1851 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
1852 {
1853 /* Preload TX register */
1854 /* Write data to TXDR */
1855 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1856
1857 /* Increment Buffer pointer */
1858 hi2c->pBuffPtr++;
1859
1860 hi2c->XferCount--;
1861 hi2c->XferSize--;
1862 }
1863
1864 /* Process Unlocked */
1865 __HAL_UNLOCK(hi2c);
1866
1867 /* Note : The I2C interrupts must be enabled after unlocking current process
1868 to avoid the risk of I2C interrupt handle execution before current
1869 process unlock */
1870
1871 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1872 /* possible to enable all of these */
1873 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1874 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1875 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
1876
1877 return HAL_OK;
1878 }
1879 else
1880 {
1881 return HAL_BUSY;
1882 }
1883 }
1884
1885 /**
1886 * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
1887 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1888 * the configuration information for the specified I2C.
1889 * @param pData Pointer to data buffer
1890 * @param Size Amount of data to be sent
1891 * @retval HAL status
1892 */
HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1893 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1894 {
1895 if (hi2c->State == HAL_I2C_STATE_READY)
1896 {
1897 /* Process Locked */
1898 __HAL_LOCK(hi2c);
1899
1900 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1901 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1902 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1903
1904 /* Enable Address Acknowledge */
1905 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1906
1907 /* Prepare transfer parameters */
1908 hi2c->pBuffPtr = pData;
1909 hi2c->XferCount = Size;
1910 hi2c->XferSize = hi2c->XferCount;
1911 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1912 hi2c->XferISR = I2C_Slave_ISR_IT;
1913
1914 /* Process Unlocked */
1915 __HAL_UNLOCK(hi2c);
1916
1917 /* Note : The I2C interrupts must be enabled after unlocking current process
1918 to avoid the risk of I2C interrupt handle execution before current
1919 process unlock */
1920
1921 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1922 /* possible to enable all of these */
1923 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1924 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1925 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
1926
1927 return HAL_OK;
1928 }
1929 else
1930 {
1931 return HAL_BUSY;
1932 }
1933 }
1934
1935 #if defined(HAL_DMA_MODULE_ENABLED)
1936 /**
1937 * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
1938 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1939 * the configuration information for the specified I2C.
1940 * @param DevAddress Target device address: The device 7 bits address value
1941 * in datasheet must be shifted to the left before calling the interface
1942 * @param pData Pointer to data buffer
1943 * @param Size Amount of data to be sent
1944 * @retval HAL status
1945 */
HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1946 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1947 uint16_t Size)
1948 {
1949 uint32_t xfermode;
1950 HAL_StatusTypeDef dmaxferstatus;
1951 uint32_t sizetoxfer = 0U;
1952
1953 if (hi2c->State == HAL_I2C_STATE_READY)
1954 {
1955 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1956 {
1957 return HAL_BUSY;
1958 }
1959
1960 /* Process Locked */
1961 __HAL_LOCK(hi2c);
1962
1963 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1964 hi2c->Mode = HAL_I2C_MODE_MASTER;
1965 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1966
1967 /* Prepare transfer parameters */
1968 hi2c->pBuffPtr = pData;
1969 hi2c->XferCount = Size;
1970 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1971 hi2c->XferISR = I2C_Master_ISR_DMA;
1972
1973 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1974 {
1975 hi2c->XferSize = MAX_NBYTE_SIZE;
1976 xfermode = I2C_RELOAD_MODE;
1977 }
1978 else
1979 {
1980 hi2c->XferSize = hi2c->XferCount;
1981 xfermode = I2C_AUTOEND_MODE;
1982 }
1983
1984 if (hi2c->XferSize > 0U)
1985 {
1986 /* Preload TX register */
1987 /* Write data to TXDR */
1988 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1989
1990 /* Increment Buffer pointer */
1991 hi2c->pBuffPtr++;
1992
1993 sizetoxfer = hi2c->XferSize;
1994 hi2c->XferCount--;
1995 hi2c->XferSize--;
1996 }
1997
1998 if (hi2c->XferSize > 0U)
1999 {
2000 if (hi2c->hdmatx != NULL)
2001 {
2002 /* Set the I2C DMA transfer complete callback */
2003 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
2004
2005 /* Set the DMA error callback */
2006 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2007
2008 /* Set the unused DMA callbacks to NULL */
2009 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2010 hi2c->hdmatx->XferAbortCallback = NULL;
2011
2012 /* Enable the DMA channel */
2013 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
2014 (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
2015 }
2016 else
2017 {
2018 /* Update I2C state */
2019 hi2c->State = HAL_I2C_STATE_READY;
2020 hi2c->Mode = HAL_I2C_MODE_NONE;
2021
2022 /* Update I2C error code */
2023 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2024
2025 /* Process Unlocked */
2026 __HAL_UNLOCK(hi2c);
2027
2028 return HAL_ERROR;
2029 }
2030
2031 if (dmaxferstatus == HAL_OK)
2032 {
2033 /* Send Slave Address */
2034 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2035 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U),
2036 xfermode, I2C_GENERATE_START_WRITE);
2037
2038 /* Update XferCount value */
2039 hi2c->XferCount -= hi2c->XferSize;
2040
2041 /* Process Unlocked */
2042 __HAL_UNLOCK(hi2c);
2043
2044 /* Note : The I2C interrupts must be enabled after unlocking current process
2045 to avoid the risk of I2C interrupt handle execution before current
2046 process unlock */
2047 /* Enable ERR and NACK interrupts */
2048 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2049
2050 /* Enable DMA Request */
2051 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
2052 }
2053 else
2054 {
2055 /* Update I2C state */
2056 hi2c->State = HAL_I2C_STATE_READY;
2057 hi2c->Mode = HAL_I2C_MODE_NONE;
2058
2059 /* Update I2C error code */
2060 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2061
2062 /* Process Unlocked */
2063 __HAL_UNLOCK(hi2c);
2064
2065 return HAL_ERROR;
2066 }
2067 }
2068 else
2069 {
2070 /* Update Transfer ISR function pointer */
2071 hi2c->XferISR = I2C_Master_ISR_IT;
2072
2073 /* Send Slave Address */
2074 /* Set NBYTES to write and generate START condition */
2075 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, I2C_AUTOEND_MODE,
2076 I2C_GENERATE_START_WRITE);
2077
2078 /* Process Unlocked */
2079 __HAL_UNLOCK(hi2c);
2080
2081 /* Note : The I2C interrupts must be enabled after unlocking current process
2082 to avoid the risk of I2C interrupt handle execution before current
2083 process unlock */
2084 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2085 /* possible to enable all of these */
2086 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2087 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2088 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2089 }
2090
2091 return HAL_OK;
2092 }
2093 else
2094 {
2095 return HAL_BUSY;
2096 }
2097 }
2098
2099 /**
2100 * @brief Receive in master mode an amount of data in non-blocking mode with DMA
2101 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2102 * the configuration information for the specified I2C.
2103 * @param DevAddress Target device address: The device 7 bits address value
2104 * in datasheet must be shifted to the left before calling the interface
2105 * @param pData Pointer to data buffer
2106 * @param Size Amount of data to be sent
2107 * @retval HAL status
2108 */
HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)2109 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
2110 uint16_t Size)
2111 {
2112 uint32_t xfermode;
2113 HAL_StatusTypeDef dmaxferstatus;
2114
2115 if (hi2c->State == HAL_I2C_STATE_READY)
2116 {
2117 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2118 {
2119 return HAL_BUSY;
2120 }
2121
2122 /* Process Locked */
2123 __HAL_LOCK(hi2c);
2124
2125 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2126 hi2c->Mode = HAL_I2C_MODE_MASTER;
2127 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2128
2129 /* Prepare transfer parameters */
2130 hi2c->pBuffPtr = pData;
2131 hi2c->XferCount = Size;
2132 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2133 hi2c->XferISR = I2C_Master_ISR_DMA;
2134
2135 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2136 {
2137 hi2c->XferSize = MAX_NBYTE_SIZE;
2138 xfermode = I2C_RELOAD_MODE;
2139 }
2140 else
2141 {
2142 hi2c->XferSize = hi2c->XferCount;
2143 xfermode = I2C_AUTOEND_MODE;
2144 }
2145
2146 if (hi2c->XferSize > 0U)
2147 {
2148 if (hi2c->hdmarx != NULL)
2149 {
2150 /* Set the I2C DMA transfer complete callback */
2151 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
2152
2153 /* Set the DMA error callback */
2154 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2155
2156 /* Set the unused DMA callbacks to NULL */
2157 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2158 hi2c->hdmarx->XferAbortCallback = NULL;
2159
2160 /* Enable the DMA channel */
2161 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2162 hi2c->XferSize);
2163 }
2164 else
2165 {
2166 /* Update I2C state */
2167 hi2c->State = HAL_I2C_STATE_READY;
2168 hi2c->Mode = HAL_I2C_MODE_NONE;
2169
2170 /* Update I2C error code */
2171 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2172
2173 /* Process Unlocked */
2174 __HAL_UNLOCK(hi2c);
2175
2176 return HAL_ERROR;
2177 }
2178
2179 if (dmaxferstatus == HAL_OK)
2180 {
2181 /* Send Slave Address */
2182 /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2183 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
2184
2185 /* Update XferCount value */
2186 hi2c->XferCount -= hi2c->XferSize;
2187
2188 /* Process Unlocked */
2189 __HAL_UNLOCK(hi2c);
2190
2191 /* Note : The I2C interrupts must be enabled after unlocking current process
2192 to avoid the risk of I2C interrupt handle execution before current
2193 process unlock */
2194 /* Enable ERR and NACK interrupts */
2195 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2196
2197 /* Enable DMA Request */
2198 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2199 }
2200 else
2201 {
2202 /* Update I2C state */
2203 hi2c->State = HAL_I2C_STATE_READY;
2204 hi2c->Mode = HAL_I2C_MODE_NONE;
2205
2206 /* Update I2C error code */
2207 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2208
2209 /* Process Unlocked */
2210 __HAL_UNLOCK(hi2c);
2211
2212 return HAL_ERROR;
2213 }
2214 }
2215 else
2216 {
2217 /* Update Transfer ISR function pointer */
2218 hi2c->XferISR = I2C_Master_ISR_IT;
2219
2220 /* Send Slave Address */
2221 /* Set NBYTES to read and generate START condition */
2222 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2223 I2C_GENERATE_START_READ);
2224
2225 /* Process Unlocked */
2226 __HAL_UNLOCK(hi2c);
2227
2228 /* Note : The I2C interrupts must be enabled after unlocking current process
2229 to avoid the risk of I2C interrupt handle execution before current
2230 process unlock */
2231 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
2232 /* possible to enable all of these */
2233 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2234 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2235 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
2236 }
2237
2238 return HAL_OK;
2239 }
2240 else
2241 {
2242 return HAL_BUSY;
2243 }
2244 }
2245
2246 /**
2247 * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
2248 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2249 * the configuration information for the specified I2C.
2250 * @param pData Pointer to data buffer
2251 * @param Size Amount of data to be sent
2252 * @retval HAL status
2253 */
HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2254 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2255 {
2256 HAL_StatusTypeDef dmaxferstatus;
2257
2258 if (hi2c->State == HAL_I2C_STATE_READY)
2259 {
2260 if ((pData == NULL) || (Size == 0U))
2261 {
2262 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2263 return HAL_ERROR;
2264 }
2265 /* Process Locked */
2266 __HAL_LOCK(hi2c);
2267
2268 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2269 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2270 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2271
2272 /* Prepare transfer parameters */
2273 hi2c->pBuffPtr = pData;
2274 hi2c->XferCount = Size;
2275 hi2c->XferSize = hi2c->XferCount;
2276 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2277 hi2c->XferISR = I2C_Slave_ISR_DMA;
2278
2279 /* Preload TX data if no stretch enable */
2280 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
2281 {
2282 /* Preload TX register */
2283 /* Write data to TXDR */
2284 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
2285
2286 /* Increment Buffer pointer */
2287 hi2c->pBuffPtr++;
2288
2289 hi2c->XferCount--;
2290 hi2c->XferSize--;
2291 }
2292
2293 if (hi2c->XferCount != 0U)
2294 {
2295 if (hi2c->hdmatx != NULL)
2296 {
2297 /* Set the I2C DMA transfer complete callback */
2298 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
2299
2300 /* Set the DMA error callback */
2301 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2302
2303 /* Set the unused DMA callbacks to NULL */
2304 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2305 hi2c->hdmatx->XferAbortCallback = NULL;
2306
2307 /* Enable the DMA channel */
2308 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx,
2309 (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
2310 hi2c->XferSize);
2311 }
2312 else
2313 {
2314 /* Update I2C state */
2315 hi2c->State = HAL_I2C_STATE_LISTEN;
2316 hi2c->Mode = HAL_I2C_MODE_NONE;
2317
2318 /* Update I2C error code */
2319 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2320
2321 /* Process Unlocked */
2322 __HAL_UNLOCK(hi2c);
2323
2324 return HAL_ERROR;
2325 }
2326
2327 if (dmaxferstatus == HAL_OK)
2328 {
2329 /* Enable Address Acknowledge */
2330 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2331
2332 /* Process Unlocked */
2333 __HAL_UNLOCK(hi2c);
2334
2335 /* Note : The I2C interrupts must be enabled after unlocking current process
2336 to avoid the risk of I2C interrupt handle execution before current
2337 process unlock */
2338 /* Enable ERR, STOP, NACK, ADDR interrupts */
2339 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2340
2341 /* Enable DMA Request */
2342 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
2343 }
2344 else
2345 {
2346 /* Update I2C state */
2347 hi2c->State = HAL_I2C_STATE_LISTEN;
2348 hi2c->Mode = HAL_I2C_MODE_NONE;
2349
2350 /* Update I2C error code */
2351 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2352
2353 /* Process Unlocked */
2354 __HAL_UNLOCK(hi2c);
2355
2356 return HAL_ERROR;
2357 }
2358 }
2359 else
2360 {
2361 /* Enable Address Acknowledge */
2362 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2363
2364 /* Process Unlocked */
2365 __HAL_UNLOCK(hi2c);
2366
2367 /* Note : The I2C interrupts must be enabled after unlocking current process
2368 to avoid the risk of I2C interrupt handle execution before current
2369 process unlock */
2370 /* Enable ERR, STOP, NACK, ADDR interrupts */
2371 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2372 }
2373
2374 return HAL_OK;
2375 }
2376 else
2377 {
2378 return HAL_BUSY;
2379 }
2380 }
2381
2382 /**
2383 * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
2384 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2385 * the configuration information for the specified I2C.
2386 * @param pData Pointer to data buffer
2387 * @param Size Amount of data to be sent
2388 * @retval HAL status
2389 */
HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2390 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2391 {
2392 HAL_StatusTypeDef dmaxferstatus;
2393
2394 if (hi2c->State == HAL_I2C_STATE_READY)
2395 {
2396 if ((pData == NULL) || (Size == 0U))
2397 {
2398 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2399 return HAL_ERROR;
2400 }
2401 /* Process Locked */
2402 __HAL_LOCK(hi2c);
2403
2404 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2405 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2406 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2407
2408 /* Prepare transfer parameters */
2409 hi2c->pBuffPtr = pData;
2410 hi2c->XferCount = Size;
2411 hi2c->XferSize = hi2c->XferCount;
2412 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2413 hi2c->XferISR = I2C_Slave_ISR_DMA;
2414
2415 if (hi2c->hdmarx != NULL)
2416 {
2417 /* Set the I2C DMA transfer complete callback */
2418 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
2419
2420 /* Set the DMA error callback */
2421 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2422
2423 /* Set the unused DMA callbacks to NULL */
2424 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2425 hi2c->hdmarx->XferAbortCallback = NULL;
2426
2427 /* Enable the DMA channel */
2428 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2429 hi2c->XferSize);
2430 }
2431 else
2432 {
2433 /* Update I2C state */
2434 hi2c->State = HAL_I2C_STATE_LISTEN;
2435 hi2c->Mode = HAL_I2C_MODE_NONE;
2436
2437 /* Update I2C error code */
2438 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2439
2440 /* Process Unlocked */
2441 __HAL_UNLOCK(hi2c);
2442
2443 return HAL_ERROR;
2444 }
2445
2446 if (dmaxferstatus == HAL_OK)
2447 {
2448 /* Enable Address Acknowledge */
2449 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2450
2451 /* Process Unlocked */
2452 __HAL_UNLOCK(hi2c);
2453
2454 /* Note : The I2C interrupts must be enabled after unlocking current process
2455 to avoid the risk of I2C interrupt handle execution before current
2456 process unlock */
2457 /* Enable ERR, STOP, NACK, ADDR interrupts */
2458 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2459
2460 /* Enable DMA Request */
2461 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2462 }
2463 else
2464 {
2465 /* Update I2C state */
2466 hi2c->State = HAL_I2C_STATE_LISTEN;
2467 hi2c->Mode = HAL_I2C_MODE_NONE;
2468
2469 /* Update I2C error code */
2470 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2471
2472 /* Process Unlocked */
2473 __HAL_UNLOCK(hi2c);
2474
2475 return HAL_ERROR;
2476 }
2477
2478 return HAL_OK;
2479 }
2480 else
2481 {
2482 return HAL_BUSY;
2483 }
2484 }
2485 #endif /* HAL_DMA_MODULE_ENABLED */
2486
2487 /**
2488 * @brief Write an amount of data in blocking mode to a specific memory address
2489 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2490 * the configuration information for the specified I2C.
2491 * @param DevAddress Target device address: The device 7 bits address value
2492 * in datasheet must be shifted to the left before calling the interface
2493 * @param MemAddress Internal memory address
2494 * @param MemAddSize Size of internal memory address
2495 * @param pData Pointer to data buffer
2496 * @param Size Amount of data to be sent
2497 * @param Timeout Timeout duration
2498 * @retval HAL status
2499 */
HAL_I2C_Mem_Write(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2500 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2501 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2502 {
2503 uint32_t tickstart;
2504
2505 /* Check the parameters */
2506 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2507
2508 if (hi2c->State == HAL_I2C_STATE_READY)
2509 {
2510 if ((pData == NULL) || (Size == 0U))
2511 {
2512 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2513 return HAL_ERROR;
2514 }
2515
2516 /* Process Locked */
2517 __HAL_LOCK(hi2c);
2518
2519 /* Init tickstart for timeout management*/
2520 tickstart = HAL_GetTick();
2521
2522 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2523 {
2524 return HAL_ERROR;
2525 }
2526
2527 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2528 hi2c->Mode = HAL_I2C_MODE_MEM;
2529 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2530
2531 /* Prepare transfer parameters */
2532 hi2c->pBuffPtr = pData;
2533 hi2c->XferCount = Size;
2534 hi2c->XferISR = NULL;
2535
2536 /* Send Slave Address and Memory Address */
2537 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2538 {
2539 /* Process Unlocked */
2540 __HAL_UNLOCK(hi2c);
2541 return HAL_ERROR;
2542 }
2543
2544 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
2545 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2546 {
2547 hi2c->XferSize = MAX_NBYTE_SIZE;
2548 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
2549 }
2550 else
2551 {
2552 hi2c->XferSize = hi2c->XferCount;
2553 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
2554 }
2555
2556 do
2557 {
2558 /* Wait until TXIS flag is set */
2559 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2560 {
2561 return HAL_ERROR;
2562 }
2563
2564 /* Write data to TXDR */
2565 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
2566
2567 /* Increment Buffer pointer */
2568 hi2c->pBuffPtr++;
2569
2570 hi2c->XferCount--;
2571 hi2c->XferSize--;
2572
2573 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2574 {
2575 /* Wait until TCR flag is set */
2576 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2577 {
2578 return HAL_ERROR;
2579 }
2580
2581 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2582 {
2583 hi2c->XferSize = MAX_NBYTE_SIZE;
2584 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
2585 I2C_NO_STARTSTOP);
2586 }
2587 else
2588 {
2589 hi2c->XferSize = hi2c->XferCount;
2590 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2591 I2C_NO_STARTSTOP);
2592 }
2593 }
2594
2595 } while (hi2c->XferCount > 0U);
2596
2597 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2598 /* Wait until STOPF flag is reset */
2599 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2600 {
2601 return HAL_ERROR;
2602 }
2603
2604 /* Clear STOP Flag */
2605 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2606
2607 /* Clear Configuration Register 2 */
2608 I2C_RESET_CR2(hi2c);
2609
2610 hi2c->State = HAL_I2C_STATE_READY;
2611 hi2c->Mode = HAL_I2C_MODE_NONE;
2612
2613 /* Process Unlocked */
2614 __HAL_UNLOCK(hi2c);
2615
2616 return HAL_OK;
2617 }
2618 else
2619 {
2620 return HAL_BUSY;
2621 }
2622 }
2623
2624 /**
2625 * @brief Read an amount of data in blocking mode from a specific memory address
2626 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2627 * the configuration information for the specified I2C.
2628 * @param DevAddress Target device address: The device 7 bits address value
2629 * in datasheet must be shifted to the left before calling the interface
2630 * @param MemAddress Internal memory address
2631 * @param MemAddSize Size of internal memory address
2632 * @param pData Pointer to data buffer
2633 * @param Size Amount of data to be sent
2634 * @param Timeout Timeout duration
2635 * @retval HAL status
2636 */
HAL_I2C_Mem_Read(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2637 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2638 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2639 {
2640 uint32_t tickstart;
2641
2642 /* Check the parameters */
2643 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2644
2645 if (hi2c->State == HAL_I2C_STATE_READY)
2646 {
2647 if ((pData == NULL) || (Size == 0U))
2648 {
2649 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2650 return HAL_ERROR;
2651 }
2652
2653 /* Process Locked */
2654 __HAL_LOCK(hi2c);
2655
2656 /* Init tickstart for timeout management*/
2657 tickstart = HAL_GetTick();
2658
2659 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2660 {
2661 return HAL_ERROR;
2662 }
2663
2664 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2665 hi2c->Mode = HAL_I2C_MODE_MEM;
2666 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2667
2668 /* Prepare transfer parameters */
2669 hi2c->pBuffPtr = pData;
2670 hi2c->XferCount = Size;
2671 hi2c->XferISR = NULL;
2672
2673 /* Send Slave Address and Memory Address */
2674 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2675 {
2676 /* Process Unlocked */
2677 __HAL_UNLOCK(hi2c);
2678 return HAL_ERROR;
2679 }
2680
2681 /* Send Slave Address */
2682 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2683 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2684 {
2685 hi2c->XferSize = MAX_NBYTE_SIZE;
2686 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
2687 I2C_GENERATE_START_READ);
2688 }
2689 else
2690 {
2691 hi2c->XferSize = hi2c->XferCount;
2692 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2693 I2C_GENERATE_START_READ);
2694 }
2695
2696 do
2697 {
2698 /* Wait until RXNE flag is set */
2699 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
2700 {
2701 return HAL_ERROR;
2702 }
2703
2704 /* Read data from RXDR */
2705 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
2706
2707 /* Increment Buffer pointer */
2708 hi2c->pBuffPtr++;
2709
2710 hi2c->XferSize--;
2711 hi2c->XferCount--;
2712
2713 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2714 {
2715 /* Wait until TCR flag is set */
2716 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2717 {
2718 return HAL_ERROR;
2719 }
2720
2721 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2722 {
2723 hi2c->XferSize = MAX_NBYTE_SIZE;
2724 I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
2725 I2C_NO_STARTSTOP);
2726 }
2727 else
2728 {
2729 hi2c->XferSize = hi2c->XferCount;
2730 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2731 I2C_NO_STARTSTOP);
2732 }
2733 }
2734 } while (hi2c->XferCount > 0U);
2735
2736 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2737 /* Wait until STOPF flag is reset */
2738 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2739 {
2740 return HAL_ERROR;
2741 }
2742
2743 /* Clear STOP Flag */
2744 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2745
2746 /* Clear Configuration Register 2 */
2747 I2C_RESET_CR2(hi2c);
2748
2749 hi2c->State = HAL_I2C_STATE_READY;
2750 hi2c->Mode = HAL_I2C_MODE_NONE;
2751
2752 /* Process Unlocked */
2753 __HAL_UNLOCK(hi2c);
2754
2755 return HAL_OK;
2756 }
2757 else
2758 {
2759 return HAL_BUSY;
2760 }
2761 }
2762 /**
2763 * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
2764 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2765 * the configuration information for the specified I2C.
2766 * @param DevAddress Target device address: The device 7 bits address value
2767 * in datasheet must be shifted to the left before calling the interface
2768 * @param MemAddress Internal memory address
2769 * @param MemAddSize Size of internal memory address
2770 * @param pData Pointer to data buffer
2771 * @param Size Amount of data to be sent
2772 * @retval HAL status
2773 */
HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2774 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2775 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2776 {
2777 /* Check the parameters */
2778 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2779
2780 if (hi2c->State == HAL_I2C_STATE_READY)
2781 {
2782 if ((pData == NULL) || (Size == 0U))
2783 {
2784 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2785 return HAL_ERROR;
2786 }
2787
2788 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2789 {
2790 return HAL_BUSY;
2791 }
2792
2793 /* Process Locked */
2794 __HAL_LOCK(hi2c);
2795
2796 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2797 hi2c->Mode = HAL_I2C_MODE_MEM;
2798 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2799
2800 /* Prepare transfer parameters */
2801 hi2c->XferSize = 0U;
2802 hi2c->pBuffPtr = pData;
2803 hi2c->XferCount = Size;
2804 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2805 hi2c->XferISR = I2C_Mem_ISR_IT;
2806 hi2c->Devaddress = DevAddress;
2807
2808 /* If Memory address size is 8Bit */
2809 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
2810 {
2811 /* Prefetch Memory Address */
2812 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
2813
2814 /* Reset Memaddress content */
2815 hi2c->Memaddress = 0xFFFFFFFFU;
2816 }
2817 /* If Memory address size is 16Bit */
2818 else
2819 {
2820 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
2821 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
2822
2823 /* Prepare Memaddress buffer for LSB part */
2824 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
2825 }
2826 /* Send Slave Address and Memory Address */
2827 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
2828
2829 /* Process Unlocked */
2830 __HAL_UNLOCK(hi2c);
2831
2832 /* Note : The I2C interrupts must be enabled after unlocking current process
2833 to avoid the risk of I2C interrupt handle execution before current
2834 process unlock */
2835
2836 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2837 /* possible to enable all of these */
2838 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2839 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2840 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2841
2842 return HAL_OK;
2843 }
2844 else
2845 {
2846 return HAL_BUSY;
2847 }
2848 }
2849
2850 /**
2851 * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
2852 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2853 * the configuration information for the specified I2C.
2854 * @param DevAddress Target device address: The device 7 bits address value
2855 * in datasheet must be shifted to the left before calling the interface
2856 * @param MemAddress Internal memory address
2857 * @param MemAddSize Size of internal memory address
2858 * @param pData Pointer to data buffer
2859 * @param Size Amount of data to be sent
2860 * @retval HAL status
2861 */
HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2862 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2863 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2864 {
2865 /* Check the parameters */
2866 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2867
2868 if (hi2c->State == HAL_I2C_STATE_READY)
2869 {
2870 if ((pData == NULL) || (Size == 0U))
2871 {
2872 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2873 return HAL_ERROR;
2874 }
2875
2876 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2877 {
2878 return HAL_BUSY;
2879 }
2880
2881 /* Process Locked */
2882 __HAL_LOCK(hi2c);
2883
2884 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2885 hi2c->Mode = HAL_I2C_MODE_MEM;
2886 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2887
2888 /* Prepare transfer parameters */
2889 hi2c->pBuffPtr = pData;
2890 hi2c->XferCount = Size;
2891 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2892 hi2c->XferISR = I2C_Mem_ISR_IT;
2893 hi2c->Devaddress = DevAddress;
2894
2895 /* If Memory address size is 8Bit */
2896 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
2897 {
2898 /* Prefetch Memory Address */
2899 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
2900
2901 /* Reset Memaddress content */
2902 hi2c->Memaddress = 0xFFFFFFFFU;
2903 }
2904 /* If Memory address size is 16Bit */
2905 else
2906 {
2907 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
2908 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
2909
2910 /* Prepare Memaddress buffer for LSB part */
2911 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
2912 }
2913 /* Send Slave Address and Memory Address */
2914 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
2915
2916 /* Process Unlocked */
2917 __HAL_UNLOCK(hi2c);
2918
2919 /* Note : The I2C interrupts must be enabled after unlocking current process
2920 to avoid the risk of I2C interrupt handle execution before current
2921 process unlock */
2922
2923 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2924 /* possible to enable all of these */
2925 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2926 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2927 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2928
2929 return HAL_OK;
2930 }
2931 else
2932 {
2933 return HAL_BUSY;
2934 }
2935 }
2936
2937 #if defined(HAL_DMA_MODULE_ENABLED)
2938 /**
2939 * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
2940 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2941 * the configuration information for the specified I2C.
2942 * @param DevAddress Target device address: The device 7 bits address value
2943 * in datasheet must be shifted to the left before calling the interface
2944 * @param MemAddress Internal memory address
2945 * @param MemAddSize Size of internal memory address
2946 * @param pData Pointer to data buffer
2947 * @param Size Amount of data to be sent
2948 * @retval HAL status
2949 */
HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2950 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2951 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2952 {
2953 HAL_StatusTypeDef dmaxferstatus;
2954
2955 /* Check the parameters */
2956 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2957
2958 if (hi2c->State == HAL_I2C_STATE_READY)
2959 {
2960 if ((pData == NULL) || (Size == 0U))
2961 {
2962 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2963 return HAL_ERROR;
2964 }
2965
2966 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2967 {
2968 return HAL_BUSY;
2969 }
2970
2971 /* Process Locked */
2972 __HAL_LOCK(hi2c);
2973
2974 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2975 hi2c->Mode = HAL_I2C_MODE_MEM;
2976 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2977
2978 /* Prepare transfer parameters */
2979 hi2c->pBuffPtr = pData;
2980 hi2c->XferCount = Size;
2981 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2982 hi2c->XferISR = I2C_Mem_ISR_DMA;
2983 hi2c->Devaddress = DevAddress;
2984
2985 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2986 {
2987 hi2c->XferSize = MAX_NBYTE_SIZE;
2988 }
2989 else
2990 {
2991 hi2c->XferSize = hi2c->XferCount;
2992 }
2993
2994 /* If Memory address size is 8Bit */
2995 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
2996 {
2997 /* Prefetch Memory Address */
2998 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
2999
3000 /* Reset Memaddress content */
3001 hi2c->Memaddress = 0xFFFFFFFFU;
3002 }
3003 /* If Memory address size is 16Bit */
3004 else
3005 {
3006 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
3007 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3008
3009 /* Prepare Memaddress buffer for LSB part */
3010 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
3011 }
3012
3013 if (hi2c->hdmatx != NULL)
3014 {
3015 /* Set the I2C DMA transfer complete callback */
3016 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
3017
3018 /* Set the DMA error callback */
3019 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3020
3021 /* Set the unused DMA callbacks to NULL */
3022 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3023 hi2c->hdmatx->XferAbortCallback = NULL;
3024
3025 /* Enable the DMA channel */
3026 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
3027 hi2c->XferSize);
3028 }
3029 else
3030 {
3031 /* Update I2C state */
3032 hi2c->State = HAL_I2C_STATE_READY;
3033 hi2c->Mode = HAL_I2C_MODE_NONE;
3034
3035 /* Update I2C error code */
3036 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3037
3038 /* Process Unlocked */
3039 __HAL_UNLOCK(hi2c);
3040
3041 return HAL_ERROR;
3042 }
3043
3044 if (dmaxferstatus == HAL_OK)
3045 {
3046 /* Send Slave Address and Memory Address */
3047 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
3048
3049 /* Process Unlocked */
3050 __HAL_UNLOCK(hi2c);
3051
3052 /* Note : The I2C interrupts must be enabled after unlocking current process
3053 to avoid the risk of I2C interrupt handle execution before current
3054 process unlock */
3055 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3056 /* possible to enable all of these */
3057 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3058 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3059 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3060 }
3061 else
3062 {
3063 /* Update I2C state */
3064 hi2c->State = HAL_I2C_STATE_READY;
3065 hi2c->Mode = HAL_I2C_MODE_NONE;
3066
3067 /* Update I2C error code */
3068 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3069
3070 /* Process Unlocked */
3071 __HAL_UNLOCK(hi2c);
3072
3073 return HAL_ERROR;
3074 }
3075
3076 return HAL_OK;
3077 }
3078 else
3079 {
3080 return HAL_BUSY;
3081 }
3082 }
3083
3084 /**
3085 * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
3086 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3087 * the configuration information for the specified I2C.
3088 * @param DevAddress Target device address: The device 7 bits address value
3089 * in datasheet must be shifted to the left before calling the interface
3090 * @param MemAddress Internal memory address
3091 * @param MemAddSize Size of internal memory address
3092 * @param pData Pointer to data buffer
3093 * @param Size Amount of data to be read
3094 * @retval HAL status
3095 */
HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)3096 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
3097 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3098 {
3099 HAL_StatusTypeDef dmaxferstatus;
3100
3101 /* Check the parameters */
3102 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3103
3104 if (hi2c->State == HAL_I2C_STATE_READY)
3105 {
3106 if ((pData == NULL) || (Size == 0U))
3107 {
3108 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3109 return HAL_ERROR;
3110 }
3111
3112 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3113 {
3114 return HAL_BUSY;
3115 }
3116
3117 /* Process Locked */
3118 __HAL_LOCK(hi2c);
3119
3120 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3121 hi2c->Mode = HAL_I2C_MODE_MEM;
3122 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3123
3124 /* Prepare transfer parameters */
3125 hi2c->pBuffPtr = pData;
3126 hi2c->XferCount = Size;
3127 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3128 hi2c->XferISR = I2C_Mem_ISR_DMA;
3129 hi2c->Devaddress = DevAddress;
3130
3131 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3132 {
3133 hi2c->XferSize = MAX_NBYTE_SIZE;
3134 }
3135 else
3136 {
3137 hi2c->XferSize = hi2c->XferCount;
3138 }
3139
3140 /* If Memory address size is 8Bit */
3141 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
3142 {
3143 /* Prefetch Memory Address */
3144 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3145
3146 /* Reset Memaddress content */
3147 hi2c->Memaddress = 0xFFFFFFFFU;
3148 }
3149 /* If Memory address size is 16Bit */
3150 else
3151 {
3152 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
3153 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3154
3155 /* Prepare Memaddress buffer for LSB part */
3156 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
3157 }
3158
3159 if (hi2c->hdmarx != NULL)
3160 {
3161 /* Set the I2C DMA transfer complete callback */
3162 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
3163
3164 /* Set the DMA error callback */
3165 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3166
3167 /* Set the unused DMA callbacks to NULL */
3168 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3169 hi2c->hdmarx->XferAbortCallback = NULL;
3170
3171 /* Enable the DMA channel */
3172 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
3173 hi2c->XferSize);
3174 }
3175 else
3176 {
3177 /* Update I2C state */
3178 hi2c->State = HAL_I2C_STATE_READY;
3179 hi2c->Mode = HAL_I2C_MODE_NONE;
3180
3181 /* Update I2C error code */
3182 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3183
3184 /* Process Unlocked */
3185 __HAL_UNLOCK(hi2c);
3186
3187 return HAL_ERROR;
3188 }
3189
3190 if (dmaxferstatus == HAL_OK)
3191 {
3192 /* Send Slave Address and Memory Address */
3193 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
3194
3195 /* Process Unlocked */
3196 __HAL_UNLOCK(hi2c);
3197
3198 /* Note : The I2C interrupts must be enabled after unlocking current process
3199 to avoid the risk of I2C interrupt handle execution before current
3200 process unlock */
3201 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3202 /* possible to enable all of these */
3203 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3204 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3205 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3206 }
3207 else
3208 {
3209 /* Update I2C state */
3210 hi2c->State = HAL_I2C_STATE_READY;
3211 hi2c->Mode = HAL_I2C_MODE_NONE;
3212
3213 /* Update I2C error code */
3214 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3215
3216 /* Process Unlocked */
3217 __HAL_UNLOCK(hi2c);
3218
3219 return HAL_ERROR;
3220 }
3221
3222 return HAL_OK;
3223 }
3224 else
3225 {
3226 return HAL_BUSY;
3227 }
3228 }
3229 #endif /* HAL_DMA_MODULE_ENABLED */
3230
3231 /**
3232 * @brief Checks if target device is ready for communication.
3233 * @note This function is used with Memory devices
3234 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3235 * the configuration information for the specified I2C.
3236 * @param DevAddress Target device address: The device 7 bits address value
3237 * in datasheet must be shifted to the left before calling the interface
3238 * @param Trials Number of trials
3239 * @param Timeout Timeout duration
3240 * @retval HAL status
3241 */
HAL_I2C_IsDeviceReady(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Trials,uint32_t Timeout)3242 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
3243 uint32_t Timeout)
3244 {
3245 uint32_t tickstart;
3246
3247 __IO uint32_t I2C_Trials = 0UL;
3248
3249 FlagStatus tmp1;
3250 FlagStatus tmp2;
3251
3252 if (hi2c->State == HAL_I2C_STATE_READY)
3253 {
3254 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3255 {
3256 return HAL_BUSY;
3257 }
3258
3259 /* Process Locked */
3260 __HAL_LOCK(hi2c);
3261
3262 hi2c->State = HAL_I2C_STATE_BUSY;
3263 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3264
3265 do
3266 {
3267 /* Generate Start */
3268 hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
3269
3270 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
3271 /* Wait until STOPF flag is set or a NACK flag is set*/
3272 tickstart = HAL_GetTick();
3273
3274 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3275 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3276
3277 while ((tmp1 == RESET) && (tmp2 == RESET))
3278 {
3279 if (Timeout != HAL_MAX_DELAY)
3280 {
3281 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3282 {
3283 /* Update I2C state */
3284 hi2c->State = HAL_I2C_STATE_READY;
3285
3286 /* Update I2C error code */
3287 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3288
3289 /* Process Unlocked */
3290 __HAL_UNLOCK(hi2c);
3291
3292 return HAL_ERROR;
3293 }
3294 }
3295
3296 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3297 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3298 }
3299
3300 /* Check if the NACKF flag has not been set */
3301 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
3302 {
3303 /* Wait until STOPF flag is reset */
3304 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3305 {
3306 return HAL_ERROR;
3307 }
3308
3309 /* Clear STOP Flag */
3310 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3311
3312 /* Device is ready */
3313 hi2c->State = HAL_I2C_STATE_READY;
3314
3315 /* Process Unlocked */
3316 __HAL_UNLOCK(hi2c);
3317
3318 return HAL_OK;
3319 }
3320 else
3321 {
3322 /* Wait until STOPF flag is reset */
3323 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3324 {
3325 return HAL_ERROR;
3326 }
3327
3328 /* Clear NACK Flag */
3329 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3330
3331 /* Clear STOP Flag, auto generated with autoend*/
3332 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3333 }
3334
3335 /* Check if the maximum allowed number of trials has been reached */
3336 if (I2C_Trials == Trials)
3337 {
3338 /* Generate Stop */
3339 hi2c->Instance->CR2 |= I2C_CR2_STOP;
3340
3341 /* Wait until STOPF flag is reset */
3342 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3343 {
3344 return HAL_ERROR;
3345 }
3346
3347 /* Clear STOP Flag */
3348 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3349 }
3350
3351 /* Increment Trials */
3352 I2C_Trials++;
3353 } while (I2C_Trials < Trials);
3354
3355 /* Update I2C state */
3356 hi2c->State = HAL_I2C_STATE_READY;
3357
3358 /* Update I2C error code */
3359 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3360
3361 /* Process Unlocked */
3362 __HAL_UNLOCK(hi2c);
3363
3364 return HAL_ERROR;
3365 }
3366 else
3367 {
3368 return HAL_BUSY;
3369 }
3370 }
3371
3372 /**
3373 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
3374 * @note This interface allow to manage repeated start condition when a direction change during transfer
3375 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3376 * the configuration information for the specified I2C.
3377 * @param DevAddress Target device address: The device 7 bits address value
3378 * in datasheet must be shifted to the left before calling the interface
3379 * @param pData Pointer to data buffer
3380 * @param Size Amount of data to be sent
3381 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3382 * @retval HAL status
3383 */
HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3384 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3385 uint16_t Size, uint32_t XferOptions)
3386 {
3387 uint32_t xfermode;
3388 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3389 uint32_t sizetoxfer = 0U;
3390
3391 /* Check the parameters */
3392 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3393
3394 if (hi2c->State == HAL_I2C_STATE_READY)
3395 {
3396 /* Process Locked */
3397 __HAL_LOCK(hi2c);
3398
3399 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3400 hi2c->Mode = HAL_I2C_MODE_MASTER;
3401 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3402
3403 /* Prepare transfer parameters */
3404 hi2c->pBuffPtr = pData;
3405 hi2c->XferCount = Size;
3406 hi2c->XferOptions = XferOptions;
3407 hi2c->XferISR = I2C_Master_ISR_IT;
3408
3409 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3410 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3411 {
3412 hi2c->XferSize = MAX_NBYTE_SIZE;
3413 xfermode = I2C_RELOAD_MODE;
3414 }
3415 else
3416 {
3417 hi2c->XferSize = hi2c->XferCount;
3418 xfermode = hi2c->XferOptions;
3419 }
3420
3421 if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
3422 (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
3423 {
3424 /* Preload TX register */
3425 /* Write data to TXDR */
3426 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
3427
3428 /* Increment Buffer pointer */
3429 hi2c->pBuffPtr++;
3430
3431 sizetoxfer = hi2c->XferSize;
3432 hi2c->XferCount--;
3433 hi2c->XferSize--;
3434 }
3435
3436 /* If transfer direction not change and there is no request to start another frame,
3437 do not generate Restart Condition */
3438 /* Mean Previous state is same as current state */
3439 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
3440 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3441 {
3442 xferrequest = I2C_NO_STARTSTOP;
3443 }
3444 else
3445 {
3446 /* Convert OTHER_xxx XferOptions if any */
3447 I2C_ConvertOtherXferOptions(hi2c);
3448
3449 /* Update xfermode accordingly if no reload is necessary */
3450 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3451 {
3452 xfermode = hi2c->XferOptions;
3453 }
3454 }
3455
3456 /* Send Slave Address and set NBYTES to write */
3457 if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
3458 {
3459 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
3460 }
3461 else
3462 {
3463 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3464 }
3465
3466 /* Process Unlocked */
3467 __HAL_UNLOCK(hi2c);
3468
3469 /* Note : The I2C interrupts must be enabled after unlocking current process
3470 to avoid the risk of I2C interrupt handle execution before current
3471 process unlock */
3472 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3473 /* possible to enable all of these */
3474 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3475 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3476 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3477
3478 return HAL_OK;
3479 }
3480 else
3481 {
3482 return HAL_BUSY;
3483 }
3484 }
3485
3486 #if defined(HAL_DMA_MODULE_ENABLED)
3487 /**
3488 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
3489 * @note This interface allow to manage repeated start condition when a direction change during transfer
3490 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3491 * the configuration information for the specified I2C.
3492 * @param DevAddress Target device address: The device 7 bits address value
3493 * in datasheet must be shifted to the left before calling the interface
3494 * @param pData Pointer to data buffer
3495 * @param Size Amount of data to be sent
3496 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3497 * @retval HAL status
3498 */
HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3499 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3500 uint16_t Size, uint32_t XferOptions)
3501 {
3502 uint32_t xfermode;
3503 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3504 HAL_StatusTypeDef dmaxferstatus;
3505 uint32_t sizetoxfer = 0U;
3506
3507 /* Check the parameters */
3508 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3509
3510 if (hi2c->State == HAL_I2C_STATE_READY)
3511 {
3512 /* Process Locked */
3513 __HAL_LOCK(hi2c);
3514
3515 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3516 hi2c->Mode = HAL_I2C_MODE_MASTER;
3517 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3518
3519 /* Prepare transfer parameters */
3520 hi2c->pBuffPtr = pData;
3521 hi2c->XferCount = Size;
3522 hi2c->XferOptions = XferOptions;
3523 hi2c->XferISR = I2C_Master_ISR_DMA;
3524
3525 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3526 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3527 {
3528 hi2c->XferSize = MAX_NBYTE_SIZE;
3529 xfermode = I2C_RELOAD_MODE;
3530 }
3531 else
3532 {
3533 hi2c->XferSize = hi2c->XferCount;
3534 xfermode = hi2c->XferOptions;
3535 }
3536
3537 if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
3538 (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
3539 {
3540 /* Preload TX register */
3541 /* Write data to TXDR */
3542 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
3543
3544 /* Increment Buffer pointer */
3545 hi2c->pBuffPtr++;
3546
3547 sizetoxfer = hi2c->XferSize;
3548 hi2c->XferCount--;
3549 hi2c->XferSize--;
3550 }
3551
3552 /* If transfer direction not change and there is no request to start another frame,
3553 do not generate Restart Condition */
3554 /* Mean Previous state is same as current state */
3555 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
3556 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3557 {
3558 xferrequest = I2C_NO_STARTSTOP;
3559 }
3560 else
3561 {
3562 /* Convert OTHER_xxx XferOptions if any */
3563 I2C_ConvertOtherXferOptions(hi2c);
3564
3565 /* Update xfermode accordingly if no reload is necessary */
3566 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3567 {
3568 xfermode = hi2c->XferOptions;
3569 }
3570 }
3571
3572 if (hi2c->XferSize > 0U)
3573 {
3574 if (hi2c->hdmatx != NULL)
3575 {
3576 /* Set the I2C DMA transfer complete callback */
3577 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
3578
3579 /* Set the DMA error callback */
3580 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3581
3582 /* Set the unused DMA callbacks to NULL */
3583 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3584 hi2c->hdmatx->XferAbortCallback = NULL;
3585
3586 /* Enable the DMA channel */
3587 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
3588 (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
3589 }
3590 else
3591 {
3592 /* Update I2C state */
3593 hi2c->State = HAL_I2C_STATE_READY;
3594 hi2c->Mode = HAL_I2C_MODE_NONE;
3595
3596 /* Update I2C error code */
3597 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3598
3599 /* Process Unlocked */
3600 __HAL_UNLOCK(hi2c);
3601
3602 return HAL_ERROR;
3603 }
3604
3605 if (dmaxferstatus == HAL_OK)
3606 {
3607 /* Send Slave Address and set NBYTES to write */
3608 if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
3609 {
3610 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
3611 }
3612 else
3613 {
3614 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3615 }
3616
3617 /* Update XferCount value */
3618 hi2c->XferCount -= hi2c->XferSize;
3619
3620 /* Process Unlocked */
3621 __HAL_UNLOCK(hi2c);
3622
3623 /* Note : The I2C interrupts must be enabled after unlocking current process
3624 to avoid the risk of I2C interrupt handle execution before current
3625 process unlock */
3626 /* Enable ERR and NACK interrupts */
3627 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
3628
3629 /* Enable DMA Request */
3630 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
3631 }
3632 else
3633 {
3634 /* Update I2C state */
3635 hi2c->State = HAL_I2C_STATE_READY;
3636 hi2c->Mode = HAL_I2C_MODE_NONE;
3637
3638 /* Update I2C error code */
3639 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3640
3641 /* Process Unlocked */
3642 __HAL_UNLOCK(hi2c);
3643
3644 return HAL_ERROR;
3645 }
3646 }
3647 else
3648 {
3649 /* Update Transfer ISR function pointer */
3650 hi2c->XferISR = I2C_Master_ISR_IT;
3651
3652 /* Send Slave Address */
3653 /* Set NBYTES to write and generate START condition */
3654 if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
3655 {
3656 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
3657 }
3658 else
3659 {
3660 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3661 }
3662
3663 /* Process Unlocked */
3664 __HAL_UNLOCK(hi2c);
3665
3666 /* Note : The I2C interrupts must be enabled after unlocking current process
3667 to avoid the risk of I2C interrupt handle execution before current
3668 process unlock */
3669 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3670 /* possible to enable all of these */
3671 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3672 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3673 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3674 }
3675
3676 return HAL_OK;
3677 }
3678 else
3679 {
3680 return HAL_BUSY;
3681 }
3682 }
3683 #endif /* HAL_DMA_MODULE_ENABLED */
3684
3685 /**
3686 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
3687 * @note This interface allow to manage repeated start condition when a direction change during transfer
3688 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3689 * the configuration information for the specified I2C.
3690 * @param DevAddress Target device address: The device 7 bits address value
3691 * in datasheet must be shifted to the left before calling the interface
3692 * @param pData Pointer to data buffer
3693 * @param Size Amount of data to be sent
3694 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3695 * @retval HAL status
3696 */
HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3697 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3698 uint16_t Size, uint32_t XferOptions)
3699 {
3700 uint32_t xfermode;
3701 uint32_t xferrequest = I2C_GENERATE_START_READ;
3702
3703 /* Check the parameters */
3704 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3705
3706 if (hi2c->State == HAL_I2C_STATE_READY)
3707 {
3708 /* Process Locked */
3709 __HAL_LOCK(hi2c);
3710
3711 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3712 hi2c->Mode = HAL_I2C_MODE_MASTER;
3713 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3714
3715 /* Prepare transfer parameters */
3716 hi2c->pBuffPtr = pData;
3717 hi2c->XferCount = Size;
3718 hi2c->XferOptions = XferOptions;
3719 hi2c->XferISR = I2C_Master_ISR_IT;
3720
3721 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3722 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3723 {
3724 hi2c->XferSize = MAX_NBYTE_SIZE;
3725 xfermode = I2C_RELOAD_MODE;
3726 }
3727 else
3728 {
3729 hi2c->XferSize = hi2c->XferCount;
3730 xfermode = hi2c->XferOptions;
3731 }
3732
3733 /* If transfer direction not change and there is no request to start another frame,
3734 do not generate Restart Condition */
3735 /* Mean Previous state is same as current state */
3736 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
3737 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3738 {
3739 xferrequest = I2C_NO_STARTSTOP;
3740 }
3741 else
3742 {
3743 /* Convert OTHER_xxx XferOptions if any */
3744 I2C_ConvertOtherXferOptions(hi2c);
3745
3746 /* Update xfermode accordingly if no reload is necessary */
3747 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3748 {
3749 xfermode = hi2c->XferOptions;
3750 }
3751 }
3752
3753 /* Send Slave Address and set NBYTES to read */
3754 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3755
3756 /* Process Unlocked */
3757 __HAL_UNLOCK(hi2c);
3758
3759 /* Note : The I2C interrupts must be enabled after unlocking current process
3760 to avoid the risk of I2C interrupt handle execution before current
3761 process unlock */
3762 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
3763
3764 return HAL_OK;
3765 }
3766 else
3767 {
3768 return HAL_BUSY;
3769 }
3770 }
3771
3772 #if defined(HAL_DMA_MODULE_ENABLED)
3773 /**
3774 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
3775 * @note This interface allow to manage repeated start condition when a direction change during transfer
3776 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3777 * the configuration information for the specified I2C.
3778 * @param DevAddress Target device address: The device 7 bits address value
3779 * in datasheet must be shifted to the left before calling the interface
3780 * @param pData Pointer to data buffer
3781 * @param Size Amount of data to be sent
3782 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3783 * @retval HAL status
3784 */
HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3785 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3786 uint16_t Size, uint32_t XferOptions)
3787 {
3788 uint32_t xfermode;
3789 uint32_t xferrequest = I2C_GENERATE_START_READ;
3790 HAL_StatusTypeDef dmaxferstatus;
3791
3792 /* Check the parameters */
3793 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3794
3795 if (hi2c->State == HAL_I2C_STATE_READY)
3796 {
3797 /* Process Locked */
3798 __HAL_LOCK(hi2c);
3799
3800 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3801 hi2c->Mode = HAL_I2C_MODE_MASTER;
3802 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3803
3804 /* Prepare transfer parameters */
3805 hi2c->pBuffPtr = pData;
3806 hi2c->XferCount = Size;
3807 hi2c->XferOptions = XferOptions;
3808 hi2c->XferISR = I2C_Master_ISR_DMA;
3809
3810 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3811 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3812 {
3813 hi2c->XferSize = MAX_NBYTE_SIZE;
3814 xfermode = I2C_RELOAD_MODE;
3815 }
3816 else
3817 {
3818 hi2c->XferSize = hi2c->XferCount;
3819 xfermode = hi2c->XferOptions;
3820 }
3821
3822 /* If transfer direction not change and there is no request to start another frame,
3823 do not generate Restart Condition */
3824 /* Mean Previous state is same as current state */
3825 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
3826 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3827 {
3828 xferrequest = I2C_NO_STARTSTOP;
3829 }
3830 else
3831 {
3832 /* Convert OTHER_xxx XferOptions if any */
3833 I2C_ConvertOtherXferOptions(hi2c);
3834
3835 /* Update xfermode accordingly if no reload is necessary */
3836 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3837 {
3838 xfermode = hi2c->XferOptions;
3839 }
3840 }
3841
3842 if (hi2c->XferSize > 0U)
3843 {
3844 if (hi2c->hdmarx != NULL)
3845 {
3846 /* Set the I2C DMA transfer complete callback */
3847 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
3848
3849 /* Set the DMA error callback */
3850 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3851
3852 /* Set the unused DMA callbacks to NULL */
3853 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3854 hi2c->hdmarx->XferAbortCallback = NULL;
3855
3856 /* Enable the DMA channel */
3857 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
3858 hi2c->XferSize);
3859 }
3860 else
3861 {
3862 /* Update I2C state */
3863 hi2c->State = HAL_I2C_STATE_READY;
3864 hi2c->Mode = HAL_I2C_MODE_NONE;
3865
3866 /* Update I2C error code */
3867 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3868
3869 /* Process Unlocked */
3870 __HAL_UNLOCK(hi2c);
3871
3872 return HAL_ERROR;
3873 }
3874
3875 if (dmaxferstatus == HAL_OK)
3876 {
3877 /* Send Slave Address and set NBYTES to read */
3878 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3879
3880 /* Update XferCount value */
3881 hi2c->XferCount -= hi2c->XferSize;
3882
3883 /* Process Unlocked */
3884 __HAL_UNLOCK(hi2c);
3885
3886 /* Note : The I2C interrupts must be enabled after unlocking current process
3887 to avoid the risk of I2C interrupt handle execution before current
3888 process unlock */
3889 /* Enable ERR and NACK interrupts */
3890 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
3891
3892 /* Enable DMA Request */
3893 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
3894 }
3895 else
3896 {
3897 /* Update I2C state */
3898 hi2c->State = HAL_I2C_STATE_READY;
3899 hi2c->Mode = HAL_I2C_MODE_NONE;
3900
3901 /* Update I2C error code */
3902 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3903
3904 /* Process Unlocked */
3905 __HAL_UNLOCK(hi2c);
3906
3907 return HAL_ERROR;
3908 }
3909 }
3910 else
3911 {
3912 /* Update Transfer ISR function pointer */
3913 hi2c->XferISR = I2C_Master_ISR_IT;
3914
3915 /* Send Slave Address */
3916 /* Set NBYTES to read and generate START condition */
3917 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
3918 I2C_GENERATE_START_READ);
3919
3920 /* Process Unlocked */
3921 __HAL_UNLOCK(hi2c);
3922
3923 /* Note : The I2C interrupts must be enabled after unlocking current process
3924 to avoid the risk of I2C interrupt handle execution before current
3925 process unlock */
3926 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
3927 /* possible to enable all of these */
3928 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3929 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3930 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
3931 }
3932
3933 return HAL_OK;
3934 }
3935 else
3936 {
3937 return HAL_BUSY;
3938 }
3939 }
3940 #endif /* HAL_DMA_MODULE_ENABLED */
3941
3942 /**
3943 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
3944 * @note This interface allow to manage repeated start condition when a direction change during transfer
3945 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3946 * the configuration information for the specified I2C.
3947 * @param pData Pointer to data buffer
3948 * @param Size Amount of data to be sent
3949 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3950 * @retval HAL status
3951 */
HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3952 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
3953 uint32_t XferOptions)
3954 {
3955 /* Declaration of tmp to prevent undefined behavior of volatile usage */
3956 FlagStatus tmp;
3957
3958 /* Check the parameters */
3959 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3960
3961 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
3962 {
3963 if ((pData == NULL) || (Size == 0U))
3964 {
3965 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3966 return HAL_ERROR;
3967 }
3968
3969 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
3970 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
3971
3972 /* Process Locked */
3973 __HAL_LOCK(hi2c);
3974
3975 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
3976 /* and then toggle the HAL slave RX state to TX state */
3977 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
3978 {
3979 /* Disable associated Interrupts */
3980 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
3981
3982 #if defined(HAL_DMA_MODULE_ENABLED)
3983 /* Abort DMA Xfer if any */
3984 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
3985 {
3986 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
3987
3988 if (hi2c->hdmarx != NULL)
3989 {
3990 /* Set the I2C DMA Abort callback :
3991 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
3992 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
3993
3994 /* Abort DMA RX */
3995 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
3996 {
3997 /* Call Directly XferAbortCallback function in case of error */
3998 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
3999 }
4000 }
4001 }
4002 #endif /* HAL_DMA_MODULE_ENABLED */
4003 }
4004
4005 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4006 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4007 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4008
4009 /* Enable Address Acknowledge */
4010 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4011
4012 /* Prepare transfer parameters */
4013 hi2c->pBuffPtr = pData;
4014 hi2c->XferCount = Size;
4015 hi2c->XferSize = hi2c->XferCount;
4016 hi2c->XferOptions = XferOptions;
4017 hi2c->XferISR = I2C_Slave_ISR_IT;
4018
4019 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4020 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
4021 {
4022 /* Clear ADDR flag after prepare the transfer parameters */
4023 /* This action will generate an acknowledge to the Master */
4024 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4025 }
4026
4027 /* Process Unlocked */
4028 __HAL_UNLOCK(hi2c);
4029
4030 /* Note : The I2C interrupts must be enabled after unlocking current process
4031 to avoid the risk of I2C interrupt handle execution before current
4032 process unlock */
4033 /* REnable ADDR interrupt */
4034 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
4035
4036 return HAL_OK;
4037 }
4038 else
4039 {
4040 return HAL_ERROR;
4041 }
4042 }
4043
4044 #if defined(HAL_DMA_MODULE_ENABLED)
4045 /**
4046 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
4047 * @note This interface allow to manage repeated start condition when a direction change during transfer
4048 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4049 * the configuration information for the specified I2C.
4050 * @param pData Pointer to data buffer
4051 * @param Size Amount of data to be sent
4052 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4053 * @retval HAL status
4054 */
HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4055 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4056 uint32_t XferOptions)
4057 {
4058 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4059 FlagStatus tmp;
4060 HAL_StatusTypeDef dmaxferstatus;
4061
4062 /* Check the parameters */
4063 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4064
4065 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4066 {
4067 if ((pData == NULL) || (Size == 0U))
4068 {
4069 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4070 return HAL_ERROR;
4071 }
4072
4073 /* Process Locked */
4074 __HAL_LOCK(hi2c);
4075
4076 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4077 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
4078
4079 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4080 /* and then toggle the HAL slave RX state to TX state */
4081 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4082 {
4083 /* Disable associated Interrupts */
4084 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4085
4086 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4087 {
4088 /* Abort DMA Xfer if any */
4089 if (hi2c->hdmarx != NULL)
4090 {
4091 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4092
4093 /* Set the I2C DMA Abort callback :
4094 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4095 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4096
4097 /* Abort DMA RX */
4098 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4099 {
4100 /* Call Directly XferAbortCallback function in case of error */
4101 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4102 }
4103 }
4104 }
4105 }
4106 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4107 {
4108 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4109 {
4110 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4111
4112 /* Abort DMA Xfer if any */
4113 if (hi2c->hdmatx != NULL)
4114 {
4115 /* Set the I2C DMA Abort callback :
4116 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4117 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4118
4119 /* Abort DMA TX */
4120 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4121 {
4122 /* Call Directly XferAbortCallback function in case of error */
4123 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4124 }
4125 }
4126 }
4127 }
4128 else
4129 {
4130 /* Nothing to do */
4131 }
4132
4133 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4134 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4135 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4136
4137 /* Enable Address Acknowledge */
4138 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4139
4140 /* Prepare transfer parameters */
4141 hi2c->pBuffPtr = pData;
4142 hi2c->XferCount = Size;
4143 hi2c->XferSize = hi2c->XferCount;
4144 hi2c->XferOptions = XferOptions;
4145 hi2c->XferISR = I2C_Slave_ISR_DMA;
4146
4147 if (hi2c->hdmatx != NULL)
4148 {
4149 /* Set the I2C DMA transfer complete callback */
4150 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
4151
4152 /* Set the DMA error callback */
4153 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
4154
4155 /* Set the unused DMA callbacks to NULL */
4156 hi2c->hdmatx->XferHalfCpltCallback = NULL;
4157 hi2c->hdmatx->XferAbortCallback = NULL;
4158
4159 /* Enable the DMA channel */
4160 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
4161 hi2c->XferSize);
4162 }
4163 else
4164 {
4165 /* Update I2C state */
4166 hi2c->State = HAL_I2C_STATE_LISTEN;
4167 hi2c->Mode = HAL_I2C_MODE_NONE;
4168
4169 /* Update I2C error code */
4170 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4171
4172 /* Process Unlocked */
4173 __HAL_UNLOCK(hi2c);
4174
4175 return HAL_ERROR;
4176 }
4177
4178 if (dmaxferstatus == HAL_OK)
4179 {
4180 /* Update XferCount value */
4181 hi2c->XferCount -= hi2c->XferSize;
4182
4183 /* Reset XferSize */
4184 hi2c->XferSize = 0;
4185 }
4186 else
4187 {
4188 /* Update I2C state */
4189 hi2c->State = HAL_I2C_STATE_LISTEN;
4190 hi2c->Mode = HAL_I2C_MODE_NONE;
4191
4192 /* Update I2C error code */
4193 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4194
4195 /* Process Unlocked */
4196 __HAL_UNLOCK(hi2c);
4197
4198 return HAL_ERROR;
4199 }
4200
4201 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4202 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
4203 {
4204 /* Clear ADDR flag after prepare the transfer parameters */
4205 /* This action will generate an acknowledge to the Master */
4206 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4207 }
4208
4209 /* Process Unlocked */
4210 __HAL_UNLOCK(hi2c);
4211
4212 /* Enable DMA Request */
4213 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
4214
4215 /* Note : The I2C interrupts must be enabled after unlocking current process
4216 to avoid the risk of I2C interrupt handle execution before current
4217 process unlock */
4218 /* Enable ERR, STOP, NACK, ADDR interrupts */
4219 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4220
4221 return HAL_OK;
4222 }
4223 else
4224 {
4225 return HAL_ERROR;
4226 }
4227 }
4228 #endif /* HAL_DMA_MODULE_ENABLED */
4229
4230 /**
4231 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
4232 * @note This interface allow to manage repeated start condition when a direction change during transfer
4233 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4234 * the configuration information for the specified I2C.
4235 * @param pData Pointer to data buffer
4236 * @param Size Amount of data to be sent
4237 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4238 * @retval HAL status
4239 */
HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4240 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4241 uint32_t XferOptions)
4242 {
4243 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4244 FlagStatus tmp;
4245
4246 /* Check the parameters */
4247 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4248
4249 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4250 {
4251 if ((pData == NULL) || (Size == 0U))
4252 {
4253 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4254 return HAL_ERROR;
4255 }
4256
4257 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4258 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
4259
4260 /* Process Locked */
4261 __HAL_LOCK(hi2c);
4262
4263 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4264 /* and then toggle the HAL slave TX state to RX state */
4265 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4266 {
4267 /* Disable associated Interrupts */
4268 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4269
4270 #if defined(HAL_DMA_MODULE_ENABLED)
4271 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4272 {
4273 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4274
4275 /* Abort DMA Xfer if any */
4276 if (hi2c->hdmatx != NULL)
4277 {
4278 /* Set the I2C DMA Abort callback :
4279 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4280 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4281
4282 /* Abort DMA TX */
4283 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4284 {
4285 /* Call Directly XferAbortCallback function in case of error */
4286 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4287 }
4288 }
4289 }
4290 #endif /* HAL_DMA_MODULE_ENABLED */
4291 }
4292
4293 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4294 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4295 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4296
4297 /* Enable Address Acknowledge */
4298 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4299
4300 /* Prepare transfer parameters */
4301 hi2c->pBuffPtr = pData;
4302 hi2c->XferCount = Size;
4303 hi2c->XferSize = hi2c->XferCount;
4304 hi2c->XferOptions = XferOptions;
4305 hi2c->XferISR = I2C_Slave_ISR_IT;
4306
4307 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4308 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
4309 {
4310 /* Clear ADDR flag after prepare the transfer parameters */
4311 /* This action will generate an acknowledge to the Master */
4312 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4313 }
4314
4315 /* Process Unlocked */
4316 __HAL_UNLOCK(hi2c);
4317
4318 /* Note : The I2C interrupts must be enabled after unlocking current process
4319 to avoid the risk of I2C interrupt handle execution before current
4320 process unlock */
4321 /* REnable ADDR interrupt */
4322 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
4323
4324 return HAL_OK;
4325 }
4326 else
4327 {
4328 return HAL_ERROR;
4329 }
4330 }
4331
4332 #if defined(HAL_DMA_MODULE_ENABLED)
4333 /**
4334 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
4335 * @note This interface allow to manage repeated start condition when a direction change during transfer
4336 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4337 * the configuration information for the specified I2C.
4338 * @param pData Pointer to data buffer
4339 * @param Size Amount of data to be sent
4340 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4341 * @retval HAL status
4342 */
HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4343 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4344 uint32_t XferOptions)
4345 {
4346 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4347 FlagStatus tmp;
4348 HAL_StatusTypeDef dmaxferstatus;
4349
4350 /* Check the parameters */
4351 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4352
4353 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4354 {
4355 if ((pData == NULL) || (Size == 0U))
4356 {
4357 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4358 return HAL_ERROR;
4359 }
4360
4361 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4362 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
4363
4364 /* Process Locked */
4365 __HAL_LOCK(hi2c);
4366
4367 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4368 /* and then toggle the HAL slave TX state to RX state */
4369 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4370 {
4371 /* Disable associated Interrupts */
4372 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4373
4374 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4375 {
4376 /* Abort DMA Xfer if any */
4377 if (hi2c->hdmatx != NULL)
4378 {
4379 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4380
4381 /* Set the I2C DMA Abort callback :
4382 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4383 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4384
4385 /* Abort DMA TX */
4386 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4387 {
4388 /* Call Directly XferAbortCallback function in case of error */
4389 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4390 }
4391 }
4392 }
4393 }
4394 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4395 {
4396 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4397 {
4398 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4399
4400 /* Abort DMA Xfer if any */
4401 if (hi2c->hdmarx != NULL)
4402 {
4403 /* Set the I2C DMA Abort callback :
4404 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4405 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4406
4407 /* Abort DMA RX */
4408 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4409 {
4410 /* Call Directly XferAbortCallback function in case of error */
4411 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4412 }
4413 }
4414 }
4415 }
4416 else
4417 {
4418 /* Nothing to do */
4419 }
4420
4421 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4422 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4423 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4424
4425 /* Enable Address Acknowledge */
4426 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4427
4428 /* Prepare transfer parameters */
4429 hi2c->pBuffPtr = pData;
4430 hi2c->XferCount = Size;
4431 hi2c->XferSize = hi2c->XferCount;
4432 hi2c->XferOptions = XferOptions;
4433 hi2c->XferISR = I2C_Slave_ISR_DMA;
4434
4435 if (hi2c->hdmarx != NULL)
4436 {
4437 /* Set the I2C DMA transfer complete callback */
4438 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
4439
4440 /* Set the DMA error callback */
4441 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4442
4443 /* Set the unused DMA callbacks to NULL */
4444 hi2c->hdmarx->XferHalfCpltCallback = NULL;
4445 hi2c->hdmarx->XferAbortCallback = NULL;
4446
4447 /* Enable the DMA channel */
4448 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR,
4449 (uint32_t)pData, hi2c->XferSize);
4450 }
4451 else
4452 {
4453 /* Update I2C state */
4454 hi2c->State = HAL_I2C_STATE_LISTEN;
4455 hi2c->Mode = HAL_I2C_MODE_NONE;
4456
4457 /* Update I2C error code */
4458 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4459
4460 /* Process Unlocked */
4461 __HAL_UNLOCK(hi2c);
4462
4463 return HAL_ERROR;
4464 }
4465
4466 if (dmaxferstatus == HAL_OK)
4467 {
4468 /* Update XferCount value */
4469 hi2c->XferCount -= hi2c->XferSize;
4470
4471 /* Reset XferSize */
4472 hi2c->XferSize = 0;
4473 }
4474 else
4475 {
4476 /* Update I2C state */
4477 hi2c->State = HAL_I2C_STATE_LISTEN;
4478 hi2c->Mode = HAL_I2C_MODE_NONE;
4479
4480 /* Update I2C error code */
4481 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4482
4483 /* Process Unlocked */
4484 __HAL_UNLOCK(hi2c);
4485
4486 return HAL_ERROR;
4487 }
4488
4489 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4490 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
4491 {
4492 /* Clear ADDR flag after prepare the transfer parameters */
4493 /* This action will generate an acknowledge to the Master */
4494 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4495 }
4496
4497 /* Process Unlocked */
4498 __HAL_UNLOCK(hi2c);
4499
4500 /* Enable DMA Request */
4501 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
4502
4503 /* Note : The I2C interrupts must be enabled after unlocking current process
4504 to avoid the risk of I2C interrupt handle execution before current
4505 process unlock */
4506 /* REnable ADDR interrupt */
4507 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
4508
4509 return HAL_OK;
4510 }
4511 else
4512 {
4513 return HAL_ERROR;
4514 }
4515 }
4516 #endif /* HAL_DMA_MODULE_ENABLED */
4517
4518 /**
4519 * @brief Enable the Address listen mode with Interrupt.
4520 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4521 * the configuration information for the specified I2C.
4522 * @retval HAL status
4523 */
HAL_I2C_EnableListen_IT(I2C_HandleTypeDef * hi2c)4524 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
4525 {
4526 if (hi2c->State == HAL_I2C_STATE_READY)
4527 {
4528 hi2c->State = HAL_I2C_STATE_LISTEN;
4529 hi2c->XferISR = I2C_Slave_ISR_IT;
4530
4531 /* Enable the Address Match interrupt */
4532 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4533
4534 return HAL_OK;
4535 }
4536 else
4537 {
4538 return HAL_BUSY;
4539 }
4540 }
4541
4542 /**
4543 * @brief Disable the Address listen mode with Interrupt.
4544 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4545 * the configuration information for the specified I2C
4546 * @retval HAL status
4547 */
HAL_I2C_DisableListen_IT(I2C_HandleTypeDef * hi2c)4548 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
4549 {
4550 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4551 uint32_t tmp;
4552
4553 /* Disable Address listen mode only if a transfer is not ongoing */
4554 if (hi2c->State == HAL_I2C_STATE_LISTEN)
4555 {
4556 tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
4557 hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
4558 hi2c->State = HAL_I2C_STATE_READY;
4559 hi2c->Mode = HAL_I2C_MODE_NONE;
4560 hi2c->XferISR = NULL;
4561
4562 /* Disable the Address Match interrupt */
4563 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4564
4565 return HAL_OK;
4566 }
4567 else
4568 {
4569 return HAL_BUSY;
4570 }
4571 }
4572
4573 /**
4574 * @brief Abort a master I2C IT or DMA process communication with Interrupt.
4575 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4576 * the configuration information for the specified I2C.
4577 * @param DevAddress Target device address: The device 7 bits address value
4578 * in datasheet must be shifted to the left before calling the interface
4579 * @retval HAL status
4580 */
HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress)4581 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
4582 {
4583 if (hi2c->Mode == HAL_I2C_MODE_MASTER)
4584 {
4585 /* Process Locked */
4586 __HAL_LOCK(hi2c);
4587
4588 /* Disable Interrupts and Store Previous state */
4589 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
4590 {
4591 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4592 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
4593 }
4594 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
4595 {
4596 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4597 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
4598 }
4599 else
4600 {
4601 /* Do nothing */
4602 }
4603
4604 /* Set State at HAL_I2C_STATE_ABORT */
4605 hi2c->State = HAL_I2C_STATE_ABORT;
4606
4607 /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
4608 /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
4609 I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
4610
4611 /* Process Unlocked */
4612 __HAL_UNLOCK(hi2c);
4613
4614 /* Note : The I2C interrupts must be enabled after unlocking current process
4615 to avoid the risk of I2C interrupt handle execution before current
4616 process unlock */
4617 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
4618
4619 return HAL_OK;
4620 }
4621 else
4622 {
4623 /* Wrong usage of abort function */
4624 /* This function should be used only in case of abort monitored by master device */
4625 return HAL_ERROR;
4626 }
4627 }
4628
4629 /**
4630 * @}
4631 */
4632
4633 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
4634 * @{
4635 */
4636
4637 /**
4638 * @brief This function handles I2C event interrupt request.
4639 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4640 * the configuration information for the specified I2C.
4641 * @retval None
4642 */
HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef * hi2c)4643 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */
4644 {
4645 /* Get current IT Flags and IT sources value */
4646 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4647 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4648
4649 /* I2C events treatment -------------------------------------*/
4650 if (hi2c->XferISR != NULL)
4651 {
4652 hi2c->XferISR(hi2c, itflags, itsources);
4653 }
4654 }
4655
4656 /**
4657 * @brief This function handles I2C error interrupt request.
4658 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4659 * the configuration information for the specified I2C.
4660 * @retval None
4661 */
HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef * hi2c)4662 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
4663 {
4664 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4665 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4666 uint32_t tmperror;
4667
4668 /* I2C Bus error interrupt occurred ------------------------------------*/
4669 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
4670 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4671 {
4672 hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
4673
4674 /* Clear BERR flag */
4675 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
4676 }
4677
4678 /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
4679 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
4680 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4681 {
4682 hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
4683
4684 /* Clear OVR flag */
4685 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
4686 }
4687
4688 /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
4689 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
4690 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4691 {
4692 hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
4693
4694 /* Clear ARLO flag */
4695 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
4696 }
4697
4698 /* Store current volatile hi2c->ErrorCode, misra rule */
4699 tmperror = hi2c->ErrorCode;
4700
4701 /* Call the Error Callback in case of Error detected */
4702 if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
4703 {
4704 I2C_ITError(hi2c, tmperror);
4705 }
4706 }
4707
4708 /**
4709 * @brief Master Tx Transfer completed callback.
4710 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4711 * the configuration information for the specified I2C.
4712 * @retval None
4713 */
HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef * hi2c)4714 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
4715 {
4716 /* Prevent unused argument(s) compilation warning */
4717 UNUSED(hi2c);
4718
4719 /* NOTE : This function should not be modified, when the callback is needed,
4720 the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
4721 */
4722 }
4723
4724 /**
4725 * @brief Master Rx Transfer completed callback.
4726 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4727 * the configuration information for the specified I2C.
4728 * @retval None
4729 */
HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef * hi2c)4730 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
4731 {
4732 /* Prevent unused argument(s) compilation warning */
4733 UNUSED(hi2c);
4734
4735 /* NOTE : This function should not be modified, when the callback is needed,
4736 the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
4737 */
4738 }
4739
4740 /** @brief Slave Tx Transfer completed callback.
4741 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4742 * the configuration information for the specified I2C.
4743 * @retval None
4744 */
HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef * hi2c)4745 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
4746 {
4747 /* Prevent unused argument(s) compilation warning */
4748 UNUSED(hi2c);
4749
4750 /* NOTE : This function should not be modified, when the callback is needed,
4751 the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
4752 */
4753 }
4754
4755 /**
4756 * @brief Slave Rx Transfer completed callback.
4757 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4758 * the configuration information for the specified I2C.
4759 * @retval None
4760 */
HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef * hi2c)4761 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
4762 {
4763 /* Prevent unused argument(s) compilation warning */
4764 UNUSED(hi2c);
4765
4766 /* NOTE : This function should not be modified, when the callback is needed,
4767 the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
4768 */
4769 }
4770
4771 /**
4772 * @brief Slave Address Match callback.
4773 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4774 * the configuration information for the specified I2C.
4775 * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
4776 * @param AddrMatchCode Address Match Code
4777 * @retval None
4778 */
HAL_I2C_AddrCallback(I2C_HandleTypeDef * hi2c,uint8_t TransferDirection,uint16_t AddrMatchCode)4779 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
4780 {
4781 /* Prevent unused argument(s) compilation warning */
4782 UNUSED(hi2c);
4783 UNUSED(TransferDirection);
4784 UNUSED(AddrMatchCode);
4785
4786 /* NOTE : This function should not be modified, when the callback is needed,
4787 the HAL_I2C_AddrCallback() could be implemented in the user file
4788 */
4789 }
4790
4791 /**
4792 * @brief Listen Complete callback.
4793 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4794 * the configuration information for the specified I2C.
4795 * @retval None
4796 */
HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef * hi2c)4797 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
4798 {
4799 /* Prevent unused argument(s) compilation warning */
4800 UNUSED(hi2c);
4801
4802 /* NOTE : This function should not be modified, when the callback is needed,
4803 the HAL_I2C_ListenCpltCallback() could be implemented in the user file
4804 */
4805 }
4806
4807 /**
4808 * @brief Memory Tx Transfer completed callback.
4809 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4810 * the configuration information for the specified I2C.
4811 * @retval None
4812 */
HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef * hi2c)4813 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
4814 {
4815 /* Prevent unused argument(s) compilation warning */
4816 UNUSED(hi2c);
4817
4818 /* NOTE : This function should not be modified, when the callback is needed,
4819 the HAL_I2C_MemTxCpltCallback could be implemented in the user file
4820 */
4821 }
4822
4823 /**
4824 * @brief Memory Rx Transfer completed callback.
4825 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4826 * the configuration information for the specified I2C.
4827 * @retval None
4828 */
HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef * hi2c)4829 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
4830 {
4831 /* Prevent unused argument(s) compilation warning */
4832 UNUSED(hi2c);
4833
4834 /* NOTE : This function should not be modified, when the callback is needed,
4835 the HAL_I2C_MemRxCpltCallback could be implemented in the user file
4836 */
4837 }
4838
4839 /**
4840 * @brief I2C error callback.
4841 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4842 * the configuration information for the specified I2C.
4843 * @retval None
4844 */
HAL_I2C_ErrorCallback(I2C_HandleTypeDef * hi2c)4845 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
4846 {
4847 /* Prevent unused argument(s) compilation warning */
4848 UNUSED(hi2c);
4849
4850 /* NOTE : This function should not be modified, when the callback is needed,
4851 the HAL_I2C_ErrorCallback could be implemented in the user file
4852 */
4853 }
4854
4855 /**
4856 * @brief I2C abort callback.
4857 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4858 * the configuration information for the specified I2C.
4859 * @retval None
4860 */
HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef * hi2c)4861 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
4862 {
4863 /* Prevent unused argument(s) compilation warning */
4864 UNUSED(hi2c);
4865
4866 /* NOTE : This function should not be modified, when the callback is needed,
4867 the HAL_I2C_AbortCpltCallback could be implemented in the user file
4868 */
4869 }
4870
4871 /**
4872 * @}
4873 */
4874
4875 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
4876 * @brief Peripheral State, Mode and Error functions
4877 *
4878 @verbatim
4879 ===============================================================================
4880 ##### Peripheral State, Mode and Error functions #####
4881 ===============================================================================
4882 [..]
4883 This subsection permit to get in run-time the status of the peripheral
4884 and the data flow.
4885
4886 @endverbatim
4887 * @{
4888 */
4889
4890 /**
4891 * @brief Return the I2C handle state.
4892 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4893 * the configuration information for the specified I2C.
4894 * @retval HAL state
4895 */
HAL_I2C_GetState(const I2C_HandleTypeDef * hi2c)4896 HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c)
4897 {
4898 /* Return I2C handle state */
4899 return hi2c->State;
4900 }
4901
4902 /**
4903 * @brief Returns the I2C Master, Slave, Memory or no mode.
4904 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4905 * the configuration information for I2C module
4906 * @retval HAL mode
4907 */
HAL_I2C_GetMode(const I2C_HandleTypeDef * hi2c)4908 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c)
4909 {
4910 return hi2c->Mode;
4911 }
4912
4913 /**
4914 * @brief Return the I2C error code.
4915 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4916 * the configuration information for the specified I2C.
4917 * @retval I2C Error Code
4918 */
HAL_I2C_GetError(const I2C_HandleTypeDef * hi2c)4919 uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c)
4920 {
4921 return hi2c->ErrorCode;
4922 }
4923
4924 /**
4925 * @}
4926 */
4927
4928 /**
4929 * @}
4930 */
4931
4932 /** @addtogroup I2C_Private_Functions
4933 * @{
4934 */
4935
4936 /**
4937 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
4938 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4939 * the configuration information for the specified I2C.
4940 * @param ITFlags Interrupt flags to handle.
4941 * @param ITSources Interrupt sources enabled.
4942 * @retval HAL status
4943 */
I2C_Master_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)4944 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
4945 uint32_t ITSources)
4946 {
4947 uint16_t devaddress;
4948 uint32_t tmpITFlags = ITFlags;
4949
4950 /* Process Locked */
4951 __HAL_LOCK(hi2c);
4952
4953 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
4954 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
4955 {
4956 /* Clear NACK Flag */
4957 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4958
4959 /* Set corresponding Error Code */
4960 /* No need to generate STOP, it is automatically done */
4961 /* Error callback will be send during stop flag treatment */
4962 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
4963
4964 /* Flush TX register */
4965 I2C_Flush_TXDR(hi2c);
4966 }
4967 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
4968 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
4969 {
4970 /* Remove RXNE flag on temporary variable as read done */
4971 tmpITFlags &= ~I2C_FLAG_RXNE;
4972
4973 /* Read data from RXDR */
4974 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
4975
4976 /* Increment Buffer pointer */
4977 hi2c->pBuffPtr++;
4978
4979 hi2c->XferSize--;
4980 hi2c->XferCount--;
4981 }
4982 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) == RESET) && \
4983 ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
4984 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)))
4985 {
4986 /* Write data to TXDR */
4987 if (hi2c->XferCount != 0U)
4988 {
4989 /* Write data to TXDR */
4990 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
4991
4992 /* Increment Buffer pointer */
4993 hi2c->pBuffPtr++;
4994
4995 hi2c->XferSize--;
4996 hi2c->XferCount--;
4997 }
4998 }
4999 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
5000 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5001 {
5002 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
5003 {
5004 devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
5005
5006 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5007 {
5008 hi2c->XferSize = MAX_NBYTE_SIZE;
5009 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5010 }
5011 else
5012 {
5013 hi2c->XferSize = hi2c->XferCount;
5014 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
5015 {
5016 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
5017 hi2c->XferOptions, I2C_NO_STARTSTOP);
5018 }
5019 else
5020 {
5021 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
5022 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5023 }
5024 }
5025 }
5026 else
5027 {
5028 /* Call TxCpltCallback() if no stop mode is set */
5029 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5030 {
5031 /* Call I2C Master Sequential complete process */
5032 I2C_ITMasterSeqCplt(hi2c);
5033 }
5034 else
5035 {
5036 /* Wrong size Status regarding TCR flag event */
5037 /* Call the corresponding callback to inform upper layer of End of Transfer */
5038 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5039 }
5040 }
5041 }
5042 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
5043 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5044 {
5045 if (hi2c->XferCount == 0U)
5046 {
5047 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5048 {
5049 /* Generate a stop condition in case of no transfer option */
5050 if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
5051 {
5052 /* Generate Stop */
5053 hi2c->Instance->CR2 |= I2C_CR2_STOP;
5054 }
5055 else
5056 {
5057 /* Call I2C Master Sequential complete process */
5058 I2C_ITMasterSeqCplt(hi2c);
5059 }
5060 }
5061 }
5062 else
5063 {
5064 /* Wrong size Status regarding TC flag event */
5065 /* Call the corresponding callback to inform upper layer of End of Transfer */
5066 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5067 }
5068 }
5069 else
5070 {
5071 /* Nothing to do */
5072 }
5073
5074 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5075 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5076 {
5077 /* Call I2C Master complete process */
5078 I2C_ITMasterCplt(hi2c, tmpITFlags);
5079 }
5080
5081 /* Process Unlocked */
5082 __HAL_UNLOCK(hi2c);
5083
5084 return HAL_OK;
5085 }
5086
5087 /**
5088 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
5089 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5090 * the configuration information for the specified I2C.
5091 * @param ITFlags Interrupt flags to handle.
5092 * @param ITSources Interrupt sources enabled.
5093 * @retval HAL status
5094 */
I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5095 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5096 uint32_t ITSources)
5097 {
5098 uint32_t direction = I2C_GENERATE_START_WRITE;
5099 uint32_t tmpITFlags = ITFlags;
5100
5101 /* Process Locked */
5102 __HAL_LOCK(hi2c);
5103
5104 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
5105 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5106 {
5107 /* Clear NACK Flag */
5108 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5109
5110 /* Set corresponding Error Code */
5111 /* No need to generate STOP, it is automatically done */
5112 /* Error callback will be send during stop flag treatment */
5113 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5114
5115 /* Flush TX register */
5116 I2C_Flush_TXDR(hi2c);
5117 }
5118 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
5119 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
5120 {
5121 /* Remove RXNE flag on temporary variable as read done */
5122 tmpITFlags &= ~I2C_FLAG_RXNE;
5123
5124 /* Read data from RXDR */
5125 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5126
5127 /* Increment Buffer pointer */
5128 hi2c->pBuffPtr++;
5129
5130 hi2c->XferSize--;
5131 hi2c->XferCount--;
5132 }
5133 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5134 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5135 {
5136 if (hi2c->Memaddress == 0xFFFFFFFFU)
5137 {
5138 /* Write data to TXDR */
5139 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5140
5141 /* Increment Buffer pointer */
5142 hi2c->pBuffPtr++;
5143
5144 hi2c->XferSize--;
5145 hi2c->XferCount--;
5146 }
5147 else
5148 {
5149 /* Write LSB part of Memory Address */
5150 hi2c->Instance->TXDR = hi2c->Memaddress;
5151
5152 /* Reset Memaddress content */
5153 hi2c->Memaddress = 0xFFFFFFFFU;
5154 }
5155 }
5156 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
5157 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5158 {
5159 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
5160 {
5161 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5162 {
5163 hi2c->XferSize = MAX_NBYTE_SIZE;
5164 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5165 I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5166 }
5167 else
5168 {
5169 hi2c->XferSize = hi2c->XferCount;
5170 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5171 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5172 }
5173 }
5174 else
5175 {
5176 /* Wrong size Status regarding TCR flag event */
5177 /* Call the corresponding callback to inform upper layer of End of Transfer */
5178 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5179 }
5180 }
5181 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
5182 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5183 {
5184 /* Disable Interrupt related to address step */
5185 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5186
5187 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
5188 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
5189
5190 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5191 {
5192 direction = I2C_GENERATE_START_READ;
5193 }
5194
5195 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5196 {
5197 hi2c->XferSize = MAX_NBYTE_SIZE;
5198
5199 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
5200 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5201 I2C_RELOAD_MODE, direction);
5202 }
5203 else
5204 {
5205 hi2c->XferSize = hi2c->XferCount;
5206
5207 /* Set NBYTES to write and generate RESTART */
5208 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5209 I2C_AUTOEND_MODE, direction);
5210 }
5211 }
5212 else
5213 {
5214 /* Nothing to do */
5215 }
5216
5217 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5218 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5219 {
5220 /* Call I2C Master complete process */
5221 I2C_ITMasterCplt(hi2c, tmpITFlags);
5222 }
5223
5224 /* Process Unlocked */
5225 __HAL_UNLOCK(hi2c);
5226
5227 return HAL_OK;
5228 }
5229
5230 /**
5231 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
5232 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5233 * the configuration information for the specified I2C.
5234 * @param ITFlags Interrupt flags to handle.
5235 * @param ITSources Interrupt sources enabled.
5236 * @retval HAL status
5237 */
I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5238 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5239 uint32_t ITSources)
5240 {
5241 uint32_t tmpoptions = hi2c->XferOptions;
5242 uint32_t tmpITFlags = ITFlags;
5243
5244 /* Process locked */
5245 __HAL_LOCK(hi2c);
5246
5247 /* Check if STOPF is set */
5248 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5249 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5250 {
5251 /* Call I2C Slave complete process */
5252 I2C_ITSlaveCplt(hi2c, tmpITFlags);
5253 }
5254
5255 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
5256 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5257 {
5258 /* Check that I2C transfer finished */
5259 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
5260 /* Mean XferCount == 0*/
5261 /* So clear Flag NACKF only */
5262 if (hi2c->XferCount == 0U)
5263 {
5264 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
5265 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
5266 Warning[Pa134]: left and right operands are identical */
5267 {
5268 /* Call I2C Listen complete process */
5269 I2C_ITListenCplt(hi2c, tmpITFlags);
5270 }
5271 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
5272 {
5273 /* Clear NACK Flag */
5274 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5275
5276 /* Flush TX register */
5277 I2C_Flush_TXDR(hi2c);
5278
5279 /* Last Byte is Transmitted */
5280 /* Call I2C Slave Sequential complete process */
5281 I2C_ITSlaveSeqCplt(hi2c);
5282 }
5283 else
5284 {
5285 /* Clear NACK Flag */
5286 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5287 }
5288 }
5289 else
5290 {
5291 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
5292 /* Clear NACK Flag */
5293 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5294
5295 /* Set ErrorCode corresponding to a Non-Acknowledge */
5296 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5297
5298 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
5299 {
5300 /* Call the corresponding callback to inform upper layer of End of Transfer */
5301 I2C_ITError(hi2c, hi2c->ErrorCode);
5302 }
5303 }
5304 }
5305 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
5306 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
5307 {
5308 if (hi2c->XferCount > 0U)
5309 {
5310 /* Read data from RXDR */
5311 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5312
5313 /* Increment Buffer pointer */
5314 hi2c->pBuffPtr++;
5315
5316 hi2c->XferSize--;
5317 hi2c->XferCount--;
5318 }
5319
5320 if ((hi2c->XferCount == 0U) && \
5321 (tmpoptions != I2C_NO_OPTION_FRAME))
5322 {
5323 /* Call I2C Slave Sequential complete process */
5324 I2C_ITSlaveSeqCplt(hi2c);
5325 }
5326 }
5327 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
5328 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
5329 {
5330 I2C_ITAddrCplt(hi2c, tmpITFlags);
5331 }
5332 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5333 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5334 {
5335 /* Write data to TXDR only if XferCount not reach "0" */
5336 /* A TXIS flag can be set, during STOP treatment */
5337 /* Check if all Data have already been sent */
5338 /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
5339 if (hi2c->XferCount > 0U)
5340 {
5341 /* Write data to TXDR */
5342 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5343
5344 /* Increment Buffer pointer */
5345 hi2c->pBuffPtr++;
5346
5347 hi2c->XferCount--;
5348 hi2c->XferSize--;
5349 }
5350 else
5351 {
5352 if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
5353 {
5354 /* Last Byte is Transmitted */
5355 /* Call I2C Slave Sequential complete process */
5356 I2C_ITSlaveSeqCplt(hi2c);
5357 }
5358 }
5359 }
5360 else
5361 {
5362 /* Nothing to do */
5363 }
5364
5365 /* Process Unlocked */
5366 __HAL_UNLOCK(hi2c);
5367
5368 return HAL_OK;
5369 }
5370
5371 #if defined(HAL_DMA_MODULE_ENABLED)
5372 /**
5373 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
5374 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5375 * the configuration information for the specified I2C.
5376 * @param ITFlags Interrupt flags to handle.
5377 * @param ITSources Interrupt sources enabled.
5378 * @retval HAL status
5379 */
I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5380 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5381 uint32_t ITSources)
5382 {
5383 uint16_t devaddress;
5384 uint32_t xfermode;
5385
5386 /* Process Locked */
5387 __HAL_LOCK(hi2c);
5388
5389 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5390 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5391 {
5392 /* Clear NACK Flag */
5393 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5394
5395 /* Set corresponding Error Code */
5396 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5397
5398 /* No need to generate STOP, it is automatically done */
5399 /* But enable STOP interrupt, to treat it */
5400 /* Error callback will be send during stop flag treatment */
5401 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
5402
5403 /* Flush TX register */
5404 I2C_Flush_TXDR(hi2c);
5405 }
5406 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
5407 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5408 {
5409 /* Disable TC interrupt */
5410 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
5411
5412 if (hi2c->XferCount != 0U)
5413 {
5414 /* Recover Slave address */
5415 devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
5416
5417 /* Prepare the new XferSize to transfer */
5418 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5419 {
5420 hi2c->XferSize = MAX_NBYTE_SIZE;
5421 xfermode = I2C_RELOAD_MODE;
5422 }
5423 else
5424 {
5425 hi2c->XferSize = hi2c->XferCount;
5426 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
5427 {
5428 xfermode = hi2c->XferOptions;
5429 }
5430 else
5431 {
5432 xfermode = I2C_AUTOEND_MODE;
5433 }
5434 }
5435
5436 /* Set the new XferSize in Nbytes register */
5437 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
5438
5439 /* Update XferCount value */
5440 hi2c->XferCount -= hi2c->XferSize;
5441
5442 /* Enable DMA Request */
5443 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5444 {
5445 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5446 }
5447 else
5448 {
5449 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5450 }
5451 }
5452 else
5453 {
5454 /* Call TxCpltCallback() if no stop mode is set */
5455 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5456 {
5457 /* Call I2C Master Sequential complete process */
5458 I2C_ITMasterSeqCplt(hi2c);
5459 }
5460 else
5461 {
5462 /* Wrong size Status regarding TCR flag event */
5463 /* Call the corresponding callback to inform upper layer of End of Transfer */
5464 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5465 }
5466 }
5467 }
5468 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
5469 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5470 {
5471 if (hi2c->XferCount == 0U)
5472 {
5473 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5474 {
5475 /* Generate a stop condition in case of no transfer option */
5476 if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
5477 {
5478 /* Generate Stop */
5479 hi2c->Instance->CR2 |= I2C_CR2_STOP;
5480 }
5481 else
5482 {
5483 /* Call I2C Master Sequential complete process */
5484 I2C_ITMasterSeqCplt(hi2c);
5485 }
5486 }
5487 }
5488 else
5489 {
5490 /* Wrong size Status regarding TC flag event */
5491 /* Call the corresponding callback to inform upper layer of End of Transfer */
5492 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5493 }
5494 }
5495 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5496 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5497 {
5498 /* Call I2C Master complete process */
5499 I2C_ITMasterCplt(hi2c, ITFlags);
5500 }
5501 else
5502 {
5503 /* Nothing to do */
5504 }
5505
5506 /* Process Unlocked */
5507 __HAL_UNLOCK(hi2c);
5508
5509 return HAL_OK;
5510 }
5511
5512 /**
5513 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
5514 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5515 * the configuration information for the specified I2C.
5516 * @param ITFlags Interrupt flags to handle.
5517 * @param ITSources Interrupt sources enabled.
5518 * @retval HAL status
5519 */
I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5520 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5521 uint32_t ITSources)
5522 {
5523 uint32_t direction = I2C_GENERATE_START_WRITE;
5524
5525 /* Process Locked */
5526 __HAL_LOCK(hi2c);
5527
5528 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5529 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5530 {
5531 /* Clear NACK Flag */
5532 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5533
5534 /* Set corresponding Error Code */
5535 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5536
5537 /* No need to generate STOP, it is automatically done */
5538 /* But enable STOP interrupt, to treat it */
5539 /* Error callback will be send during stop flag treatment */
5540 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
5541
5542 /* Flush TX register */
5543 I2C_Flush_TXDR(hi2c);
5544 }
5545 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
5546 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5547 {
5548 /* Write LSB part of Memory Address */
5549 hi2c->Instance->TXDR = hi2c->Memaddress;
5550
5551 /* Reset Memaddress content */
5552 hi2c->Memaddress = 0xFFFFFFFFU;
5553 }
5554 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
5555 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5556 {
5557 /* Disable Interrupt related to address step */
5558 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5559
5560 /* Enable only Error interrupt */
5561 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
5562
5563 if (hi2c->XferCount != 0U)
5564 {
5565 /* Prepare the new XferSize to transfer */
5566 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5567 {
5568 hi2c->XferSize = MAX_NBYTE_SIZE;
5569 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5570 I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5571 }
5572 else
5573 {
5574 hi2c->XferSize = hi2c->XferCount;
5575 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5576 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5577 }
5578
5579 /* Update XferCount value */
5580 hi2c->XferCount -= hi2c->XferSize;
5581
5582 /* Enable DMA Request */
5583 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5584 {
5585 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5586 }
5587 else
5588 {
5589 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5590 }
5591 }
5592 else
5593 {
5594 /* Wrong size Status regarding TCR flag event */
5595 /* Call the corresponding callback to inform upper layer of End of Transfer */
5596 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5597 }
5598 }
5599 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
5600 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5601 {
5602 /* Disable Interrupt related to address step */
5603 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5604
5605 /* Enable only Error and NACK interrupt for data transfer */
5606 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
5607
5608 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5609 {
5610 direction = I2C_GENERATE_START_READ;
5611 }
5612
5613 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5614 {
5615 hi2c->XferSize = MAX_NBYTE_SIZE;
5616
5617 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
5618 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5619 I2C_RELOAD_MODE, direction);
5620 }
5621 else
5622 {
5623 hi2c->XferSize = hi2c->XferCount;
5624
5625 /* Set NBYTES to write and generate RESTART */
5626 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5627 I2C_AUTOEND_MODE, direction);
5628 }
5629
5630 /* Update XferCount value */
5631 hi2c->XferCount -= hi2c->XferSize;
5632
5633 /* Enable DMA Request */
5634 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5635 {
5636 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5637 }
5638 else
5639 {
5640 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5641 }
5642 }
5643 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5644 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5645 {
5646 /* Call I2C Master complete process */
5647 I2C_ITMasterCplt(hi2c, ITFlags);
5648 }
5649 else
5650 {
5651 /* Nothing to do */
5652 }
5653
5654 /* Process Unlocked */
5655 __HAL_UNLOCK(hi2c);
5656
5657 return HAL_OK;
5658 }
5659
5660 /**
5661 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
5662 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5663 * the configuration information for the specified I2C.
5664 * @param ITFlags Interrupt flags to handle.
5665 * @param ITSources Interrupt sources enabled.
5666 * @retval HAL status
5667 */
I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5668 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5669 uint32_t ITSources)
5670 {
5671 uint32_t tmpoptions = hi2c->XferOptions;
5672 uint32_t treatdmanack = 0U;
5673 HAL_I2C_StateTypeDef tmpstate;
5674
5675 /* Process locked */
5676 __HAL_LOCK(hi2c);
5677
5678 /* Check if STOPF is set */
5679 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5680 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5681 {
5682 /* Call I2C Slave complete process */
5683 I2C_ITSlaveCplt(hi2c, ITFlags);
5684 }
5685
5686 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5687 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5688 {
5689 /* Check that I2C transfer finished */
5690 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
5691 /* Mean XferCount == 0 */
5692 /* So clear Flag NACKF only */
5693 if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
5694 (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
5695 {
5696 /* Split check of hdmarx, for MISRA compliance */
5697 if (hi2c->hdmarx != NULL)
5698 {
5699 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
5700 {
5701 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
5702 {
5703 treatdmanack = 1U;
5704 }
5705 }
5706 }
5707
5708 /* Split check of hdmatx, for MISRA compliance */
5709 if (hi2c->hdmatx != NULL)
5710 {
5711 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
5712 {
5713 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
5714 {
5715 treatdmanack = 1U;
5716 }
5717 }
5718 }
5719
5720 if (treatdmanack == 1U)
5721 {
5722 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
5723 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
5724 Warning[Pa134]: left and right operands are identical */
5725 {
5726 /* Call I2C Listen complete process */
5727 I2C_ITListenCplt(hi2c, ITFlags);
5728 }
5729 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
5730 {
5731 /* Clear NACK Flag */
5732 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5733
5734 /* Flush TX register */
5735 I2C_Flush_TXDR(hi2c);
5736
5737 /* Last Byte is Transmitted */
5738 /* Call I2C Slave Sequential complete process */
5739 I2C_ITSlaveSeqCplt(hi2c);
5740 }
5741 else
5742 {
5743 /* Clear NACK Flag */
5744 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5745 }
5746 }
5747 else
5748 {
5749 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
5750 /* Clear NACK Flag */
5751 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5752
5753 /* Set ErrorCode corresponding to a Non-Acknowledge */
5754 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5755
5756 /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
5757 tmpstate = hi2c->State;
5758
5759 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
5760 {
5761 if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
5762 {
5763 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
5764 }
5765 else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
5766 {
5767 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
5768 }
5769 else
5770 {
5771 /* Do nothing */
5772 }
5773
5774 /* Call the corresponding callback to inform upper layer of End of Transfer */
5775 I2C_ITError(hi2c, hi2c->ErrorCode);
5776 }
5777 }
5778 }
5779 else
5780 {
5781 /* Only Clear NACK Flag, no DMA treatment is pending */
5782 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5783 }
5784 }
5785 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
5786 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
5787 {
5788 I2C_ITAddrCplt(hi2c, ITFlags);
5789 }
5790 else
5791 {
5792 /* Nothing to do */
5793 }
5794
5795 /* Process Unlocked */
5796 __HAL_UNLOCK(hi2c);
5797
5798 return HAL_OK;
5799 }
5800 #endif /* HAL_DMA_MODULE_ENABLED */
5801
5802 /**
5803 * @brief Master sends target device address followed by internal memory address for write request.
5804 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5805 * the configuration information for the specified I2C.
5806 * @param DevAddress Target device address: The device 7 bits address value
5807 * in datasheet must be shifted to the left before calling the interface
5808 * @param MemAddress Internal memory address
5809 * @param MemAddSize Size of internal memory address
5810 * @param Timeout Timeout duration
5811 * @param Tickstart Tick start value
5812 * @retval HAL status
5813 */
I2C_RequestMemoryWrite(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)5814 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
5815 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
5816 uint32_t Tickstart)
5817 {
5818 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
5819
5820 /* Wait until TXIS flag is set */
5821 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5822 {
5823 return HAL_ERROR;
5824 }
5825
5826 /* If Memory address size is 8Bit */
5827 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
5828 {
5829 /* Send Memory Address */
5830 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5831 }
5832 /* If Memory address size is 16Bit */
5833 else
5834 {
5835 /* Send MSB of Memory Address */
5836 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
5837
5838 /* Wait until TXIS flag is set */
5839 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5840 {
5841 return HAL_ERROR;
5842 }
5843
5844 /* Send LSB of Memory Address */
5845 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5846 }
5847
5848 /* Wait until TCR flag is set */
5849 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
5850 {
5851 return HAL_ERROR;
5852 }
5853
5854 return HAL_OK;
5855 }
5856
5857 /**
5858 * @brief Master sends target device address followed by internal memory address for read request.
5859 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5860 * the configuration information for the specified I2C.
5861 * @param DevAddress Target device address: The device 7 bits address value
5862 * in datasheet must be shifted to the left before calling the interface
5863 * @param MemAddress Internal memory address
5864 * @param MemAddSize Size of internal memory address
5865 * @param Timeout Timeout duration
5866 * @param Tickstart Tick start value
5867 * @retval HAL status
5868 */
I2C_RequestMemoryRead(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)5869 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
5870 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
5871 uint32_t Tickstart)
5872 {
5873 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
5874
5875 /* Wait until TXIS flag is set */
5876 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5877 {
5878 return HAL_ERROR;
5879 }
5880
5881 /* If Memory address size is 8Bit */
5882 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
5883 {
5884 /* Send Memory Address */
5885 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5886 }
5887 /* If Memory address size is 16Bit */
5888 else
5889 {
5890 /* Send MSB of Memory Address */
5891 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
5892
5893 /* Wait until TXIS flag is set */
5894 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5895 {
5896 return HAL_ERROR;
5897 }
5898
5899 /* Send LSB of Memory Address */
5900 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5901 }
5902
5903 /* Wait until TC flag is set */
5904 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
5905 {
5906 return HAL_ERROR;
5907 }
5908
5909 return HAL_OK;
5910 }
5911
5912 /**
5913 * @brief I2C Address complete process callback.
5914 * @param hi2c I2C handle.
5915 * @param ITFlags Interrupt flags to handle.
5916 * @retval None
5917 */
I2C_ITAddrCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)5918 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
5919 {
5920 uint8_t transferdirection;
5921 uint16_t slaveaddrcode;
5922 uint16_t ownadd1code;
5923 uint16_t ownadd2code;
5924
5925 /* Prevent unused argument(s) compilation warning */
5926 UNUSED(ITFlags);
5927
5928 /* In case of Listen state, need to inform upper layer of address match code event */
5929 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
5930 {
5931 transferdirection = I2C_GET_DIR(hi2c);
5932 slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
5933 ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
5934 ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
5935
5936 /* If 10bits addressing mode is selected */
5937 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
5938 {
5939 if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
5940 {
5941 slaveaddrcode = ownadd1code;
5942 hi2c->AddrEventCount++;
5943 if (hi2c->AddrEventCount == 2U)
5944 {
5945 /* Reset Address Event counter */
5946 hi2c->AddrEventCount = 0U;
5947
5948 /* Clear ADDR flag */
5949 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
5950
5951 /* Process Unlocked */
5952 __HAL_UNLOCK(hi2c);
5953
5954 /* Call Slave Addr callback */
5955 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5956 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
5957 #else
5958 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
5959 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5960 }
5961 }
5962 else
5963 {
5964 slaveaddrcode = ownadd2code;
5965
5966 /* Disable ADDR Interrupts */
5967 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
5968
5969 /* Process Unlocked */
5970 __HAL_UNLOCK(hi2c);
5971
5972 /* Call Slave Addr callback */
5973 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5974 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
5975 #else
5976 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
5977 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5978 }
5979 }
5980 /* else 7 bits addressing mode is selected */
5981 else
5982 {
5983 /* Disable ADDR Interrupts */
5984 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
5985
5986 /* Process Unlocked */
5987 __HAL_UNLOCK(hi2c);
5988
5989 /* Call Slave Addr callback */
5990 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5991 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
5992 #else
5993 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
5994 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5995 }
5996 }
5997 /* Else clear address flag only */
5998 else
5999 {
6000 /* Clear ADDR flag */
6001 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
6002
6003 /* Process Unlocked */
6004 __HAL_UNLOCK(hi2c);
6005 }
6006 }
6007
6008 /**
6009 * @brief I2C Master sequential complete process.
6010 * @param hi2c I2C handle.
6011 * @retval None
6012 */
I2C_ITMasterSeqCplt(I2C_HandleTypeDef * hi2c)6013 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
6014 {
6015 /* Reset I2C handle mode */
6016 hi2c->Mode = HAL_I2C_MODE_NONE;
6017
6018 /* No Generate Stop, to permit restart mode */
6019 /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
6020 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
6021 {
6022 hi2c->State = HAL_I2C_STATE_READY;
6023 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
6024 hi2c->XferISR = NULL;
6025
6026 /* Disable Interrupts */
6027 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
6028
6029 /* Process Unlocked */
6030 __HAL_UNLOCK(hi2c);
6031
6032 /* Call the corresponding callback to inform upper layer of End of Transfer */
6033 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6034 hi2c->MasterTxCpltCallback(hi2c);
6035 #else
6036 HAL_I2C_MasterTxCpltCallback(hi2c);
6037 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6038 }
6039 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
6040 else
6041 {
6042 hi2c->State = HAL_I2C_STATE_READY;
6043 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
6044 hi2c->XferISR = NULL;
6045
6046 /* Disable Interrupts */
6047 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
6048
6049 /* Process Unlocked */
6050 __HAL_UNLOCK(hi2c);
6051
6052 /* Call the corresponding callback to inform upper layer of End of Transfer */
6053 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6054 hi2c->MasterRxCpltCallback(hi2c);
6055 #else
6056 HAL_I2C_MasterRxCpltCallback(hi2c);
6057 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6058 }
6059 }
6060
6061 /**
6062 * @brief I2C Slave sequential complete process.
6063 * @param hi2c I2C handle.
6064 * @retval None
6065 */
I2C_ITSlaveSeqCplt(I2C_HandleTypeDef * hi2c)6066 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
6067 {
6068 uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
6069
6070 /* Reset I2C handle mode */
6071 hi2c->Mode = HAL_I2C_MODE_NONE;
6072
6073 #if defined(HAL_DMA_MODULE_ENABLED)
6074 /* If a DMA is ongoing, Update handle size context */
6075 if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
6076 {
6077 /* Disable DMA Request */
6078 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6079 }
6080 else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
6081 {
6082 /* Disable DMA Request */
6083 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6084 }
6085 else
6086 {
6087 /* Do nothing */
6088 }
6089 #endif /* HAL_DMA_MODULE_ENABLED */
6090
6091 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
6092 {
6093 /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
6094 hi2c->State = HAL_I2C_STATE_LISTEN;
6095 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6096
6097 /* Disable Interrupts */
6098 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
6099
6100 /* Process Unlocked */
6101 __HAL_UNLOCK(hi2c);
6102
6103 /* Call the corresponding callback to inform upper layer of End of Transfer */
6104 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6105 hi2c->SlaveTxCpltCallback(hi2c);
6106 #else
6107 HAL_I2C_SlaveTxCpltCallback(hi2c);
6108 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6109 }
6110
6111 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
6112 {
6113 /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
6114 hi2c->State = HAL_I2C_STATE_LISTEN;
6115 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6116
6117 /* Disable Interrupts */
6118 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
6119
6120 /* Process Unlocked */
6121 __HAL_UNLOCK(hi2c);
6122
6123 /* Call the corresponding callback to inform upper layer of End of Transfer */
6124 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6125 hi2c->SlaveRxCpltCallback(hi2c);
6126 #else
6127 HAL_I2C_SlaveRxCpltCallback(hi2c);
6128 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6129 }
6130 else
6131 {
6132 /* Nothing to do */
6133 }
6134 }
6135
6136 /**
6137 * @brief I2C Master complete process.
6138 * @param hi2c I2C handle.
6139 * @param ITFlags Interrupt flags to handle.
6140 * @retval None
6141 */
I2C_ITMasterCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6142 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6143 {
6144 uint32_t tmperror;
6145 uint32_t tmpITFlags = ITFlags;
6146 __IO uint32_t tmpreg;
6147
6148 /* Clear STOP Flag */
6149 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6150
6151 /* Disable Interrupts and Store Previous state */
6152 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
6153 {
6154 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
6155 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
6156 }
6157 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6158 {
6159 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
6160 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
6161 }
6162 else
6163 {
6164 /* Do nothing */
6165 }
6166
6167 /* Clear Configuration Register 2 */
6168 I2C_RESET_CR2(hi2c);
6169
6170 /* Reset handle parameters */
6171 hi2c->XferISR = NULL;
6172 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6173
6174 if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
6175 {
6176 /* Clear NACK Flag */
6177 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6178
6179 /* Set acknowledge error code */
6180 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6181 }
6182
6183 /* Fetch Last receive data if any */
6184 if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
6185 {
6186 /* Read data from RXDR */
6187 tmpreg = (uint8_t)hi2c->Instance->RXDR;
6188 UNUSED(tmpreg);
6189 }
6190
6191 /* Flush TX register */
6192 I2C_Flush_TXDR(hi2c);
6193
6194 /* Store current volatile hi2c->ErrorCode, misra rule */
6195 tmperror = hi2c->ErrorCode;
6196
6197 /* Call the corresponding callback to inform upper layer of End of Transfer */
6198 if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
6199 {
6200 /* Call the corresponding callback to inform upper layer of End of Transfer */
6201 I2C_ITError(hi2c, hi2c->ErrorCode);
6202 }
6203 /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
6204 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
6205 {
6206 hi2c->State = HAL_I2C_STATE_READY;
6207 hi2c->PreviousState = I2C_STATE_NONE;
6208
6209 if (hi2c->Mode == HAL_I2C_MODE_MEM)
6210 {
6211 hi2c->Mode = HAL_I2C_MODE_NONE;
6212
6213 /* Process Unlocked */
6214 __HAL_UNLOCK(hi2c);
6215
6216 /* Call the corresponding callback to inform upper layer of End of Transfer */
6217 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6218 hi2c->MemTxCpltCallback(hi2c);
6219 #else
6220 HAL_I2C_MemTxCpltCallback(hi2c);
6221 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6222 }
6223 else
6224 {
6225 hi2c->Mode = HAL_I2C_MODE_NONE;
6226
6227 /* Process Unlocked */
6228 __HAL_UNLOCK(hi2c);
6229
6230 /* Call the corresponding callback to inform upper layer of End of Transfer */
6231 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6232 hi2c->MasterTxCpltCallback(hi2c);
6233 #else
6234 HAL_I2C_MasterTxCpltCallback(hi2c);
6235 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6236 }
6237 }
6238 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
6239 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6240 {
6241 hi2c->State = HAL_I2C_STATE_READY;
6242 hi2c->PreviousState = I2C_STATE_NONE;
6243
6244 if (hi2c->Mode == HAL_I2C_MODE_MEM)
6245 {
6246 hi2c->Mode = HAL_I2C_MODE_NONE;
6247
6248 /* Process Unlocked */
6249 __HAL_UNLOCK(hi2c);
6250
6251 /* Call the corresponding callback to inform upper layer of End of Transfer */
6252 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6253 hi2c->MemRxCpltCallback(hi2c);
6254 #else
6255 HAL_I2C_MemRxCpltCallback(hi2c);
6256 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6257 }
6258 else
6259 {
6260 hi2c->Mode = HAL_I2C_MODE_NONE;
6261
6262 /* Process Unlocked */
6263 __HAL_UNLOCK(hi2c);
6264
6265 /* Call the corresponding callback to inform upper layer of End of Transfer */
6266 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6267 hi2c->MasterRxCpltCallback(hi2c);
6268 #else
6269 HAL_I2C_MasterRxCpltCallback(hi2c);
6270 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6271 }
6272 }
6273 else
6274 {
6275 /* Nothing to do */
6276 }
6277 }
6278
6279 /**
6280 * @brief I2C Slave complete process.
6281 * @param hi2c I2C handle.
6282 * @param ITFlags Interrupt flags to handle.
6283 * @retval None
6284 */
I2C_ITSlaveCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6285 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6286 {
6287 uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
6288 uint32_t tmpITFlags = ITFlags;
6289 HAL_I2C_StateTypeDef tmpstate = hi2c->State;
6290
6291 /* Clear STOP Flag */
6292 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6293
6294 /* Disable Interrupts and Store Previous state */
6295 if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
6296 {
6297 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
6298 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6299 }
6300 else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6301 {
6302 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
6303 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6304 }
6305 else if (tmpstate == HAL_I2C_STATE_LISTEN)
6306 {
6307 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
6308 hi2c->PreviousState = I2C_STATE_NONE;
6309 }
6310 else
6311 {
6312 /* Do nothing */
6313 }
6314
6315 /* Disable Address Acknowledge */
6316 hi2c->Instance->CR2 |= I2C_CR2_NACK;
6317
6318 /* Clear Configuration Register 2 */
6319 I2C_RESET_CR2(hi2c);
6320
6321 /* Flush TX register */
6322 I2C_Flush_TXDR(hi2c);
6323
6324 #if defined(HAL_DMA_MODULE_ENABLED)
6325 /* If a DMA is ongoing, Update handle size context */
6326 if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
6327 {
6328 /* Disable DMA Request */
6329 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6330
6331 if (hi2c->hdmatx != NULL)
6332 {
6333 hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
6334 }
6335 }
6336 else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
6337 {
6338 /* Disable DMA Request */
6339 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6340
6341 if (hi2c->hdmarx != NULL)
6342 {
6343 hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
6344 }
6345 }
6346 else
6347 {
6348 /* Do nothing */
6349 }
6350 #endif /* HAL_DMA_MODULE_ENABLED */
6351
6352 /* Store Last receive data if any */
6353 if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
6354 {
6355 /* Remove RXNE flag on temporary variable as read done */
6356 tmpITFlags &= ~I2C_FLAG_RXNE;
6357
6358 /* Read data from RXDR */
6359 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
6360
6361 /* Increment Buffer pointer */
6362 hi2c->pBuffPtr++;
6363
6364 if ((hi2c->XferSize > 0U))
6365 {
6366 hi2c->XferSize--;
6367 hi2c->XferCount--;
6368 }
6369 }
6370
6371 /* All data are not transferred, so set error code accordingly */
6372 if (hi2c->XferCount != 0U)
6373 {
6374 /* Set ErrorCode corresponding to a Non-Acknowledge */
6375 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6376 }
6377
6378 hi2c->Mode = HAL_I2C_MODE_NONE;
6379 hi2c->XferISR = NULL;
6380
6381 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
6382 {
6383 /* Call the corresponding callback to inform upper layer of End of Transfer */
6384 I2C_ITError(hi2c, hi2c->ErrorCode);
6385
6386 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6387 if (hi2c->State == HAL_I2C_STATE_LISTEN)
6388 {
6389 /* Call I2C Listen complete process */
6390 I2C_ITListenCplt(hi2c, tmpITFlags);
6391 }
6392 }
6393 else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
6394 {
6395 /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
6396 I2C_ITSlaveSeqCplt(hi2c);
6397
6398 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6399 hi2c->State = HAL_I2C_STATE_READY;
6400 hi2c->PreviousState = I2C_STATE_NONE;
6401
6402 /* Process Unlocked */
6403 __HAL_UNLOCK(hi2c);
6404
6405 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6406 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6407 hi2c->ListenCpltCallback(hi2c);
6408 #else
6409 HAL_I2C_ListenCpltCallback(hi2c);
6410 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6411 }
6412 /* Call the corresponding callback to inform upper layer of End of Transfer */
6413 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6414 {
6415 hi2c->State = HAL_I2C_STATE_READY;
6416 hi2c->PreviousState = I2C_STATE_NONE;
6417
6418 /* Process Unlocked */
6419 __HAL_UNLOCK(hi2c);
6420
6421 /* Call the corresponding callback to inform upper layer of End of Transfer */
6422 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6423 hi2c->SlaveRxCpltCallback(hi2c);
6424 #else
6425 HAL_I2C_SlaveRxCpltCallback(hi2c);
6426 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6427 }
6428 else
6429 {
6430 hi2c->State = HAL_I2C_STATE_READY;
6431 hi2c->PreviousState = I2C_STATE_NONE;
6432
6433 /* Process Unlocked */
6434 __HAL_UNLOCK(hi2c);
6435
6436 /* Call the corresponding callback to inform upper layer of End of Transfer */
6437 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6438 hi2c->SlaveTxCpltCallback(hi2c);
6439 #else
6440 HAL_I2C_SlaveTxCpltCallback(hi2c);
6441 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6442 }
6443 }
6444
6445 /**
6446 * @brief I2C Listen complete process.
6447 * @param hi2c I2C handle.
6448 * @param ITFlags Interrupt flags to handle.
6449 * @retval None
6450 */
I2C_ITListenCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6451 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6452 {
6453 /* Reset handle parameters */
6454 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6455 hi2c->PreviousState = I2C_STATE_NONE;
6456 hi2c->State = HAL_I2C_STATE_READY;
6457 hi2c->Mode = HAL_I2C_MODE_NONE;
6458 hi2c->XferISR = NULL;
6459
6460 /* Store Last receive data if any */
6461 if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
6462 {
6463 /* Read data from RXDR */
6464 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
6465
6466 /* Increment Buffer pointer */
6467 hi2c->pBuffPtr++;
6468
6469 if ((hi2c->XferSize > 0U))
6470 {
6471 hi2c->XferSize--;
6472 hi2c->XferCount--;
6473
6474 /* Set ErrorCode corresponding to a Non-Acknowledge */
6475 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6476 }
6477 }
6478
6479 /* Disable all Interrupts*/
6480 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6481
6482 /* Clear NACK Flag */
6483 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6484
6485 /* Process Unlocked */
6486 __HAL_UNLOCK(hi2c);
6487
6488 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6489 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6490 hi2c->ListenCpltCallback(hi2c);
6491 #else
6492 HAL_I2C_ListenCpltCallback(hi2c);
6493 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6494 }
6495
6496 /**
6497 * @brief I2C interrupts error process.
6498 * @param hi2c I2C handle.
6499 * @param ErrorCode Error code to handle.
6500 * @retval None
6501 */
I2C_ITError(I2C_HandleTypeDef * hi2c,uint32_t ErrorCode)6502 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
6503 {
6504 HAL_I2C_StateTypeDef tmpstate = hi2c->State;
6505
6506 #if defined(HAL_DMA_MODULE_ENABLED)
6507 uint32_t tmppreviousstate;
6508 #endif /* HAL_DMA_MODULE_ENABLED */
6509
6510 /* Reset handle parameters */
6511 hi2c->Mode = HAL_I2C_MODE_NONE;
6512 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6513 hi2c->XferCount = 0U;
6514
6515 /* Set new error code */
6516 hi2c->ErrorCode |= ErrorCode;
6517
6518 /* Disable Interrupts */
6519 if ((tmpstate == HAL_I2C_STATE_LISTEN) ||
6520 (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
6521 (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6522 {
6523 /* Disable all interrupts, except interrupts related to LISTEN state */
6524 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6525
6526 /* keep HAL_I2C_STATE_LISTEN if set */
6527 hi2c->State = HAL_I2C_STATE_LISTEN;
6528 hi2c->XferISR = I2C_Slave_ISR_IT;
6529 }
6530 else
6531 {
6532 /* Disable all interrupts */
6533 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6534
6535 /* Flush TX register */
6536 I2C_Flush_TXDR(hi2c);
6537
6538 /* If state is an abort treatment on going, don't change state */
6539 /* This change will be do later */
6540 if (hi2c->State != HAL_I2C_STATE_ABORT)
6541 {
6542 /* Set HAL_I2C_STATE_READY */
6543 hi2c->State = HAL_I2C_STATE_READY;
6544
6545 /* Check if a STOPF is detected */
6546 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
6547 {
6548 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
6549 {
6550 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6551 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6552 }
6553
6554 /* Clear STOP Flag */
6555 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6556 }
6557
6558 }
6559 hi2c->XferISR = NULL;
6560 }
6561
6562 #if defined(HAL_DMA_MODULE_ENABLED)
6563 /* Abort DMA TX transfer if any */
6564 tmppreviousstate = hi2c->PreviousState;
6565
6566 if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
6567 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
6568 {
6569 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
6570 {
6571 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6572 }
6573
6574 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
6575 {
6576 /* Set the I2C DMA Abort callback :
6577 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6578 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6579
6580 /* Process Unlocked */
6581 __HAL_UNLOCK(hi2c);
6582
6583 /* Abort DMA TX */
6584 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6585 {
6586 /* Call Directly XferAbortCallback function in case of error */
6587 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6588 }
6589 }
6590 else
6591 {
6592 I2C_TreatErrorCallback(hi2c);
6593 }
6594 }
6595 /* Abort DMA RX transfer if any */
6596 else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
6597 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
6598 {
6599 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
6600 {
6601 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6602 }
6603
6604 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
6605 {
6606 /* Set the I2C DMA Abort callback :
6607 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6608 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6609
6610 /* Process Unlocked */
6611 __HAL_UNLOCK(hi2c);
6612
6613 /* Abort DMA RX */
6614 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6615 {
6616 /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
6617 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6618 }
6619 }
6620 else
6621 {
6622 I2C_TreatErrorCallback(hi2c);
6623 }
6624 }
6625 else
6626 #endif /* HAL_DMA_MODULE_ENABLED */
6627 {
6628 I2C_TreatErrorCallback(hi2c);
6629 }
6630 }
6631
6632 /**
6633 * @brief I2C Error callback treatment.
6634 * @param hi2c I2C handle.
6635 * @retval None
6636 */
I2C_TreatErrorCallback(I2C_HandleTypeDef * hi2c)6637 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
6638 {
6639 if (hi2c->State == HAL_I2C_STATE_ABORT)
6640 {
6641 hi2c->State = HAL_I2C_STATE_READY;
6642 hi2c->PreviousState = I2C_STATE_NONE;
6643
6644 /* Process Unlocked */
6645 __HAL_UNLOCK(hi2c);
6646
6647 /* Call the corresponding callback to inform upper layer of End of Transfer */
6648 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6649 hi2c->AbortCpltCallback(hi2c);
6650 #else
6651 HAL_I2C_AbortCpltCallback(hi2c);
6652 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6653 }
6654 else
6655 {
6656 hi2c->PreviousState = I2C_STATE_NONE;
6657
6658 /* Process Unlocked */
6659 __HAL_UNLOCK(hi2c);
6660
6661 /* Call the corresponding callback to inform upper layer of End of Transfer */
6662 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6663 hi2c->ErrorCallback(hi2c);
6664 #else
6665 HAL_I2C_ErrorCallback(hi2c);
6666 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6667 }
6668 }
6669
6670 /**
6671 * @brief I2C Tx data register flush process.
6672 * @param hi2c I2C handle.
6673 * @retval None
6674 */
I2C_Flush_TXDR(I2C_HandleTypeDef * hi2c)6675 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
6676 {
6677 /* If a pending TXIS flag is set */
6678 /* Write a dummy data in TXDR to clear it */
6679 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
6680 {
6681 hi2c->Instance->TXDR = 0x00U;
6682 }
6683
6684 /* Flush TX register if not empty */
6685 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
6686 {
6687 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
6688 }
6689 }
6690
6691 #if defined(HAL_DMA_MODULE_ENABLED)
6692 /**
6693 * @brief DMA I2C master transmit process complete callback.
6694 * @param hdma DMA handle
6695 * @retval None
6696 */
I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef * hdma)6697 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
6698 {
6699 /* Derogation MISRAC2012-Rule-11.5 */
6700 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6701
6702 /* Disable DMA Request */
6703 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6704
6705 /* If last transfer, enable STOP interrupt */
6706 if (hi2c->XferCount == 0U)
6707 {
6708 /* Enable STOP interrupt */
6709 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
6710 }
6711 /* else prepare a new DMA transfer and enable TCReload interrupt */
6712 else
6713 {
6714 /* Update Buffer pointer */
6715 hi2c->pBuffPtr += hi2c->XferSize;
6716
6717 /* Set the XferSize to transfer */
6718 if (hi2c->XferCount > MAX_NBYTE_SIZE)
6719 {
6720 hi2c->XferSize = MAX_NBYTE_SIZE;
6721 }
6722 else
6723 {
6724 hi2c->XferSize = hi2c->XferCount;
6725 }
6726
6727 /* Enable the DMA channel */
6728 if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
6729 hi2c->XferSize) != HAL_OK)
6730 {
6731 /* Call the corresponding callback to inform upper layer of End of Transfer */
6732 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6733 }
6734 else
6735 {
6736 /* Enable TC interrupts */
6737 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
6738 }
6739 }
6740 }
6741
6742
6743 /**
6744 * @brief DMA I2C slave transmit process complete callback.
6745 * @param hdma DMA handle
6746 * @retval None
6747 */
I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef * hdma)6748 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
6749 {
6750 /* Derogation MISRAC2012-Rule-11.5 */
6751 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6752 uint32_t tmpoptions = hi2c->XferOptions;
6753
6754 if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
6755 {
6756 /* Disable DMA Request */
6757 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6758
6759 /* Last Byte is Transmitted */
6760 /* Call I2C Slave Sequential complete process */
6761 I2C_ITSlaveSeqCplt(hi2c);
6762 }
6763 else
6764 {
6765 /* No specific action, Master fully manage the generation of STOP condition */
6766 /* Mean that this generation can arrive at any time, at the end or during DMA process */
6767 /* So STOP condition should be manage through Interrupt treatment */
6768 }
6769 }
6770
6771
6772 /**
6773 * @brief DMA I2C master receive process complete callback.
6774 * @param hdma DMA handle
6775 * @retval None
6776 */
I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef * hdma)6777 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
6778 {
6779 /* Derogation MISRAC2012-Rule-11.5 */
6780 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6781
6782 /* Disable DMA Request */
6783 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6784
6785 /* If last transfer, enable STOP interrupt */
6786 if (hi2c->XferCount == 0U)
6787 {
6788 /* Enable STOP interrupt */
6789 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
6790 }
6791 /* else prepare a new DMA transfer and enable TCReload interrupt */
6792 else
6793 {
6794 /* Update Buffer pointer */
6795 hi2c->pBuffPtr += hi2c->XferSize;
6796
6797 /* Set the XferSize to transfer */
6798 if (hi2c->XferCount > MAX_NBYTE_SIZE)
6799 {
6800 hi2c->XferSize = MAX_NBYTE_SIZE;
6801 }
6802 else
6803 {
6804 hi2c->XferSize = hi2c->XferCount;
6805 }
6806
6807 /* Enable the DMA channel */
6808 if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
6809 hi2c->XferSize) != HAL_OK)
6810 {
6811 /* Call the corresponding callback to inform upper layer of End of Transfer */
6812 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6813 }
6814 else
6815 {
6816 /* Enable TC interrupts */
6817 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
6818 }
6819 }
6820 }
6821
6822
6823 /**
6824 * @brief DMA I2C slave receive process complete callback.
6825 * @param hdma DMA handle
6826 * @retval None
6827 */
I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef * hdma)6828 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
6829 {
6830 /* Derogation MISRAC2012-Rule-11.5 */
6831 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6832 uint32_t tmpoptions = hi2c->XferOptions;
6833
6834 if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
6835 (tmpoptions != I2C_NO_OPTION_FRAME))
6836 {
6837 /* Disable DMA Request */
6838 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6839
6840 /* Call I2C Slave Sequential complete process */
6841 I2C_ITSlaveSeqCplt(hi2c);
6842 }
6843 else
6844 {
6845 /* No specific action, Master fully manage the generation of STOP condition */
6846 /* Mean that this generation can arrive at any time, at the end or during DMA process */
6847 /* So STOP condition should be manage through Interrupt treatment */
6848 }
6849 }
6850
6851
6852 /**
6853 * @brief DMA I2C communication error callback.
6854 * @param hdma DMA handle
6855 * @retval None
6856 */
I2C_DMAError(DMA_HandleTypeDef * hdma)6857 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
6858 {
6859 /* Derogation MISRAC2012-Rule-11.5 */
6860 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6861
6862 /* Disable Acknowledge */
6863 hi2c->Instance->CR2 |= I2C_CR2_NACK;
6864
6865 /* Call the corresponding callback to inform upper layer of End of Transfer */
6866 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6867 }
6868
6869
6870 /**
6871 * @brief DMA I2C communication abort callback
6872 * (To be called at end of DMA Abort procedure).
6873 * @param hdma DMA handle.
6874 * @retval None
6875 */
I2C_DMAAbort(DMA_HandleTypeDef * hdma)6876 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
6877 {
6878 /* Derogation MISRAC2012-Rule-11.5 */
6879 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6880
6881 /* Reset AbortCpltCallback */
6882 if (hi2c->hdmatx != NULL)
6883 {
6884 hi2c->hdmatx->XferAbortCallback = NULL;
6885 }
6886 if (hi2c->hdmarx != NULL)
6887 {
6888 hi2c->hdmarx->XferAbortCallback = NULL;
6889 }
6890
6891 I2C_TreatErrorCallback(hi2c);
6892 }
6893
6894 #endif /* HAL_DMA_MODULE_ENABLED */
6895
6896 /**
6897 * @brief This function handles I2C Communication Timeout. It waits
6898 * until a flag is no longer in the specified status.
6899 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6900 * the configuration information for the specified I2C.
6901 * @param Flag Specifies the I2C flag to check.
6902 * @param Status The actual Flag status (SET or RESET).
6903 * @param Timeout Timeout duration
6904 * @param Tickstart Tick start value
6905 * @retval HAL status
6906 */
I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Flag,FlagStatus Status,uint32_t Timeout,uint32_t Tickstart)6907 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
6908 uint32_t Timeout, uint32_t Tickstart)
6909 {
6910 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
6911 {
6912 /* Check for the Timeout */
6913 if (Timeout != HAL_MAX_DELAY)
6914 {
6915 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6916 {
6917 if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
6918 {
6919 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6920 hi2c->State = HAL_I2C_STATE_READY;
6921 hi2c->Mode = HAL_I2C_MODE_NONE;
6922
6923 /* Process Unlocked */
6924 __HAL_UNLOCK(hi2c);
6925 return HAL_ERROR;
6926 }
6927 }
6928 }
6929 }
6930 return HAL_OK;
6931 }
6932
6933 /**
6934 * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
6935 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6936 * the configuration information for the specified I2C.
6937 * @param Timeout Timeout duration
6938 * @param Tickstart Tick start value
6939 * @retval HAL status
6940 */
I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)6941 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
6942 uint32_t Tickstart)
6943 {
6944 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
6945 {
6946 /* Check if an error is detected */
6947 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
6948 {
6949 return HAL_ERROR;
6950 }
6951
6952 /* Check for the Timeout */
6953 if (Timeout != HAL_MAX_DELAY)
6954 {
6955 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6956 {
6957 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET))
6958 {
6959 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6960 hi2c->State = HAL_I2C_STATE_READY;
6961 hi2c->Mode = HAL_I2C_MODE_NONE;
6962
6963 /* Process Unlocked */
6964 __HAL_UNLOCK(hi2c);
6965
6966 return HAL_ERROR;
6967 }
6968 }
6969 }
6970 }
6971 return HAL_OK;
6972 }
6973
6974 /**
6975 * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
6976 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6977 * the configuration information for the specified I2C.
6978 * @param Timeout Timeout duration
6979 * @param Tickstart Tick start value
6980 * @retval HAL status
6981 */
I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)6982 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
6983 uint32_t Tickstart)
6984 {
6985 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
6986 {
6987 /* Check if an error is detected */
6988 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
6989 {
6990 return HAL_ERROR;
6991 }
6992
6993 /* Check for the Timeout */
6994 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6995 {
6996 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
6997 {
6998 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6999 hi2c->State = HAL_I2C_STATE_READY;
7000 hi2c->Mode = HAL_I2C_MODE_NONE;
7001
7002 /* Process Unlocked */
7003 __HAL_UNLOCK(hi2c);
7004
7005 return HAL_ERROR;
7006 }
7007 }
7008 }
7009 return HAL_OK;
7010 }
7011
7012 /**
7013 * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
7014 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7015 * the configuration information for the specified I2C.
7016 * @param Timeout Timeout duration
7017 * @param Tickstart Tick start value
7018 * @retval HAL status
7019 */
I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7020 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
7021 uint32_t Tickstart)
7022 {
7023 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
7024 {
7025 /* Check if an error is detected */
7026 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
7027 {
7028 return HAL_ERROR;
7029 }
7030
7031 /* Check if a STOPF is detected */
7032 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
7033 {
7034 /* Check if an RXNE is pending */
7035 /* Store Last receive data if any */
7036 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
7037 {
7038 /* Return HAL_OK */
7039 /* The Reading of data from RXDR will be done in caller function */
7040 return HAL_OK;
7041 }
7042 else
7043 {
7044 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
7045 {
7046 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7047 hi2c->ErrorCode = HAL_I2C_ERROR_AF;
7048 }
7049 else
7050 {
7051 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
7052 }
7053
7054 /* Clear STOP Flag */
7055 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
7056
7057 /* Clear Configuration Register 2 */
7058 I2C_RESET_CR2(hi2c);
7059
7060 hi2c->State = HAL_I2C_STATE_READY;
7061 hi2c->Mode = HAL_I2C_MODE_NONE;
7062
7063 /* Process Unlocked */
7064 __HAL_UNLOCK(hi2c);
7065
7066 return HAL_ERROR;
7067 }
7068 }
7069
7070 /* Check for the Timeout */
7071 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7072 {
7073 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
7074 {
7075 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7076 hi2c->State = HAL_I2C_STATE_READY;
7077
7078 /* Process Unlocked */
7079 __HAL_UNLOCK(hi2c);
7080
7081 return HAL_ERROR;
7082 }
7083 }
7084 }
7085 return HAL_OK;
7086 }
7087
7088 /**
7089 * @brief This function handles errors detection during an I2C Communication.
7090 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7091 * the configuration information for the specified I2C.
7092 * @param Timeout Timeout duration
7093 * @param Tickstart Tick start value
7094 * @retval HAL status
7095 */
I2C_IsErrorOccurred(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7096 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7097 {
7098 HAL_StatusTypeDef status = HAL_OK;
7099 uint32_t itflag = hi2c->Instance->ISR;
7100 uint32_t error_code = 0;
7101 uint32_t tickstart = Tickstart;
7102 uint32_t tmp1;
7103 HAL_I2C_ModeTypeDef tmp2;
7104
7105 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
7106 {
7107 /* Clear NACKF Flag */
7108 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7109
7110 /* Wait until STOP Flag is set or timeout occurred */
7111 /* AutoEnd should be initiate after AF */
7112 while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
7113 {
7114 /* Check for the Timeout */
7115 if (Timeout != HAL_MAX_DELAY)
7116 {
7117 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7118 {
7119 tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
7120 tmp2 = hi2c->Mode;
7121
7122 /* In case of I2C still busy, try to regenerate a STOP manually */
7123 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
7124 (tmp1 != I2C_CR2_STOP) && \
7125 (tmp2 != HAL_I2C_MODE_SLAVE))
7126 {
7127 /* Generate Stop */
7128 hi2c->Instance->CR2 |= I2C_CR2_STOP;
7129
7130 /* Update Tick with new reference */
7131 tickstart = HAL_GetTick();
7132 }
7133
7134 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
7135 {
7136 /* Check for the Timeout */
7137 if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
7138 {
7139 error_code |= HAL_I2C_ERROR_TIMEOUT;
7140
7141 status = HAL_ERROR;
7142
7143 break;
7144 }
7145 }
7146 }
7147 }
7148 }
7149
7150 /* In case STOP Flag is detected, clear it */
7151 if (status == HAL_OK)
7152 {
7153 /* Clear STOP Flag */
7154 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
7155 }
7156
7157 error_code |= HAL_I2C_ERROR_AF;
7158
7159 status = HAL_ERROR;
7160 }
7161
7162 /* Refresh Content of Status register */
7163 itflag = hi2c->Instance->ISR;
7164
7165 /* Then verify if an additional errors occurs */
7166 /* Check if a Bus error occurred */
7167 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
7168 {
7169 error_code |= HAL_I2C_ERROR_BERR;
7170
7171 /* Clear BERR flag */
7172 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
7173
7174 status = HAL_ERROR;
7175 }
7176
7177 /* Check if an Over-Run/Under-Run error occurred */
7178 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
7179 {
7180 error_code |= HAL_I2C_ERROR_OVR;
7181
7182 /* Clear OVR flag */
7183 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
7184
7185 status = HAL_ERROR;
7186 }
7187
7188 /* Check if an Arbitration Loss error occurred */
7189 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
7190 {
7191 error_code |= HAL_I2C_ERROR_ARLO;
7192
7193 /* Clear ARLO flag */
7194 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
7195
7196 status = HAL_ERROR;
7197 }
7198
7199 if (status != HAL_OK)
7200 {
7201 /* Flush TX register */
7202 I2C_Flush_TXDR(hi2c);
7203
7204 /* Clear Configuration Register 2 */
7205 I2C_RESET_CR2(hi2c);
7206
7207 hi2c->ErrorCode |= error_code;
7208 hi2c->State = HAL_I2C_STATE_READY;
7209 hi2c->Mode = HAL_I2C_MODE_NONE;
7210
7211 /* Process Unlocked */
7212 __HAL_UNLOCK(hi2c);
7213 }
7214
7215 return status;
7216 }
7217
7218 /**
7219 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
7220 * @param hi2c I2C handle.
7221 * @param DevAddress Specifies the slave address to be programmed.
7222 * @param Size Specifies the number of bytes to be programmed.
7223 * This parameter must be a value between 0 and 255.
7224 * @param Mode New state of the I2C START condition generation.
7225 * This parameter can be one of the following values:
7226 * @arg @ref I2C_RELOAD_MODE Enable Reload mode .
7227 * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
7228 * @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
7229 * @param Request New state of the I2C START condition generation.
7230 * This parameter can be one of the following values:
7231 * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
7232 * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
7233 * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
7234 * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
7235 * @retval None
7236 */
I2C_TransferConfig(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t Size,uint32_t Mode,uint32_t Request)7237 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
7238 uint32_t Request)
7239 {
7240 /* Check the parameters */
7241 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
7242 assert_param(IS_TRANSFER_MODE(Mode));
7243 assert_param(IS_TRANSFER_REQUEST(Request));
7244
7245 /* Declaration of tmp to prevent undefined behavior of volatile usage */
7246 uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
7247 (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
7248 (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
7249
7250 /* update CR2 register */
7251 MODIFY_REG(hi2c->Instance->CR2, \
7252 ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
7253 (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
7254 I2C_CR2_START | I2C_CR2_STOP)), tmp);
7255 }
7256
7257 /**
7258 * @brief Manage the enabling of Interrupts.
7259 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7260 * the configuration information for the specified I2C.
7261 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
7262 * @retval None
7263 */
I2C_Enable_IRQ(I2C_HandleTypeDef * hi2c,uint16_t InterruptRequest)7264 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
7265 {
7266 uint32_t tmpisr = 0U;
7267
7268 #if defined(HAL_DMA_MODULE_ENABLED)
7269 if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \
7270 (hi2c->XferISR != I2C_Slave_ISR_DMA) && \
7271 (hi2c->XferISR != I2C_Mem_ISR_DMA))
7272 #endif /* HAL_DMA_MODULE_ENABLED */
7273 {
7274 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7275 {
7276 /* Enable ERR, STOP, NACK and ADDR interrupts */
7277 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7278 }
7279
7280 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7281 {
7282 /* Enable ERR, TC, STOP, NACK and TXI interrupts */
7283 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
7284 }
7285
7286 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7287 {
7288 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
7289 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
7290 }
7291
7292 if (InterruptRequest == I2C_XFER_ERROR_IT)
7293 {
7294 /* Enable ERR and NACK interrupts */
7295 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7296 }
7297
7298 if (InterruptRequest == I2C_XFER_CPLT_IT)
7299 {
7300 /* Enable STOP interrupts */
7301 tmpisr |= I2C_IT_STOPI;
7302 }
7303 }
7304
7305 #if defined(HAL_DMA_MODULE_ENABLED)
7306 else
7307 {
7308 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7309 {
7310 /* Enable ERR, STOP, NACK and ADDR interrupts */
7311 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7312 }
7313
7314 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7315 {
7316 /* Enable ERR, TC, STOP, NACK and TXI interrupts */
7317 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
7318 }
7319
7320 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7321 {
7322 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
7323 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
7324 }
7325
7326 if (InterruptRequest == I2C_XFER_ERROR_IT)
7327 {
7328 /* Enable ERR and NACK interrupts */
7329 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7330 }
7331
7332 if (InterruptRequest == I2C_XFER_CPLT_IT)
7333 {
7334 /* Enable STOP interrupts */
7335 tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
7336 }
7337
7338 if (InterruptRequest == I2C_XFER_RELOAD_IT)
7339 {
7340 /* Enable TC interrupts */
7341 tmpisr |= I2C_IT_TCI;
7342 }
7343 }
7344 #endif /* HAL_DMA_MODULE_ENABLED */
7345
7346 /* Enable interrupts only at the end */
7347 /* to avoid the risk of I2C interrupt handle execution before */
7348 /* all interrupts requested done */
7349 __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
7350 }
7351
7352 /**
7353 * @brief Manage the disabling of Interrupts.
7354 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7355 * the configuration information for the specified I2C.
7356 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
7357 * @retval None
7358 */
I2C_Disable_IRQ(I2C_HandleTypeDef * hi2c,uint16_t InterruptRequest)7359 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
7360 {
7361 uint32_t tmpisr = 0U;
7362
7363 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7364 {
7365 /* Disable TC and TXI interrupts */
7366 tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
7367
7368 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
7369 {
7370 /* Disable NACK and STOP interrupts */
7371 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7372 }
7373 }
7374
7375 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7376 {
7377 /* Disable TC and RXI interrupts */
7378 tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
7379
7380 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
7381 {
7382 /* Disable NACK and STOP interrupts */
7383 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7384 }
7385 }
7386
7387 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7388 {
7389 /* Disable ADDR, NACK and STOP interrupts */
7390 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7391 }
7392
7393 if (InterruptRequest == I2C_XFER_ERROR_IT)
7394 {
7395 /* Enable ERR and NACK interrupts */
7396 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7397 }
7398
7399 if (InterruptRequest == I2C_XFER_CPLT_IT)
7400 {
7401 /* Enable STOP interrupts */
7402 tmpisr |= I2C_IT_STOPI;
7403 }
7404
7405 if (InterruptRequest == I2C_XFER_RELOAD_IT)
7406 {
7407 /* Enable TC interrupts */
7408 tmpisr |= I2C_IT_TCI;
7409 }
7410
7411 /* Disable interrupts only at the end */
7412 /* to avoid a breaking situation like at "t" time */
7413 /* all disable interrupts request are not done */
7414 __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
7415 }
7416
7417 /**
7418 * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
7419 * @param hi2c I2C handle.
7420 * @retval None
7421 */
I2C_ConvertOtherXferOptions(I2C_HandleTypeDef * hi2c)7422 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
7423 {
7424 /* if user set XferOptions to I2C_OTHER_FRAME */
7425 /* it request implicitly to generate a restart condition */
7426 /* set XferOptions to I2C_FIRST_FRAME */
7427 if (hi2c->XferOptions == I2C_OTHER_FRAME)
7428 {
7429 hi2c->XferOptions = I2C_FIRST_FRAME;
7430 }
7431 /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
7432 /* it request implicitly to generate a restart condition */
7433 /* then generate a stop condition at the end of transfer */
7434 /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
7435 else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
7436 {
7437 hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
7438 }
7439 else
7440 {
7441 /* Nothing to do */
7442 }
7443 }
7444
7445 /**
7446 * @}
7447 */
7448
7449 #endif /* HAL_I2C_MODULE_ENABLED */
7450 /**
7451 * @}
7452 */
7453
7454 /**
7455 * @}
7456 */
7457
