1 /** 2 ****************************************************************************** 3 * @file stm32c0xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32C0xx_HAL_DMA_H 21 #define STM32C0xx_HAL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32c0xx_hal_def.h" 29 30 /** @addtogroup STM32C0xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup DMA 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup DMA_Exported_Types DMA Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief DMA Configuration Structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Request; /*!< Specifies the request selected for the specified channel. 49 This parameter can be a value of @ref DMA_request */ 50 51 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 52 from memory to memory or from peripheral to memory. 53 This parameter can be a value of @ref DMA_Data_transfer_direction */ 54 55 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 56 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 57 58 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 59 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 60 61 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 62 This parameter can be a value of @ref DMA_Peripheral_data_size */ 63 64 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 65 This parameter can be a value of @ref DMA_Memory_data_size */ 66 67 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. 68 This parameter can be a value of @ref DMA_mode 69 @note The circular buffer mode cannot be used if the memory-to-memory 70 data transfer is configured on the selected Channel */ 71 72 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 73 This parameter can be a value of @ref DMA_Priority_level */ 74 } DMA_InitTypeDef; 75 76 /** 77 * @brief HAL DMA State structures definition 78 */ 79 typedef enum 80 { 81 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 82 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 83 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 84 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ 85 } HAL_DMA_StateTypeDef; 86 87 /** 88 * @brief HAL DMA Error Code structure definition 89 */ 90 typedef enum 91 { 92 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 93 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 94 } HAL_DMA_LevelCompleteTypeDef; 95 96 /** 97 * @brief HAL DMA Callback ID structure definition 98 */ 99 typedef enum 100 { 101 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 102 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ 103 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ 104 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ 105 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ 106 107 } HAL_DMA_CallbackIDTypeDef; 108 109 /** 110 * @brief DMA handle Structure definition 111 */ 112 typedef struct __DMA_HandleTypeDef 113 { 114 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 115 116 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 117 118 HAL_LockTypeDef Lock; /*!< DMA locking object */ 119 120 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 121 122 void *Parent; /*!< Parent object state */ 123 124 void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ 125 126 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */ 127 128 void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ 129 130 void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */ 131 132 __IO uint32_t ErrorCode; /*!< DMA Error code */ 133 134 uint32_t ChannelIndex; /*!< DMA Channel Index */ 135 136 DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ 137 138 DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ 139 140 uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ 141 142 DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ 143 144 DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ 145 146 uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ 147 } DMA_HandleTypeDef; 148 /** 149 * @} 150 */ 151 152 /* Exported constants --------------------------------------------------------*/ 153 154 /** @defgroup DMA_Exported_Constants DMA Exported Constants 155 * @{ 156 */ 157 158 /** @defgroup DMA_Error_Code DMA Error Code 159 * @{ 160 */ 161 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 162 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 163 #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ 164 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 165 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 166 #define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */ 167 #define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */ 168 169 /** 170 * @} 171 */ 172 173 /** @defgroup DMA_request DMA request 174 * @{ 175 */ 176 #define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ 177 178 #define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX request generator 0 */ 179 #define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX request generator 1 */ 180 #define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX request generator 2 */ 181 #define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX request generator 3 */ 182 #define DMA_REQUEST_ADC1 5U /*!< DMAMUX ADC1 request */ 183 #define DMA_REQUEST_I2C1_RX 10U /*!< DMAMUX I2C1 RX request */ 184 #define DMA_REQUEST_I2C1_TX 11U /*!< DMAMUX I2C1 TX request */ 185 #if defined(I2C2) 186 #define DMA_REQUEST_I2C2_RX 12U /*!< DMAMUX I2C2 RX request */ 187 #define DMA_REQUEST_I2C2_TX 13U /*!< DMAMUX I2C2 TX request */ 188 #endif /* I2C2 */ 189 #define DMA_REQUEST_SPI1_RX 16U /*!< DMAMUX SPI1 RX request */ 190 #define DMA_REQUEST_SPI1_TX 17U /*!< DMAMUX SPI1 TX request */ 191 #if defined(SPI2) 192 #define DMA_REQUEST_SPI2_RX 18U /*!< DMAMUX SPI2 RX request */ 193 #define DMA_REQUEST_SPI2_TX 19U /*!< DMAMUX SPI2 TX request */ 194 #endif /* SPI2 */ 195 #define DMA_REQUEST_TIM1_CH1 20U /*!< DMAMUX TIM1 CH1 request */ 196 #define DMA_REQUEST_TIM1_CH2 21U /*!< DMAMUX TIM1 CH2 request */ 197 #define DMA_REQUEST_TIM1_CH3 22U /*!< DMAMUX TIM1 CH3 request */ 198 #define DMA_REQUEST_TIM1_CH4 23U /*!< DMAMUX TIM1 CH4 request */ 199 #define DMA_REQUEST_TIM1_TRIG_COM 24U /*!< DMAMUX TIM1 TRIG COM request */ 200 #define DMA_REQUEST_TIM1_UP 25U /*!< DMAMUX TIM1 UP request */ 201 #if defined(TIM2) 202 #define DMA_REQUEST_TIM2_CH1 26U /*!< DMAMUX TIM2 CH1 request */ 203 #define DMA_REQUEST_TIM2_CH2 27U /*!< DMAMUX TIM2 CH2 request */ 204 #define DMA_REQUEST_TIM2_CH3 28U /*!< DMAMUX TIM2 CH3 request */ 205 #define DMA_REQUEST_TIM2_CH4 29U /*!< DMAMUX TIM2 CH4 request */ 206 #define DMA_REQUEST_TIM2_TRIG 30U /*!< DMAMUX TIM2 TRIG request */ 207 #define DMA_REQUEST_TIM2_UP 31U /*!< DMAMUX TIM2 UP request */ 208 #endif /* TIM2 */ 209 #define DMA_REQUEST_TIM3_CH1 32U /*!< DMAMUX TIM3 CH1 request */ 210 #define DMA_REQUEST_TIM3_CH2 33U /*!< DMAMUX TIM3 CH2 request */ 211 #define DMA_REQUEST_TIM3_CH3 34U /*!< DMAMUX TIM3 CH3 request */ 212 #define DMA_REQUEST_TIM3_CH4 35U /*!< DMAMUX TIM3 CH4 request */ 213 #define DMA_REQUEST_TIM3_TRIG 36U /*!< DMAMUX TIM3 TRIG request */ 214 #define DMA_REQUEST_TIM3_UP 37U /*!< DMAMUX TIM3 UP request */ 215 #define DMA_REQUEST_TIM16_CH1 44U /*!< DMAMUX TIM16 CH1 request */ 216 #define DMA_REQUEST_TIM16_TRIG_COM 45U /*!< DMAMUX TIM16 TRIG COM request */ 217 #define DMA_REQUEST_TIM16_UP 46U /*!< DMAMUX TIM16 UP request */ 218 #define DMA_REQUEST_TIM17_CH1 47U /*!< DMAMUX TIM17 CH2 request */ 219 #define DMA_REQUEST_TIM17_TRIG_COM 48U /*!< DMAMUX TIM17 TRIG COM request */ 220 #define DMA_REQUEST_TIM17_UP 49U /*!< DMAMUX TIM17 UP request */ 221 #define DMA_REQUEST_USART1_RX 50U /*!< DMAMUX USART1 RX request */ 222 #define DMA_REQUEST_USART1_TX 51U /*!< DMAMUX USART1 TX request */ 223 #define DMA_REQUEST_USART2_RX 52U /*!< DMAMUX USART2 RX request */ 224 #define DMA_REQUEST_USART2_TX 53U /*!< DMAMUX USART2 TX request */ 225 /** 226 * @} 227 */ 228 229 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 230 * @{ 231 */ 232 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 233 #define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ 234 #define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ 235 236 /** 237 * @} 238 */ 239 240 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 241 * @{ 242 */ 243 #define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */ 244 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ 245 /** 246 * @} 247 */ 248 249 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 250 * @{ 251 */ 252 #define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */ 253 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ 254 /** 255 * @} 256 */ 257 258 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 259 * @{ 260 */ 261 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ 262 #define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ 263 #define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ 264 /** 265 * @} 266 */ 267 268 /** @defgroup DMA_Memory_data_size DMA Memory data size 269 * @{ 270 */ 271 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ 272 #define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ 273 #define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ 274 /** 275 * @} 276 */ 277 278 /** @defgroup DMA_mode DMA mode 279 * @{ 280 */ 281 #define DMA_NORMAL 0x00000000U /*!< Normal mode */ 282 #define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */ 283 /** 284 * @} 285 */ 286 287 /** @defgroup DMA_Priority_level DMA Priority level 288 * @{ 289 */ 290 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ 291 #define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ 292 #define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ 293 #define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */ 294 /** 295 * @} 296 */ 297 298 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 299 * @{ 300 */ 301 #define DMA_IT_TC DMA_CCR_TCIE 302 #define DMA_IT_HT DMA_CCR_HTIE 303 #define DMA_IT_TE DMA_CCR_TEIE 304 /** 305 * @} 306 */ 307 308 /** @defgroup DMA_flag_definitions DMA flag definitions 309 * @{ 310 */ 311 312 #define DMA_FLAG_GI1 DMA_ISR_GIF1 313 #define DMA_FLAG_TC1 DMA_ISR_TCIF1 314 #define DMA_FLAG_HT1 DMA_ISR_HTIF1 315 #define DMA_FLAG_TE1 DMA_ISR_TEIF1 316 #define DMA_FLAG_GI2 DMA_ISR_GIF2 317 #define DMA_FLAG_TC2 DMA_ISR_TCIF2 318 #define DMA_FLAG_HT2 DMA_ISR_HTIF2 319 #define DMA_FLAG_TE2 DMA_ISR_TEIF2 320 #define DMA_FLAG_GI3 DMA_ISR_GIF3 321 #define DMA_FLAG_TC3 DMA_ISR_TCIF3 322 #define DMA_FLAG_HT3 DMA_ISR_HTIF3 323 #define DMA_FLAG_TE3 DMA_ISR_TEIF3 324 #if defined(DMA1_Channel4) 325 #define DMA_FLAG_GI4 DMA_ISR_GIF4 326 #define DMA_FLAG_TC4 DMA_ISR_TCIF4 327 #define DMA_FLAG_HT4 DMA_ISR_HTIF4 328 #define DMA_FLAG_TE4 DMA_ISR_TEIF4 329 #endif /* DMA1_Channel4 */ 330 #if defined(DMA1_Channel5) 331 #define DMA_FLAG_GI5 DMA_ISR_GIF5 332 #define DMA_FLAG_TC5 DMA_ISR_TCIF5 333 #define DMA_FLAG_HT5 DMA_ISR_HTIF5 334 #define DMA_FLAG_TE5 DMA_ISR_TEIF5 335 #endif /* DMA1_Channel5 */ 336 337 /** 338 * @} 339 */ 340 341 /** 342 * @} 343 */ 344 345 /* Exported macros -----------------------------------------------------------*/ 346 /** @defgroup DMA_Exported_Macros DMA Exported Macros 347 * @{ 348 */ 349 350 /** @brief Reset DMA handle state 351 * @param __HANDLE__ DMA handle 352 * @retval None 353 */ 354 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 355 356 /** 357 * @brief Enable the specified DMA Channel. 358 * @param __HANDLE__ DMA handle 359 * @retval None 360 */ 361 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 362 363 /** 364 * @brief Disable the specified DMA Channel. 365 * @param __HANDLE__ DMA handle 366 * @retval None 367 */ 368 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) 369 370 /* Interrupt & Flag management */ 371 372 /** 373 * @brief Return the current DMA Channel transfer complete flag. 374 * @param __HANDLE__ DMA handle 375 * @retval The specified transfer complete flag index. 376 */ 377 #if defined(DMA1_Channel5) 378 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 379 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 380 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 381 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 382 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 383 DMA_FLAG_TC5) 384 #else 385 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 386 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 387 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 388 DMA_FLAG_TC3) 389 #endif /* DMA1_Channel5 */ 390 391 /** 392 * @brief Return the current DMA Channel half transfer complete flag. 393 * @param __HANDLE__ DMA handle 394 * @retval The specified half transfer complete flag index. 395 */ 396 #if defined(DMA1_Channel5) 397 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 398 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 399 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 400 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 401 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 402 DMA_FLAG_HT5) 403 #else 404 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 405 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 406 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 407 DMA_FLAG_HT3) 408 #endif /* DMA1_Channel5 */ 409 410 /** 411 * @brief Return the current DMA Channel transfer error flag. 412 * @param __HANDLE__ DMA handle 413 * @retval The specified transfer error flag index. 414 */ 415 #if defined(DMA1_Channel5) 416 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 417 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 418 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 419 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 420 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 421 DMA_FLAG_TE5) 422 #else 423 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 424 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 425 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 426 DMA_FLAG_TE3) 427 #endif /* DMA1_Channel5 */ 428 429 /** 430 * @brief Return the current DMA Channel Global interrupt flag. 431 * @param __HANDLE__ DMA handle 432 * @retval The specified transfer error flag index. 433 */ 434 #if defined(DMA1_Channel5) 435 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 436 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\ 437 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\ 438 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\ 439 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\ 440 DMA_FLAG_GI5) 441 #else 442 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 443 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\ 444 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\ 445 DMA_FLAG_GI3) 446 #endif /* DMA1_Channel5 */ 447 448 /** 449 * @brief Get the DMA Channel pending flags. 450 * @param __HANDLE__ DMA handle 451 * @param __FLAG__ Get the specified flag. 452 * This parameter can be any combination of the following values: 453 * @arg DMA_FLAG_TCIFx: Transfer complete flag 454 * @arg DMA_FLAG_HTIFx: Half transfer complete flag 455 * @arg DMA_FLAG_TEIFx: Transfer error flag 456 * @arg DMA_FLAG_GIFx: Global interrupt flag 457 * Where x can be 1_5 to select the DMA Channel flag. 458 * @retval The state of FLAG (SET or RESET). 459 */ 460 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) 461 462 /** 463 * @brief Clear the DMA Channel pending flags. 464 * @param __HANDLE__ DMA handle 465 * @param __FLAG__ specifies the flag to clear. 466 * This parameter can be any combination of the following values: 467 * @arg DMA_FLAG_TCIFx: Transfer complete flag 468 * @arg DMA_FLAG_HTIFx: Half transfer complete flag 469 * @arg DMA_FLAG_TEIFx: Transfer error flag 470 * @arg DMA_FLAG_GIFx: Global interrupt flag 471 * Where x can be 1_5 to select the DMA Channel flag. 472 * @retval None 473 */ 474 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR |= (__FLAG__)) 475 476 /** 477 * @brief Enable the specified DMA Channel interrupts. 478 * @param __HANDLE__ DMA handle 479 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 480 * This parameter can be any combination of the following values: 481 * @arg DMA_IT_TC: Transfer complete interrupt mask 482 * @arg DMA_IT_HT: Half transfer complete interrupt mask 483 * @arg DMA_IT_TE: Transfer error interrupt mask 484 * @retval None 485 */ 486 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 487 488 /** 489 * @brief Disable the specified DMA Channel interrupts. 490 * @param __HANDLE__ DMA handle 491 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 492 * This parameter can be any combination of the following values: 493 * @arg DMA_IT_TC: Transfer complete interrupt mask 494 * @arg DMA_IT_HT: Half transfer complete interrupt mask 495 * @arg DMA_IT_TE: Transfer error interrupt mask 496 * @retval None 497 */ 498 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 499 500 /** 501 * @brief Check whether the specified DMA Channel interrupt is enabled or disabled. 502 * @param __HANDLE__ DMA handle 503 * @param __INTERRUPT__ specifies the DMA interrupt source to check. 504 * This parameter can be one of the following values: 505 * @arg DMA_IT_TC: Transfer complete interrupt mask 506 * @arg DMA_IT_HT: Half transfer complete interrupt mask 507 * @arg DMA_IT_TE: Transfer error interrupt mask 508 * @retval The state of DMA_IT (SET or RESET). 509 */ 510 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 511 512 /** 513 * @brief Returns the number of remaining data units in the current DMA Channel transfer. 514 * @param __HANDLE__ DMA handle 515 * @retval The number of remaining data units in the current DMA Channel transfer. 516 */ 517 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) 518 519 /** 520 * @} 521 */ 522 523 /* Include DMA HAL Extension module */ 524 #include "stm32c0xx_hal_dma_ex.h" 525 526 /* Exported functions --------------------------------------------------------*/ 527 528 /** @addtogroup DMA_Exported_Functions 529 * @{ 530 */ 531 532 /** @addtogroup DMA_Exported_Functions_Group1 533 * @{ 534 */ 535 /* Initialization and de-initialization functions *****************************/ 536 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 537 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); 538 /** 539 * @} 540 */ 541 542 /** @addtogroup DMA_Exported_Functions_Group2 543 * @{ 544 */ 545 /* IO operation functions *****************************************************/ 546 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 547 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, 548 uint32_t DataLength); 549 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 550 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 551 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, 552 uint32_t Timeout); 553 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 554 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, 555 void (* pCallback)(DMA_HandleTypeDef *_hdma)); 556 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 557 558 /** 559 * @} 560 */ 561 562 /** @addtogroup DMA_Exported_Functions_Group3 563 * @{ 564 */ 565 /* Peripheral State and Error functions ***************************************/ 566 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 567 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 568 /** 569 * @} 570 */ 571 572 /** 573 * @} 574 */ 575 576 /* Private macros ------------------------------------------------------------*/ 577 /** @defgroup DMA_Private_Macros DMA Private Macros 578 * @{ 579 */ 580 581 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 582 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 583 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 584 585 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) 586 587 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 588 ((STATE) == DMA_PINC_DISABLE)) 589 590 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 591 ((STATE) == DMA_MINC_DISABLE)) 592 593 #define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_USART2_TX) 594 595 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 596 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 597 ((SIZE) == DMA_PDATAALIGN_WORD)) 598 599 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 600 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 601 ((SIZE) == DMA_MDATAALIGN_WORD )) 602 603 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 604 ((MODE) == DMA_CIRCULAR)) 605 606 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 607 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 608 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 609 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 610 611 /** 612 * @} 613 */ 614 615 /* Private functions ---------------------------------------------------------*/ 616 617 /** 618 * @} 619 */ 620 621 /** 622 * @} 623 */ 624 625 #ifdef __cplusplus 626 } 627 #endif 628 629 #endif /* STM32C0xx_HAL_DMA_H */ 630
