1 /** 2 ****************************************************************************** 3 * @file stm32c0xx_hal_adc.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32C0xx_HAL_ADC_H 21 #define STM32C0xx_HAL_ADC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32c0xx_hal_def.h" 29 30 /* Include low level driver */ 31 #include "stm32c0xx_ll_adc.h" 32 33 /** @addtogroup STM32C0xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup ADC 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup ADC_Exported_Types ADC Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief ADC group regular oversampling structure definition 48 */ 49 typedef struct 50 { 51 uint32_t Ratio; /*!< Configures the oversampling ratio. 52 This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ 53 54 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 55 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 56 57 uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. 58 This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ 59 60 } ADC_OversamplingTypeDef; 61 62 /** 63 * @brief Structure definition of ADC instance and ADC group regular. 64 * @note Parameters of this structure are shared within 2 scopes: 65 * - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC 66 * groups regular and injected): ClockPrescaler, Resolution, DataAlign, 67 * ScanConvMode, EOCSelection, LowPowerAutoWait. 68 * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, 69 * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling. 70 * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. 71 * ADC state can be either: 72 * - For all parameters: ADC disabled 73 * - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on 74 * group regular. 75 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 76 * without error reporting (as it can be the expected behavior in case of intended action to update another 77 * parameter (which fulfills the ADC state condition) on the fly). 78 */ 79 typedef struct 80 { 81 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous 82 clock derived from system clock or PLL (Refer to reference manual for list of 83 clocks available)) and clock prescaler. 84 This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. 85 Note: The ADC clock configuration is common to all ADC instances. 86 Note: In case of synchronous clock mode based on HCLK/1, the configuration must 87 be enabled only if the system clock has a 50% duty clock cycle (APB 88 prescaler configured inside RCC must be bypassed and PCLK clock must have 89 50% duty cycle). Refer to reference manual for details. 90 Note: In case of usage of asynchronous clock, the selected clock must be 91 preliminarily enabled at RCC top level. 92 Note: This parameter can be modified only if all ADC instances are disabled. */ 93 94 uint32_t Resolution; /*!< Configure the ADC resolution. 95 This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ 96 97 uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). 98 Refer to reference manual for alignments formats versus resolutions. 99 This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */ 100 101 uint32_t ScanConvMode; /*!< Configure the sequencer of ADC group regular. 102 On this STM32 series, ADC group regular sequencer both modes "fully configurable" 103 or "not fully configurable" are available: 104 - sequencer configured to fully configurable: 105 sequencer length and each rank affectation to a channel are configurable. 106 - Sequence length: Set number of ranks in the scan sequence. 107 - Sequence direction: Unless specified in parameters, sequencer 108 scan direction is forward (from rank 1 to rank n). 109 - sequencer configured to not fully configurable: 110 sequencer length and each rank affectation to a channel are fixed by channel 111 HW number. 112 - Sequence length: Number of ranks in the scan sequence is 113 defined by number of channels set in the sequence, 114 rank of each channel is fixed by channel HW number. 115 (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 116 - Sequence direction: Unless specified in parameters, sequencer 117 scan direction is forward (from lowest channel number to 118 highest channel number). 119 This parameter can be associated to parameter 'DiscontinuousConvMode' to have 120 main sequence subdivided in successive parts. Sequencer is automatically enabled 121 if several channels are set (sequencer cannot be disabled, as it can be the case 122 on other STM32 devices): 123 If only 1 channel is set: Conversion is performed in single mode. 124 If several channels are set: Conversions are performed in sequence mode. 125 This parameter can be a value of @ref ADC_Scan_mode */ 126 127 uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and 128 interruption: end of unitary conversion or end of sequence conversions. 129 This parameter can be a value of @ref ADC_EOCSelection. */ 130 131 FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the 132 previous conversion (for ADC group regular) has been retrieved by user software, 133 using function HAL_ADC_GetValue(). 134 This feature automatically adapts the frequency of ADC conversions triggers to 135 the speed of the system that reads the data. Moreover, this avoids risk of 136 overrun for low frequency applications. 137 This parameter can be set to ENABLE or DISABLE. 138 Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), 139 HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC 140 flag (by CPU to free the IRQ pending event or by DMA). 141 Auto wait will work but fort a very short time, discarding its intended 142 benefit (except specific case of high load of CPU or DMA transfers which 143 can justify usage of auto wait). 144 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, 145 when ADC conversion data is needed: 146 use HAL_ADC_PollForConversion() to ensure that conversion is completed and 147 HAL_ADC_GetValue() to retrieve conversion result and trig another 148 conversion start. */ 149 150 FunctionalState LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a 151 conversion and automatically wakes-up when a new conversion is triggered 152 (with startup time between trigger and start of sampling). 153 This feature can be combined with automatic wait mode 154 (parameter 'LowPowerAutoWait'). 155 This parameter can be set to ENABLE or DISABLE. */ 156 157 FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) 158 or continuous mode for ADC group regular, after the first ADC conversion 159 start trigger occurred (software start or external trigger). This parameter 160 can be set to ENABLE or DISABLE. */ 161 162 uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group 163 sequencer. 164 This parameter is dependent on ScanConvMode: 165 - sequencer configured to fully configurable: 166 Number of ranks in the scan sequence is configurable using this parameter. 167 Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to 168 parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'. 169 Afterwards, when all needed sequencer ranks are set, parameter 170 'NbrOfConversion' can be updated without modifying configuration of 171 sequencer ranks (sequencer ranks above 'NbrOfConversion' are discarded). 172 - sequencer configured to not fully configurable: 173 Number of ranks in the scan sequence is defined by number of channels set in 174 the sequence. This parameter is discarded. 175 This parameter must be a number between Min_Data = 1 and Max_Data = 8. 176 Note: This parameter must be modified when no conversion is on going on regular 177 group (ADC disabled, or ADC enabled without continuous mode or external 178 trigger that could launch a conversion). */ 179 180 FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed 181 in Complete-sequence/Discontinuous-sequence (main sequence subdivided in 182 successive parts). 183 Discontinuous mode is used only if sequencer is enabled (parameter 184 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 185 Discontinuous mode can be enabled only if continuous mode is disabled. 186 If continuous mode is enabled, this parameter setting is discarded. 187 This parameter can be set to ENABLE or DISABLE. 188 Note: On this STM32 series, ADC group regular number of discontinuous 189 ranks increment is fixed to one-by-one. */ 190 191 uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion 192 start. 193 If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger 194 is used instead. 195 This parameter can be a value of @ref ADC_regular_external_trigger_source. 196 Caution: external trigger source is common to all ADC instances. */ 197 198 uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start 199 If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. 200 This parameter can be a value of @ref ADC_regular_external_trigger_edge */ 201 202 FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA 203 transfer stops when number of conversions is reached) or in continuous 204 mode (DMA transfer unlimited, whatever number of conversions). 205 This parameter can be set to ENABLE or DISABLE. 206 Note: In continuous mode, DMA must be configured in circular mode. 207 Otherwise an overrun will be triggered when DMA buffer maximum 208 pointer is reached. */ 209 210 uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). 211 This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. 212 Note: In case of overrun set to data preserved and usage with programming model 213 with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of 214 conversion flags, this induces the release of the preserved data. If 215 needed, this data can be saved in function HAL_ADC_ConvCpltCallback(), 216 placed in user program code (called before end of conversion flags clear) 217 Note: Error reporting with respect to the conversion mode: 218 - Usage with ADC conversion by polling for event or interruption: Error is 219 reported only if overrun is set to data preserved. If overrun is set to 220 data overwritten, user can willingly not read all the converted data, 221 this is not considered as an erroneous case. 222 - Usage with ADC conversion by DMA: Error is reported whatever overrun 223 setting (DMA is expected to process all data from data register). */ 224 225 uint32_t SamplingTimeCommon1; /*!< Set sampling time common to a group of channels. 226 Unit: ADC clock cycles 227 Conversion time is the addition of sampling time and processing time 228 (12.5 ADC clock cycles at ADC resolution 12 bits, 229 10.5 cycles at 10 bits, 230 8.5 cycles at 8 bits, 231 6.5 cycles at 6 bits). 232 Note: On this STM32 family, two different sampling time settings are available, 233 each channel can use one of these two settings. On some other STM32 devices 234 this parameter in channel wise and is located into ADC channel 235 initialization structure. 236 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME 237 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor) 238 sampling time constraints must be respected (sampling time can be adjusted 239 in function of ADC clock frequency and sampling time setting) 240 Refer to device datasheet for timings values, parameters TS_vrefint, 241 TS_vbat, TS_temp (values rough order: few tens of microseconds). */ 242 243 uint32_t SamplingTimeCommon2; /*!< Set sampling time common to a group of channels, second common setting possible. 244 Unit: ADC clock cycles 245 Conversion time is the addition of sampling time and processing time 246 (12.5 ADC clock cycles at ADC resolution 12 bits, 247 10.5 cycles at 10 bits, 248 8.5 cycles at 8 bits, 249 6.5 cycles at 6 bits). 250 Note: On this STM32 family, two different sampling time settings are available, 251 each channel can use one of these two settings. On some other STM32 devices 252 this parameter in channel wise and is located into ADC channel 253 initialization structure. 254 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME 255 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor) 256 sampling time constraints must be respected (sampling time can be adjusted 257 in function of ADC clock frequency and sampling time setting) 258 Refer to device datasheet for timings values, parameters TS_vrefint, 259 TS_vbat, TS_temp (values rough order: few tens of microseconds). */ 260 261 FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. 262 This parameter can be set to ENABLE or DISABLE. 263 Note: This parameter can be modified only if there is no conversion is 264 ongoing on ADC group regular. */ 265 266 ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. 267 Caution: this setting overwrites the previous oversampling configuration 268 if oversampling is already enabled. */ 269 270 uint32_t TriggerFrequencyMode; /*!< Set ADC trigger frequency mode. 271 This parameter can be a value of @ref ADC_HAL_EC_REG_TRIGGER_FREQ. 272 Note: ADC trigger frequency mode must be set to low frequency when 273 a duration is exceeded before ADC conversion start trigger event 274 (between ADC enable and ADC conversion start trigger event 275 or between two ADC conversion start trigger event). 276 Duration value: Refer to device datasheet, parameter "tIdle". 277 Note: When ADC trigger frequency mode is set to low frequency, 278 some rearm cycles are inserted before performing ADC conversion 279 start, inducing a delay of 2 ADC clock cycles. */ 280 281 } ADC_InitTypeDef; 282 283 /** 284 * @brief Structure definition of ADC channel for regular group 285 * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. 286 * ADC state can be either: 287 * - For all parameters: ADC disabled or enabled without conversion on going on regular group. 288 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 289 * without error reporting (as it can be the expected behavior in case of intended action to update another 290 * parameter (which fulfills the ADC state condition) on the fly). 291 */ 292 typedef struct 293 { 294 uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. 295 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 296 Note: Depending on devices and ADC instances, some channels may not be available 297 on device package pins. Refer to device datasheet for channels 298 availability. */ 299 300 uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer and specify its 301 conversion rank. 302 This parameter is dependent on ScanConvMode: 303 - sequencer configured to fully configurable: 304 Channels ordering into each rank of scan sequence: 305 whatever channel can be placed into whatever rank. 306 - sequencer configured to not fully configurable: 307 rank of each channel is fixed by channel HW number. 308 (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 309 Despite the channel rank is fixed, this parameter allow an additional 310 possibility: to remove the selected rank (selected channel) from sequencer. 311 This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS */ 312 313 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 314 Unit: ADC clock cycles 315 Conversion time is the addition of sampling time and processing time 316 (12.5 ADC clock cycles at ADC resolution 12 bits, 317 10.5 cycles at 10 bits, 318 8.5 cycles at 8 bits, 319 6.5 cycles at 6 bits). 320 This parameter can be a value of @ref ADC_HAL_EC_SAMPLINGTIME_COMMON 321 Note: On this STM32 family, two different sampling time settings are available 322 (refer to parameters "SamplingTimeCommon1" and "SamplingTimeCommon2"), 323 each channel can use one of these two settings. 324 325 Note: In case of usage of internal measurement channels (VrefInt/Vbat/ 326 TempSensor), sampling time constraints must be respected (sampling time 327 can be adjusted in function of ADC clock frequency and sampling time 328 setting) 329 Refer to device datasheet for timings values. */ 330 331 } ADC_ChannelConfTypeDef; 332 333 /** 334 * @brief Structure definition of ADC analog watchdog 335 * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. 336 * ADC state can be either: 337 * - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion 338 on going on ADC groups regular. 339 * - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular. 340 */ 341 typedef struct 342 { 343 uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. 344 For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels 345 by setting parameter 'WatchdogMode') 346 For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls 347 of 'HAL_ADC_AnalogWDGConfig()' for each channel) 348 This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ 349 350 uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. 351 For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all 352 channels, ADC group regular. 353 For Analog Watchdog 2 and 3: Several channels can be monitored by applying 354 successively the AWD init structure. 355 This parameter can be a value of @ref ADC_analog_watchdog_mode. */ 356 357 uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. 358 For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' 359 is configured on single channel (only 1 channel can be 360 monitored). 361 For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, 362 call successively the function HAL_ADC_AnalogWDGConfig() 363 for each channel to be added (or removed with value 364 'ADC_ANALOGWATCHDOG_NONE'). 365 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ 366 367 FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. 368 This parameter can be set to ENABLE or DISABLE */ 369 370 uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. 371 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a 372 number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F 373 respectively. 374 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC 375 resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 376 LSB are ignored. 377 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 378 impacted: the comparison of analog watchdog thresholds is done on 379 oversampling final computation (after ratio and shift application): 380 ADC data register bitfield [15:4] (12 most significant bits). */ 381 382 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. 383 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a 384 number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F 385 respectively. 386 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC 387 resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 388 LSB are ignored. 389 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 390 impacted: the comparison of analog watchdog thresholds is done on 391 oversampling final computation (after ratio and shift application): 392 ADC data register bitfield [15:4] (12 most significant bits).*/ 393 } ADC_AnalogWDGConfTypeDef; 394 395 /** @defgroup ADC_States ADC States 396 * @{ 397 */ 398 399 /** 400 * @brief HAL ADC state machine: ADC states definition (bitfields) 401 * @note ADC state machine is managed by bitfields, state must be compared 402 * with bit by bit. 403 * For example: 404 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " 405 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " 406 */ 407 /* States of ADC global scope */ 408 #define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ 409 #define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ 410 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy from internal process (ex : calibration, ...) */ 411 #define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ 412 413 /* States of ADC errors */ 414 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ 415 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ 416 #define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ 417 418 /* States of ADC group regular */ 419 #define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur 420 (either by continuous mode, external trigger, low power 421 auto power-on (if feature available), multimode ADC master 422 control (if feature available)) */ 423 #define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ 424 #define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ 425 #define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag 426 raised */ 427 428 /* States of ADC group injected */ 429 #define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< Not available on this STM32 series: A conversion on group 430 injected is ongoing or can occur (either by auto-injection 431 mode, external trigger, low power auto power-on (if feature 432 available), multimode ADC master control (if feature 433 available))*/ 434 #define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Not available on this STM32 series: Conversion data 435 available on group injected */ 436 #define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Not available on this STM32 series: Injected queue overflow 437 occurrence */ 438 439 /* States of ADC analog watchdogs */ 440 #define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ 441 #define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Not available on this STM32 series: Out-of-window occurrence 442 of ADC analog watchdog 2 */ 443 #define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Not available on this STM32 series: Out-of-window occurrence 444 of ADC analog watchdog 3 */ 445 446 /* States of ADC multi-mode */ 447 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< Not available on this STM32 series: ADC in multimode slave 448 state, controlled by another ADC master (when feature 449 available) */ 450 451 452 /** 453 * @} 454 */ 455 456 /** 457 * @brief ADC handle Structure definition 458 */ 459 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 460 typedef struct __ADC_HandleTypeDef 461 #else 462 typedef struct 463 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 464 { 465 ADC_TypeDef *Instance; /*!< Register base address */ 466 ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ 467 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 468 HAL_LockTypeDef Lock; /*!< ADC locking object */ 469 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 470 __IO uint32_t ErrorCode; /*!< ADC Error code */ 471 472 uint32_t ADCGroupRegularSequencerRanks; /*!< ADC group regular sequencer memorization of ranks 473 setting, used in mode "fully configurable" (refer to 474 parameter 'ScanConvMode') */ 475 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 476 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ 477 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer 478 callback */ 479 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ 480 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ 481 void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ 482 void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ 483 void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ 484 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ 485 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ 486 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 487 } ADC_HandleTypeDef; 488 489 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 490 /** 491 * @brief HAL ADC Callback ID enumeration definition 492 */ 493 typedef enum 494 { 495 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ 496 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ 497 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ 498 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ 499 HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ 500 HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ 501 HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ 502 HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ 503 HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ 504 } HAL_ADC_CallbackIDTypeDef; 505 506 /** 507 * @brief HAL ADC Callback pointer definition 508 */ 509 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ 510 511 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 512 513 /** 514 * @} 515 */ 516 517 518 /* Exported constants --------------------------------------------------------*/ 519 520 /** @defgroup ADC_Exported_Constants ADC Exported Constants 521 * @{ 522 */ 523 524 /** @defgroup ADC_Error_Code ADC Error Code 525 * @{ 526 */ 527 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ 528 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, 529 enable/disable, erroneous state, ...) */ 530 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ 531 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ 532 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 533 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 534 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 535 /** 536 * @} 537 */ 538 539 /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source 540 * @{ 541 */ 542 #define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock from AHB clock 543 without prescaler. This configuration must be enabled only if PCLK has 544 a 50% duty clock cycle (APB prescaler configured inside the RCC must 545 be bypassed and the system clock must by 50% duty cycle) */ 546 #define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock from AHB clock 547 with prescaler division by 2 */ 548 #define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock from AHB clock 549 with prescaler division by 4 */ 550 551 #define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without 552 prescaler */ 553 #define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler 554 division by 2 */ 555 #define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler 556 division by 4 */ 557 #define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler 558 division by 6 */ 559 #define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler 560 division by 8 */ 561 #define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler 562 division by 10 */ 563 #define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler 564 division by 12 */ 565 #define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler 566 division by 16 */ 567 #define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler 568 division by 32 */ 569 #define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler 570 division by 64 */ 571 #define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler 572 division by 128 */ 573 #define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler 574 division by 256 */ 575 /** 576 * @} 577 */ 578 579 /** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution 580 * @{ 581 */ 582 #define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ 583 #define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ 584 #define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ 585 #define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */ 586 /** 587 * @} 588 */ 589 590 /** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment 591 * @{ 592 */ 593 #define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned 594 (alignment on data register LSB bit 0)*/ 595 #define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned 596 (alignment on data register MSB bit 15)*/ 597 /** 598 * @} 599 */ 600 601 /** @defgroup ADC_Scan_mode ADC sequencer scan mode 602 * @{ 603 */ 604 /* Note: On this STM32 family, ADC group regular sequencer both modes */ 605 /* "fully configurable" or "not fully configurable" are */ 606 /* available. */ 607 /* Scan mode values must be compatible with other STM32 devices having */ 608 /* a configurable sequencer. */ 609 /* Scan direction setting values are defined by taking in account */ 610 /* already defined values for other STM32 devices: */ 611 /* ADC_SCAN_DISABLE (0x00000000UL) */ 612 /* ADC_SCAN_ENABLE (0x00000001UL) */ 613 /* Sequencer fully configurable with only rank 1 enabled is considered */ 614 /* as default setting equivalent to scan enable. */ 615 /* In case of migration from another STM32 device, the user will be */ 616 /* warned of change of setting choices with assert check. */ 617 /* Sequencer set to fully configurable */ 618 #define ADC_SCAN_DISABLE (0x00000000UL) /*!< Sequencer set to fully configurable: 619 only the rank 1 is enabled (no scan sequence on several ranks) */ 620 #define ADC_SCAN_ENABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer set to fully configurable: 621 sequencer length and each rank affectation to a channel are configurable. */ 622 623 /* Sequencer set to not fully configurable */ 624 #define ADC_SCAN_SEQ_FIXED (ADC_SCAN_SEQ_FIXED_INT) /*!< Sequencer set to not fully configurable: 625 sequencer length and each rank affectation to a channel are fixed by 626 channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 627 Scan direction forward: from channel 0 to channel 18 */ 628 #define ADC_SCAN_SEQ_FIXED_BACKWARD (ADC_SCAN_SEQ_FIXED_INT \ 629 | ADC_CFGR1_SCANDIR) /*!< Sequencer set to not fully configurable: 630 sequencer length and each rank affectation to a channel are fixed by 631 channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 632 Scan direction backward: from channel 18 to channel 0 */ 633 634 #define ADC_SCAN_DIRECTION_FORWARD (ADC_SCAN_SEQ_FIXED) /* For compatibility with other STM32 series */ 635 #define ADC_SCAN_DIRECTION_BACKWARD (ADC_SCAN_SEQ_FIXED_BACKWARD) /* For compatibility with other STM32 series */ 636 /** 637 * @} 638 */ 639 640 /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source 641 * @{ 642 */ 643 /* ADC group regular trigger sources for all ADC instances */ 644 #define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion 645 trigger internal: SW start. */ 646 #define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion 647 trigger from external peripheral: TIM1 TRGO. 648 Trigger edge set to rising edge (default setting). */ 649 #define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< ADC group regular conversion 650 trigger from external peripheral: TIM1 channel 4 event 651 (capture compare: input capture or output capture). 652 Trigger edge set to rising edge (default setting). */ 653 #if defined(TIM2) 654 #define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion 655 trigger from external peripheral: TIM2 TRGO. 656 Trigger edge set to rising edge (default setting). */ 657 #endif /* TIM2 */ 658 #define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion 659 trigger from external peripheral: TIM3 TRGO. 660 Trigger edge set to rising edge (default setting). */ 661 #if defined(TIM4) 662 #define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion 663 trigger from external peripheral: TIM4 TRGO. 664 Trigger edge set to rising edge (default setting). */ 665 #endif /* TIM4 */ 666 #if defined(TIM6) 667 #define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion 668 trigger from external peripheral: TIM6 TRGO. 669 Trigger edge set to rising edge (default setting). */ 670 #endif /* TIM6 */ 671 #if defined(TIM15) 672 #define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion 673 trigger from external peripheral: TIM15 TRGO. 674 Trigger edge set to rising edge (default setting). */ 675 #endif /* TIM15 */ 676 #define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion 677 trigger from external peripheral: external interrupt line 11. 678 Trigger edge set to rising edge (default setting). */ 679 /** 680 * @} 681 */ 682 683 /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) 684 * @{ 685 */ 686 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware 687 trigger detection disabled */ 688 #define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion 689 trigger polarity set to rising edge */ 690 #define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion 691 trigger polarity set to falling edge */ 692 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion 693 trigger polarity set to both rising and falling edges */ 694 /** 695 * @} 696 */ 697 698 /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions 699 * @{ 700 */ 701 #define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ 702 #define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ 703 /** 704 * @} 705 */ 706 707 /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data 708 * @{ 709 */ 710 #define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case 711 of overrun: data preserved */ 712 #define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case 713 of overrun: data overwritten */ 714 /** 715 * @} 716 */ 717 718 /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks 719 * @{ 720 */ 721 #define ADC_RANK_CHANNEL_NUMBER (0x00000001U) /*!< Setting relevant if parameter "ScanConvMode" is set 722 to sequencer not fully configurable: Enable the rank of the selected 723 channels. Number of ranks in the sequence is defined by number of channels 724 enabled, rank of each channel is defined by channel number 725 (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */ 726 #define ADC_RANK_NONE (0x00000002U) /*!< Setting relevant if parameter "ScanConvMode" 727 is set to sequencer not fully configurable: Disable the selected rank 728 (selected channel) from sequencer */ 729 730 #define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ 731 #define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ 732 #define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ 733 #define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ 734 #define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ 735 #define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ 736 #define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ 737 #define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ 738 /** 739 * @} 740 */ 741 742 /** @defgroup ADC_HAL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels 743 * @{ 744 */ 745 #define ADC_SAMPLINGTIME_COMMON_1 (LL_ADC_SAMPLINGTIME_COMMON_1) /*!< Set sampling time common to a group of 746 channels: sampling time nb 1 */ 747 #define ADC_SAMPLINGTIME_COMMON_2 (LL_ADC_SAMPLINGTIME_COMMON_2) /*!< Set sampling time common to a group of 748 channels: sampling time nb 2 */ 749 /** 750 * @} 751 */ 752 753 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 754 * @{ 755 */ 756 #define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycle */ 757 #define ADC_SAMPLETIME_3CYCLES_5 (LL_ADC_SAMPLINGTIME_3CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles */ 758 #define ADC_SAMPLETIME_7CYCLES_5 (LL_ADC_SAMPLINGTIME_7CYCLES_5) /*!< Sampling time 7.5 ADC clock cycles */ 759 #define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ 760 #define ADC_SAMPLETIME_19CYCLES_5 (LL_ADC_SAMPLINGTIME_19CYCLES_5) /*!< Sampling time 19.5 ADC clock cycles */ 761 #define ADC_SAMPLETIME_39CYCLES_5 (LL_ADC_SAMPLINGTIME_39CYCLES_5) /*!< Sampling time 39.5 ADC clock cycles */ 762 #define ADC_SAMPLETIME_79CYCLES_5 (LL_ADC_SAMPLINGTIME_79CYCLES_5) /*!< Sampling time 79.5 ADC clock cycles */ 763 #define ADC_SAMPLETIME_160CYCLES_5 (LL_ADC_SAMPLINGTIME_160CYCLES_5) /*!< Sampling time 160.5 ADC clock cycles */ 764 /** 765 * @} 766 */ 767 768 /** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number 769 * @{ 770 */ 771 #define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< External channel (GPIO pin) ADCx_IN0 */ 772 #define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< External channel (GPIO pin) ADCx_IN1 */ 773 #define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< External channel (GPIO pin) ADCx_IN2 */ 774 #define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< External channel (GPIO pin) ADCx_IN3 */ 775 #define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< External channel (GPIO pin) ADCx_IN4 */ 776 #define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< External channel (GPIO pin) ADCx_IN5 */ 777 #define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< External channel (GPIO pin) ADCx_IN6 */ 778 #define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< External channel (GPIO pin) ADCx_IN7 */ 779 #define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< External channel (GPIO pin) ADCx_IN8 */ 780 #define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< External channel (GPIO pin) ADCx_IN9 */ 781 #define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< External channel (GPIO pin) ADCx_IN10 */ 782 #define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< External channel (GPIO pin) ADCx_IN11 */ 783 #define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< External channel (GPIO pin) ADCx_IN12 */ 784 #define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< External channel (GPIO pin) ADCx_IN13 */ 785 #define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< External channel (GPIO pin) ADCx_IN14 */ 786 #define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< External channel (GPIO pin) ADCx_IN15 */ 787 #define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< External channel (GPIO pin) ADCx_IN16 */ 788 #define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< External channel (GPIO pin) ADCx_IN17 */ 789 #define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< External channel (GPIO pin) ADCx_IN18 */ 790 #define ADC_CHANNEL_19 (LL_ADC_CHANNEL_19) /*!< External channel (GPIO pin) ADCx_IN19 */ 791 #define ADC_CHANNEL_20 (LL_ADC_CHANNEL_20) /*!< External channel (GPIO pin) ADCx_IN20 */ 792 #define ADC_CHANNEL_21 (LL_ADC_CHANNEL_21) /*!< External channel (GPIO pin) ADCx_IN21 */ 793 #define ADC_CHANNEL_22 (LL_ADC_CHANNEL_22) /*!< External channel (GPIO pin) ADCx_IN22 */ 794 #define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< Internal channel VrefInt: 795 Internal voltage reference. */ 796 #define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< Internal channel Temperature sensor. */ 797 #define ADC_CHANNEL_VDDA (LL_ADC_CHANNEL_VDDA) /*!< Internal channel VDDA */ 798 #define ADC_CHANNEL_VSSA (LL_ADC_CHANNEL_VSSA) /*!< Internal channel VSSA */ 799 /** 800 * @} 801 */ 802 803 /** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number 804 * @{ 805 */ 806 #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ 807 #define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ 808 #define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ 809 /** 810 * @} 811 */ 812 813 /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode 814 * @{ 815 */ 816 #define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< ADC AWD not selected */ 817 #define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN) /*!< ADC AWD applied to a regular 818 group single channel */ 819 #define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR1_AWD1EN) /*!< ADC AWD applied to regular 820 group all channels */ 821 /** 822 * @} 823 */ 824 825 /** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio 826 * @{ 827 */ 828 /** 829 * @note The oversampling ratio is the number of ADC conversions performed, sum of these conversions data is computed 830 * to result as the ADC oversampling conversion data (before potential shift) 831 */ 832 #define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio 2 */ 833 #define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio 4 */ 834 #define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio 8 */ 835 #define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio 16 */ 836 #define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio 32 */ 837 #define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio 64 */ 838 #define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio 128 */ 839 #define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio 256 */ 840 /** 841 * @} 842 */ 843 844 /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift 845 * @{ 846 */ 847 /** 848 * @note The sum of the ADC conversions data is divided by "Rightbitshift" number to result as the ADC oversampling 849 * conversion data) 850 */ 851 #define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift */ 852 #define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 ranks */ 853 #define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 ranks */ 854 #define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 ranks */ 855 #define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 ranks */ 856 #define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 ranks */ 857 #define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 ranks */ 858 #define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 ranks */ 859 #define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 ranks */ 860 /** 861 * @} 862 */ 863 864 /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode 865 * @{ 866 */ 867 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: 868 continuous mode (all conversions of OVS ratio are done from 1 trigger) */ 869 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: 870 discontinuous mode (each conversion of OVS ratio needs a trigger) */ 871 /** 872 * @} 873 */ 874 875 /** @defgroup ADC_HAL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode 876 * @{ 877 */ 878 879 /** 880 * @note ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion 881 * start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion 882 * start trigger event). 883 * Duration value: Refer to device datasheet, parameter "tIdle". 884 */ 885 #define ADC_TRIGGER_FREQ_HIGH (LL_ADC_TRIGGER_FREQ_HIGH) /*!< Trigger frequency mode set to high frequency. */ 886 #define ADC_TRIGGER_FREQ_LOW (LL_ADC_TRIGGER_FREQ_LOW) /*!< Trigger frequency mode set to low frequency. */ 887 /** 888 * @} 889 */ 890 891 /** @defgroup ADC_Event_type ADC Event type 892 * @{ 893 */ 894 /** 895 * @note Analog watchdog 1 is available on all stm32 series 896 * Analog watchdog 2 and 3 are not available on all series 897 */ 898 #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ 899 #define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog) */ 900 #define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog) */ 901 #define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog) */ 902 #define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ 903 /** 904 * @} 905 */ 906 #define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility 907 with other STM32 devices having only one analog watchdog */ 908 909 /** @defgroup ADC_interrupts_definition ADC interrupts definition 910 * @{ 911 */ 912 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ 913 #define ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC channel configuration ready interrupt source */ 914 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ 915 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ 916 #define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ 917 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ 918 #define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ 919 #define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog 920 watchdog) */ 921 #define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog 922 watchdog) */ 923 #define ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC End of Calibration interrupt source */ 924 /** 925 * @} 926 */ 927 928 /** @defgroup ADC_flags_definition ADC flags definition 929 * @{ 930 */ 931 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ 932 #define ADC_FLAG_CCRDY ADC_ISR_CCRDY /*!< ADC channel configuration ready flag */ 933 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ 934 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ 935 #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ 936 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ 937 #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag */ 938 #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag */ 939 #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag */ 940 #define ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC End of Calibration interrupt flag */ 941 /** 942 * @} 943 */ 944 945 /** 946 * @} 947 */ 948 949 /* Private macro -------------------------------------------------------------*/ 950 951 /** @defgroup ADC_Private_Macros ADC Private Macros 952 * @{ 953 */ 954 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 955 /* code of final user. */ 956 957 /** 958 * @brief Test if conversion trigger of regular group is software start 959 * or external trigger. 960 * @param __HANDLE__ ADC handle 961 * @retval SET (software start) or RESET (external trigger) 962 */ 963 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ 964 (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == 0UL) 965 966 /** 967 * @brief Return resolution bits in CFGR1 register RES[1:0] field. 968 * @param __HANDLE__ ADC handle 969 * @retval Value of bitfield RES in CFGR1 register. 970 */ 971 #define ADC_GET_RESOLUTION(__HANDLE__) \ 972 (LL_ADC_GetResolution((__HANDLE__)->Instance)) 973 974 /** 975 * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). 976 * @param __HANDLE__ ADC handle 977 * @retval None 978 */ 979 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 980 981 /** 982 * @brief Simultaneously clear and set specific bits of the handle State. 983 * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 984 * the first parameter is the ADC handle State, the second parameter is the 985 * bit field to clear, the third and last parameter is the bit field to set. 986 * @retval None 987 */ 988 #define ADC_STATE_CLR_SET MODIFY_REG 989 990 /** 991 * @brief Enable ADC discontinuous conversion mode for regular group 992 * @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode. 993 * @retval None 994 */ 995 #define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) \ 996 ((_REG_DISCONTINUOUS_MODE_) << 16U) 997 998 /** 999 * @brief Enable the ADC auto off mode. 1000 * @param _AUTOOFF_ Auto off bit enable or disable. 1001 * @retval None 1002 */ 1003 #define ADC_CFGR1_AUTOOFF(_AUTOOFF_) \ 1004 ((_AUTOOFF_) << 15U) 1005 1006 /** 1007 * @brief Enable the ADC auto delay mode. 1008 * @param _AUTOWAIT_ Auto delay bit enable or disable. 1009 * @retval None 1010 */ 1011 #define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) \ 1012 ((_AUTOWAIT_) << 14U) 1013 1014 /** 1015 * @brief Enable ADC continuous conversion mode. 1016 * @param _CONTINUOUS_MODE_ Continuous mode. 1017 * @retval None 1018 */ 1019 #define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) \ 1020 ((_CONTINUOUS_MODE_) << 13U) 1021 1022 /** 1023 * @brief Enable ADC overrun mode. 1024 * @param _OVERRUN_MODE_ Overrun mode. 1025 * @retval Overrun bit setting to be programmed into CFGR register 1026 */ 1027 /* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */ 1028 /* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */ 1029 /* as the default case to be compliant with other STM32 devices. */ 1030 #define ADC_CFGR1_OVERRUN(_OVERRUN_MODE_) \ 1031 ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \ 1032 )? (ADC_CFGR1_OVRMOD) : (0x00000000UL) \ 1033 ) 1034 1035 /** 1036 * @brief Set ADC scan mode with differentiation of sequencer setting 1037 * fixed or configurable 1038 * @param _SCAN_MODE_ Scan conversion mode. 1039 * @retval None 1040 */ 1041 /* Note: Scan mode set using this macro (instead of parameter direct set) */ 1042 /* due to different modes on other STM32 devices: */ 1043 /* if scan mode is disabled, sequencer is set to fully configurable */ 1044 /* with setting of only rank 1 enabled afterwards. */ 1045 #define ADC_SCAN_SEQ_MODE(_SCAN_MODE_) \ 1046 ( (((_SCAN_MODE_) & ADC_SCAN_SEQ_FIXED_INT) != 0UL \ 1047 )? \ 1048 ((_SCAN_MODE_) & (~ADC_SCAN_SEQ_FIXED_INT)) \ 1049 : \ 1050 (ADC_CFGR1_CHSELRMOD) \ 1051 ) 1052 1053 /** 1054 * @brief Enable the ADC DMA continuous request. 1055 * @param _DMACONTREQ_MODE_: DMA continuous request mode. 1056 * @retval None 1057 */ 1058 #define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) \ 1059 ((_DMACONTREQ_MODE_) << 1U) 1060 1061 /** 1062 * @brief Shift the AWD threshold in function of the selected ADC resolution. 1063 * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. 1064 * If resolution 12 bits, no shift. 1065 * If resolution 10 bits, shift of 2 ranks on the left. 1066 * If resolution 8 bits, shift of 4 ranks on the left. 1067 * If resolution 6 bits, shift of 6 ranks on the left. 1068 * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) 1069 * @param __HANDLE__ ADC handle 1070 * @param _Threshold_ Value to be shifted 1071 * @retval None 1072 */ 1073 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ 1074 ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2U)) 1075 1076 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) ||\ 1077 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) ||\ 1078 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ||\ 1079 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1 ) ||\ 1080 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) ||\ 1081 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) ||\ 1082 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) ||\ 1083 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) ||\ 1084 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) ||\ 1085 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) ||\ 1086 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) ||\ 1087 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) ||\ 1088 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) ||\ 1089 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) ||\ 1090 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256)) 1091 1092 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ 1093 ((RESOLUTION) == ADC_RESOLUTION_10B) || \ 1094 ((RESOLUTION) == ADC_RESOLUTION_8B) || \ 1095 ((RESOLUTION) == ADC_RESOLUTION_6B) ) 1096 1097 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ 1098 ((ALIGN) == ADC_DATAALIGN_LEFT) ) 1099 1100 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ 1101 ((SCAN_MODE) == ADC_SCAN_ENABLE) || \ 1102 ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED) || \ 1103 ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED_BACKWARD) ) 1104 1105 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 1106 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 1107 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 1108 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) 1109 1110 #if defined(TIM2) 1111 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 1112 ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC4) || \ 1113 ((REGTRIG) == ADC_EXTERNALTRIG_T2_TRGO) || \ 1114 ((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO) || \ 1115 ((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) || \ 1116 ((REGTRIG) == ADC_SOFTWARE_START)) 1117 #else 1118 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 1119 ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC4) || \ 1120 ((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO) || \ 1121 ((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) || \ 1122 ((REGTRIG) == ADC_SOFTWARE_START)) 1123 #endif /* TIM2 */ 1124 1125 #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ 1126 ((EOC_SELECTION) == ADC_EOC_SEQ_CONV)) 1127 1128 #define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \ 1129 ((OVR) == ADC_OVR_DATA_OVERWRITTEN) ) 1130 1131 #define IS_ADC_REGULAR_RANK_SEQ_FIXED(RANK) (((RANK) == ADC_RANK_CHANNEL_NUMBER) || \ 1132 ((RANK) == ADC_RANK_NONE) ) 1133 1134 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) == ADC_REGULAR_RANK_1 ) || \ 1135 ((RANK) == ADC_REGULAR_RANK_2 ) || \ 1136 ((RANK) == ADC_REGULAR_RANK_3 ) || \ 1137 ((RANK) == ADC_REGULAR_RANK_4 ) || \ 1138 ((RANK) == ADC_REGULAR_RANK_5 ) || \ 1139 ((RANK) == ADC_REGULAR_RANK_6 ) || \ 1140 ((RANK) == ADC_REGULAR_RANK_7 ) || \ 1141 ((RANK) == ADC_REGULAR_RANK_8 ) ) 1142 1143 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ 1144 ((CHANNEL) == ADC_CHANNEL_1) || \ 1145 ((CHANNEL) == ADC_CHANNEL_2) || \ 1146 ((CHANNEL) == ADC_CHANNEL_3) || \ 1147 ((CHANNEL) == ADC_CHANNEL_4) || \ 1148 ((CHANNEL) == ADC_CHANNEL_5) || \ 1149 ((CHANNEL) == ADC_CHANNEL_6) || \ 1150 ((CHANNEL) == ADC_CHANNEL_7) || \ 1151 ((CHANNEL) == ADC_CHANNEL_8) || \ 1152 ((CHANNEL) == ADC_CHANNEL_9) || \ 1153 ((CHANNEL) == ADC_CHANNEL_10) || \ 1154 ((CHANNEL) == ADC_CHANNEL_11) || \ 1155 ((CHANNEL) == ADC_CHANNEL_12) || \ 1156 ((CHANNEL) == ADC_CHANNEL_13) || \ 1157 ((CHANNEL) == ADC_CHANNEL_14) || \ 1158 ((CHANNEL) == ADC_CHANNEL_15) || \ 1159 ((CHANNEL) == ADC_CHANNEL_16) || \ 1160 ((CHANNEL) == ADC_CHANNEL_17) || \ 1161 ((CHANNEL) == ADC_CHANNEL_18) || \ 1162 ((CHANNEL) == ADC_CHANNEL_19) || \ 1163 ((CHANNEL) == ADC_CHANNEL_20) || \ 1164 ((CHANNEL) == ADC_CHANNEL_21) || \ 1165 ((CHANNEL) == ADC_CHANNEL_22) || \ 1166 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ 1167 ((CHANNEL) == ADC_CHANNEL_VREFINT) || \ 1168 ((CHANNEL) == ADC_CHANNEL_VDDA) || \ 1169 ((CHANNEL) == ADC_CHANNEL_VSSA) ) 1170 1171 #define IS_ADC_SAMPLING_TIME_COMMON(SAMPLING_TIME_COMMON) (((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_1) || \ 1172 ((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_2) ) 1173 1174 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ 1175 ((TIME) == ADC_SAMPLETIME_3CYCLES_5) || \ 1176 ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ 1177 ((TIME) == ADC_SAMPLETIME_12CYCLES_5) || \ 1178 ((TIME) == ADC_SAMPLETIME_19CYCLES_5) || \ 1179 ((TIME) == ADC_SAMPLETIME_39CYCLES_5) || \ 1180 ((TIME) == ADC_SAMPLETIME_79CYCLES_5) || \ 1181 ((TIME) == ADC_SAMPLETIME_160CYCLES_5) ) 1182 1183 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_1) || \ 1184 ((WATCHDOG) == ADC_ANALOGWATCHDOG_2) || \ 1185 ((WATCHDOG) == ADC_ANALOGWATCHDOG_3) ) 1186 1187 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ 1188 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 1189 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) ) 1190 1191 #define IS_ADC_TRIGGER_FREQ(TRIGGER_FREQ) (((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_HIGH) || \ 1192 ((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_LOW) ) 1193 1194 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_EOSMP_EVENT) || \ 1195 ((EVENT) == ADC_AWD1_EVENT) || \ 1196 ((EVENT) == ADC_AWD2_EVENT) || \ 1197 ((EVENT) == ADC_AWD3_EVENT) || \ 1198 ((EVENT) == ADC_OVR_EVENT) ) 1199 1200 /** 1201 * @brief Verify that a given value is aligned with the ADC resolution range. 1202 * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). 1203 * @param __ADC_VALUE__ value checked against the resolution. 1204 * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) 1205 */ 1206 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ 1207 ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)) 1208 1209 /** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification 1210 * @{ 1211 */ 1212 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1UL) && ((LENGTH) <= 8UL)) 1213 /** 1214 * @} 1215 */ 1216 1217 1218 /* Private constants ---------------------------------------------------------*/ 1219 1220 /** @defgroup ADC_Private_Constants ADC Private Constants 1221 * @{ 1222 */ 1223 1224 /* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */ 1225 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC) 1226 1227 /* Internal definition to differentiate sequencer setting fixed or configurable */ 1228 #define ADC_SCAN_SEQ_FIXED_INT 0x80000000U 1229 1230 /** 1231 * @} 1232 */ 1233 1234 /* Exported macro ------------------------------------------------------------*/ 1235 1236 /** @defgroup ADC_Exported_Macros ADC Exported Macros 1237 * @{ 1238 */ 1239 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 1240 /* final user. */ 1241 1242 /** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. 1243 * @{ 1244 */ 1245 1246 /** @brief Reset ADC handle state. 1247 * @param __HANDLE__ ADC handle 1248 * @retval None 1249 */ 1250 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1251 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1252 do{ \ 1253 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ 1254 (__HANDLE__)->MspInitCallback = NULL; \ 1255 (__HANDLE__)->MspDeInitCallback = NULL; \ 1256 } while(0) 1257 #else 1258 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1259 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 1260 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1261 1262 /** 1263 * @brief Enable ADC interrupt. 1264 * @param __HANDLE__ ADC handle 1265 * @param __INTERRUPT__ ADC Interrupt 1266 * This parameter can be one of the following values: 1267 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1268 * @arg @ref ADC_IT_CCRDY ADC channel configuration ready interrupt source 1269 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1270 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1271 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1272 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1273 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1274 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1275 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1276 * @retval None 1277 */ 1278 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 1279 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 1280 1281 /** 1282 * @brief Disable ADC interrupt. 1283 * @param __HANDLE__ ADC handle 1284 * @param __INTERRUPT__ ADC Interrupt 1285 * This parameter can be one of the following values: 1286 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1287 * @arg @ref ADC_IT_CCRDY ADC channel configuration ready interrupt source 1288 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1289 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1290 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1291 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1292 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1293 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1294 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1295 * @retval None 1296 */ 1297 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 1298 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 1299 1300 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 1301 * @param __HANDLE__ ADC handle 1302 * @param __INTERRUPT__ ADC interrupt source to check 1303 * This parameter can be one of the following values: 1304 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1305 * @arg @ref ADC_IT_CCRDY ADC channel configuration ready interrupt source 1306 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1307 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1308 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1309 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1310 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1311 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1312 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1313 * @retval State of interruption (SET or RESET) 1314 */ 1315 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 1316 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) 1317 1318 /** 1319 * @brief Check whether the specified ADC flag is set or not. 1320 * @param __HANDLE__ ADC handle 1321 * @param __FLAG__ ADC flag 1322 * This parameter can be one of the following values: 1323 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1324 * @arg @ref ADC_FLAG_CCRDY ADC channel configuration ready flag 1325 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1326 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1327 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1328 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1329 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1330 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1331 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1332 * @retval State of flag (TRUE or FALSE). 1333 */ 1334 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 1335 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) 1336 1337 /** 1338 * @brief Clear the specified ADC flag. 1339 * @param __HANDLE__ ADC handle 1340 * @param __FLAG__ ADC flag 1341 * This parameter can be one of the following values: 1342 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1343 * @arg @ref ADC_FLAG_CCRDY ADC channel configuration ready flag 1344 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1345 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1346 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1347 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1348 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1349 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1350 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1351 * @retval None 1352 */ 1353 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ 1354 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 1355 (((__HANDLE__)->Instance->ISR) = (__FLAG__)) 1356 1357 /** 1358 * @} 1359 */ 1360 1361 /** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro 1362 * @{ 1363 */ 1364 1365 /** 1366 * @brief Helper macro to get ADC channel number in decimal format 1367 * from literals ADC_CHANNEL_x. 1368 * @note Example: 1369 * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) 1370 * will return decimal number "4". 1371 * @note The input can be a value from functions where a channel 1372 * number is returned, either defined with number 1373 * or with bitfield (only one bit must be set). 1374 * @param __CHANNEL__ This parameter can be one of the following values: 1375 * @arg @ref ADC_CHANNEL_0 1376 * @arg @ref ADC_CHANNEL_1 1377 * @arg @ref ADC_CHANNEL_2 1378 * @arg @ref ADC_CHANNEL_3 1379 * @arg @ref ADC_CHANNEL_4 1380 * @arg @ref ADC_CHANNEL_5 1381 * @arg @ref ADC_CHANNEL_6 1382 * @arg @ref ADC_CHANNEL_7 1383 * @arg @ref ADC_CHANNEL_8 (1) 1384 * @arg @ref ADC_CHANNEL_9 (1) 1385 * @arg @ref ADC_CHANNEL_10 1386 * @arg @ref ADC_CHANNEL_11 1387 * @arg @ref ADC_CHANNEL_12 1388 * @arg @ref ADC_CHANNEL_13 1389 * @arg @ref ADC_CHANNEL_14 1390 * @arg @ref ADC_CHANNEL_15 (1) 1391 * @arg @ref ADC_CHANNEL_16 (1) 1392 * @arg @ref ADC_CHANNEL_17 (3) 1393 * @arg @ref ADC_CHANNEL_18 (3) 1394 * @arg @ref ADC_CHANNEL_19 (3) 1395 * @arg @ref ADC_CHANNEL_20 (3) 1396 * @arg @ref ADC_CHANNEL_21 (3) 1397 * @arg @ref ADC_CHANNEL_22 (3) 1398 * @arg @ref ADC_CHANNEL_VREFINT (2) 1399 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) 1400 * @arg @ref ADC_CHANNEL_VDDA (2) 1401 * @arg @ref ADC_CHANNEL_VSSA (2) 1402 * 1403 * (1) On STM32C0, parameter can be set in ADC group sequencer 1404 * only if sequencer is set in mode "not fully configurable", 1405 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n 1406 * (2) For ADC channel read back from ADC register, 1407 * comparison with internal channel parameter to be done 1408 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 1409 * (3) ADC channels available on STM32C031xx device only. 1410 * @retval Value between Min_Data=0 and Max_Data=18 1411 */ 1412 #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 1413 __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) 1414 1415 /** 1416 * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x 1417 * from number in decimal format. 1418 * @note Example: 1419 * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) 1420 * will return a data equivalent to "ADC_CHANNEL_4". 1421 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 1422 * @retval Returned value can be one of the following values: 1423 * @arg @ref ADC_CHANNEL_0 1424 * @arg @ref ADC_CHANNEL_1 1425 * @arg @ref ADC_CHANNEL_2 1426 * @arg @ref ADC_CHANNEL_3 1427 * @arg @ref ADC_CHANNEL_4 1428 * @arg @ref ADC_CHANNEL_5 1429 * @arg @ref ADC_CHANNEL_6 1430 * @arg @ref ADC_CHANNEL_7 1431 * @arg @ref ADC_CHANNEL_8 (1) 1432 * @arg @ref ADC_CHANNEL_9 (1) 1433 * @arg @ref ADC_CHANNEL_10 1434 * @arg @ref ADC_CHANNEL_11 1435 * @arg @ref ADC_CHANNEL_12 1436 * @arg @ref ADC_CHANNEL_13 1437 * @arg @ref ADC_CHANNEL_14 1438 * @arg @ref ADC_CHANNEL_15 (1) 1439 * @arg @ref ADC_CHANNEL_16 (1) 1440 * @arg @ref ADC_CHANNEL_17 (3) 1441 * @arg @ref ADC_CHANNEL_18 (3) 1442 * @arg @ref ADC_CHANNEL_19 (3) 1443 * @arg @ref ADC_CHANNEL_20 (3) 1444 * @arg @ref ADC_CHANNEL_21 (3) 1445 * @arg @ref ADC_CHANNEL_22 (3) 1446 * @arg @ref ADC_CHANNEL_VREFINT (2) 1447 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) 1448 * @arg @ref ADC_CHANNEL_VDDA (2) 1449 * @arg @ref ADC_CHANNEL_VSSA (2) 1450 * 1451 * (1) On STM32C0, parameter can be set in ADC group sequencer 1452 * only if sequencer is set in mode "not fully configurable", 1453 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n 1454 * (2) For ADC channel read back from ADC register, 1455 * comparison with internal channel parameter to be done 1456 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 1457 * (3) ADC channels available on STM32C031xx device only. 1458 */ 1459 #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 1460 __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) 1461 1462 /** 1463 * @brief Helper macro to determine whether the selected channel 1464 * corresponds to literal definitions of driver. 1465 * @note The different literal definitions of ADC channels are: 1466 * - ADC internal channel: 1467 * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... 1468 * - ADC external channel (channel connected to a GPIO pin): 1469 * ADC_CHANNEL_1, ADC_CHANNEL_2, ... 1470 * @note The channel parameter must be a value defined from literal 1471 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1472 * ADC_CHANNEL_TEMPSENSOR, ...), 1473 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), 1474 * must not be a value from functions where a channel number is 1475 * returned from ADC registers, 1476 * because internal and external channels share the same channel 1477 * number in ADC registers. The differentiation is made only with 1478 * parameters definitions of driver. 1479 * @param __CHANNEL__ This parameter can be one of the following values: 1480 * @arg @ref ADC_CHANNEL_0 1481 * @arg @ref ADC_CHANNEL_1 1482 * @arg @ref ADC_CHANNEL_2 1483 * @arg @ref ADC_CHANNEL_3 1484 * @arg @ref ADC_CHANNEL_4 1485 * @arg @ref ADC_CHANNEL_5 1486 * @arg @ref ADC_CHANNEL_6 1487 * @arg @ref ADC_CHANNEL_7 1488 * @arg @ref ADC_CHANNEL_8 (1) 1489 * @arg @ref ADC_CHANNEL_9 (1) 1490 * @arg @ref ADC_CHANNEL_10 1491 * @arg @ref ADC_CHANNEL_11 1492 * @arg @ref ADC_CHANNEL_12 1493 * @arg @ref ADC_CHANNEL_13 1494 * @arg @ref ADC_CHANNEL_14 1495 * @arg @ref ADC_CHANNEL_15 (1) 1496 * @arg @ref ADC_CHANNEL_16 (1) 1497 * @arg @ref ADC_CHANNEL_17 (3) 1498 * @arg @ref ADC_CHANNEL_18 (3) 1499 * @arg @ref ADC_CHANNEL_19 (3) 1500 * @arg @ref ADC_CHANNEL_20 (3) 1501 * @arg @ref ADC_CHANNEL_21 (3) 1502 * @arg @ref ADC_CHANNEL_22 (3) 1503 * @arg @ref ADC_CHANNEL_VREFINT (2) 1504 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) 1505 * @arg @ref ADC_CHANNEL_VDDA (2) 1506 * @arg @ref ADC_CHANNEL_VSSA (2) 1507 * 1508 * (1) On STM32C0, parameter can be set in ADC group sequencer 1509 * only if sequencer is set in mode "not fully configurable", 1510 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n 1511 * (2) For ADC channel read back from ADC register, 1512 * comparison with internal channel parameter to be done 1513 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 1514 * (3) ADC channels available on STM32C031xx device only. 1515 * @retval Value "0" if the channel corresponds to a parameter definition of a 1516 * ADC external channel (channel connected to a GPIO pin). 1517 * Value "1" if the channel corresponds to a parameter definition of 1518 * a ADC internal channel. 1519 */ 1520 #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ 1521 __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) 1522 1523 /** 1524 * @brief Helper macro to convert a channel defined from parameter 1525 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1526 * ADC_CHANNEL_TEMPSENSOR, ...), 1527 * to its equivalent parameter definition of a ADC external channel 1528 * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). 1529 * @note The channel parameter can be, additionally to a value 1530 * defined from parameter definition of a ADC internal channel 1531 * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), 1532 * a value defined from parameter definition of 1533 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1534 * or a value from functions where a channel number is returned 1535 * from ADC registers. 1536 * @param __CHANNEL__ This parameter can be one of the following values: 1537 * @arg @ref ADC_CHANNEL_0 1538 * @arg @ref ADC_CHANNEL_1 1539 * @arg @ref ADC_CHANNEL_2 1540 * @arg @ref ADC_CHANNEL_3 1541 * @arg @ref ADC_CHANNEL_4 1542 * @arg @ref ADC_CHANNEL_5 1543 * @arg @ref ADC_CHANNEL_6 1544 * @arg @ref ADC_CHANNEL_7 1545 * @arg @ref ADC_CHANNEL_8 (1) 1546 * @arg @ref ADC_CHANNEL_9 (1) 1547 * @arg @ref ADC_CHANNEL_10 1548 * @arg @ref ADC_CHANNEL_11 1549 * @arg @ref ADC_CHANNEL_12 1550 * @arg @ref ADC_CHANNEL_13 1551 * @arg @ref ADC_CHANNEL_14 1552 * @arg @ref ADC_CHANNEL_15 (1) 1553 * @arg @ref ADC_CHANNEL_16 (1) 1554 * @arg @ref ADC_CHANNEL_17 (3) 1555 * @arg @ref ADC_CHANNEL_18 (3) 1556 * @arg @ref ADC_CHANNEL_19 (3) 1557 * @arg @ref ADC_CHANNEL_20 (3) 1558 * @arg @ref ADC_CHANNEL_21 (3) 1559 * @arg @ref ADC_CHANNEL_22 (3) 1560 * @arg @ref ADC_CHANNEL_VREFINT (2) 1561 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) 1562 * @arg @ref ADC_CHANNEL_VDDA (2) 1563 * @arg @ref ADC_CHANNEL_VSSA (2) 1564 * 1565 * (1) On STM32C0, parameter can be set in ADC group sequencer 1566 * only if sequencer is set in mode "not fully configurable", 1567 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n 1568 * (2) For ADC channel read back from ADC register, 1569 * comparison with internal channel parameter to be done 1570 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 1571 * (3) ADC channels available on STM32C031xx device only. 1572 * @retval Returned value can be one of the following values: 1573 * @arg @ref ADC_CHANNEL_0 1574 * @arg @ref ADC_CHANNEL_1 1575 * @arg @ref ADC_CHANNEL_2 1576 * @arg @ref ADC_CHANNEL_3 1577 * @arg @ref ADC_CHANNEL_4 1578 * @arg @ref ADC_CHANNEL_5 1579 * @arg @ref ADC_CHANNEL_6 1580 * @arg @ref ADC_CHANNEL_7 1581 * @arg @ref ADC_CHANNEL_8 1582 * @arg @ref ADC_CHANNEL_9 1583 * @arg @ref ADC_CHANNEL_10 1584 * @arg @ref ADC_CHANNEL_11 1585 * @arg @ref ADC_CHANNEL_12 1586 * @arg @ref ADC_CHANNEL_13 1587 * @arg @ref ADC_CHANNEL_14 1588 * @arg @ref ADC_CHANNEL_15 1589 * @arg @ref ADC_CHANNEL_16 1590 * @arg @ref ADC_CHANNEL_17 1591 * @arg @ref ADC_CHANNEL_18 1592 * @arg @ref ADC_CHANNEL_19 1593 * @arg @ref ADC_CHANNEL_20 1594 * @arg @ref ADC_CHANNEL_21 1595 * @arg @ref ADC_CHANNEL_22 1596 */ 1597 #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ 1598 __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) 1599 1600 /** 1601 * @brief Helper macro to determine whether the internal channel 1602 * selected is available on the ADC instance selected. 1603 * @note The channel parameter must be a value defined from parameter 1604 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1605 * ADC_CHANNEL_TEMPSENSOR, ...), 1606 * must not be a value defined from parameter definition of 1607 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1608 * or a value from functions where a channel number is 1609 * returned from ADC registers, 1610 * because internal and external channels share the same channel 1611 * number in ADC registers. The differentiation is made only with 1612 * parameters definitions of driver. 1613 * @param __ADC_INSTANCE__ ADC instance 1614 * @param __CHANNEL__ This parameter can be one of the following values: 1615 * @arg @ref ADC_CHANNEL_VREFINT 1616 * @arg @ref ADC_CHANNEL_TEMPSENSOR 1617 * @arg @ref ADC_CHANNEL_VDDA 1618 * @arg @ref ADC_CHANNEL_VSSA 1619 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. 1620 * Value "1" if the internal channel selected is available on the ADC instance selected. 1621 */ 1622 #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 1623 __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) 1624 1625 /** 1626 * @brief Helper macro to select the ADC common instance 1627 * to which is belonging the selected ADC instance. 1628 * @note ADC common register instance can be used for: 1629 * - Set parameters common to several ADC instances 1630 * - Multimode (for devices with several ADC instances) 1631 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1632 * @param __ADCx__ ADC instance 1633 * @retval ADC common register instance 1634 */ 1635 #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ 1636 __LL_ADC_COMMON_INSTANCE((__ADCx__)) 1637 1638 /** 1639 * @brief Helper macro to check if all ADC instances sharing the same 1640 * ADC common instance are disabled. 1641 * @note This check is required by functions with setting conditioned to 1642 * ADC state: 1643 * All ADC instances of the ADC common group must be disabled. 1644 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1645 * @note On devices with only 1 ADC common instance, parameter of this macro 1646 * is useless and can be ignored (parameter kept for compatibility 1647 * with devices featuring several ADC common instances). 1648 * @param __ADCXY_COMMON__ ADC common instance 1649 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 1650 * @retval Value "0" if all ADC instances sharing the same ADC common instance 1651 * are disabled. 1652 * Value "1" if at least one ADC instance sharing the same ADC common instance 1653 * is enabled. 1654 */ 1655 #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 1656 __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) 1657 1658 /** 1659 * @brief Helper macro to define the ADC conversion data full-scale digital 1660 * value corresponding to the selected ADC resolution. 1661 * @note ADC conversion data full-scale corresponds to voltage range 1662 * determined by analog voltage references Vref+ and Vref- 1663 * (refer to reference manual). 1664 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1665 * @arg @ref ADC_RESOLUTION_12B 1666 * @arg @ref ADC_RESOLUTION_10B 1667 * @arg @ref ADC_RESOLUTION_8B 1668 * @arg @ref ADC_RESOLUTION_6B 1669 * @retval ADC conversion data full-scale digital value 1670 */ 1671 #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 1672 __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) 1673 1674 /** 1675 * @brief Helper macro to convert the ADC conversion data from 1676 * a resolution to another resolution. 1677 * @param __DATA__ ADC conversion data to be converted 1678 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted 1679 * This parameter can be one of the following values: 1680 * @arg @ref ADC_RESOLUTION_12B 1681 * @arg @ref ADC_RESOLUTION_10B 1682 * @arg @ref ADC_RESOLUTION_8B 1683 * @arg @ref ADC_RESOLUTION_6B 1684 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion 1685 * This parameter can be one of the following values: 1686 * @arg @ref ADC_RESOLUTION_12B 1687 * @arg @ref ADC_RESOLUTION_10B 1688 * @arg @ref ADC_RESOLUTION_8B 1689 * @arg @ref ADC_RESOLUTION_6B 1690 * @retval ADC conversion data to the requested resolution 1691 */ 1692 #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ 1693 __ADC_RESOLUTION_CURRENT__,\ 1694 __ADC_RESOLUTION_TARGET__) \ 1695 __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ 1696 (__ADC_RESOLUTION_CURRENT__),\ 1697 (__ADC_RESOLUTION_TARGET__)) 1698 1699 /** 1700 * @brief Helper macro to calculate the voltage (unit: mVolt) 1701 * corresponding to a ADC conversion data (unit: digital value). 1702 * @note Analog reference voltage (Vref+) must be either known from 1703 * user board environment or can be calculated using ADC measurement 1704 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1705 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1706 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 1707 * (unit: digital value). 1708 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1709 * @arg @ref ADC_RESOLUTION_12B 1710 * @arg @ref ADC_RESOLUTION_10B 1711 * @arg @ref ADC_RESOLUTION_8B 1712 * @arg @ref ADC_RESOLUTION_6B 1713 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 1714 */ 1715 #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 1716 __ADC_DATA__,\ 1717 __ADC_RESOLUTION__) \ 1718 __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ 1719 (__ADC_DATA__),\ 1720 (__ADC_RESOLUTION__)) 1721 1722 /** 1723 * @brief Helper macro to calculate analog reference voltage (Vref+) 1724 * (unit: mVolt) from ADC conversion data of internal voltage 1725 * reference VrefInt. 1726 * @note Computation is using VrefInt calibration value 1727 * stored in system memory for each device during production. 1728 * @note This voltage depends on user board environment: voltage level 1729 * connected to pin Vref+. 1730 * On devices with small package, the pin Vref+ is not present 1731 * and internally bonded to pin Vdda. 1732 * @note On this STM32 series, calibration data of internal voltage reference 1733 * VrefInt corresponds to a resolution of 12 bits, 1734 * this is the recommended ADC resolution to convert voltage of 1735 * internal voltage reference VrefInt. 1736 * Otherwise, this macro performs the processing to scale 1737 * ADC conversion data to 12 bits. 1738 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) 1739 * of internal voltage reference VrefInt (unit: digital value). 1740 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1741 * @arg @ref ADC_RESOLUTION_12B 1742 * @arg @ref ADC_RESOLUTION_10B 1743 * @arg @ref ADC_RESOLUTION_8B 1744 * @arg @ref ADC_RESOLUTION_6B 1745 * @retval Analog reference voltage (unit: mV) 1746 */ 1747 #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ 1748 __ADC_RESOLUTION__) \ 1749 __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ 1750 (__ADC_RESOLUTION__)) 1751 1752 /** 1753 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 1754 * from ADC conversion data of internal temperature sensor. 1755 * @note Computation is using temperature sensor typical values 1756 * (refer to device datasheet). 1757 * @note Calculation formula: 1758 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) 1759 * / Avg_Slope + CALx_TEMP 1760 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 1761 * (unit: digital value) 1762 * Avg_Slope = temperature sensor slope 1763 * (unit: uV/Degree Celsius) 1764 * TS_TYP_CALx_VOLT = temperature sensor digital value at 1765 * temperature CALx_TEMP (unit: mV) 1766 * Caution: Calculation relevancy under reserve the temperature sensor 1767 * of the current device has characteristics in line with 1768 * datasheet typical values. 1769 * @note: On this STM32 series, calibtation parameter TS_CAL1 can be used 1770 * to improve calculation accuracy. 1771 * Refer to @ref TEMPSENSOR_CAL1_ADDR. 1772 * @note As calculation input, the analog reference voltage (Vref+) must be 1773 * defined as it impacts the ADC LSB equivalent voltage. 1774 * @note Analog reference voltage (Vref+) must be either known from 1775 * user board environment or can be calculated using ADC measurement 1776 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1777 * @note ADC measurement data must correspond to a resolution of 12bits 1778 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value 1779 * (unit: uV/DegCelsius). 1780 * On this STM32 series, refer to device datasheet parameter "Avg_Slope". 1781 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at 1782 * temperature and Vref+ defined in parameters below) (unit: mV). 1783 * On this STM32 series, refer to device datasheet parameter "V30" 1784 * (corresponding to TS_CAL1). 1785 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see 1786 * parameter above) is corresponding (unit: mV) 1787 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) 1788 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). 1789 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. 1790 * This parameter can be one of the following values: 1791 * @arg @ref ADC_RESOLUTION_12B 1792 * @arg @ref ADC_RESOLUTION_10B 1793 * @arg @ref ADC_RESOLUTION_8B 1794 * @arg @ref ADC_RESOLUTION_6B 1795 * @retval Temperature (unit: degree Celsius) 1796 */ 1797 #define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ 1798 __TEMPSENSOR_TYP_CALX_V__,\ 1799 __TEMPSENSOR_CALX_TEMP__,\ 1800 __VREFANALOG_VOLTAGE__,\ 1801 __TEMPSENSOR_ADC_DATA__,\ 1802 __ADC_RESOLUTION__) \ 1803 __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ 1804 (__TEMPSENSOR_TYP_CALX_V__),\ 1805 (__TEMPSENSOR_CALX_TEMP__),\ 1806 (__VREFANALOG_VOLTAGE__),\ 1807 (__TEMPSENSOR_ADC_DATA__),\ 1808 (__ADC_RESOLUTION__)) 1809 1810 /** 1811 * @} 1812 */ 1813 1814 /** 1815 * @} 1816 */ 1817 1818 /* Include ADC HAL Extended module */ 1819 #include "stm32c0xx_hal_adc_ex.h" 1820 1821 /* Exported functions --------------------------------------------------------*/ 1822 /** @addtogroup ADC_Exported_Functions 1823 * @{ 1824 */ 1825 1826 /** @addtogroup ADC_Exported_Functions_Group1 1827 * @brief Initialization and Configuration functions 1828 * @{ 1829 */ 1830 /* Initialization and de-initialization functions ****************************/ 1831 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); 1832 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 1833 void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); 1834 void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); 1835 1836 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1837 /* Callbacks Register/UnRegister functions ***********************************/ 1838 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, 1839 pADC_CallbackTypeDef pCallback); 1840 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); 1841 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1842 /** 1843 * @} 1844 */ 1845 1846 /** @addtogroup ADC_Exported_Functions_Group2 1847 * @brief IO operation functions 1848 * @{ 1849 */ 1850 /* IO operation functions *****************************************************/ 1851 1852 /* Blocking mode: Polling */ 1853 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); 1854 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); 1855 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 1856 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); 1857 1858 /* Non-blocking mode: Interruption */ 1859 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); 1860 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); 1861 1862 /* Non-blocking mode: DMA */ 1863 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 1864 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); 1865 1866 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1867 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); 1868 1869 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 1870 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); 1871 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); 1872 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); 1873 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); 1874 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 1875 void HAL_ADC_CalibrationCpltCallback(ADC_HandleTypeDef *hadc); 1876 void HAL_ADC_ADCReadyCallback(ADC_HandleTypeDef *hadc); 1877 /** 1878 * @} 1879 */ 1880 1881 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions 1882 * @brief Peripheral Control functions 1883 * @{ 1884 */ 1885 /* Peripheral Control functions ***********************************************/ 1886 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig); 1887 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); 1888 1889 /** 1890 * @} 1891 */ 1892 1893 /* Peripheral State functions *************************************************/ 1894 /** @addtogroup ADC_Exported_Functions_Group4 1895 * @{ 1896 */ 1897 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); 1898 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); 1899 1900 /** 1901 * @} 1902 */ 1903 1904 /** 1905 * @} 1906 */ 1907 1908 /* Private functions ---------------------------------------------------------*/ 1909 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc); 1910 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); 1911 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); 1912 1913 /** 1914 * @} 1915 */ 1916 1917 /** 1918 * @} 1919 */ 1920 1921 /** 1922 * @} 1923 */ 1924 1925 #ifdef __cplusplus 1926 } 1927 #endif 1928 1929 1930 #endif /* STM32C0xx_HAL_ADC_H */ 1931
