1 /*
2 * Copyright (c) 2018 Foundries.io Ltd
3 * Copyright (c) 2019 STMicroelectronics
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include <zephyr/init.h>
9 #include <soc.h>
10 #include <stm32_ll_lptim.h>
11 #include <stm32_ll_bus.h>
12 #include <stm32_ll_rcc.h>
13 #include <stm32_ll_pwr.h>
14 #include <stm32_ll_system.h>
15 #include <zephyr/drivers/clock_control.h>
16 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
17 #include <zephyr/drivers/timer/system_timer.h>
18 #include <zephyr/sys_clock.h>
19 #include <zephyr/irq.h>
20 #include <zephyr/drivers/counter.h>
21 #include <zephyr/pm/policy.h>
22
23 #include <zephyr/spinlock.h>
24
25 #define DT_DRV_COMPAT st_stm32_lptim
26
27 #if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 1
28 #error Only one LPTIM instance should be enabled
29 #endif
30
31 #define LPTIM (LPTIM_TypeDef *) DT_INST_REG_ADDR(0)
32
33 #if DT_INST_NUM_CLOCKS(0) == 1
34 #warning Kconfig for LPTIM source clock (LSI/LSE) is deprecated, use device tree.
35 static const struct stm32_pclken lptim_clk[] = {
36 STM32_CLOCK_INFO(0, DT_DRV_INST(0)),
37 /* Use Kconfig to configure source clocks fields */
38 /* Fortunately, values are consistent across enabled series */
39 #ifdef CONFIG_STM32_LPTIM_CLOCK_LSI
40 {.bus = STM32_SRC_LSI, .enr = LPTIM1_SEL(1)}
41 #else
42 {.bus = STM32_SRC_LSE, .enr = LPTIM1_SEL(3)}
43 #endif
44 };
45 #else
46 static const struct stm32_pclken lptim_clk[] = STM32_DT_INST_CLOCKS(0);
47 #endif
48
49 static const struct device *const clk_ctrl = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
50
51 /*
52 * Assumptions and limitations:
53 *
54 * - system clock based on an LPTIM instance, clocked by LSI or LSE
55 * - prescaler is set to a 2^value from 1 (division of the LPTIM source clock by 1)
56 * to 128 (division of the LPTIM source clock by 128)
57 * - using LPTIM AutoReload capability to trig the IRQ (timeout irq)
58 * - when timeout irq occurs the counter is already reset
59 * - the maximum timeout duration is reached with the lptim_time_base value
60 * - with prescaler of 1, the max timeout (LPTIM_TIMEBASE) is 2 seconds:
61 * 0xFFFF / (LSE freq (32768Hz) / 1)
62 * - with prescaler of 128, the max timeout (LPTIM_TIMEBASE) is 256 seconds:
63 * 0xFFFF / (LSE freq (32768Hz) / 128)
64 */
65
66 static int32_t lptim_time_base;
67 static uint32_t lptim_clock_freq = CONFIG_STM32_LPTIM_CLOCK;
68 /* The prescaler given by the DTS and to apply to the lptim_clock_freq */
69 static uint32_t lptim_clock_presc = DT_PROP(DT_DRV_INST(0), st_prescaler);
70
71 /* Minimum nb of clock cycles to have to set autoreload register correctly */
72 #define LPTIM_GUARD_VALUE 2
73
74 /* A 32bit value cannot exceed 0xFFFFFFFF/LPTIM_TIMEBASE counting cycles.
75 * This is for example about of 65000 x 2000ms when clocked by LSI
76 */
77 static uint32_t accumulated_lptim_cnt;
78 /* Next autoreload value to set */
79 static uint32_t autoreload_next;
80 /* Indicate if the autoreload register is ready for a write */
81 static bool autoreload_ready = true;
82
83 static struct k_spinlock lock;
84
85 #ifdef CONFIG_STM32_LPTIM_STDBY_TIMER
86
87 #define CURRENT_CPU \
88 (COND_CODE_1(CONFIG_SMP, (arch_curr_cpu()->id), (_current_cpu->id)))
89
90 #define cycle_t uint32_t
91
92 /* This local variable indicates that the timeout was set right before
93 * entering standby state.
94 *
95 * It is used for chips that has to use a separate standby timer in such
96 * case because the LPTIM is not clocked in some low power mode state.
97 */
98 static bool timeout_stdby;
99
100 /* Cycle counter before entering the standby state. */
101 static cycle_t lptim_cnt_pre_stdby;
102
103 /* Standby timer value before entering the standby state. */
104 static uint32_t stdby_timer_pre_stdby;
105
106 /* Standby timer used for timer while entering the standby state */
107 static const struct device *stdby_timer = DEVICE_DT_GET(DT_CHOSEN(st_lptim_stdby_timer));
108
109 #endif /* CONFIG_STM32_LPTIM_STDBY_TIMER */
110
arrm_state_get(void)111 static inline bool arrm_state_get(void)
112 {
113 return (LL_LPTIM_IsActiveFlag_ARRM(LPTIM) && LL_LPTIM_IsEnabledIT_ARRM(LPTIM));
114 }
115
lptim_irq_handler(const struct device * unused)116 static void lptim_irq_handler(const struct device *unused)
117 {
118
119 ARG_UNUSED(unused);
120
121 uint32_t autoreload = LL_LPTIM_GetAutoReload(LPTIM);
122
123 if ((LL_LPTIM_IsActiveFlag_ARROK(LPTIM) != 0)
124 && LL_LPTIM_IsEnabledIT_ARROK(LPTIM) != 0) {
125 LL_LPTIM_ClearFlag_ARROK(LPTIM);
126 if ((autoreload_next > 0) && (autoreload_next != autoreload)) {
127 /* the new autoreload value change, we set it */
128 autoreload_ready = false;
129 LL_LPTIM_SetAutoReload(LPTIM, autoreload_next);
130 } else {
131 autoreload_ready = true;
132 }
133 }
134
135 if (arrm_state_get()) {
136 k_spinlock_key_t key = k_spin_lock(&lock);
137
138 /* do not change ARR yet, sys_clock_announce will do */
139 LL_LPTIM_ClearFLAG_ARRM(LPTIM);
140
141 /* increase the total nb of autoreload count
142 * used in the sys_clock_cycle_get_32() function.
143 */
144 autoreload++;
145
146 accumulated_lptim_cnt += autoreload;
147
148 k_spin_unlock(&lock, key);
149
150 /* announce the elapsed time in ms (count register is 16bit) */
151 uint32_t dticks = (autoreload
152 * CONFIG_SYS_CLOCK_TICKS_PER_SEC)
153 / lptim_clock_freq;
154
155 sys_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL)
156 ? dticks : (dticks > 0));
157 }
158 }
159
lptim_set_autoreload(uint32_t arr)160 static void lptim_set_autoreload(uint32_t arr)
161 {
162 /* Update autoreload register */
163 autoreload_next = arr;
164
165 if (!autoreload_ready)
166 return;
167
168 /* The ARR register ready, we could set it directly */
169 if ((arr > 0) && (arr != LL_LPTIM_GetAutoReload(LPTIM))) {
170 /* The new autoreload value change, we set it */
171 autoreload_ready = false;
172 LL_LPTIM_ClearFlag_ARROK(LPTIM);
173 LL_LPTIM_SetAutoReload(LPTIM, arr);
174 }
175 }
176
z_clock_lptim_getcounter(void)177 static inline uint32_t z_clock_lptim_getcounter(void)
178 {
179 uint32_t lp_time;
180 uint32_t lp_time_prev_read;
181
182 /* It should be noted that to read reliably the content
183 * of the LPTIM_CNT register, two successive read accesses
184 * must be performed and compared
185 */
186 lp_time = LL_LPTIM_GetCounter(LPTIM);
187 do {
188 lp_time_prev_read = lp_time;
189 lp_time = LL_LPTIM_GetCounter(LPTIM);
190 } while (lp_time != lp_time_prev_read);
191 return lp_time;
192 }
193
sys_clock_set_timeout(int32_t ticks,bool idle)194 void sys_clock_set_timeout(int32_t ticks, bool idle)
195 {
196 /* new LPTIM AutoReload value to set (aligned on Kernel ticks) */
197 uint32_t next_arr = 0;
198 int err;
199
200 ARG_UNUSED(idle);
201
202 #ifdef CONFIG_STM32_LPTIM_STDBY_TIMER
203 const struct pm_state_info *next;
204
205 next = pm_policy_next_state(CURRENT_CPU, ticks);
206
207 if ((next != NULL) && (next->state == PM_STATE_SUSPEND_TO_RAM)) {
208 uint64_t timeout_us =
209 ((uint64_t)ticks * USEC_PER_SEC) / CONFIG_SYS_CLOCK_TICKS_PER_SEC;
210
211 struct counter_alarm_cfg cfg = {
212 .callback = NULL,
213 .ticks = counter_us_to_ticks(stdby_timer, timeout_us),
214 .user_data = NULL,
215 .flags = 0,
216 };
217
218 timeout_stdby = true;
219
220 /* Set the alarm using timer that runs the standby.
221 * Needed rump-up/setting time, lower accurency etc. should be
222 * included in the exit-latency in the power state definition.
223 */
224 counter_cancel_channel_alarm(stdby_timer, 0);
225 counter_set_channel_alarm(stdby_timer, 0, &cfg);
226
227 /* Store current values to calculate a difference in
228 * measurements after exiting the standby state.
229 */
230 counter_get_value(stdby_timer, &stdby_timer_pre_stdby);
231 lptim_cnt_pre_stdby = z_clock_lptim_getcounter();
232
233 return;
234 }
235 #endif /* CONFIG_STM32_LPTIM_STDBY_TIMER */
236
237 if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
238 return;
239 }
240
241 if (ticks == K_TICKS_FOREVER) {
242 clock_control_off(clk_ctrl, (clock_control_subsys_t) &lptim_clk[0]);
243 return;
244 }
245
246 /* if LPTIM clock was previously stopped, it must now be restored */
247 err = clock_control_on(clk_ctrl, (clock_control_subsys_t) &lptim_clk[0]);
248
249 if (err < 0) {
250 return;
251 }
252 /* passing ticks==1 means "announce the next tick",
253 * ticks value of zero (or even negative) is legal and
254 * treated identically: it simply indicates the kernel would like the
255 * next tick announcement as soon as possible.
256 */
257 ticks = CLAMP(ticks - 1, 1, lptim_time_base);
258
259 k_spinlock_key_t key = k_spin_lock(&lock);
260
261 /* read current counter value (cannot exceed 16bit) */
262
263 uint32_t lp_time = z_clock_lptim_getcounter();
264
265 uint32_t autoreload = LL_LPTIM_GetAutoReload(LPTIM);
266
267 if (LL_LPTIM_IsActiveFlag_ARRM(LPTIM)
268 || ((autoreload - lp_time) < LPTIM_GUARD_VALUE)) {
269 /* interrupt happens or happens soon.
270 * It's impossible to set autoreload value.
271 */
272 k_spin_unlock(&lock, key);
273 return;
274 }
275
276 /* calculate the next arr value (cannot exceed 16bit)
277 * adjust the next ARR match value to align on Ticks
278 * from the current counter value to first next Tick
279 */
280 next_arr = (((lp_time * CONFIG_SYS_CLOCK_TICKS_PER_SEC)
281 / lptim_clock_freq) + 1) * lptim_clock_freq
282 / (CONFIG_SYS_CLOCK_TICKS_PER_SEC);
283 next_arr = next_arr + ((uint32_t)(ticks) * lptim_clock_freq)
284 / CONFIG_SYS_CLOCK_TICKS_PER_SEC;
285 /* if the lptim_clock_freq < one ticks/sec, then next_arr must be > 0 */
286
287 /* maximise to TIMEBASE */
288 if (next_arr > lptim_time_base) {
289 next_arr = lptim_time_base;
290 }
291 /* The new autoreload value must be LPTIM_GUARD_VALUE clock cycles
292 * after current lptim to make sure we don't miss
293 * an autoreload interrupt
294 */
295 else if (next_arr < (lp_time + LPTIM_GUARD_VALUE)) {
296 next_arr = lp_time + LPTIM_GUARD_VALUE;
297 }
298 /* with slow lptim_clock_freq, LPTIM_GUARD_VALUE of 1 is enough */
299 next_arr = next_arr - 1;
300
301 /* Update autoreload register */
302 lptim_set_autoreload(next_arr);
303
304 k_spin_unlock(&lock, key);
305 }
306
sys_clock_lp_time_get(void)307 static uint32_t sys_clock_lp_time_get(void)
308 {
309 uint32_t lp_time;
310
311 do {
312 /* In case of counter roll-over, add the autoreload value,
313 * because the irq has not yet been handled
314 */
315 if (arrm_state_get()) {
316 lp_time = LL_LPTIM_GetAutoReload(LPTIM) + 1;
317 lp_time += z_clock_lptim_getcounter();
318 break;
319 }
320
321 lp_time = z_clock_lptim_getcounter();
322
323 /* Check if the flag ARRM wasn't be set during the process */
324 } while (arrm_state_get());
325
326 return lp_time;
327 }
328
329
sys_clock_elapsed(void)330 uint32_t sys_clock_elapsed(void)
331 {
332 if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
333 return 0;
334 }
335
336 k_spinlock_key_t key = k_spin_lock(&lock);
337
338 uint32_t lp_time = sys_clock_lp_time_get();
339
340 k_spin_unlock(&lock, key);
341
342 /* gives the value of LPTIM counter (ms)
343 * since the previous 'announce'
344 */
345 uint64_t ret = ((uint64_t)lp_time * CONFIG_SYS_CLOCK_TICKS_PER_SEC) / lptim_clock_freq;
346
347 return (uint32_t)(ret);
348 }
349
sys_clock_cycle_get_32(void)350 uint32_t sys_clock_cycle_get_32(void)
351 {
352 /* just gives the accumulated count in a number of hw cycles */
353
354 k_spinlock_key_t key = k_spin_lock(&lock);
355
356 uint32_t lp_time = sys_clock_lp_time_get();
357
358 lp_time += accumulated_lptim_cnt;
359
360 /* convert lptim count in a nb of hw cycles with precision */
361 uint64_t ret = ((uint64_t)lp_time * sys_clock_hw_cycles_per_sec()) / lptim_clock_freq;
362
363 k_spin_unlock(&lock, key);
364
365 /* convert in hw cycles (keeping 32bit value) */
366 return (uint32_t)(ret);
367 }
368
369 /* Wait for the IER register of the stm32U5 ready, after any bit write operation */
stm32_lptim_wait_ready(void)370 void stm32_lptim_wait_ready(void)
371 {
372 #ifdef CONFIG_SOC_SERIES_STM32U5X
373 while (LL_LPTIM_IsActiveFlag_DIEROK(LPTIM) == 0) {
374 }
375 LL_LPTIM_ClearFlag_DIEROK(LPTIM);
376 #else
377 /* Empty : not relevant */
378 #endif
379 }
380
sys_clock_driver_init(void)381 static int sys_clock_driver_init(void)
382 {
383 uint32_t count_per_tick;
384 int err;
385
386 if (!device_is_ready(clk_ctrl)) {
387 return -ENODEV;
388 }
389
390 /* Enable LPTIM bus clock */
391 err = clock_control_on(clk_ctrl, (clock_control_subsys_t) &lptim_clk[0]);
392 if (err < 0) {
393 return -EIO;
394 }
395
396 #if defined(LL_APB1_GRP1_PERIPH_LPTIM1)
397 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1);
398 #elif defined(LL_APB3_GRP1_PERIPH_LPTIM1)
399 LL_SRDAMR_GRP1_EnableAutonomousClock(LL_SRDAMR_GRP1_PERIPH_LPTIM1AMEN);
400 #elif defined(LL_APB7_GRP1_PERIPH_LPTIM1)
401 LL_APB7_GRP1_ReleaseReset(LL_APB7_GRP1_PERIPH_LPTIM1);
402 #endif
403
404 /* Enable LPTIM clock source */
405 err = clock_control_configure(clk_ctrl,
406 (clock_control_subsys_t) &lptim_clk[1],
407 NULL);
408 if (err < 0) {
409 return -EIO;
410 }
411
412 /* Get LPTIM clock freq */
413 err = clock_control_get_rate(clk_ctrl, (clock_control_subsys_t) &lptim_clk[1],
414 &lptim_clock_freq);
415
416 if (err < 0) {
417 return -EIO;
418 }
419 #if defined(CONFIG_SOC_SERIES_STM32L0X)
420 /* Driver only supports freqs up to 32768Hz. On L0, LSI freq is 37KHz,
421 * which will overflow the LPTIM counter.
422 * Previous LPTIM configuration using device tree was doing forcing this
423 * with a Kconfig default. Impact is that time is 1.13 faster than reality.
424 * Following lines reproduce this behavior in order not to change behavior.
425 * This issue will be fixed by implementation LPTIM prescaler support.
426 */
427 if (lptim_clk[1].bus == STM32_SRC_LSI) {
428 lptim_clock_freq = KHZ(32);
429 }
430 #endif
431
432 /* Set LPTIM time base based on clock source freq */
433 if (lptim_clock_freq == KHZ(32)) {
434 lptim_time_base = 0xF9FF;
435 } else if (lptim_clock_freq == 32768) {
436 lptim_time_base = 0xFFFF;
437 } else {
438 return -EIO;
439 }
440
441 #if !defined(CONFIG_STM32_LPTIM_TICK_FREQ_RATIO_OVERRIDE)
442 /*
443 * Check coherency between CONFIG_SYS_CLOCK_TICKS_PER_SEC
444 * and the lptim_clock_freq which is the CONFIG_STM32_LPTIM_CLOCK reduced
445 * by the lptim_clock_presc
446 */
447 if (lptim_clock_presc <= 8) {
448 __ASSERT(CONFIG_STM32_LPTIM_CLOCK / 8 >= CONFIG_SYS_CLOCK_TICKS_PER_SEC,
449 "It is recommended to set SYS_CLOCK_TICKS_PER_SEC to CONFIG_STM32_LPTIM_CLOCK/8");
450 } else {
451 __ASSERT(CONFIG_STM32_LPTIM_CLOCK / lptim_clock_presc >=
452 CONFIG_SYS_CLOCK_TICKS_PER_SEC,
453 "Set SYS_CLOCK_TICKS_PER_SEC to CONFIG_STM32_LPTIM_CLOCK/lptim_clock_presc");
454 }
455 #endif /* !CONFIG_STM32_LPTIM_TICK_FREQ_RATIO_OVERRIDE */
456
457 /* Actual lptim clock freq when the clock source is reduced by the prescaler */
458 lptim_clock_freq = lptim_clock_freq / lptim_clock_presc;
459
460 /* Clear the event flag and possible pending interrupt */
461 IRQ_CONNECT(DT_INST_IRQN(0),
462 DT_INST_IRQ(0, priority),
463 lptim_irq_handler, 0, 0);
464 irq_enable(DT_INST_IRQN(0));
465
466 #ifdef CONFIG_SOC_SERIES_STM32WLX
467 /* Enable the LPTIM wakeup EXTI line */
468 LL_EXTI_EnableIT_0_31(LL_EXTI_LINE_29);
469 #endif
470
471 /* configure the LPTIM counter */
472 LL_LPTIM_SetClockSource(LPTIM, LL_LPTIM_CLK_SOURCE_INTERNAL);
473 /* the LPTIM clock freq is affected by the prescaler */
474 LL_LPTIM_SetPrescaler(LPTIM, (__CLZ(__RBIT(lptim_clock_presc)) << LPTIM_CFGR_PRESC_Pos));
475
476 #if defined(CONFIG_SOC_SERIES_STM32U5X) || \
477 defined(CONFIG_SOC_SERIES_STM32WBAX)
478 LL_LPTIM_OC_SetPolarity(LPTIM, LL_LPTIM_CHANNEL_CH1,
479 LL_LPTIM_OUTPUT_POLARITY_REGULAR);
480 #else
481 LL_LPTIM_SetPolarity(LPTIM, LL_LPTIM_OUTPUT_POLARITY_REGULAR);
482 #endif
483 LL_LPTIM_SetUpdateMode(LPTIM, LL_LPTIM_UPDATE_MODE_IMMEDIATE);
484 LL_LPTIM_SetCounterMode(LPTIM, LL_LPTIM_COUNTER_MODE_INTERNAL);
485 LL_LPTIM_DisableTimeout(LPTIM);
486 /* counting start is initiated by software */
487 LL_LPTIM_TrigSw(LPTIM);
488
489 #if defined(CONFIG_SOC_SERIES_STM32U5X) || \
490 defined(CONFIG_SOC_SERIES_STM32WBAX)
491 /* Enable the LPTIM before proceeding with configuration */
492 LL_LPTIM_Enable(LPTIM);
493
494 LL_LPTIM_DisableIT_CC1(LPTIM);
495 stm32_lptim_wait_ready();
496 LL_LPTIM_ClearFLAG_CC1(LPTIM);
497 #else
498 /* LPTIM interrupt set-up before enabling */
499 /* no Compare match Interrupt */
500 LL_LPTIM_DisableIT_CMPM(LPTIM);
501 LL_LPTIM_ClearFLAG_CMPM(LPTIM);
502 #endif
503
504 /* Autoreload match Interrupt */
505 LL_LPTIM_EnableIT_ARRM(LPTIM);
506 stm32_lptim_wait_ready();
507 LL_LPTIM_ClearFLAG_ARRM(LPTIM);
508
509 /* ARROK bit validates the write operation to ARR register */
510 LL_LPTIM_EnableIT_ARROK(LPTIM);
511 stm32_lptim_wait_ready();
512 LL_LPTIM_ClearFlag_ARROK(LPTIM);
513
514 #if !defined(CONFIG_SOC_SERIES_STM32U5X) && \
515 !defined(CONFIG_SOC_SERIES_STM32WBAX)
516 /* Enable the LPTIM counter */
517 LL_LPTIM_Enable(LPTIM);
518 #endif
519
520 /* Set the Autoreload value once the timer is enabled */
521 if (IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
522 /* LPTIM is triggered on a LPTIM_TIMEBASE period */
523 lptim_set_autoreload(lptim_time_base);
524 } else {
525 /* nb of LPTIM counter unit per kernel tick (depends on lptim clock prescaler) */
526 count_per_tick = (lptim_clock_freq / CONFIG_SYS_CLOCK_TICKS_PER_SEC);
527 /* LPTIM is triggered on a Tick period */
528 lptim_set_autoreload(count_per_tick - 1);
529 }
530
531 /* Start the LPTIM counter in continuous mode */
532 LL_LPTIM_StartCounter(LPTIM, LL_LPTIM_OPERATING_MODE_CONTINUOUS);
533
534 #ifdef CONFIG_DEBUG
535 /* stop LPTIM during DEBUG */
536 #if defined(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)
537 LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP);
538 #elif defined(LL_DBGMCU_APB3_GRP1_LPTIM1_STOP)
539 LL_DBGMCU_APB3_GRP1_FreezePeriph(LL_DBGMCU_APB3_GRP1_LPTIM1_STOP);
540 #endif
541
542 #endif
543 return 0;
544 }
545
sys_clock_idle_exit(void)546 void sys_clock_idle_exit(void)
547 {
548 #ifdef CONFIG_STM32_LPTIM_STDBY_TIMER
549 if (clock_control_get_status(clk_ctrl,
550 (clock_control_subsys_t) &lptim_clk[0])
551 != CLOCK_CONTROL_STATUS_ON) {
552 sys_clock_driver_init();
553 } else if (timeout_stdby) {
554 cycle_t missed_lptim_cnt;
555 uint32_t stdby_timer_diff, stdby_timer_post, dticks;
556 uint64_t stdby_timer_us;
557
558 /* Get current value for standby timer and reset LPTIM counter value
559 * to start anew.
560 */
561 LL_LPTIM_ResetCounter(LPTIM);
562 counter_get_value(stdby_timer, &stdby_timer_post);
563
564 /* Calculate how much time has passed since last measurement for standby timer */
565 /* Check IDLE timer overflow */
566 if (stdby_timer_pre_stdby > stdby_timer_post) {
567 stdby_timer_diff =
568 (counter_get_top_value(stdby_timer) - stdby_timer_pre_stdby) +
569 stdby_timer_post + 1;
570
571 } else {
572 stdby_timer_diff = stdby_timer_post - stdby_timer_pre_stdby;
573 }
574 stdby_timer_us = counter_ticks_to_us(stdby_timer, stdby_timer_diff);
575
576 /* Convert standby time in LPTIM cnt */
577 missed_lptim_cnt = (sys_clock_hw_cycles_per_sec() * stdby_timer_us) /
578 USEC_PER_SEC;
579 /* Add the LPTIM cnt pre standby */
580 missed_lptim_cnt += lptim_cnt_pre_stdby;
581
582 /* Update the cycle counter to include the cycles missed in standby */
583 accumulated_lptim_cnt += missed_lptim_cnt;
584
585 /* Announce the passed ticks to the kernel */
586 dticks = (missed_lptim_cnt * CONFIG_SYS_CLOCK_TICKS_PER_SEC)
587 / lptim_clock_freq;
588 sys_clock_announce(dticks);
589
590 /* We've already performed all needed operations */
591 timeout_stdby = false;
592 }
593 #endif /* CONFIG_STM32_LPTIM_STDBY_TIMER */
594 }
595
596 SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
597 CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
598
