1/* ------------------------------------------------------------------------- */
2/*  @file:    startup_RV32M1_ri5cy.s                                         */
3/*  @purpose: RI5CY Core Device Startup File                                 */
4/*            RV32M1_ri5cy                                                   */
5/*  @version: 1.0                                                            */
6/*  @date:    2018-10-2                                                      */
7/*  @build:   b180926                                                        */
8/* ------------------------------------------------------------------------- */
9/*                                                                           */
10/* Copyright 1997-2016 Freescale Semiconductor, Inc.                         */
11/* Copyright 2016-2018 NXP                                                   */
12/* All rights reserved.                                                      */
13/*                                                                           */
14/* SPDX-License-Identifier: BSD-3-Clause                                     */
15
16
17// Copyright 2017 ETH Zurich and University of Bologna.
18// Copyright and related rights are licensed under the Solderpad Hardware
19// License, Version 0.51 (the "License"); you may not use this file except in
20// compliance with the License.  You may obtain a copy of the License at
21// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
22// or agreed to in writing, software, hardware and materials distributed under
23// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
24// CONDITIONS OF ANY KIND, either express or implied. See the License for the
25// specific language governing permissions and limitations under the License.
26
27#define EXCEPTION_STACK_SIZE 0x58
28
29    .text
30    .section .vectors, "ax"
31    .option norvc;
32
33    jal x0, IRQ_Handler
34    jal x0, IRQ_Handler
35    jal x0, IRQ_Handler
36    jal x0, IRQ_Handler
37    jal x0, IRQ_Handler
38    jal x0, IRQ_Handler
39    jal x0, IRQ_Handler
40    jal x0, IRQ_Handler
41    jal x0, IRQ_Handler
42    jal x0, IRQ_Handler
43    jal x0, IRQ_Handler
44    jal x0, IRQ_Handler
45    jal x0, IRQ_Handler
46    jal x0, IRQ_Handler
47    jal x0, IRQ_Handler
48    jal x0, IRQ_Handler
49    jal x0, IRQ_Handler
50    jal x0, IRQ_Handler
51    jal x0, IRQ_Handler
52    jal x0, IRQ_Handler
53    jal x0, IRQ_Handler
54    jal x0, IRQ_Handler
55    jal x0, IRQ_Handler
56    jal x0, IRQ_Handler
57    jal x0, IRQ_Handler
58    jal x0, IRQ_Handler
59    jal x0, IRQ_Handler
60    jal x0, IRQ_Handler
61    jal x0, IRQ_Handler
62    jal x0, IRQ_Handler
63    jal x0, IRQ_Handler
64    jal x0, IRQ_Handler
65
66    // reset vector
67    jal x0, Reset_Handler
68
69    // Illegal instrution exception
70    jal x0, IllegalInstruction_Handler
71
72    // ecall handler
73    jal x0, Ecall_Handler
74
75    // LSU error
76    jal x0, LSU_Handler
77
78    .section .startup
79
80/* Reset Handler */
81Reset_Handler:
82
83    # Disable global interrupt. */
84    csrci mstatus, 8
85
86    # initialize stack pointer
87    la sp, __StackTop
88
89    # initialize global pointer
90    la gp, __global_pointer
91
92#ifndef __NO_SYSTEM_INIT
93    jal SystemInit
94#endif
95
96    call __libc_init_array
97
98    # Enable global interrupt. */
99    csrsi mstatus, 8
100
101    jal main
102    ebreak
103
104    .size Reset_Handler, . - Reset_Handler
105
106    .global _init
107    .global _fini
108_init:
109_fini:
110    ret
111
112  // saves all caller-saved registers (except return address)
113store_regs:
114    sw  x3, 0x00(x2)  // gp
115    sw  x4, 0x04(x2)  // tp
116    sw  x5, 0x08(x2)  // t0
117    sw  x6, 0x0c(x2)  // t1
118    sw  x7, 0x10(x2)  // t2
119    sw x10, 0x14(x2)  // a0
120    sw x11, 0x18(x2)  // a1
121    sw x12, 0x1c(x2)  // a2
122    sw x13, 0x20(x2)  // a3
123    sw x14, 0x24(x2)  // a4
124    sw x15, 0x28(x2)  // a5
125    sw x16, 0x2c(x2)  // a6
126    sw x17, 0x30(x2)  // a7
127
128    csrr a0, 0x7B0
129    csrr a1, 0x7B1
130    csrr a2, 0x7B2
131    sw a0, 0x34(x2)  // lpstart[0]
132    sw a1, 0x38(x2)  // lpend[0]
133    sw a2, 0x3c(x2)  // lpcount[0]
134    csrr a0, 0x7B4
135    csrr a1, 0x7B5
136    csrr a2, 0x7B6
137    sw a0, 0x40(x2)  // lpstart[1]
138    sw a1, 0x44(x2)  // lpend[1]
139    sw a2, 0x48(x2)  // lpcount[1]
140
141    csrr a0, 0x341
142    sw a0, 0x4c(x2)  // mepc
143    csrr a1, 0x300
144    sw a1, 0x50(x2)  // mstatus
145    jalr x0, x1
146
147    // load back registers from stack
148end_except:
149    lw a1, 0x50(x2)  // mstatus
150    csrrw x0, 0x300, a1
151    lw a0, 0x4c(x2)  // mepc
152    csrrw x0, 0x341, a0
153
154    lw a0, 0x40(x2)  // lpstart[1]
155    lw a1, 0x44(x2)  // lpend[1]
156    lw a2, 0x48(x2)  // lpcount[1]
157    csrrw x0, 0x7B4, a0
158    csrrw x0, 0x7B5, a1
159    csrrw x0, 0x7B6, a2
160    lw a0, 0x34(x2)  // lpstart[0]
161    lw a1, 0x38(x2)  // lpend[0]
162    lw a2, 0x3c(x2)  // lpcount[0]
163    csrrw x0, 0x7B0, a0
164    csrrw x0, 0x7B1, a1
165    csrrw x0, 0x7B2, a2
166
167    lw  x3, 0x00(x2)  // gp
168    lw  x4, 0x04(x2)  // tp
169    lw  x5, 0x08(x2)  // t0
170    lw  x6, 0x0c(x2)  // t1
171    lw  x7, 0x10(x2)  // t2
172    lw x10, 0x14(x2)  // a0
173    lw x11, 0x18(x2)  // a1
174    lw x12, 0x1c(x2)  // a2
175    lw x13, 0x20(x2)  // a3
176    lw x14, 0x24(x2)  // a4
177    lw x15, 0x28(x2)  // a5
178    lw x16, 0x2c(x2)  // a6
179    lw x17, 0x30(x2)  // a7
180
181    lw  x1, 0x54(x2)
182    addi x2, x2, EXCEPTION_STACK_SIZE
183    mret
184
185    .weak IRQ_Handler
186    .type IRQ_Handler, %function
187IRQ_Handler:
188    addi x2, x2, -EXCEPTION_STACK_SIZE
189    sw x1, 0x54(x2)
190    jal x1, store_regs
191    la x1, end_except
192    csrr a0, mcause
193    jal x0, SystemIrqHandler
194    .size IRQ_Handler, . - IRQ_Handler
195
196    .macro define_exception_entry entry_name handler_name
197    .weak \entry_name
198\entry_name:
199    addi x2, x2, -EXCEPTION_STACK_SIZE
200    sw x1, 0x54(x2)
201    jal x1, store_regs
202    la x1, end_except
203    jal x0, \handler_name
204    .endm
205
206define_exception_entry IllegalInstruction_Handler IllegalInstruction_HandlerFunc
207define_exception_entry Ecall_Handler Ecall_HandlerFunc
208define_exception_entry LSU_Handler LSU_HandlerFunc
209
210    .weak IllegalInstruction_HandlerFunc
211    .type IllegalInstruction_HandlerFunc, %function
212IllegalInstruction_HandlerFunc:
213    j .
214    .size IllegalInstruction_HandlerFunc, . - IllegalInstruction_HandlerFunc
215
216    .weak Ecall_HandlerFunc
217    .type Ecall_HandlerFunc, %function
218Ecall_HandlerFunc:
219    j .
220    .size Ecall_HandlerFunc, . - Ecall_HandlerFunc
221
222    .weak LSU_HandlerFunc
223    .type LSU_HandlerFunc, %function
224LSU_HandlerFunc:
225    j .
226    .size LSU_HandlerFunc, . - LSU_HandlerFunc
227