1/* ------------------------------------------------------------------------- */ 2/* @file: startup_MIMX8MQ5_cm4.s */ 3/* @purpose: CMSIS Cortex-M4 Core Device Startup File */ 4/* MIMX8MQ5_cm4 */ 5/* @version: 4.0 */ 6/* @date: 2018-1-26 */ 7/* @build: b231019 */ 8/* ------------------------------------------------------------------------- */ 9/* */ 10/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ 11/* Copyright 2016-2023 NXP */ 12/* SPDX-License-Identifier: BSD-3-Clause */ 13/*****************************************************************************/ 14/* Version: GCC for ARM Embedded Processors */ 15/*****************************************************************************/ 16 .syntax unified 17 .arch armv7-m 18 19 .section .isr_vector, "a" 20 .align 2 21 .globl __isr_vector 22__isr_vector: 23 .long __StackTop /* Top of Stack */ 24 .long Reset_Handler /* Reset Handler */ 25 .long NMI_Handler /* NMI Handler*/ 26 .long HardFault_Handler /* Hard Fault Handler*/ 27 .long MemManage_Handler /* MPU Fault Handler*/ 28 .long BusFault_Handler /* Bus Fault Handler*/ 29 .long UsageFault_Handler /* Usage Fault Handler*/ 30 .long 0 /* Reserved*/ 31 .long 0 /* Reserved*/ 32 .long 0 /* Reserved*/ 33 .long 0 /* Reserved*/ 34 .long SVC_Handler /* SVCall Handler*/ 35 .long DebugMon_Handler /* Debug Monitor Handler*/ 36 .long 0 /* Reserved*/ 37 .long PendSV_Handler /* PendSV Handler*/ 38 .long SysTick_Handler /* SysTick Handler*/ 39 40 /* External Interrupts*/ 41 .long GPR_IRQ_IRQHandler /* GPR Interrupt. Used to notify cores on exception condition while boot.*/ 42 .long DAP_IRQHandler /* DAP Interrupt*/ 43 .long SDMA1_IRQHandler /* AND of all 48 SDMA interrupts (events) from all the channels*/ 44 .long GPU_IRQHandler /* GPU Interrupt*/ 45 .long SNVS_IRQHandler /* ON-OFF button press shorter than 5 seconds (pulse event)*/ 46 .long LCDIF_IRQHandler /* LCDIF Sync Interrupt*/ 47 .long SPDIF1_IRQHandler /* SPDIF1 Interrupt*/ 48 .long H264_IRQHandler /* h264 Decoder Interrupt*/ 49 .long VPUDMA_IRQHandler /* VPU DMA Interrupt*/ 50 .long QOS_IRQHandler /* QOS interrupt*/ 51 .long WDOG3_IRQHandler /* Watchdog Timer reset*/ 52 .long HS_CP1_IRQHandler /* HS Interrupt Request*/ 53 .long APBHDMA_IRQHandler /* GPMI operation channel 0-3 description complete interrupt*/ 54 .long SPDIF2_IRQHandler /* SPDIF2 Interrupt*/ 55 .long BCH_IRQHandler /* BCH operation complete interrupt*/ 56 .long GPMI_IRQHandler /* GPMI operation TIMEOUT ERROR interrupt*/ 57 .long HDMI_IRQ0_IRQHandler /* HDMI Interrupt 0*/ 58 .long HDMI_IRQ1_IRQHandler /* HDMI Interrupt 1*/ 59 .long HDMI_IRQ2_IRQHandler /* HDMI Interrupt 2*/ 60 .long SNVS_Consolidated_IRQHandler /* SRTC Consolidated Interrupt. Non TZ.*/ 61 .long SNVS_Security_IRQHandler /* SRTC Security Interrupt. TZ.*/ 62 .long CSU_IRQHandler /* CSU Interrupt Request. Indicates to the processor that one or more alarm inputs were asserted.*/ 63 .long USDHC1_IRQHandler /* uSDHC1 Enhanced SDHC Interrupt Request*/ 64 .long USDHC2_IRQHandler /* uSDHC2 Enhanced SDHC Interrupt Request*/ 65 .long DDC_IRQHandler /* DC8000 Display Controller IRQ*/ 66 .long DTRC_IRQHandler /* DTRC interrupt*/ 67 .long UART1_IRQHandler /* UART-1 ORed interrupt*/ 68 .long UART2_IRQHandler /* UART-2 ORed interrupt*/ 69 .long UART3_IRQHandler /* UART-3 ORed interrupt*/ 70 .long UART4_IRQHandler /* UART-4 ORed interrupt*/ 71 .long VP9_IRQHandler /* VP9 Decoder interrupt*/ 72 .long ECSPI1_IRQHandler /* ECSPI1 interrupt request line to the core.*/ 73 .long ECSPI2_IRQHandler /* ECSPI2 interrupt request line to the core.*/ 74 .long ECSPI3_IRQHandler /* ECSPI3 interrupt request line to the core.*/ 75 .long MIPI_DSI_IRQHandler /* DSI Interrupt*/ 76 .long I2C1_IRQHandler /* I2C-1 Interrupt*/ 77 .long I2C2_IRQHandler /* I2C-2 Interrupt*/ 78 .long I2C3_IRQHandler /* I2C-3 Interrupt*/ 79 .long I2C4_IRQHandler /* I2C-4 Interrupt*/ 80 .long RDC_IRQHandler /* RDC interrupt*/ 81 .long USB1_IRQHandler /* USB1 Interrupt*/ 82 .long USB2_IRQHandler /* USB1 Interrupt*/ 83 .long CSI1_IRQHandler /* CSI1 interrupt*/ 84 .long CSI2_IRQHandler /* CSI2 interrupt*/ 85 .long MIPI_CSI1_IRQHandler /* MIPI-CSI-1 Interrupt*/ 86 .long MIPI_CSI2_IRQHandler /* MIPI-CSI-2 Interrupt*/ 87 .long GPT6_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ 88 .long SCTR_IRQ0_IRQHandler /* ISO7816IP Interrupt 0*/ 89 .long SCTR_IRQ1_IRQHandler /* ISO7816IP Interrupt 1*/ 90 .long TEMPMON_IRQHandler /* TempSensor (Temperature alarm).*/ 91 .long I2S3_IRQHandler /* SAI3 Receive / Transmit Interrupt*/ 92 .long GPT5_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ 93 .long GPT4_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ 94 .long GPT3_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ 95 .long GPT2_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ 96 .long GPT1_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ 97 .long GPIO1_INT7_IRQHandler /* Active HIGH Interrupt from INT7 from GPIO*/ 98 .long GPIO1_INT6_IRQHandler /* Active HIGH Interrupt from INT6 from GPIO*/ 99 .long GPIO1_INT5_IRQHandler /* Active HIGH Interrupt from INT5 from GPIO*/ 100 .long GPIO1_INT4_IRQHandler /* Active HIGH Interrupt from INT4 from GPIO*/ 101 .long GPIO1_INT3_IRQHandler /* Active HIGH Interrupt from INT3 from GPIO*/ 102 .long GPIO1_INT2_IRQHandler /* Active HIGH Interrupt from INT2 from GPIO*/ 103 .long GPIO1_INT1_IRQHandler /* Active HIGH Interrupt from INT1 from GPIO*/ 104 .long GPIO1_INT0_IRQHandler /* Active HIGH Interrupt from INT0 from GPIO*/ 105 .long GPIO1_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO1 signal 0 throughout 15*/ 106 .long GPIO1_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO1 signal 16 throughout 31*/ 107 .long GPIO2_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO2 signal 0 throughout 15*/ 108 .long GPIO2_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO2 signal 16 throughout 31*/ 109 .long GPIO3_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO3 signal 0 throughout 15*/ 110 .long GPIO3_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO3 signal 16 throughout 31*/ 111 .long GPIO4_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO4 signal 0 throughout 15*/ 112 .long GPIO4_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO4 signal 16 throughout 31*/ 113 .long GPIO5_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO5 signal 0 throughout 15*/ 114 .long GPIO5_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO5 signal 16 throughout 31*/ 115 .long PCIE_CTRL2_IRQ0_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ 116 .long PCIE_CTRL2_IRQ1_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ 117 .long PCIE_CTRL2_IRQ2_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ 118 .long PCIE_CTRL2_IRQ3_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ 119 .long WDOG1_IRQHandler /* Watchdog Timer reset*/ 120 .long WDOG2_IRQHandler /* Watchdog Timer reset*/ 121 .long PCIE_CTRL2_IRQHandler /* Channels [63:32] interrupts requests*/ 122 .long PWM1_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/ 123 .long PWM2_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/ 124 .long PWM3_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/ 125 .long PWM4_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/ 126 .long CCM_IRQ1_IRQHandler /* CCM, Interrupt Request 1*/ 127 .long CCM_IRQ2_IRQHandler /* CCM, Interrupt Request 2*/ 128 .long GPC_IRQHandler /* GPC Interrupt Request 1*/ 129 .long MU_A53_IRQHandler /* Interrupt to A53*/ 130 .long SRC_IRQHandler /* SRC interrupt request*/ 131 .long I2S56_IRQHandler /* SAI5/6 Receive / Transmit Interrupt*/ 132 .long RTIC_IRQHandler /* RTIC Interrupt*/ 133 .long CPU_PerformanceUnit_IRQHandler /* Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[n]*/ 134 .long CPU_CTI_Trigger_IRQHandler /* CTI trigger outputs (internal: nCTIIRQ[n]*/ 135 .long SRC_Combined_IRQHandler /* Combined CPU wdog interrupts (4x) out of SRC.*/ 136 .long I2S1_IRQHandler /* SAI1 Receive / Transmit Interrupt*/ 137 .long I2S2_IRQHandler /* SAI2 Receive / Transmit Interrupt*/ 138 .long MU_M4_IRQHandler /* Interrupt to M4*/ 139 .long DDR_PerformanceMonitor_IRQHandler /* ddr Interrupt for performance monitor*/ 140 .long DDR_IRQHandler /* ddr Interrupt*/ 141 .long I2S4_IRQHandler /* SAI4 Receive / Transmit Interrupt*/ 142 .long CPU_Error_AXI_IRQHandler /* CPU Error indicator for AXI transaction with a write response error condition*/ 143 .long CPU_Error_L2RAM_IRQHandler /* CPU Error indicator for L2 RAM double-bit ECC error*/ 144 .long SDMA2_IRQHandler /* AND of all 48 SDMA interrupts (events) from all the channels*/ 145 .long Reserved120_IRQHandler /* Reserved*/ 146 .long CAAM_IRQ0_IRQHandler /* CAAM interrupt queue for JQ*/ 147 .long CAAM_IRQ1_IRQHandler /* CAAM interrupt queue for JQ*/ 148 .long QSPI_IRQHandler /* QSPI Interrupt*/ 149 .long TZASC_IRQHandler /* TZASC (PL380) interrupt*/ 150 .long Reserved125_IRQHandler /* Reserved*/ 151 .long Reserved126_IRQHandler /* Reserved*/ 152 .long Reserved127_IRQHandler /* Reserved*/ 153 .long PERFMON1_IRQHandler /* General Interrupt*/ 154 .long PERFMON2_IRQHandler /* General Interrupt*/ 155 .long CAAM_IRQ2_IRQHandler /* CAAM interrupt queue for JQ*/ 156 .long CAAM_ERROR_IRQHandler /* Recoverable error interrupt*/ 157 .long HS_CP0_IRQHandler /* HS Interrupt Request*/ 158 .long HEVC_IRQHandler /* HEVC interrupt*/ 159 .long ENET1_MAC0_Rx_Tx_Done1_IRQHandler /* MAC 0 Receive / Trasmit Frame / Buffer Done*/ 160 .long ENET1_MAC0_Rx_Tx_Done2_IRQHandler /* MAC 0 Receive / Trasmit Frame / Buffer Done*/ 161 .long ENET1_IRQHandler /* MAC 0 IRQ*/ 162 .long ENET1_1588_Timer_IRQHandler /* MAC 0 1588 Timer Interrupt - synchronous*/ 163 .long PCIE_CTRL1_IRQ0_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ 164 .long PCIE_CTRL1_IRQ1_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ 165 .long PCIE_CTRL1_IRQ2_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ 166 .long PCIE_CTRL1_IRQ3_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ 167 .long Reserved142_IRQHandler /* Reserved*/ 168 .long PCIE_CTRL1_IRQHandler /* Channels [63:32] interrupts requests*/ 169 170 .size __isr_vector, . - __isr_vector 171 172 .text 173 .thumb 174 175#if defined (__cplusplus) 176#ifdef __REDLIB__ 177#error Redlib does not support C++ 178#endif 179#endif 180/* Reset Handler */ 181 182 .thumb_func 183 .align 2 184 .globl Reset_Handler 185 .weak Reset_Handler 186 .type Reset_Handler, %function 187Reset_Handler: 188 cpsid i /* Mask interrupts */ 189 .equ VTOR, 0xE000ED08 190 ldr r0, =VTOR 191 ldr r1, =__isr_vector 192 str r1, [r0] 193 ldr r2, [r1] 194 msr msp, r2 195#ifndef __NO_SYSTEM_INIT 196 ldr r0,=SystemInit 197 blx r0 198#endif 199/* Loop to copy data from read only memory to RAM. The ranges 200 * of copy from/to are specified by following symbols evaluated in 201 * linker script. 202 * __etext: End of code section, i.e., begin of data sections to copy from. 203 * __data_start__/__data_end__: RAM address range that data should be 204 * __noncachedata_start__/__noncachedata_end__ : none cachable region 205 * copied to. Both must be aligned to 4 bytes boundary. */ 206 207 ldr r1, =__etext 208 ldr r2, =__data_start__ 209 ldr r3, =__data_end__ 210 211#ifdef __PERFORMANCE_IMPLEMENTATION 212/* Here are two copies of loop implementations. First one favors performance 213 * and the second one favors code size. Default uses the second one. 214 * Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */ 215 subs r3, r2 216 ble .LC1 217.LC0: 218 subs r3, #4 219 ldr r0, [r1, r3] 220 str r0, [r2, r3] 221 bgt .LC0 222.LC1: 223#else /* code size implemenation */ 224.LC0: 225 cmp r2, r3 226 ittt lt 227 ldrlt r0, [r1], #4 228 strlt r0, [r2], #4 229 blt .LC0 230#endif 231#ifdef __STARTUP_INITIALIZE_NONCACHEDATA 232 ldr r2, =__noncachedata_start__ 233 ldr r3, =__noncachedata_init_end__ 234#ifdef __PERFORMANCE_IMPLEMENTATION 235/* Here are two copies of loop implementations. First one favors performance 236 * and the second one favors code size. Default uses the second one. 237 * Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */ 238 subs r3, r2 239 ble .LC3 240.LC2: 241 subs r3, #4 242 ldr r0, [r1, r3] 243 str r0, [r2, r3] 244 bgt .LC2 245.LC3: 246#else /* code size implemenation */ 247.LC2: 248 cmp r2, r3 249 ittt lt 250 ldrlt r0, [r1], #4 251 strlt r0, [r2], #4 252 blt .LC2 253#endif 254/* zero inited ncache section initialization */ 255 ldr r3, =__noncachedata_end__ 256 movs r0,0 257.LC4: 258 cmp r2,r3 259 itt lt 260 strlt r0,[r2],#4 261 blt .LC4 262#endif /* __STARTUP_INITIALIZE_NONCACHEDATA */ 263 264#ifdef __STARTUP_CLEAR_BSS 265/* This part of work usually is done in C library startup code. Otherwise, 266 * define this macro to enable it in this startup. 267 * 268 * Loop to zero out BSS section, which uses following symbols 269 * in linker script: 270 * __bss_start__: start of BSS section. Must align to 4 271 * __bss_end__: end of BSS section. Must align to 4 272 */ 273 ldr r1, =__bss_start__ 274 ldr r2, =__bss_end__ 275 276 movs r0, 0 277.LC5: 278 cmp r1, r2 279 itt lt 280 strlt r0, [r1], #4 281 blt .LC5 282#endif /* __STARTUP_CLEAR_BSS */ 283 284 cpsie i /* Unmask interrupts */ 285#ifndef __START 286#ifdef __REDLIB__ 287#define __START __main 288#else 289#define __START _start 290#endif 291#endif 292#ifndef __ATOLLIC__ 293 ldr r0,=__START 294 blx r0 295#else 296 ldr r0,=__libc_init_array 297 blx r0 298 ldr r0,=main 299 bx r0 300#endif 301 .pool 302 .size Reset_Handler, . - Reset_Handler 303 304 .align 1 305 .thumb_func 306 .weak DefaultISR 307 .type DefaultISR, %function 308DefaultISR: 309 b DefaultISR 310 .size DefaultISR, . - DefaultISR 311 312 .align 1 313 .thumb_func 314 .weak NMI_Handler 315 .type NMI_Handler, %function 316NMI_Handler: 317 ldr r0,=NMI_Handler 318 bx r0 319 .size NMI_Handler, . - NMI_Handler 320 321 .align 1 322 .thumb_func 323 .weak HardFault_Handler 324 .type HardFault_Handler, %function 325HardFault_Handler: 326 ldr r0,=HardFault_Handler 327 bx r0 328 .size HardFault_Handler, . - HardFault_Handler 329 330 .align 1 331 .thumb_func 332 .weak SVC_Handler 333 .type SVC_Handler, %function 334SVC_Handler: 335 ldr r0,=SVC_Handler 336 bx r0 337 .size SVC_Handler, . - SVC_Handler 338 339 .align 1 340 .thumb_func 341 .weak PendSV_Handler 342 .type PendSV_Handler, %function 343PendSV_Handler: 344 ldr r0,=PendSV_Handler 345 bx r0 346 .size PendSV_Handler, . - PendSV_Handler 347 348 .align 1 349 .thumb_func 350 .weak SysTick_Handler 351 .type SysTick_Handler, %function 352SysTick_Handler: 353 ldr r0,=SysTick_Handler 354 bx r0 355 .size SysTick_Handler, . - SysTick_Handler 356 357 .align 1 358 .thumb_func 359 .weak SDMA1_IRQHandler 360 .type SDMA1_IRQHandler, %function 361SDMA1_IRQHandler: 362 ldr r0,=SDMA1_DriverIRQHandler 363 bx r0 364 .size SDMA1_IRQHandler, . - SDMA1_IRQHandler 365 366 .align 1 367 .thumb_func 368 .weak SPDIF1_IRQHandler 369 .type SPDIF1_IRQHandler, %function 370SPDIF1_IRQHandler: 371 ldr r0,=SPDIF1_DriverIRQHandler 372 bx r0 373 .size SPDIF1_IRQHandler, . - SPDIF1_IRQHandler 374 375 .align 1 376 .thumb_func 377 .weak VPUDMA_IRQHandler 378 .type VPUDMA_IRQHandler, %function 379VPUDMA_IRQHandler: 380 ldr r0,=VPUDMA_DriverIRQHandler 381 bx r0 382 .size VPUDMA_IRQHandler, . - VPUDMA_IRQHandler 383 384 .align 1 385 .thumb_func 386 .weak APBHDMA_IRQHandler 387 .type APBHDMA_IRQHandler, %function 388APBHDMA_IRQHandler: 389 ldr r0,=APBHDMA_DriverIRQHandler 390 bx r0 391 .size APBHDMA_IRQHandler, . - APBHDMA_IRQHandler 392 393 .align 1 394 .thumb_func 395 .weak SPDIF2_IRQHandler 396 .type SPDIF2_IRQHandler, %function 397SPDIF2_IRQHandler: 398 ldr r0,=SPDIF2_DriverIRQHandler 399 bx r0 400 .size SPDIF2_IRQHandler, . - SPDIF2_IRQHandler 401 402 .align 1 403 .thumb_func 404 .weak USDHC1_IRQHandler 405 .type USDHC1_IRQHandler, %function 406USDHC1_IRQHandler: 407 ldr r0,=USDHC1_DriverIRQHandler 408 bx r0 409 .size USDHC1_IRQHandler, . - USDHC1_IRQHandler 410 411 .align 1 412 .thumb_func 413 .weak USDHC2_IRQHandler 414 .type USDHC2_IRQHandler, %function 415USDHC2_IRQHandler: 416 ldr r0,=USDHC2_DriverIRQHandler 417 bx r0 418 .size USDHC2_IRQHandler, . - USDHC2_IRQHandler 419 420 .align 1 421 .thumb_func 422 .weak UART1_IRQHandler 423 .type UART1_IRQHandler, %function 424UART1_IRQHandler: 425 ldr r0,=UART1_DriverIRQHandler 426 bx r0 427 .size UART1_IRQHandler, . - UART1_IRQHandler 428 429 .align 1 430 .thumb_func 431 .weak UART2_IRQHandler 432 .type UART2_IRQHandler, %function 433UART2_IRQHandler: 434 ldr r0,=UART2_DriverIRQHandler 435 bx r0 436 .size UART2_IRQHandler, . - UART2_IRQHandler 437 438 .align 1 439 .thumb_func 440 .weak UART3_IRQHandler 441 .type UART3_IRQHandler, %function 442UART3_IRQHandler: 443 ldr r0,=UART3_DriverIRQHandler 444 bx r0 445 .size UART3_IRQHandler, . - UART3_IRQHandler 446 447 .align 1 448 .thumb_func 449 .weak UART4_IRQHandler 450 .type UART4_IRQHandler, %function 451UART4_IRQHandler: 452 ldr r0,=UART4_DriverIRQHandler 453 bx r0 454 .size UART4_IRQHandler, . - UART4_IRQHandler 455 456 .align 1 457 .thumb_func 458 .weak ECSPI1_IRQHandler 459 .type ECSPI1_IRQHandler, %function 460ECSPI1_IRQHandler: 461 ldr r0,=ECSPI1_DriverIRQHandler 462 bx r0 463 .size ECSPI1_IRQHandler, . - ECSPI1_IRQHandler 464 465 .align 1 466 .thumb_func 467 .weak ECSPI2_IRQHandler 468 .type ECSPI2_IRQHandler, %function 469ECSPI2_IRQHandler: 470 ldr r0,=ECSPI2_DriverIRQHandler 471 bx r0 472 .size ECSPI2_IRQHandler, . - ECSPI2_IRQHandler 473 474 .align 1 475 .thumb_func 476 .weak ECSPI3_IRQHandler 477 .type ECSPI3_IRQHandler, %function 478ECSPI3_IRQHandler: 479 ldr r0,=ECSPI3_DriverIRQHandler 480 bx r0 481 .size ECSPI3_IRQHandler, . - ECSPI3_IRQHandler 482 483 .align 1 484 .thumb_func 485 .weak I2C1_IRQHandler 486 .type I2C1_IRQHandler, %function 487I2C1_IRQHandler: 488 ldr r0,=I2C1_DriverIRQHandler 489 bx r0 490 .size I2C1_IRQHandler, . - I2C1_IRQHandler 491 492 .align 1 493 .thumb_func 494 .weak I2C2_IRQHandler 495 .type I2C2_IRQHandler, %function 496I2C2_IRQHandler: 497 ldr r0,=I2C2_DriverIRQHandler 498 bx r0 499 .size I2C2_IRQHandler, . - I2C2_IRQHandler 500 501 .align 1 502 .thumb_func 503 .weak I2C3_IRQHandler 504 .type I2C3_IRQHandler, %function 505I2C3_IRQHandler: 506 ldr r0,=I2C3_DriverIRQHandler 507 bx r0 508 .size I2C3_IRQHandler, . - I2C3_IRQHandler 509 510 .align 1 511 .thumb_func 512 .weak I2C4_IRQHandler 513 .type I2C4_IRQHandler, %function 514I2C4_IRQHandler: 515 ldr r0,=I2C4_DriverIRQHandler 516 bx r0 517 .size I2C4_IRQHandler, . - I2C4_IRQHandler 518 519 .align 1 520 .thumb_func 521 .weak I2S3_IRQHandler 522 .type I2S3_IRQHandler, %function 523I2S3_IRQHandler: 524 ldr r0,=I2S3_DriverIRQHandler 525 bx r0 526 .size I2S3_IRQHandler, . - I2S3_IRQHandler 527 528 .align 1 529 .thumb_func 530 .weak I2S56_IRQHandler 531 .type I2S56_IRQHandler, %function 532I2S56_IRQHandler: 533 ldr r0,=I2S56_DriverIRQHandler 534 bx r0 535 .size I2S56_IRQHandler, . - I2S56_IRQHandler 536 537 .align 1 538 .thumb_func 539 .weak I2S1_IRQHandler 540 .type I2S1_IRQHandler, %function 541I2S1_IRQHandler: 542 ldr r0,=I2S1_DriverIRQHandler 543 bx r0 544 .size I2S1_IRQHandler, . - I2S1_IRQHandler 545 546 .align 1 547 .thumb_func 548 .weak I2S2_IRQHandler 549 .type I2S2_IRQHandler, %function 550I2S2_IRQHandler: 551 ldr r0,=I2S2_DriverIRQHandler 552 bx r0 553 .size I2S2_IRQHandler, . - I2S2_IRQHandler 554 555 .align 1 556 .thumb_func 557 .weak I2S4_IRQHandler 558 .type I2S4_IRQHandler, %function 559I2S4_IRQHandler: 560 ldr r0,=I2S4_DriverIRQHandler 561 bx r0 562 .size I2S4_IRQHandler, . - I2S4_IRQHandler 563 564 .align 1 565 .thumb_func 566 .weak SDMA2_IRQHandler 567 .type SDMA2_IRQHandler, %function 568SDMA2_IRQHandler: 569 ldr r0,=SDMA2_DriverIRQHandler 570 bx r0 571 .size SDMA2_IRQHandler, . - SDMA2_IRQHandler 572 573 .align 1 574 .thumb_func 575 .weak QSPI_IRQHandler 576 .type QSPI_IRQHandler, %function 577QSPI_IRQHandler: 578 ldr r0,=QSPI_DriverIRQHandler 579 bx r0 580 .size QSPI_IRQHandler, . - QSPI_IRQHandler 581 582 .align 1 583 .thumb_func 584 .weak ENET1_MAC0_Rx_Tx_Done1_IRQHandler 585 .type ENET1_MAC0_Rx_Tx_Done1_IRQHandler, %function 586ENET1_MAC0_Rx_Tx_Done1_IRQHandler: 587 ldr r0,=ENET1_MAC0_Rx_Tx_Done1_DriverIRQHandler 588 bx r0 589 .size ENET1_MAC0_Rx_Tx_Done1_IRQHandler, . - ENET1_MAC0_Rx_Tx_Done1_IRQHandler 590 591 .align 1 592 .thumb_func 593 .weak ENET1_MAC0_Rx_Tx_Done2_IRQHandler 594 .type ENET1_MAC0_Rx_Tx_Done2_IRQHandler, %function 595ENET1_MAC0_Rx_Tx_Done2_IRQHandler: 596 ldr r0,=ENET1_MAC0_Rx_Tx_Done2_DriverIRQHandler 597 bx r0 598 .size ENET1_MAC0_Rx_Tx_Done2_IRQHandler, . - ENET1_MAC0_Rx_Tx_Done2_IRQHandler 599 600 .align 1 601 .thumb_func 602 .weak ENET1_IRQHandler 603 .type ENET1_IRQHandler, %function 604ENET1_IRQHandler: 605 ldr r0,=ENET1_DriverIRQHandler 606 bx r0 607 .size ENET1_IRQHandler, . - ENET1_IRQHandler 608 609 .align 1 610 .thumb_func 611 .weak ENET1_1588_Timer_IRQHandler 612 .type ENET1_1588_Timer_IRQHandler, %function 613ENET1_1588_Timer_IRQHandler: 614 ldr r0,=ENET1_1588_Timer_DriverIRQHandler 615 bx r0 616 .size ENET1_1588_Timer_IRQHandler, . - ENET1_1588_Timer_IRQHandler 617 618 619/* Macro to define default handlers. Default handler 620 * will be weak symbol and just dead loops. They can be 621 * overwritten by other handlers */ 622 .macro def_irq_handler handler_name 623 .weak \handler_name 624 .set \handler_name, DefaultISR 625 .endm 626/* Exception Handlers */ 627 def_irq_handler MemManage_Handler 628 def_irq_handler BusFault_Handler 629 def_irq_handler UsageFault_Handler 630 def_irq_handler DebugMon_Handler 631 def_irq_handler GPR_IRQ_IRQHandler 632 def_irq_handler DAP_IRQHandler 633 def_irq_handler SDMA1_DriverIRQHandler 634 def_irq_handler GPU_IRQHandler 635 def_irq_handler SNVS_IRQHandler 636 def_irq_handler LCDIF_IRQHandler 637 def_irq_handler SPDIF1_DriverIRQHandler 638 def_irq_handler H264_IRQHandler 639 def_irq_handler VPUDMA_DriverIRQHandler 640 def_irq_handler QOS_IRQHandler 641 def_irq_handler WDOG3_IRQHandler 642 def_irq_handler HS_CP1_IRQHandler 643 def_irq_handler APBHDMA_DriverIRQHandler 644 def_irq_handler SPDIF2_DriverIRQHandler 645 def_irq_handler BCH_IRQHandler 646 def_irq_handler GPMI_IRQHandler 647 def_irq_handler HDMI_IRQ0_IRQHandler 648 def_irq_handler HDMI_IRQ1_IRQHandler 649 def_irq_handler HDMI_IRQ2_IRQHandler 650 def_irq_handler SNVS_Consolidated_IRQHandler 651 def_irq_handler SNVS_Security_IRQHandler 652 def_irq_handler CSU_IRQHandler 653 def_irq_handler USDHC1_DriverIRQHandler 654 def_irq_handler USDHC2_DriverIRQHandler 655 def_irq_handler DDC_IRQHandler 656 def_irq_handler DTRC_IRQHandler 657 def_irq_handler UART1_DriverIRQHandler 658 def_irq_handler UART2_DriverIRQHandler 659 def_irq_handler UART3_DriverIRQHandler 660 def_irq_handler UART4_DriverIRQHandler 661 def_irq_handler VP9_IRQHandler 662 def_irq_handler ECSPI1_DriverIRQHandler 663 def_irq_handler ECSPI2_DriverIRQHandler 664 def_irq_handler ECSPI3_DriverIRQHandler 665 def_irq_handler MIPI_DSI_IRQHandler 666 def_irq_handler I2C1_DriverIRQHandler 667 def_irq_handler I2C2_DriverIRQHandler 668 def_irq_handler I2C3_DriverIRQHandler 669 def_irq_handler I2C4_DriverIRQHandler 670 def_irq_handler RDC_IRQHandler 671 def_irq_handler USB1_IRQHandler 672 def_irq_handler USB2_IRQHandler 673 def_irq_handler CSI1_IRQHandler 674 def_irq_handler CSI2_IRQHandler 675 def_irq_handler MIPI_CSI1_IRQHandler 676 def_irq_handler MIPI_CSI2_IRQHandler 677 def_irq_handler GPT6_IRQHandler 678 def_irq_handler SCTR_IRQ0_IRQHandler 679 def_irq_handler SCTR_IRQ1_IRQHandler 680 def_irq_handler TEMPMON_IRQHandler 681 def_irq_handler I2S3_DriverIRQHandler 682 def_irq_handler GPT5_IRQHandler 683 def_irq_handler GPT4_IRQHandler 684 def_irq_handler GPT3_IRQHandler 685 def_irq_handler GPT2_IRQHandler 686 def_irq_handler GPT1_IRQHandler 687 def_irq_handler GPIO1_INT7_IRQHandler 688 def_irq_handler GPIO1_INT6_IRQHandler 689 def_irq_handler GPIO1_INT5_IRQHandler 690 def_irq_handler GPIO1_INT4_IRQHandler 691 def_irq_handler GPIO1_INT3_IRQHandler 692 def_irq_handler GPIO1_INT2_IRQHandler 693 def_irq_handler GPIO1_INT1_IRQHandler 694 def_irq_handler GPIO1_INT0_IRQHandler 695 def_irq_handler GPIO1_Combined_0_15_IRQHandler 696 def_irq_handler GPIO1_Combined_16_31_IRQHandler 697 def_irq_handler GPIO2_Combined_0_15_IRQHandler 698 def_irq_handler GPIO2_Combined_16_31_IRQHandler 699 def_irq_handler GPIO3_Combined_0_15_IRQHandler 700 def_irq_handler GPIO3_Combined_16_31_IRQHandler 701 def_irq_handler GPIO4_Combined_0_15_IRQHandler 702 def_irq_handler GPIO4_Combined_16_31_IRQHandler 703 def_irq_handler GPIO5_Combined_0_15_IRQHandler 704 def_irq_handler GPIO5_Combined_16_31_IRQHandler 705 def_irq_handler PCIE_CTRL2_IRQ0_IRQHandler 706 def_irq_handler PCIE_CTRL2_IRQ1_IRQHandler 707 def_irq_handler PCIE_CTRL2_IRQ2_IRQHandler 708 def_irq_handler PCIE_CTRL2_IRQ3_IRQHandler 709 def_irq_handler WDOG1_IRQHandler 710 def_irq_handler WDOG2_IRQHandler 711 def_irq_handler PCIE_CTRL2_IRQHandler 712 def_irq_handler PWM1_IRQHandler 713 def_irq_handler PWM2_IRQHandler 714 def_irq_handler PWM3_IRQHandler 715 def_irq_handler PWM4_IRQHandler 716 def_irq_handler CCM_IRQ1_IRQHandler 717 def_irq_handler CCM_IRQ2_IRQHandler 718 def_irq_handler GPC_IRQHandler 719 def_irq_handler MU_A53_IRQHandler 720 def_irq_handler SRC_IRQHandler 721 def_irq_handler I2S56_DriverIRQHandler 722 def_irq_handler RTIC_IRQHandler 723 def_irq_handler CPU_PerformanceUnit_IRQHandler 724 def_irq_handler CPU_CTI_Trigger_IRQHandler 725 def_irq_handler SRC_Combined_IRQHandler 726 def_irq_handler I2S1_DriverIRQHandler 727 def_irq_handler I2S2_DriverIRQHandler 728 def_irq_handler MU_M4_IRQHandler 729 def_irq_handler DDR_PerformanceMonitor_IRQHandler 730 def_irq_handler DDR_IRQHandler 731 def_irq_handler I2S4_DriverIRQHandler 732 def_irq_handler CPU_Error_AXI_IRQHandler 733 def_irq_handler CPU_Error_L2RAM_IRQHandler 734 def_irq_handler SDMA2_DriverIRQHandler 735 def_irq_handler Reserved120_IRQHandler 736 def_irq_handler CAAM_IRQ0_IRQHandler 737 def_irq_handler CAAM_IRQ1_IRQHandler 738 def_irq_handler QSPI_DriverIRQHandler 739 def_irq_handler TZASC_IRQHandler 740 def_irq_handler Reserved125_IRQHandler 741 def_irq_handler Reserved126_IRQHandler 742 def_irq_handler Reserved127_IRQHandler 743 def_irq_handler PERFMON1_IRQHandler 744 def_irq_handler PERFMON2_IRQHandler 745 def_irq_handler CAAM_IRQ2_IRQHandler 746 def_irq_handler CAAM_ERROR_IRQHandler 747 def_irq_handler HS_CP0_IRQHandler 748 def_irq_handler HEVC_IRQHandler 749 def_irq_handler ENET1_MAC0_Rx_Tx_Done1_DriverIRQHandler 750 def_irq_handler ENET1_MAC0_Rx_Tx_Done2_DriverIRQHandler 751 def_irq_handler ENET1_DriverIRQHandler 752 def_irq_handler ENET1_1588_Timer_DriverIRQHandler 753 def_irq_handler PCIE_CTRL1_IRQ0_IRQHandler 754 def_irq_handler PCIE_CTRL1_IRQ1_IRQHandler 755 def_irq_handler PCIE_CTRL1_IRQ2_IRQHandler 756 def_irq_handler PCIE_CTRL1_IRQ3_IRQHandler 757 def_irq_handler Reserved142_IRQHandler 758 def_irq_handler PCIE_CTRL1_IRQHandler 759 760 .end 761
