1/* ------------------------------------------------------------------------- */ 2/* @file: startup_MIMX8MM5_cm4.s */ 3/* @purpose: CMSIS Cortex-M4 Core Device Startup File */ 4/* MIMX8MM5_cm4 */ 5/* @version: 4.0 */ 6/* @date: 2019-2-18 */ 7/* @build: b220622 */ 8/* ------------------------------------------------------------------------- */ 9/* */ 10/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ 11/* Copyright 2016-2022 NXP */ 12/* All rights reserved. */ 13/* */ 14/* SPDX-License-Identifier: BSD-3-Clause */ 15/*****************************************************************************/ 16/* Version: GCC for ARM Embedded Processors */ 17/*****************************************************************************/ 18 .syntax unified 19 .arch armv7-m 20 21 .section .isr_vector, "a" 22 .align 2 23 .globl __isr_vector 24__isr_vector: 25 .long __StackTop /* Top of Stack */ 26 .long Reset_Handler /* Reset Handler */ 27 .long NMI_Handler /* NMI Handler*/ 28 .long HardFault_Handler /* Hard Fault Handler*/ 29 .long MemManage_Handler /* MPU Fault Handler*/ 30 .long BusFault_Handler /* Bus Fault Handler*/ 31 .long UsageFault_Handler /* Usage Fault Handler*/ 32 .long 0 /* Reserved*/ 33 .long 0 /* Reserved*/ 34 .long 0 /* Reserved*/ 35 .long 0 /* Reserved*/ 36 .long SVC_Handler /* SVCall Handler*/ 37 .long DebugMon_Handler /* Debug Monitor Handler*/ 38 .long 0 /* Reserved*/ 39 .long PendSV_Handler /* PendSV Handler*/ 40 .long SysTick_Handler /* SysTick Handler*/ 41 42 /* External Interrupts*/ 43 .long GPR_IRQ_IRQHandler /* GPR Interrupt. Used to notify cores on exception condition while boot.*/ 44 .long DAP_IRQHandler /* DAP Interrupt*/ 45 .long SDMA1_IRQHandler /* AND of all 48 SDMA1 interrupts (events) from all the channels*/ 46 .long GPU3D_IRQHandler /* GPU3D Interrupt*/ 47 .long SNVS_IRQHandler /* ON-OFF button press shorter than 5 seconds (pulse event)*/ 48 .long LCDIF_IRQHandler /* LCDIF Interrupt*/ 49 .long SPDIF1_IRQHandler /* SPDIF1 RZX/TX Interrupt*/ 50 .long VPU_G1_IRQHandler /* VPU G1 Decoder Interrupt*/ 51 .long VPU_G2_IRQHandler /* VPU G2 Decoder Interrupt*/ 52 .long QOS_IRQHandler /* QOS interrupt*/ 53 .long WDOG3_IRQHandler /* Watchdog Timer reset*/ 54 .long HS_CP1_IRQHandler /* HS Interrupt Request*/ 55 .long APBHDMA_IRQHandler /* GPMI operation channel 0-3 description complete interrupt*/ 56 .long Reserved29_IRQHandler /* Reserved*/ 57 .long BCH_IRQHandler /* BCH operation complete interrupt*/ 58 .long GPMI_IRQHandler /* GPMI operation TIMEOUT ERROR interrupt*/ 59 .long CSI1_IRQHandler /* CSI Interrupt*/ 60 .long MIPI_CSI1_IRQHandler /* MIPI CSI Interrupt*/ 61 .long MIPI_DSI_IRQHandler /* MIPI DSI Interrupt*/ 62 .long SNVS_Consolidated_IRQHandler /* SRTC Consolidated Interrupt. Non TZ.*/ 63 .long SNVS_Security_IRQHandler /* SRTC Security Interrupt. TZ.*/ 64 .long CSU_IRQHandler /* CSU Interrupt Request. Indicates to the processor that one or more alarm inputs were asserted.*/ 65 .long USDHC1_IRQHandler /* uSDHC1 Enhanced SDHC Interrupt Request*/ 66 .long USDHC2_IRQHandler /* uSDHC2 Enhanced SDHC Interrupt Request*/ 67 .long USDHC3_IRQHandler /* uSDHC3 Enhanced SDHC Interrupt Request*/ 68 .long GPU2D_IRQHandler /* GPU2D Interrupt*/ 69 .long UART1_IRQHandler /* UART-1 ORed interrupt*/ 70 .long UART2_IRQHandler /* UART-2 ORed interrupt*/ 71 .long UART3_IRQHandler /* UART-3 ORed interrupt*/ 72 .long UART4_IRQHandler /* UART-4 ORed interrupt*/ 73 .long VPU_H1_IRQHandler /* VPU H1 Encoder Interrupt*/ 74 .long ECSPI1_IRQHandler /* ECSPI1 interrupt request line to the core.*/ 75 .long ECSPI2_IRQHandler /* ECSPI2 interrupt request line to the core.*/ 76 .long ECSPI3_IRQHandler /* ECSPI3 interrupt request line to the core.*/ 77 .long SDMA3_IRQHandler /* AND of all 48 SDMA3 interrupts (events) from all the channels*/ 78 .long I2C1_IRQHandler /* I2C-1 Interrupt*/ 79 .long I2C2_IRQHandler /* I2C-2 Interrupt*/ 80 .long I2C3_IRQHandler /* I2C-3 Interrupt*/ 81 .long I2C4_IRQHandler /* I2C-4 Interrupt*/ 82 .long RDC_IRQHandler /* RDC interrupt*/ 83 .long USB1_IRQHandler /* USB1 Interrupt*/ 84 .long USB2_IRQHandler /* USB1 Interrupt*/ 85 .long Reserved58_IRQHandler /* Reserved interrupt*/ 86 .long Reserved59_IRQHandler /* Reserved interrupt*/ 87 .long PDM_HWVAD_EVENT_IRQHandler /* Digital Microphone interface voice activity detector event interrupt*/ 88 .long PDM_HWVAD_ERROR_IRQHandler /* Digital Microphone interface voice activity detector error interrupt*/ 89 .long GPT6_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ 90 .long SCTR_IRQ0_IRQHandler /* System Counter Interrupt 0*/ 91 .long SCTR_IRQ1_IRQHandler /* System Counter Interrupt 1*/ 92 .long TEMPMON_LOW_IRQHandler /* TempSensor (Temperature low alarm).*/ 93 .long I2S3_IRQHandler /* SAI3 Receive / Transmit Interrupt*/ 94 .long GPT5_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ 95 .long GPT4_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ 96 .long GPT3_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ 97 .long GPT2_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ 98 .long GPT1_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ 99 .long GPIO1_INT7_IRQHandler /* Active HIGH Interrupt from INT7 from GPIO*/ 100 .long GPIO1_INT6_IRQHandler /* Active HIGH Interrupt from INT6 from GPIO*/ 101 .long GPIO1_INT5_IRQHandler /* Active HIGH Interrupt from INT5 from GPIO*/ 102 .long GPIO1_INT4_IRQHandler /* Active HIGH Interrupt from INT4 from GPIO*/ 103 .long GPIO1_INT3_IRQHandler /* Active HIGH Interrupt from INT3 from GPIO*/ 104 .long GPIO1_INT2_IRQHandler /* Active HIGH Interrupt from INT2 from GPIO*/ 105 .long GPIO1_INT1_IRQHandler /* Active HIGH Interrupt from INT1 from GPIO*/ 106 .long GPIO1_INT0_IRQHandler /* Active HIGH Interrupt from INT0 from GPIO*/ 107 .long GPIO1_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO1 signal 0 throughout 15*/ 108 .long GPIO1_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO1 signal 16 throughout 31*/ 109 .long GPIO2_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO2 signal 0 throughout 15*/ 110 .long GPIO2_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO2 signal 16 throughout 31*/ 111 .long GPIO3_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO3 signal 0 throughout 15*/ 112 .long GPIO3_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO3 signal 16 throughout 31*/ 113 .long GPIO4_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO4 signal 0 throughout 15*/ 114 .long GPIO4_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO4 signal 16 throughout 31*/ 115 .long GPIO5_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO5 signal 0 throughout 15*/ 116 .long GPIO5_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO5 signal 16 throughout 31*/ 117 .long Reserved90_IRQHandler /* Reserved interrupt*/ 118 .long Reserved91_IRQHandler /* Reserved interrupt*/ 119 .long Reserved92_IRQHandler /* Reserved interrupt*/ 120 .long Reserved93_IRQHandler /* Reserved interrupt*/ 121 .long WDOG1_IRQHandler /* Watchdog Timer reset*/ 122 .long WDOG2_IRQHandler /* Watchdog Timer reset*/ 123 .long Reserved96_IRQHandler /* Reserved interrupt*/ 124 .long PWM1_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/ 125 .long PWM2_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/ 126 .long PWM3_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/ 127 .long PWM4_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/ 128 .long CCM_IRQ1_IRQHandler /* CCM Interrupt Request 1*/ 129 .long CCM_IRQ2_IRQHandler /* CCM Interrupt Request 2*/ 130 .long GPC_IRQHandler /* GPC Interrupt Request 1*/ 131 .long MU_A53_IRQHandler /* Interrupt to A53*/ 132 .long SRC_IRQHandler /* SRC interrupt request*/ 133 .long I2S56_IRQHandler /* SAI5/6 Receive / Transmit Interrupt*/ 134 .long RTIC_IRQHandler /* RTIC Interrupt*/ 135 .long CPU_PerformanceUnit_IRQHandler /* Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[n]*/ 136 .long CPU_CTI_Trigger_IRQHandler /* CTI trigger outputs (internal: nCTIIRQ[n]*/ 137 .long SRC_Combined_IRQHandler /* Combined CPU wdog interrupts (4x) out of SRC.*/ 138 .long I2S1_IRQHandler /* SAI1 Receive / Transmit Interrupt*/ 139 .long I2S2_IRQHandler /* SAI2 Receive / Transmit Interrupt*/ 140 .long MU_M4_IRQHandler /* Interrupt to M4*/ 141 .long DDR_PerformanceMonitor_IRQHandler /* ddr Interrupt for performance monitor*/ 142 .long DDR_IRQHandler /* ddr Interrupt*/ 143 .long Reserved116_IRQHandler /* Reserved interrupt*/ 144 .long CPU_Error_AXI_IRQHandler /* CPU Error indicator for AXI transaction with a write response error condition*/ 145 .long CPU_Error_L2RAM_IRQHandler /* CPU Error indicator for L2 RAM double-bit ECC error*/ 146 .long SDMA2_IRQHandler /* AND of all 48 SDMA2 interrupts (events) from all the channels*/ 147 .long SJC_IRQHandler /* Interrupt triggered by SJC register*/ 148 .long CAAM_IRQ0_IRQHandler /* CAAM interrupt queue for JQ*/ 149 .long CAAM_IRQ1_IRQHandler /* CAAM interrupt queue for JQ*/ 150 .long QSPI_IRQHandler /* QSPI Interrupt*/ 151 .long TZASC_IRQHandler /* TZASC (PL380) interrupt*/ 152 .long PDM_EVENT_IRQHandler /* Digital Microphone interface interrupt*/ 153 .long PDM_ERROR_IRQHandler /* Digital Microphone interface error interrupt*/ 154 .long Reserved127_IRQHandler /* Reserved interrupt*/ 155 .long PERFMON1_IRQHandler /* General Interrupt*/ 156 .long PERFMON2_IRQHandler /* General Interrupt*/ 157 .long CAAM_IRQ2_IRQHandler /* CAAM interrupt queue for JQ*/ 158 .long CAAM_ERROR_IRQHandler /* Recoverable error interrupt*/ 159 .long HS_CP0_IRQHandler /* HS Interrupt Request*/ 160 .long Reserved133_IRQHandler /* Reserved interrupt*/ 161 .long ENET1_MAC0_Rx_Tx_Done1_IRQHandler /* MAC 0 Receive / Trasmit Frame / Buffer Done*/ 162 .long ENET1_MAC0_Rx_Tx_Done2_IRQHandler /* MAC 0 Receive / Trasmit Frame / Buffer Done*/ 163 .long ENET1_IRQHandler /* MAC 0 IRQ*/ 164 .long ENET1_1588_Timer_IRQHandler /* MAC 0 1588 Timer Interrupt - synchronous*/ 165 .long PCIE_CTRL1_IRQ0_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ 166 .long PCIE_CTRL1_IRQ1_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ 167 .long PCIE_CTRL1_IRQ2_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ 168 .long PCIE_CTRL1_IRQ3_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ 169 .long Reserved142_IRQHandler /* Reserved*/ 170 .long PCIE_CTRL1_IRQHandler /* Channels [63:32] interrupts requests*/ 171 172 .size __isr_vector, . - __isr_vector 173 174 .text 175 .thumb 176 177/* Reset Handler */ 178 179 .thumb_func 180 .align 2 181 .globl Reset_Handler 182 .weak Reset_Handler 183 .type Reset_Handler, %function 184Reset_Handler: 185 cpsid i /* Mask interrupts */ 186 .equ VTOR, 0xE000ED08 187 ldr r0, =VTOR 188 ldr r1, =__isr_vector 189 str r1, [r0] 190 ldr r2, [r1] 191 msr msp, r2 192#ifndef __NO_SYSTEM_INIT 193 ldr r0,=SystemInit 194 blx r0 195#endif 196/* Loop to copy data from read only memory to RAM. The ranges 197 * of copy from/to are specified by following symbols evaluated in 198 * linker script. 199 * __etext: End of code section, i.e., begin of data sections to copy from. 200 * __data_start__/__data_end__: RAM address range that data should be 201 * __noncachedata_start__/__noncachedata_end__ : none cachable region 202 * copied to. Both must be aligned to 4 bytes boundary. */ 203 204 ldr r1, =__etext 205 ldr r2, =__data_start__ 206 ldr r3, =__data_end__ 207 208#if 1 209/* Here are two copies of loop implemenations. First one favors code size 210 * and the second one favors performance. Default uses the first one. 211 * Change to "#if 0" to use the second one */ 212.LC0: 213 cmp r2, r3 214 ittt lt 215 ldrlt r0, [r1], #4 216 strlt r0, [r2], #4 217 blt .LC0 218#else 219 subs r3, r2 220 ble .LC1 221.LC0: 222 subs r3, #4 223 ldr r0, [r1, r3] 224 str r0, [r2, r3] 225 bgt .LC0 226.LC1: 227#endif 228 229#ifdef __STARTUP_INITIALIZE_NONCACHEDATA 230 ldr r2, =__noncachedata_start__ 231 ldr r3, =__noncachedata_init_end__ 232#if 1 233.LC2: 234 cmp r2, r3 235 ittt lt 236 ldrlt r0, [r1], #4 237 strlt r0, [r2], #4 238 blt .LC2 239#else 240 subs r3, r2 241 ble .LC3 242.LC2: 243 subs r3, #4 244 ldr r0, [r1, r3] 245 str r0, [r2, r3] 246 bgt .LC2 247.LC3: 248#endif 249/* zero inited ncache section initialization */ 250 ldr r3, =__noncachedata_end__ 251 movs r0,0 252.LC4: 253 cmp r2,r3 254 itt lt 255 strlt r0,[r2],#4 256 blt .LC4 257#endif /* __STARTUP_INITIALIZE_NONCACHEDATA */ 258 259#ifdef __STARTUP_CLEAR_BSS 260/* This part of work usually is done in C library startup code. Otherwise, 261 * define this macro to enable it in this startup. 262 * 263 * Loop to zero out BSS section, which uses following symbols 264 * in linker script: 265 * __bss_start__: start of BSS section. Must align to 4 266 * __bss_end__: end of BSS section. Must align to 4 267 */ 268 ldr r1, =__bss_start__ 269 ldr r2, =__bss_end__ 270 271 movs r0, 0 272.LC5: 273 cmp r1, r2 274 itt lt 275 strlt r0, [r1], #4 276 blt .LC5 277#endif /* __STARTUP_CLEAR_BSS */ 278 279 cpsie i /* Unmask interrupts */ 280#ifndef __START 281#define __START _start 282#endif 283#ifndef __ATOLLIC__ 284 ldr r0,=__START 285 blx r0 286#else 287 ldr r0,=__libc_init_array 288 blx r0 289 ldr r0,=main 290 bx r0 291#endif 292 .pool 293 .size Reset_Handler, . - Reset_Handler 294 295 .align 1 296 .thumb_func 297 .weak DefaultISR 298 .type DefaultISR, %function 299DefaultISR: 300 b DefaultISR 301 .size DefaultISR, . - DefaultISR 302 303 .align 1 304 .thumb_func 305 .weak NMI_Handler 306 .type NMI_Handler, %function 307NMI_Handler: 308 ldr r0,=NMI_Handler 309 bx r0 310 .size NMI_Handler, . - NMI_Handler 311 312 .align 1 313 .thumb_func 314 .weak HardFault_Handler 315 .type HardFault_Handler, %function 316HardFault_Handler: 317 ldr r0,=HardFault_Handler 318 bx r0 319 .size HardFault_Handler, . - HardFault_Handler 320 321 .align 1 322 .thumb_func 323 .weak SVC_Handler 324 .type SVC_Handler, %function 325SVC_Handler: 326 ldr r0,=SVC_Handler 327 bx r0 328 .size SVC_Handler, . - SVC_Handler 329 330 .align 1 331 .thumb_func 332 .weak PendSV_Handler 333 .type PendSV_Handler, %function 334PendSV_Handler: 335 ldr r0,=PendSV_Handler 336 bx r0 337 .size PendSV_Handler, . - PendSV_Handler 338 339 .align 1 340 .thumb_func 341 .weak SysTick_Handler 342 .type SysTick_Handler, %function 343SysTick_Handler: 344 ldr r0,=SysTick_Handler 345 bx r0 346 .size SysTick_Handler, . - SysTick_Handler 347 348 .align 1 349 .thumb_func 350 .weak SDMA1_IRQHandler 351 .type SDMA1_IRQHandler, %function 352SDMA1_IRQHandler: 353 ldr r0,=SDMA1_DriverIRQHandler 354 bx r0 355 .size SDMA1_IRQHandler, . - SDMA1_IRQHandler 356 357 .align 1 358 .thumb_func 359 .weak SPDIF1_IRQHandler 360 .type SPDIF1_IRQHandler, %function 361SPDIF1_IRQHandler: 362 ldr r0,=SPDIF1_DriverIRQHandler 363 bx r0 364 .size SPDIF1_IRQHandler, . - SPDIF1_IRQHandler 365 366 .align 1 367 .thumb_func 368 .weak APBHDMA_IRQHandler 369 .type APBHDMA_IRQHandler, %function 370APBHDMA_IRQHandler: 371 ldr r0,=APBHDMA_DriverIRQHandler 372 bx r0 373 .size APBHDMA_IRQHandler, . - APBHDMA_IRQHandler 374 375 .align 1 376 .thumb_func 377 .weak USDHC1_IRQHandler 378 .type USDHC1_IRQHandler, %function 379USDHC1_IRQHandler: 380 ldr r0,=USDHC1_DriverIRQHandler 381 bx r0 382 .size USDHC1_IRQHandler, . - USDHC1_IRQHandler 383 384 .align 1 385 .thumb_func 386 .weak USDHC2_IRQHandler 387 .type USDHC2_IRQHandler, %function 388USDHC2_IRQHandler: 389 ldr r0,=USDHC2_DriverIRQHandler 390 bx r0 391 .size USDHC2_IRQHandler, . - USDHC2_IRQHandler 392 393 .align 1 394 .thumb_func 395 .weak USDHC3_IRQHandler 396 .type USDHC3_IRQHandler, %function 397USDHC3_IRQHandler: 398 ldr r0,=USDHC3_DriverIRQHandler 399 bx r0 400 .size USDHC3_IRQHandler, . - USDHC3_IRQHandler 401 402 .align 1 403 .thumb_func 404 .weak UART1_IRQHandler 405 .type UART1_IRQHandler, %function 406UART1_IRQHandler: 407 ldr r0,=UART1_DriverIRQHandler 408 bx r0 409 .size UART1_IRQHandler, . - UART1_IRQHandler 410 411 .align 1 412 .thumb_func 413 .weak UART2_IRQHandler 414 .type UART2_IRQHandler, %function 415UART2_IRQHandler: 416 ldr r0,=UART2_DriverIRQHandler 417 bx r0 418 .size UART2_IRQHandler, . - UART2_IRQHandler 419 420 .align 1 421 .thumb_func 422 .weak UART3_IRQHandler 423 .type UART3_IRQHandler, %function 424UART3_IRQHandler: 425 ldr r0,=UART3_DriverIRQHandler 426 bx r0 427 .size UART3_IRQHandler, . - UART3_IRQHandler 428 429 .align 1 430 .thumb_func 431 .weak UART4_IRQHandler 432 .type UART4_IRQHandler, %function 433UART4_IRQHandler: 434 ldr r0,=UART4_DriverIRQHandler 435 bx r0 436 .size UART4_IRQHandler, . - UART4_IRQHandler 437 438 .align 1 439 .thumb_func 440 .weak ECSPI1_IRQHandler 441 .type ECSPI1_IRQHandler, %function 442ECSPI1_IRQHandler: 443 ldr r0,=ECSPI1_DriverIRQHandler 444 bx r0 445 .size ECSPI1_IRQHandler, . - ECSPI1_IRQHandler 446 447 .align 1 448 .thumb_func 449 .weak ECSPI2_IRQHandler 450 .type ECSPI2_IRQHandler, %function 451ECSPI2_IRQHandler: 452 ldr r0,=ECSPI2_DriverIRQHandler 453 bx r0 454 .size ECSPI2_IRQHandler, . - ECSPI2_IRQHandler 455 456 .align 1 457 .thumb_func 458 .weak ECSPI3_IRQHandler 459 .type ECSPI3_IRQHandler, %function 460ECSPI3_IRQHandler: 461 ldr r0,=ECSPI3_DriverIRQHandler 462 bx r0 463 .size ECSPI3_IRQHandler, . - ECSPI3_IRQHandler 464 465 .align 1 466 .thumb_func 467 .weak SDMA3_IRQHandler 468 .type SDMA3_IRQHandler, %function 469SDMA3_IRQHandler: 470 ldr r0,=SDMA3_DriverIRQHandler 471 bx r0 472 .size SDMA3_IRQHandler, . - SDMA3_IRQHandler 473 474 .align 1 475 .thumb_func 476 .weak I2C1_IRQHandler 477 .type I2C1_IRQHandler, %function 478I2C1_IRQHandler: 479 ldr r0,=I2C1_DriverIRQHandler 480 bx r0 481 .size I2C1_IRQHandler, . - I2C1_IRQHandler 482 483 .align 1 484 .thumb_func 485 .weak I2C2_IRQHandler 486 .type I2C2_IRQHandler, %function 487I2C2_IRQHandler: 488 ldr r0,=I2C2_DriverIRQHandler 489 bx r0 490 .size I2C2_IRQHandler, . - I2C2_IRQHandler 491 492 .align 1 493 .thumb_func 494 .weak I2C3_IRQHandler 495 .type I2C3_IRQHandler, %function 496I2C3_IRQHandler: 497 ldr r0,=I2C3_DriverIRQHandler 498 bx r0 499 .size I2C3_IRQHandler, . - I2C3_IRQHandler 500 501 .align 1 502 .thumb_func 503 .weak I2C4_IRQHandler 504 .type I2C4_IRQHandler, %function 505I2C4_IRQHandler: 506 ldr r0,=I2C4_DriverIRQHandler 507 bx r0 508 .size I2C4_IRQHandler, . - I2C4_IRQHandler 509 510 .align 1 511 .thumb_func 512 .weak PDM_HWVAD_EVENT_IRQHandler 513 .type PDM_HWVAD_EVENT_IRQHandler, %function 514PDM_HWVAD_EVENT_IRQHandler: 515 ldr r0,=PDM_HWVAD_EVENT_DriverIRQHandler 516 bx r0 517 .size PDM_HWVAD_EVENT_IRQHandler, . - PDM_HWVAD_EVENT_IRQHandler 518 519 .align 1 520 .thumb_func 521 .weak PDM_HWVAD_ERROR_IRQHandler 522 .type PDM_HWVAD_ERROR_IRQHandler, %function 523PDM_HWVAD_ERROR_IRQHandler: 524 ldr r0,=PDM_HWVAD_ERROR_DriverIRQHandler 525 bx r0 526 .size PDM_HWVAD_ERROR_IRQHandler, . - PDM_HWVAD_ERROR_IRQHandler 527 528 .align 1 529 .thumb_func 530 .weak I2S3_IRQHandler 531 .type I2S3_IRQHandler, %function 532I2S3_IRQHandler: 533 ldr r0,=I2S3_DriverIRQHandler 534 bx r0 535 .size I2S3_IRQHandler, . - I2S3_IRQHandler 536 537 .align 1 538 .thumb_func 539 .weak I2S56_IRQHandler 540 .type I2S56_IRQHandler, %function 541I2S56_IRQHandler: 542 ldr r0,=I2S56_DriverIRQHandler 543 bx r0 544 .size I2S56_IRQHandler, . - I2S56_IRQHandler 545 546 .align 1 547 .thumb_func 548 .weak I2S1_IRQHandler 549 .type I2S1_IRQHandler, %function 550I2S1_IRQHandler: 551 ldr r0,=I2S1_DriverIRQHandler 552 bx r0 553 .size I2S1_IRQHandler, . - I2S1_IRQHandler 554 555 .align 1 556 .thumb_func 557 .weak I2S2_IRQHandler 558 .type I2S2_IRQHandler, %function 559I2S2_IRQHandler: 560 ldr r0,=I2S2_DriverIRQHandler 561 bx r0 562 .size I2S2_IRQHandler, . - I2S2_IRQHandler 563 564 .align 1 565 .thumb_func 566 .weak SDMA2_IRQHandler 567 .type SDMA2_IRQHandler, %function 568SDMA2_IRQHandler: 569 ldr r0,=SDMA2_DriverIRQHandler 570 bx r0 571 .size SDMA2_IRQHandler, . - SDMA2_IRQHandler 572 573 .align 1 574 .thumb_func 575 .weak QSPI_IRQHandler 576 .type QSPI_IRQHandler, %function 577QSPI_IRQHandler: 578 ldr r0,=QSPI_DriverIRQHandler 579 bx r0 580 .size QSPI_IRQHandler, . - QSPI_IRQHandler 581 582 .align 1 583 .thumb_func 584 .weak PDM_EVENT_IRQHandler 585 .type PDM_EVENT_IRQHandler, %function 586PDM_EVENT_IRQHandler: 587 ldr r0,=PDM_EVENT_DriverIRQHandler 588 bx r0 589 .size PDM_EVENT_IRQHandler, . - PDM_EVENT_IRQHandler 590 591 .align 1 592 .thumb_func 593 .weak ENET1_MAC0_Rx_Tx_Done1_IRQHandler 594 .type ENET1_MAC0_Rx_Tx_Done1_IRQHandler, %function 595ENET1_MAC0_Rx_Tx_Done1_IRQHandler: 596 ldr r0,=ENET1_MAC0_Rx_Tx_Done1_DriverIRQHandler 597 bx r0 598 .size ENET1_MAC0_Rx_Tx_Done1_IRQHandler, . - ENET1_MAC0_Rx_Tx_Done1_IRQHandler 599 600 .align 1 601 .thumb_func 602 .weak ENET1_MAC0_Rx_Tx_Done2_IRQHandler 603 .type ENET1_MAC0_Rx_Tx_Done2_IRQHandler, %function 604ENET1_MAC0_Rx_Tx_Done2_IRQHandler: 605 ldr r0,=ENET1_MAC0_Rx_Tx_Done2_DriverIRQHandler 606 bx r0 607 .size ENET1_MAC0_Rx_Tx_Done2_IRQHandler, . - ENET1_MAC0_Rx_Tx_Done2_IRQHandler 608 609 .align 1 610 .thumb_func 611 .weak ENET1_IRQHandler 612 .type ENET1_IRQHandler, %function 613ENET1_IRQHandler: 614 ldr r0,=ENET1_DriverIRQHandler 615 bx r0 616 .size ENET1_IRQHandler, . - ENET1_IRQHandler 617 618 .align 1 619 .thumb_func 620 .weak ENET1_1588_Timer_IRQHandler 621 .type ENET1_1588_Timer_IRQHandler, %function 622ENET1_1588_Timer_IRQHandler: 623 ldr r0,=ENET1_1588_Timer_DriverIRQHandler 624 bx r0 625 .size ENET1_1588_Timer_IRQHandler, . - ENET1_1588_Timer_IRQHandler 626 627 628/* Macro to define default handlers. Default handler 629 * will be weak symbol and just dead loops. They can be 630 * overwritten by other handlers */ 631 .macro def_irq_handler handler_name 632 .weak \handler_name 633 .set \handler_name, DefaultISR 634 .endm 635/* Exception Handlers */ 636 def_irq_handler MemManage_Handler 637 def_irq_handler BusFault_Handler 638 def_irq_handler UsageFault_Handler 639 def_irq_handler DebugMon_Handler 640 def_irq_handler GPR_IRQ_IRQHandler 641 def_irq_handler DAP_IRQHandler 642 def_irq_handler SDMA1_DriverIRQHandler 643 def_irq_handler GPU3D_IRQHandler 644 def_irq_handler SNVS_IRQHandler 645 def_irq_handler LCDIF_IRQHandler 646 def_irq_handler SPDIF1_DriverIRQHandler 647 def_irq_handler VPU_G1_IRQHandler 648 def_irq_handler VPU_G2_IRQHandler 649 def_irq_handler QOS_IRQHandler 650 def_irq_handler WDOG3_IRQHandler 651 def_irq_handler HS_CP1_IRQHandler 652 def_irq_handler APBHDMA_DriverIRQHandler 653 def_irq_handler Reserved29_IRQHandler 654 def_irq_handler BCH_IRQHandler 655 def_irq_handler GPMI_IRQHandler 656 def_irq_handler CSI1_IRQHandler 657 def_irq_handler MIPI_CSI1_IRQHandler 658 def_irq_handler MIPI_DSI_IRQHandler 659 def_irq_handler SNVS_Consolidated_IRQHandler 660 def_irq_handler SNVS_Security_IRQHandler 661 def_irq_handler CSU_IRQHandler 662 def_irq_handler USDHC1_DriverIRQHandler 663 def_irq_handler USDHC2_DriverIRQHandler 664 def_irq_handler USDHC3_DriverIRQHandler 665 def_irq_handler GPU2D_IRQHandler 666 def_irq_handler UART1_DriverIRQHandler 667 def_irq_handler UART2_DriverIRQHandler 668 def_irq_handler UART3_DriverIRQHandler 669 def_irq_handler UART4_DriverIRQHandler 670 def_irq_handler VPU_H1_IRQHandler 671 def_irq_handler ECSPI1_DriverIRQHandler 672 def_irq_handler ECSPI2_DriverIRQHandler 673 def_irq_handler ECSPI3_DriverIRQHandler 674 def_irq_handler SDMA3_DriverIRQHandler 675 def_irq_handler I2C1_DriverIRQHandler 676 def_irq_handler I2C2_DriverIRQHandler 677 def_irq_handler I2C3_DriverIRQHandler 678 def_irq_handler I2C4_DriverIRQHandler 679 def_irq_handler RDC_IRQHandler 680 def_irq_handler USB1_IRQHandler 681 def_irq_handler USB2_IRQHandler 682 def_irq_handler Reserved58_IRQHandler 683 def_irq_handler Reserved59_IRQHandler 684 def_irq_handler PDM_HWVAD_EVENT_DriverIRQHandler 685 def_irq_handler PDM_HWVAD_ERROR_DriverIRQHandler 686 def_irq_handler GPT6_IRQHandler 687 def_irq_handler SCTR_IRQ0_IRQHandler 688 def_irq_handler SCTR_IRQ1_IRQHandler 689 def_irq_handler TEMPMON_LOW_IRQHandler 690 def_irq_handler I2S3_DriverIRQHandler 691 def_irq_handler GPT5_IRQHandler 692 def_irq_handler GPT4_IRQHandler 693 def_irq_handler GPT3_IRQHandler 694 def_irq_handler GPT2_IRQHandler 695 def_irq_handler GPT1_IRQHandler 696 def_irq_handler GPIO1_INT7_IRQHandler 697 def_irq_handler GPIO1_INT6_IRQHandler 698 def_irq_handler GPIO1_INT5_IRQHandler 699 def_irq_handler GPIO1_INT4_IRQHandler 700 def_irq_handler GPIO1_INT3_IRQHandler 701 def_irq_handler GPIO1_INT2_IRQHandler 702 def_irq_handler GPIO1_INT1_IRQHandler 703 def_irq_handler GPIO1_INT0_IRQHandler 704 def_irq_handler GPIO1_Combined_0_15_IRQHandler 705 def_irq_handler GPIO1_Combined_16_31_IRQHandler 706 def_irq_handler GPIO2_Combined_0_15_IRQHandler 707 def_irq_handler GPIO2_Combined_16_31_IRQHandler 708 def_irq_handler GPIO3_Combined_0_15_IRQHandler 709 def_irq_handler GPIO3_Combined_16_31_IRQHandler 710 def_irq_handler GPIO4_Combined_0_15_IRQHandler 711 def_irq_handler GPIO4_Combined_16_31_IRQHandler 712 def_irq_handler GPIO5_Combined_0_15_IRQHandler 713 def_irq_handler GPIO5_Combined_16_31_IRQHandler 714 def_irq_handler Reserved90_IRQHandler 715 def_irq_handler Reserved91_IRQHandler 716 def_irq_handler Reserved92_IRQHandler 717 def_irq_handler Reserved93_IRQHandler 718 def_irq_handler WDOG1_IRQHandler 719 def_irq_handler WDOG2_IRQHandler 720 def_irq_handler Reserved96_IRQHandler 721 def_irq_handler PWM1_IRQHandler 722 def_irq_handler PWM2_IRQHandler 723 def_irq_handler PWM3_IRQHandler 724 def_irq_handler PWM4_IRQHandler 725 def_irq_handler CCM_IRQ1_IRQHandler 726 def_irq_handler CCM_IRQ2_IRQHandler 727 def_irq_handler GPC_IRQHandler 728 def_irq_handler MU_A53_IRQHandler 729 def_irq_handler SRC_IRQHandler 730 def_irq_handler I2S56_DriverIRQHandler 731 def_irq_handler RTIC_IRQHandler 732 def_irq_handler CPU_PerformanceUnit_IRQHandler 733 def_irq_handler CPU_CTI_Trigger_IRQHandler 734 def_irq_handler SRC_Combined_IRQHandler 735 def_irq_handler I2S1_DriverIRQHandler 736 def_irq_handler I2S2_DriverIRQHandler 737 def_irq_handler MU_M4_IRQHandler 738 def_irq_handler DDR_PerformanceMonitor_IRQHandler 739 def_irq_handler DDR_IRQHandler 740 def_irq_handler Reserved116_IRQHandler 741 def_irq_handler CPU_Error_AXI_IRQHandler 742 def_irq_handler CPU_Error_L2RAM_IRQHandler 743 def_irq_handler SDMA2_DriverIRQHandler 744 def_irq_handler SJC_IRQHandler 745 def_irq_handler CAAM_IRQ0_IRQHandler 746 def_irq_handler CAAM_IRQ1_IRQHandler 747 def_irq_handler QSPI_DriverIRQHandler 748 def_irq_handler TZASC_IRQHandler 749 def_irq_handler PDM_EVENT_DriverIRQHandler 750 def_irq_handler PDM_ERROR_IRQHandler 751 def_irq_handler Reserved127_IRQHandler 752 def_irq_handler PERFMON1_IRQHandler 753 def_irq_handler PERFMON2_IRQHandler 754 def_irq_handler CAAM_IRQ2_IRQHandler 755 def_irq_handler CAAM_ERROR_IRQHandler 756 def_irq_handler HS_CP0_IRQHandler 757 def_irq_handler Reserved133_IRQHandler 758 def_irq_handler ENET1_MAC0_Rx_Tx_Done1_DriverIRQHandler 759 def_irq_handler ENET1_MAC0_Rx_Tx_Done2_DriverIRQHandler 760 def_irq_handler ENET1_DriverIRQHandler 761 def_irq_handler ENET1_1588_Timer_DriverIRQHandler 762 def_irq_handler PCIE_CTRL1_IRQ0_IRQHandler 763 def_irq_handler PCIE_CTRL1_IRQ1_IRQHandler 764 def_irq_handler PCIE_CTRL1_IRQ2_IRQHandler 765 def_irq_handler PCIE_CTRL1_IRQ3_IRQHandler 766 def_irq_handler Reserved142_IRQHandler 767 def_irq_handler PCIE_CTRL1_IRQHandler 768 769 .end 770
