1// See LICENSE for license details. 2 3#include "riscv_encoding.h" 4 5 .section .init 6 7 .weak eclic_msip_handler 8 .weak eclic_mtip_handler 9 .weak eclic_bwei_handler 10 .weak eclic_pmovi_handler 11 .weak WWDGT_IRQHandler 12 .weak LVD_IRQHandler 13 .weak TAMPER_IRQHandler 14 .weak RTC_IRQHandler 15 .weak FMC_IRQHandler 16 .weak RCU_IRQHandler 17 .weak EXTI0_IRQHandler 18 .weak EXTI1_IRQHandler 19 .weak EXTI2_IRQHandler 20 .weak EXTI3_IRQHandler 21 .weak EXTI4_IRQHandler 22 .weak DMA0_Channel0_IRQHandler 23 .weak DMA0_Channel1_IRQHandler 24 .weak DMA0_Channel2_IRQHandler 25 .weak DMA0_Channel3_IRQHandler 26 .weak DMA0_Channel4_IRQHandler 27 .weak DMA0_Channel5_IRQHandler 28 .weak DMA0_Channel6_IRQHandler 29 .weak ADC0_1_IRQHandler 30 .weak CAN0_TX_IRQHandler 31 .weak CAN0_RX0_IRQHandler 32 .weak CAN0_RX1_IRQHandler 33 .weak CAN0_EWMC_IRQHandler 34 .weak EXTI5_9_IRQHandler 35 .weak TIMER0_BRK_IRQHandler 36 .weak TIMER0_UP_IRQHandler 37 .weak TIMER0_TRG_CMT_IRQHandler 38 .weak TIMER0_Channel_IRQHandler 39 .weak TIMER1_IRQHandler 40 .weak TIMER2_IRQHandler 41 .weak TIMER3_IRQHandler 42 .weak I2C0_EV_IRQHandler 43 .weak I2C0_ER_IRQHandler 44 .weak I2C1_EV_IRQHandler 45 .weak I2C1_ER_IRQHandler 46 .weak SPI0_IRQHandler 47 .weak SPI1_IRQHandler 48 .weak USART0_IRQHandler 49 .weak USART1_IRQHandler 50 .weak USART2_IRQHandler 51 .weak EXTI10_15_IRQHandler 52 .weak RTC_Alarm_IRQHandler 53 .weak USBFS_WKUP_IRQHandler 54 .weak EXMC_IRQHandler 55 .weak TIMER4_IRQHandler 56 .weak SPI2_IRQHandler 57 .weak UART3_IRQHandler 58 .weak UART4_IRQHandler 59 .weak TIMER5_IRQHandler 60 .weak TIMER6_IRQHandler 61 .weak DMA1_Channel0_IRQHandler 62 .weak DMA1_Channel1_IRQHandler 63 .weak DMA1_Channel2_IRQHandler 64 .weak DMA1_Channel3_IRQHandler 65 .weak DMA1_Channel4_IRQHandler 66 .weak CAN1_TX_IRQHandler 67 .weak CAN1_RX0_IRQHandler 68 .weak CAN1_RX1_IRQHandler 69 .weak CAN1_EWMC_IRQHandler 70 .weak USBFS_IRQHandler 71 72vector_base: 73 j _start 74 .align 2 75 .word 0 76 .word 0 77 .word eclic_msip_handler 78 .word 0 79 .word 0 80 .word 0 81 .word eclic_mtip_handler 82 .word 0 83 .word 0 84 .word 0 85 .word 0 86 .word 0 87 .word 0 88 .word 0 89 .word 0 90 .word 0 91 .word eclic_bwei_handler 92 .word eclic_pmovi_handler 93 .word WWDGT_IRQHandler 94 .word LVD_IRQHandler 95 .word TAMPER_IRQHandler 96 .word RTC_IRQHandler 97 .word FMC_IRQHandler 98 .word RCU_IRQHandler 99 .word EXTI0_IRQHandler 100 .word EXTI1_IRQHandler 101 .word EXTI2_IRQHandler 102 .word EXTI3_IRQHandler 103 .word EXTI4_IRQHandler 104 .word DMA0_Channel0_IRQHandler 105 .word DMA0_Channel1_IRQHandler 106 .word DMA0_Channel2_IRQHandler 107 .word DMA0_Channel3_IRQHandler 108 .word DMA0_Channel4_IRQHandler 109 .word DMA0_Channel5_IRQHandler 110 .word DMA0_Channel6_IRQHandler 111 .word ADC0_1_IRQHandler 112 .word CAN0_TX_IRQHandler 113 .word CAN0_RX0_IRQHandler 114 .word CAN0_RX1_IRQHandler 115 .word CAN0_EWMC_IRQHandler 116 .word EXTI5_9_IRQHandler 117 .word TIMER0_BRK_IRQHandler 118 .word TIMER0_UP_IRQHandler 119 .word TIMER0_TRG_CMT_IRQHandler 120 .word TIMER0_Channel_IRQHandler 121 .word TIMER1_IRQHandler 122 .word TIMER2_IRQHandler 123 .word TIMER3_IRQHandler 124 .word I2C0_EV_IRQHandler 125 .word I2C0_ER_IRQHandler 126 .word I2C1_EV_IRQHandler 127 .word I2C1_ER_IRQHandler 128 .word SPI0_IRQHandler 129 .word SPI1_IRQHandler 130 .word USART0_IRQHandler 131 .word USART1_IRQHandler 132 .word USART2_IRQHandler 133 .word EXTI10_15_IRQHandler 134 .word RTC_Alarm_IRQHandler 135 .word USBFS_WKUP_IRQHandler 136 .word 0 137 .word 0 138 .word 0 139 .word 0 140 .word 0 141 .word EXMC_IRQHandler 142 .word 0 143 .word TIMER4_IRQHandler 144 .word SPI2_IRQHandler 145 .word UART3_IRQHandler 146 .word UART4_IRQHandler 147 .word TIMER5_IRQHandler 148 .word TIMER6_IRQHandler 149 .word DMA1_Channel0_IRQHandler 150 .word DMA1_Channel1_IRQHandler 151 .word DMA1_Channel2_IRQHandler 152 .word DMA1_Channel3_IRQHandler 153 .word DMA1_Channel4_IRQHandler 154 .word 0 155 .word 0 156 .word CAN1_TX_IRQHandler 157 .word CAN1_RX0_IRQHandler 158 .word CAN1_RX1_IRQHandler 159 .word CAN1_EWMC_IRQHandler 160 .word USBFS_IRQHandler 161 162 .globl _start 163 .type _start,@function 164 165_start: 166 167 csrc CSR_MSTATUS, MSTATUS_MIE 168 /* Jump to logical address first to ensure correct operation of RAM region */ 169 la a0, _start 170 li a1, 1 171 slli a1, a1, 29 172 bleu a1, a0, _start0800 173 srli a1, a1, 2 174 bleu a1, a0, _start0800 175 la a0, _start0800 176 add a0, a0, a1 177 jr a0 178 179_start0800: 180 181 /* Set the the NMI base to share with mtvec by setting CSR_MMISC_CTL */ 182 li t0, 0x200 183 csrs CSR_MMISC_CTL, t0 184 185 /* Intial the mtvt*/ 186 la t0, vector_base 187 csrw CSR_MTVT, t0 188 189 /* Intial the mtvt2 and enable it*/ 190 la t0, irq_entry 191 csrw CSR_MTVT2, t0 192 csrs CSR_MTVT2, 0x1 193 194 /* Intial the CSR MTVEC for the Trap ane NMI base addr*/ 195 la t0, trap_entry 196 csrw CSR_MTVEC, t0 197 198#ifdef __riscv_flen 199 /* Enable FPU */ 200 li t0, MSTATUS_FS 201 csrs mstatus, t0 202 csrw fcsr, x0 203#endif 204 205.option push 206.option norelax 207 la gp, __global_pointer$ 208.option pop 209 la sp, _sp 210 211 /* Load data section */ 212 la a0, _data_lma 213 la a1, _data 214 la a2, _edata 215 bgeu a1, a2, 2f 2161: 217 lw t0, (a0) 218 sw t0, (a1) 219 addi a0, a0, 4 220 addi a1, a1, 4 221 bltu a1, a2, 1b 2222: 223 /* Clear bss section */ 224 la a0, __bss_start 225 la a1, _end 226 bgeu a0, a1, 2f 2271: 228 sw zero, (a0) 229 addi a0, a0, 4 230 bltu a0, a1, 1b 2312: 232 /*enable mcycle_minstret*/ 233 csrci CSR_MCOUNTINHIBIT, 0x5 234 /* Call global constructors */ 235 la a0, __libc_fini_array 236 call atexit 237 call __libc_init_array 238 239 240 /* argc = argv = 0 */ 241 li a0, 0 242 li a1, 0 243 call main 244 tail exit 245 2461: 247 j 1b 248 249 .global disable_mcycle_minstret 250disable_mcycle_minstret: 251 csrsi CSR_MCOUNTINHIBIT, 0x5 252 ret 253 254 .global enable_mcycle_minstret 255enable_mcycle_minstret: 256 csrci CSR_MCOUNTINHIBIT, 0x5 257 ret 258 259
