1/* 2 * Copyright (c) 2019 Linaro Limited 3 * Copyright (c) 2019 Centaur Analytics, Inc 4 * Copyright (c) 2024 STMicroelectronics 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 9#include <arm/armv7-m.dtsi> 10#include <zephyr/dt-bindings/clock/stm32wb_clock.h> 11#include <zephyr/dt-bindings/gpio/gpio.h> 12#include <zephyr/dt-bindings/i2c/i2c.h> 13#include <zephyr/dt-bindings/pwm/pwm.h> 14#include <zephyr/dt-bindings/adc/adc.h> 15#include <zephyr/dt-bindings/pwm/stm32_pwm.h> 16#include <zephyr/dt-bindings/dma/stm32_dma.h> 17#include <zephyr/dt-bindings/adc/stm32l4_adc.h> 18#include <zephyr/dt-bindings/reset/stm32wb_l_reset.h> 19#include <zephyr/dt-bindings/power/stm32_pwr.h> 20#include <freq.h> 21 22/ { 23 chosen { 24 zephyr,entropy = &rng; 25 zephyr,flash-controller = &flash; 26 zephyr,bt-hci = &ble_rf; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-m4f"; 36 reg = <0>; 37 cpu-power-states = <&stop0 &stop1 &stop2>; 38 }; 39 40 power-states { 41 stop0: state0 { 42 compatible = "zephyr,power-state"; 43 power-state-name = "suspend-to-idle"; 44 substate-id = <1>; 45 min-residency-us = <100>; 46 }; 47 stop1: state1 { 48 compatible = "zephyr,power-state"; 49 power-state-name = "suspend-to-idle"; 50 substate-id = <2>; 51 min-residency-us = <500>; 52 }; 53 stop2: state2 { 54 compatible = "zephyr,power-state"; 55 power-state-name = "suspend-to-idle"; 56 substate-id = <3>; 57 min-residency-us = <900>; 58 }; 59 }; 60 }; 61 62 sram0: memory@20000000 { 63 compatible = "mmio-sram"; 64 }; 65 66 sram1: memory@20030000 { 67 compatible = "zephyr,memory-region", "mmio-sram"; 68 reg = <0x20030000 0x2800>; 69 zephyr,memory-region = "SRAM1"; 70 }; 71 72 sram2: memory@20038000 { 73 compatible = "zephyr,memory-region", "mmio-sram"; 74 reg = <0x20038000 0x5000>; 75 zephyr,memory-region = "SRAM2"; 76 }; 77 78 clocks { 79 clk_hse: clk-hse { 80 #clock-cells = <0>; 81 compatible = "fixed-clock"; 82 /* Expected clock-frequency on the whole series 32MHz */ 83 clock-frequency = <DT_FREQ_M(32)>; 84 status = "disabled"; 85 }; 86 87 clk_hsi: clk-hsi { 88 #clock-cells = <0>; 89 compatible = "fixed-clock"; 90 clock-frequency = <DT_FREQ_M(16)>; 91 status = "disabled"; 92 }; 93 94 clk_hsi48: clk-hsi48 { 95 #clock-cells = <0>; 96 compatible = "fixed-clock"; 97 clock-frequency = <DT_FREQ_M(48)>; 98 status = "disabled"; 99 }; 100 101 clk_msi: clk-msi { 102 #clock-cells = <0>; 103 compatible = "st,stm32-msi-clock"; 104 msi-range = <6>; /* 4MHz (reset value) */ 105 status = "disabled"; 106 }; 107 108 clk_lse: clk-lse { 109 #clock-cells = <0>; 110 compatible = "st,stm32-lse-clock"; 111 clock-frequency = <32768>; 112 driving-capability = <0>; 113 status = "disabled"; 114 }; 115 116 clk_lsi1: clk-lsi1 { 117 #clock-cells = <0>; 118 compatible = "fixed-clock"; 119 clock-frequency = <DT_FREQ_K(32)>; 120 status = "disabled"; 121 }; 122 123 clk_lsi2: clk-lsi2 { 124 #clock-cells = <0>; 125 compatible = "fixed-clock"; 126 clock-frequency = <DT_FREQ_K(32)>; 127 status = "disabled"; 128 }; 129 130 pll: pll { 131 #clock-cells = <0>; 132 compatible = "st,stm32wb-pll-clock"; 133 status = "disabled"; 134 }; 135 136 clk48: clk48 { 137 #clock-cells = <0>; 138 compatible = "st,stm32-clock-mux"; 139 status = "disabled"; 140 }; 141 }; 142 143 soc { 144 flash: flash-controller@58004000 { 145 compatible = "st,stm32-flash-controller", "st,stm32wb-flash-controller"; 146 reg = <0x58004000 0x400>; 147 interrupts = <4 0>; 148 clocks = <&rcc STM32_CLOCK(AHB3, 25U)>; 149 150 #address-cells = <1>; 151 #size-cells = <1>; 152 153 flash0: flash@8000000 { 154 compatible = "st,stm32-nv-flash", "soc-nv-flash"; 155 156 write-block-size = <8>; 157 erase-block-size = <4096>; 158 /* maximum erase time(ms) for a 4K sector */ 159 max-erase-time = <25>; 160 }; 161 }; 162 163 rcc: rcc@58000000 { 164 compatible = "st,stm32wb-rcc"; 165 #clock-cells = <2>; 166 reg = <0x58000000 0x400>; 167 168 rctl: reset-controller { 169 compatible = "st,stm32-rcc-rctl"; 170 #reset-cells = <1>; 171 }; 172 }; 173 174 exti: interrupt-controller@58000800 { 175 compatible = "st,stm32-exti"; 176 interrupt-controller; 177 #interrupt-cells = <1>; 178 #address-cells = <1>; 179 reg = <0x58000800 0x400>; 180 num-lines = <16>; 181 interrupts = <6 0>, <7 0>, <8 0>, <9 0>, 182 <10 0>, <23 0>, <40 0>; 183 interrupt-names = "line0", "line1", "line2", "line3", 184 "line4", "line5-9", "line10-15"; 185 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, 186 <4 1>, <5 5>, <10 6>; 187 }; 188 189 pinctrl: pin-controller@48000000 { 190 compatible = "st,stm32-pinctrl"; 191 #address-cells = <1>; 192 #size-cells = <1>; 193 reg = <0x48000000 0x2000>; 194 195 gpioa: gpio@48000000 { 196 compatible = "st,stm32-gpio"; 197 gpio-controller; 198 #gpio-cells = <2>; 199 reg = <0x48000000 0x400>; 200 clocks = <&rcc STM32_CLOCK(AHB2, 0U)>; 201 }; 202 203 gpiob: gpio@48000400 { 204 compatible = "st,stm32-gpio"; 205 gpio-controller; 206 #gpio-cells = <2>; 207 reg = <0x48000400 0x400>; 208 clocks = <&rcc STM32_CLOCK(AHB2, 1U)>; 209 }; 210 211 gpioc: gpio@48000800 { 212 compatible = "st,stm32-gpio"; 213 gpio-controller; 214 #gpio-cells = <2>; 215 reg = <0x48000800 0x400>; 216 clocks = <&rcc STM32_CLOCK(AHB2, 2U)>; 217 }; 218 219 gpiod: gpio@48000c00 { 220 compatible = "st,stm32-gpio"; 221 gpio-controller; 222 #gpio-cells = <2>; 223 reg = <0x48000c00 0x400>; 224 clocks = <&rcc STM32_CLOCK(AHB2, 3U)>; 225 }; 226 227 gpioe: gpio@48001000 { 228 compatible = "st,stm32-gpio"; 229 gpio-controller; 230 #gpio-cells = <2>; 231 ngpios = <5>; 232 reg = <0x48001000 0x400>; 233 clocks = <&rcc STM32_CLOCK(AHB2, 4U)>; 234 }; 235 236 gpioh: gpio@48001c00 { 237 compatible = "st,stm32-gpio"; 238 gpio-controller; 239 #gpio-cells = <2>; 240 ngpios = <4>; 241 reg = <0x48001c00 0x400>; 242 clocks = <&rcc STM32_CLOCK(AHB2, 7U)>; 243 }; 244 }; 245 246 wwdg: watchdog@40002c00 { 247 compatible = "st,stm32-window-watchdog"; 248 reg = <0x40002C00 0x400>; 249 clocks = <&rcc STM32_CLOCK(APB1, 11U)>; 250 interrupts = <0 7>; 251 status = "disabled"; 252 }; 253 254 usart1: serial@40013800 { 255 compatible = "st,stm32-usart", "st,stm32-uart"; 256 reg = <0x40013800 0x400>; 257 clocks = <&rcc STM32_CLOCK(APB2, 14U)>; 258 resets = <&rctl STM32_RESET(APB2, 14U)>; 259 interrupts = <36 0>; 260 status = "disabled"; 261 }; 262 263 i2c1: i2c@40005400 { 264 compatible = "st,stm32-i2c-v2"; 265 clock-frequency = <I2C_BITRATE_STANDARD>; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 reg = <0x40005400 0x400>; 269 clocks = <&rcc STM32_CLOCK(APB1, 21U)>; 270 interrupts = <30 0>, <31 0>; 271 interrupt-names = "event", "error"; 272 status = "disabled"; 273 }; 274 275 i2c3: i2c@40005c00 { 276 compatible = "st,stm32-i2c-v2"; 277 clock-frequency = <I2C_BITRATE_STANDARD>; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 reg = <0x40005c00 0x400>; 281 clocks = <&rcc STM32_CLOCK(APB1, 23U)>; 282 interrupts = <32 0>, <33 0>; 283 interrupt-names = "event", "error"; 284 status = "disabled"; 285 }; 286 287 rtc: rtc@40002800 { 288 compatible = "st,stm32-rtc"; 289 reg = <0x40002800 0x400>; 290 interrupts = <41 0>; 291 clocks = <&rcc STM32_CLOCK(APB1, 10U)>; 292 prescaler = <32768>; 293 alarms-count = <2>; 294 alrm-exti-line = <17>; 295 status = "disabled"; 296 297 bbram: backup_regs { 298 compatible = "st,stm32-bbram"; 299 st,backup-regs = <20>; 300 status = "disabled"; 301 }; 302 }; 303 304 spi1: spi@40013000 { 305 compatible = "st,stm32-spi-fifo", "st,stm32-spi"; 306 #address-cells = <1>; 307 #size-cells = <0>; 308 reg = <0x40013000 0x400>; 309 interrupts = <34 5>; 310 clocks = <&rcc STM32_CLOCK(APB2, 12U)>; 311 status = "disabled"; 312 }; 313 314 spi2: spi@40003800 { 315 compatible = "st,stm32-spi-fifo", "st,stm32-spi"; 316 #address-cells = <1>; 317 #size-cells = <0>; 318 reg = <0x40003800 0x400>; 319 interrupts = <35 5>; 320 clocks = <&rcc STM32_CLOCK(APB1, 14U)>; 321 status = "disabled"; 322 }; 323 324 lpuart1: serial@40008000 { 325 compatible = "st,stm32-lpuart", "st,stm32-uart"; 326 reg = <0x40008000 0x400>; 327 clocks = <&rcc STM32_CLOCK(APB1_2, 0U)>; 328 resets = <&rctl STM32_RESET(APB1H, 0U)>; 329 interrupts = <37 0>; 330 status = "disabled"; 331 }; 332 333 timers1: timers@40012c00 { 334 compatible = "st,stm32-timers"; 335 reg = <0x40012c00 0x400>; 336 clocks = <&rcc STM32_CLOCK(APB2, 11U)>; 337 resets = <&rctl STM32_RESET(APB2, 11U)>; 338 interrupts = <24 0>, <25 0>, <26 0>, <27 0>; 339 interrupt-names = "brk", "up", "trgcom", "cc"; 340 st,prescaler = <0>; 341 status = "disabled"; 342 343 pwm { 344 compatible = "st,stm32-pwm"; 345 status = "disabled"; 346 #pwm-cells = <3>; 347 }; 348 }; 349 350 timers2: timers@40000000 { 351 compatible = "st,stm32-timers"; 352 reg = <0x40000000 0x400>; 353 clocks = <&rcc STM32_CLOCK(APB1, 0U)>; 354 resets = <&rctl STM32_RESET(APB1L, 0U)>; 355 interrupts = <28 0>; 356 interrupt-names = "global"; 357 st,prescaler = <0>; 358 status = "disabled"; 359 360 pwm { 361 compatible = "st,stm32-pwm"; 362 status = "disabled"; 363 #pwm-cells = <3>; 364 }; 365 366 counter { 367 compatible = "st,stm32-counter"; 368 status = "disabled"; 369 }; 370 }; 371 372 timers16: timers@40014400 { 373 compatible = "st,stm32-timers"; 374 reg = <0x40014400 0x400>; 375 clocks = <&rcc STM32_CLOCK(APB2, 17U)>; 376 resets = <&rctl STM32_RESET(APB2, 17U)>; 377 interrupts = <25 0>; 378 interrupt-names = "global"; 379 st,prescaler = <0>; 380 status = "disabled"; 381 382 pwm { 383 compatible = "st,stm32-pwm"; 384 status = "disabled"; 385 #pwm-cells = <3>; 386 }; 387 388 counter { 389 compatible = "st,stm32-counter"; 390 status = "disabled"; 391 }; 392 }; 393 394 timers17: timers@40014800 { 395 compatible = "st,stm32-timers"; 396 reg = <0x40014800 0x400>; 397 clocks = <&rcc STM32_CLOCK(APB2, 18U)>; 398 resets = <&rctl STM32_RESET(APB2, 18U)>; 399 interrupts = <26 0>; 400 interrupt-names = "global"; 401 st,prescaler = <0>; 402 status = "disabled"; 403 404 pwm { 405 compatible = "st,stm32-pwm"; 406 status = "disabled"; 407 #pwm-cells = <3>; 408 }; 409 410 counter { 411 compatible = "st,stm32-counter"; 412 status = "disabled"; 413 }; 414 }; 415 416 adc1: adc@50040000 { 417 compatible = "st,stm32-adc"; 418 reg = <0x50040000 0x400>; 419 clocks = <&rcc STM32_CLOCK(AHB2, 13U)>; 420 interrupts = <18 0>; 421 status = "disabled"; 422 #io-channel-cells = <1>; 423 resolutions = <STM32_ADC_RES(12, 0x00) 424 STM32_ADC_RES(10, 0x01) 425 STM32_ADC_RES(8, 0x02) 426 STM32_ADC_RES(6, 0x03)>; 427 sampling-times = <3 7 13 25 48 93 248 641>; 428 st,adc-sequencer = "FULLY_CONFIGURABLE"; 429 st,adc-oversampler = "OVERSAMPLER_MINIMAL"; 430 }; 431 432 iwdg: watchdog@40003000 { 433 compatible = "st,stm32-watchdog"; 434 reg = <0x40003000 0x400>; 435 status = "disabled"; 436 }; 437 438 lptim1: timers@40007c00 { 439 compatible = "st,stm32-lptim"; 440 clocks = <&rcc STM32_CLOCK(APB1, 31U)>; 441 #address-cells = <1>; 442 #size-cells = <0>; 443 reg = <0x40007c00 0x400>; 444 interrupts = <47 1>; 445 interrupt-names = "wakeup"; 446 status = "disabled"; 447 }; 448 449 dma1: dma@40020000 { 450 compatible = "st,stm32-dma-v2"; 451 #dma-cells = <3>; 452 reg = <0x40020000 0x400>; 453 interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>; 454 clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; 455 dma-requests = <7>; 456 dma-offset = <0>; 457 status = "disabled"; 458 }; 459 460 dma2: dma@40020400 { 461 compatible = "st,stm32-dma-v2"; 462 #dma-cells = <3>; 463 reg = <0x40020400 0x400>; 464 interrupts = <55 0 56 0 57 0 58 0 59 0 60 0 61 0>; 465 clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; 466 dma-requests = <7>; 467 dma-offset = <7>; 468 status = "disabled"; 469 }; 470 471 dmamux1: dmamux@40020800 { 472 compatible = "st,stm32-dmamux"; 473 #dma-cells = <3>; 474 reg = <0x40020800 0x400>; 475 interrupts = <62 0>; 476 clocks = <&rcc STM32_CLOCK(AHB1, 2U)>; 477 dma-channels = <14>; 478 dma-generators = <4>; 479 dma-requests= <36>; 480 status = "disabled"; 481 }; 482 483 usb: usb@40006800 { 484 compatible = "st,stm32-usb"; 485 reg = <0x40006800 0x400>; 486 interrupts = <20 0>, <19 0>; 487 interrupt-names = "usb", "usbhp"; 488 num-bidir-endpoints = <8>; 489 ram-size = <1024>; 490 phys = <&usb_fs_phy>; 491 clocks = <&rcc STM32_CLOCK(APB1, 26U)>, 492 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; 493 status = "disabled"; 494 }; 495 496 quadspi: quadspi@a0001000 { 497 compatible = "st,stm32-qspi"; 498 #address-cells = <0x1>; 499 #size-cells = <0x0>; 500 reg = <0xa0001000 0x400>; 501 interrupts = <0x32 0x0>; 502 clocks = <&rcc STM32_CLOCK(AHB3, 8U)>; 503 status = "disabled"; 504 }; 505 506 rng: rng@58001000 { 507 compatible = "st,stm32-rng"; 508 reg = <0x58001000 0x400>; 509 interrupts = <53 0>; 510 clocks = <&rcc STM32_CLOCK(AHB3, 18U)>; 511 status = "disabled"; 512 }; 513 514 aes1: aes@50060000 { 515 compatible = "st,stm32-aes"; 516 reg = <0x50060000 0x400>; 517 clocks = <&rcc STM32_CLOCK(AHB2, 16U)>; 518 resets = <&rctl STM32_RESET(AHB2, 16U)>; 519 interrupts = <51 0>; 520 status = "disabled"; 521 }; 522 523 pwr: power@58000400 { 524 compatible = "st,stm32-pwr"; 525 reg = <0x58000400 0x400>; /* PWR register bank */ 526 status = "disabled"; 527 528 wkup-pins-nb = <5>; /* 5 system wake-up pins */ 529 wkup-pins-pol; 530 wkup-pins-pupd; 531 532 #address-cells = <1>; 533 #size-cells = <0>; 534 535 wkup-pin@1 { 536 reg = <0x1>; 537 wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_SRC_0>; 538 }; 539 540 wkup-pin@4 { 541 reg = <0x4>; 542 wkup-gpios = <&gpioa 2 STM32_PWR_WKUP_PIN_SRC_0>; 543 }; 544 }; 545 }; 546 547 die_temp: dietemp { 548 compatible = "st,stm32-temp-cal"; 549 ts-cal1-addr = <0x1FFF75A8>; 550 ts-cal2-addr = <0x1FFF75CA>; 551 ts-cal1-temp = <30>; 552 ts-cal2-temp = <130>; 553 ts-cal-vrefanalog = <3000>; 554 io-channels = <&adc1 17>; 555 status = "disabled"; 556 }; 557 558 vref: vref { 559 compatible = "st,stm32-vref"; 560 vrefint-cal-addr = <0x1FFF75AA>; 561 vrefint-cal-mv = <3600>; 562 io-channels = <&adc1 0>; 563 status = "disabled"; 564 }; 565 566 vbat: vbat { 567 compatible = "st,stm32-vbat"; 568 ratio = <3>; 569 io-channels = <&adc1 18>; 570 status = "disabled"; 571 }; 572 573 usb_fs_phy: usbphy { 574 compatible = "usb-nop-xceiv"; 575 #phy-cells = <0>; 576 }; 577 578 ble_rf: ble_rf { 579 compatible = "st,stm32wb-rf"; 580 clocks = <&rcc STM32_CLOCK(AHB3, 20U)>, 581 <&rcc STM32_SRC_LSE RFWKP_SEL(1)>; 582 }; 583 584 smbus1: smbus1 { 585 compatible = "st,stm32-smbus"; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 i2c = <&i2c1>; 589 status = "disabled"; 590 }; 591 592 smbus3: smbus3 { 593 compatible = "st,stm32-smbus"; 594 #address-cells = <1>; 595 #size-cells = <0>; 596 i2c = <&i2c3>; 597 status = "disabled"; 598 }; 599}; 600 601&nvic { 602 arm,num-irq-priority-bits = <4>; 603}; 604
