1/*
2 * Copyright (c) 2019 STMicroelectronics
3 * Copyright (c) 2019 Centaur Analytics, Inc
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <mem.h>
9#include <freq.h>
10#include <arm/armv7-m.dtsi>
11#include <zephyr/dt-bindings/gpio/gpio.h>
12#include <zephyr/dt-bindings/clock/stm32_clock.h>
13#include <zephyr/dt-bindings/i2c/i2c.h>
14#include <zephyr/dt-bindings/pwm/pwm.h>
15#include <zephyr/dt-bindings/pwm/stm32_pwm.h>
16#include <zephyr/dt-bindings/dma/stm32_dma.h>
17#include <zephyr/dt-bindings/reset/stm32mp1_reset.h>
18#include <zephyr/dt-bindings/display/panel.h>
19
20/ {
21	cpus {
22		#address-cells = <1>;
23		#size-cells = <0>;
24
25		cpu@0 {
26			device_type = "cpu";
27			compatible = "arm,cortex-m4";
28			reg = <0>;
29		};
30	};
31
32	retram: memory0@0 {
33		compatible = "mmio-sram";
34		reg = <0x00000000 DT_SIZE_K(64)>;
35	};
36	mcusram: memory1@10000000 {
37		compatible = "mmio-sram";
38		reg = <0x10000000 DT_SIZE_K(320)>;
39	};
40
41	soc {
42		compatible = "st,stm32mp157", "st,stm32mp1", "simple-bus";
43
44		rcc: rcc@50000000 {
45			compatible = "st,stm32mp1-rcc";
46			reg = <0x50000000 0x1000>;
47			#clock-cells = <2>;
48
49			rctl: reset-controller {
50				compatible = "st,stm32-rcc-rctl";
51				#reset-cells = <1>;
52				set-bit-to-deassert;
53			};
54		};
55
56		exti: interrupt-controller@5000d000 {
57			compatible = "st,stm32g0-exti", "st,stm32-exti";
58			interrupt-controller;
59			#interrupt-cells = <1>;
60			#address-cells = <1>;
61			reg = <0x5000d000 0x400>;
62			num-lines = <16>;
63			interrupts = <6 0>, <7 0>, <8 0>, <9 0>,
64				     <10 0>, <23 0>, <40 0>, <42 0>,
65				     <64 0>, <65 0>, <66 0>, <67 0>,
66				     <76 0>, <77 0>, <121 0>, <127 0>;
67			interrupt-names = "line0", "line1", "line2", "line3",
68					  "line4", "line5", "line6", "line7",
69					  "line8", "line9", "line10", "line11",
70					  "line12", "line13", "line14", "line15";
71			line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
72				      <4 1>, <5 1>, <6 1>, <7 1>,
73				      <8 1>, <9 1>, <10 1>, <11 1>,
74				      <12 1>, <13 1>, <14 1>, <15 1>;
75		};
76
77		pinctrl: pin-controller@50002000 {
78			compatible = "st,stm32-pinctrl";
79			reg = <0x50002000 0x9000>;
80			#address-cells = <1>;
81			#size-cells = <1>;
82
83			gpioa: gpio@50002000 {
84				compatible = "st,stm32-gpio";
85				reg = <0x50002000 0x400>;
86				gpio-controller;
87				#gpio-cells = <2>;
88				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000001>;
89			};
90
91			gpiob: gpio@50003000 {
92				compatible = "st,stm32-gpio";
93				reg = <0x50003000 0x400>;
94				gpio-controller;
95				#gpio-cells = <2>;
96				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000002>;
97			};
98
99			gpioc: gpio@50004000 {
100				compatible = "st,stm32-gpio";
101				reg = <0x50004000 0x400>;
102				gpio-controller;
103				#gpio-cells = <2>;
104				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000004>;
105			};
106
107			gpiod: gpio@50005000 {
108				compatible = "st,stm32-gpio";
109				reg = <0x50005000 0x400>;
110				gpio-controller;
111				#gpio-cells = <2>;
112				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000008>;
113			};
114
115			gpioe: gpio@50006000 {
116				compatible = "st,stm32-gpio";
117				reg = <0x50006000 0x400>;
118				gpio-controller;
119				#gpio-cells = <2>;
120				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000010>;
121			};
122
123			gpiof: gpio@50007000 {
124				compatible = "st,stm32-gpio";
125				reg = <0x50007000 0x400>;
126				gpio-controller;
127				#gpio-cells = <2>;
128				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000020>;
129			};
130
131			gpiog: gpio@50008000 {
132				compatible = "st,stm32-gpio";
133				reg = <0x50008000 0x400>;
134				gpio-controller;
135				#gpio-cells = <2>;
136				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000040>;
137			};
138
139			gpioh: gpio@50009000 {
140				compatible = "st,stm32-gpio";
141				reg = <0x50009000 0x400>;
142				gpio-controller;
143				#gpio-cells = <2>;
144				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000080>;
145			};
146
147			gpioi: gpio@5000a000 {
148				compatible = "st,stm32-gpio";
149				reg = <0x5000a000 0x400>;
150				gpio-controller;
151				#gpio-cells = <2>;
152				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000100>;
153			};
154
155			gpioj: gpio@5000b000 {
156				compatible = "st,stm32-gpio";
157				reg = <0x5000b000 0x400>;
158				gpio-controller;
159				#gpio-cells = <2>;
160				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000200>;
161			};
162
163			gpiok: gpio@5000c000 {
164				compatible = "st,stm32-gpio";
165				reg = <0x5000c000 0x400>;
166				gpio-controller;
167				#gpio-cells = <2>;
168				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000400>;
169			};
170		};
171
172		wwdg: wwdg1: watchdog@4000a000 {
173			compatible = "st,stm32-window-watchdog";
174			reg = <0x4000a000 0x400>;
175			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
176			interrupts = <0 7>;
177			status = "disabled";
178		};
179
180		dma1: dma@48000000 {
181			compatible = "st,stm32-dma-v1";
182			#dma-cells = <4>;
183			reg = <0x48000000 0x400>;
184			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x1>;
185			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>;
186			dma-offset = <0>;
187			dma-requests = <8>;
188			status = "disabled";
189		};
190
191		dma2: dma@48001000 {
192			compatible = "st,stm32-dma-v1";
193			#dma-cells = <4>;
194			reg = <0x48001000 0x400>;
195			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x2>;
196			interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>;
197			dma-offset = <8>;
198			dma-requests = <8>;
199			status = "disabled";
200		};
201
202		dmamux: dmamux@48002000 {
203			compatible = "st,stm32-dmamux";
204			#dma-cells = <3>;
205			reg = <0x48002000 0x400>;
206			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x4>;
207			interrupts = <102 0>;
208			dma-channels = <16>;
209			dma-generators = <8>;
210			dma-requests= <108>;
211			status = "disabled";
212		};
213
214		spi1: spi@44004000 {
215			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
216			reg = <0x44004000 0x400>;
217			#address-cells = <1>;
218			#size-cells = <0>;
219			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x100>;
220			interrupts = <35 5>;
221			status = "disabled";
222		};
223
224		spi2: spi@4000b000 {
225			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
226			reg = <0x4000b000 0x400>;
227			#address-cells = <1>;
228			#size-cells = <0>;
229			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x800>;
230			interrupts = <36 5>;
231			status = "disabled";
232		};
233
234		spi3: spi@4000c000 {
235			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
236			reg = <0x4000c000 0x400>;
237			#address-cells = <1>;
238			#size-cells = <0>;
239			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x1000>;
240			interrupts = <51 5>;
241			status = "disabled";
242		};
243
244		spi4: spi@44005000 {
245			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
246			reg = <0x44005000 0x400>;
247			#address-cells = <1>;
248			#size-cells = <0>;
249			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x200>;
250			interrupts = <84 5>;
251			status = "disabled";
252		};
253
254		spi5: spi@44009000 {
255			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
256			reg = <0x44009000 0x400>;
257			#address-cells = <1>;
258			#size-cells = <0>;
259			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x400>;
260			interrupts = <85 5>;
261			status = "disabled";
262		};
263
264		usart2: serial@4000e000 {
265			compatible = "st,stm32-usart", "st,stm32-uart";
266			reg = <0x4000e000 0x400>;
267			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
268			resets = <&rctl STM32_RESET(APB1, 14U)>;
269			interrupts = <38 0>;
270			status = "disabled";
271		};
272
273		usart3: serial@4000f000 {
274			compatible = "st,stm32-usart", "st,stm32-uart";
275			reg = <0x4000f000 0x400>;
276			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
277			resets = <&rctl STM32_RESET(APB1, 15U)>;
278			interrupts = <39 0>;
279			status = "disabled";
280		};
281
282		uart4: serial@40010000 {
283			compatible = "st,stm32-uart";
284			reg = <0x40010000 0x400>;
285			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00010000>;
286			resets = <&rctl STM32_RESET(APB1, 16U)>;
287			interrupts = <52 0>;
288			status = "disabled";
289		};
290
291		uart5: serial@40011000 {
292			compatible = "st,stm32-uart";
293			reg = <0x40011000 0x400>;
294			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
295			resets = <&rctl STM32_RESET(APB1, 17U)>;
296			interrupts = <53 0>;
297			status = "disabled";
298		};
299
300		usart6: serial@44003000 {
301			compatible = "st,stm32-usart", "st,stm32-uart";
302			reg = <0x44003000 0x400>;
303			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
304			resets = <&rctl STM32_RESET(APB2, 13U)>;
305			interrupts = <71 0>;
306			status = "disabled";
307		};
308
309		uart7: serial@40018000 {
310			compatible = "st,stm32-uart";
311			reg = <0x40018000 0x400>;
312			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
313			resets = <&rctl STM32_RESET(APB1, 18U)>;
314			interrupts = <82 0>;
315			status = "disabled";
316		};
317
318		uart8: serial@40019000 {
319			compatible = "st,stm32-uart";
320			reg = <0x40019000 0x400>;
321			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
322			resets = <&rctl STM32_RESET(APB1, 19U)>;
323			interrupts = <83 0>;
324			status = "disabled";
325		};
326
327		i2c5: i2c@40015000 {
328			compatible = "st,stm32-i2c-v2";
329			clock-frequency = <I2C_BITRATE_STANDARD>;
330			reg = <0x40015000 0x400>;
331			#address-cells = <1>;
332			#size-cells = <0>;
333			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x01000000>;
334			interrupt-names = "event", "error";
335			interrupts = <107 0>, <108 0>;
336			status = "disabled";
337		};
338
339		timers3: timers@40001000 {
340			compatible = "st,stm32-timers";
341			reg = <0x40001000 0x400>;
342			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
343			resets = <&rctl STM32_RESET(APB1, 1U)>;
344			interrupts = <29 0>;
345			interrupt-names = "global";
346			st,prescaler = <0>;
347			status = "disabled";
348
349			pwm {
350				compatible = "st,stm32-pwm";
351				status = "disabled";
352				#pwm-cells = <3>;
353			};
354
355			counter {
356				compatible = "st,stm32-counter";
357				status = "disabled";
358			};
359		};
360
361		timers5: timers@40003000 {
362			compatible = "st,stm32-timers";
363			reg = <0x40003000 0x400>;
364			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
365			resets = <&rctl STM32_RESET(APB1, 3U)>;
366			interrupts = <50 0>;
367			interrupt-names = "global";
368			st,prescaler = <0>;
369			status = "disabled";
370
371			pwm {
372				compatible = "st,stm32-pwm";
373				status = "disabled";
374				#pwm-cells = <3>;
375			};
376
377			counter {
378				compatible = "st,stm32-counter";
379				status = "disabled";
380			};
381		};
382
383		mailbox: mailbox@4c001000 {
384			compatible = "st,stm32-ipcc-mailbox";
385			reg = <0x4c001000 0x400>;
386			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00001000>;
387			interrupts = <103 0>, <104 0>;
388			interrupt-names = "rxo", "txf";
389			status = "disabled";
390		};
391
392		ltdc: display-controller@5a001000 {
393			compatible = "st,stm32-ltdc";
394			reg = <0x5a001000 0x200>;
395			interrupts = <88 0>, <89 0>;
396			interrupt-names = "ltdc", "ltdc_er";
397			clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00000001>;
398			status = "disabled";
399		};
400	};
401};
402
403&nvic {
404	arm,num-irq-priority-bits = <4>;
405};
406