1/*
2 * Copyright (c) 2021 Electrolance Solutions
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/h7/stm32h7.dtsi>
8#include <zephyr/dt-bindings/display/panel.h>
9#include <zephyr/dt-bindings/flash_controller/ospi.h>
10
11/delete-node/ &adc3;
12
13/ {
14	soc {
15		compatible = "st,stm32h7a3", "st,stm32h7", "simple-bus";
16
17		flash-controller@52002000 {
18			flash0: flash@8000000 {
19				compatible = "st,stm32-nv-flash", "soc-nv-flash";
20				write-block-size = <16>;
21				erase-block-size = <DT_SIZE_K(8)>;
22				/* maximum erase time for a 8K sector */
23				max-erase-time = <3>;
24			};
25		};
26
27		dmamux1: dmamux@40020800 {
28			dma-requests= <107>;
29		};
30
31		dmamux2: dmamux@58025800 {
32			dma-requests= <107>;
33		};
34
35		usbotg_hs: usb@40040000 {
36			compatible = "st,stm32-otghs";
37			reg = <0x40040000 0x40000>;
38			interrupts = <77 0>, <74 0>, <75 0>;
39			interrupt-names = "otghs", "ep1_out", "ep1_in";
40			num-bidir-endpoints = <9>;
41			ram-size = <4096>;
42			maximum-speed = "full-speed";
43			clocks = <&rcc STM32_CLOCK(AHB1, 25U)>,
44				 <&rcc STM32_SRC_HSI48 USB_SEL(3)>;
45			phys = <&otghs_fs_phy>;
46			status = "disabled";
47		};
48
49		ltdc: display-controller@50001000 {
50			compatible = "st,stm32-ltdc";
51			reg = <0x50001000 0x200>;
52			interrupts = <88 0>, <89 0>;
53			interrupt-names = "ltdc", "ltdc_er";
54			clocks = <&rcc STM32_CLOCK(APB3, 3U)>;
55			resets = <&rctl STM32_RESET(APB3, 4U)>;
56			status = "disabled";
57		};
58
59		octospi1: octospi@52005000 {
60			compatible = "st,stm32-ospi";
61			reg = <0x52005000 0x1000>;
62			interrupts = <92 0>;
63			clock-names = "ospix", "ospi-ker";
64			clocks = <&rcc STM32_CLOCK(AHB3, 14U)>,
65				<&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>;
66			#address-cells = <1>;
67			#size-cells = <0>;
68			status = "disabled";
69		};
70
71		octospi2: octospi@5200a000 {
72			compatible = "st,stm32-ospi";
73			reg = <0x5200a000 0x1000>;
74			interrupts = <150 0>;
75			clock-names = "ospix", "ospi-ker";
76			clocks = <&rcc STM32_CLOCK(AHB3, 19U)>,
77				<&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>;
78			#address-cells = <1>;
79			#size-cells = <0>;
80			status = "disabled";
81		};
82
83		i2s6: i2s@58001400 {
84			compatible = "st,stm32h7-i2s", "st,stm32-i2s";
85			#address-cells = <1>;
86			#size-cells = <0>;
87			reg = <0x58001400 0x400>;
88			clocks = <&rcc STM32_CLOCK(APB4, 5U)>,
89				 <&rcc STM32_SRC_PLL1_Q SPI6_SEL(0)>;
90			dmas = <&dmamux2 0 12 0x20440 &dmamux2 1 11 0x20480>;
91			dma-names = "tx", "rx";
92			interrupts = <86 0>;
93			status = "disabled";
94		};
95
96		rng: rng@48021800 {
97			nist-config = <0xf00d00>;
98			health-test-magic = <0x17590abc>;
99			health-test-config = <0x72ac>;
100		};
101
102		digi_die_temp: digi_dietemp@58006800 {
103			compatible = "st,stm32-digi-temp";
104			reg = <0x58006800 0x400>;
105			interrupts = <147 0>;
106			interrupt-names = "digi_temp";
107			clocks = <&rcc STM32_CLOCK(APB4, 26U)>;
108			status = "disabled";
109		};
110	};
111
112	/* System data RAM accessible over AXI bus: AXI SRAM1 in CD domain */
113	sram0: memory@24000000 {
114		compatible = "mmio-sram";
115		reg = <0x24000000 DT_SIZE_K(256)>;
116	};
117
118	/* System data RAM accessible over AXI bus: AXI SRAM2 in CD domain */
119	sram1: memory@24040000 {
120		compatible = "zephyr,memory-region", "mmio-sram";
121		reg = <0x24040000 DT_SIZE_K(384)>;
122		zephyr,memory-region = "SRAM1";
123	};
124
125	/* System data RAM accessible over AXI bus: AXI SRAM3 in CD domain */
126	sram2: memory@240A0000 {
127		compatible = "zephyr,memory-region", "mmio-sram";
128		reg = <0x240A0000 DT_SIZE_K(384)>;
129		zephyr,memory-region = "SRAM2";
130	};
131
132	/* System data RAM accessible over AHB bus: SRAM1 in CD domain */
133	sram3: memory@30000000 {
134		compatible = "zephyr,memory-region", "mmio-sram";
135		reg = <0x30000000 DT_SIZE_K(64)>;
136		zephyr,memory-region = "SRAM3";
137	};
138
139	/* System data RAM accessible over AHB bus: SRAM2 in CD domain  */
140	sram4: memory@30010000 {
141		compatible = "zephyr,memory-region", "mmio-sram";
142		reg = <0x30010000 DT_SIZE_K(64)>;
143		zephyr,memory-region = "SRAM4";
144	};
145
146	/* System data RAM accessible over AHB bus: SRD SRAM in SRD domain  */
147	sram5: memory@38000000 {
148		compatible = "zephyr,memory-region", "mmio-sram";
149		reg = <0x38000000 DT_SIZE_K(32)>;
150		zephyr,memory-region = "SRAM5";
151	};
152
153	dtcm: memory@20000000 {
154		compatible = "zephyr,memory-region", "arm,dtcm";
155		reg = <0x20000000 DT_SIZE_K(128)>;
156		zephyr,memory-region = "DTCM";
157	};
158
159	itcm: memory@0 {
160		compatible = "zephyr,memory-region", "arm,itcm";
161		reg = <0x00000000 DT_SIZE_K(64)>;
162		zephyr,memory-region = "ITCM";
163	};
164
165	ext_memory2: memory@70000000 {
166		compatible = "zephyr,memory-region";
167		reg = <0x70000000 DT_SIZE_M(256)>; /* max addressable area */
168		zephyr,memory-region = "EXTMEM2";
169		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_EXTMEM) )>;
170	};
171
172	otghs_fs_phy: otghs_fs_phy {
173		compatible = "usb-nop-xceiv";
174		#phy-cells = <0>;
175	};
176
177	die_temp: dietemp {
178		ts-cal1-addr = <0x08FFF814>;
179		ts-cal2-addr = <0x08FFF818>;
180		io-channels = <&adc2 18>;
181		ts-cal2-temp = <130>;
182	};
183
184	vref: vref {
185		vrefint-cal-addr = <0x08FFF810>;
186		io-channels = <&adc2 19>;
187	};
188
189	vbat: vbat {
190		io-channels = <&adc2 14>;
191	};
192};
193