1/* 2 * Copyright (c) 2020 Alexander Kozhinov <ak.alexander.kozhinov@gmail.com> 3 * Copyright (c) 2022 Georgij Cernysiov <geo.cgv@gmail.com> 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8#include <mem.h> 9#include <st/h7/stm32h7.dtsi> 10#include <zephyr/dt-bindings/display/panel.h> 11#include <zephyr/dt-bindings/flash_controller/ospi.h> 12 13/ { 14 soc { 15 compatible = "st,stm32h723", "st,stm32h7", "simple-bus"; 16 17 flash-controller@52002000 { 18 flash0: flash@8000000 { 19 compatible = "st,stm32-nv-flash", "soc-nv-flash"; 20 write-block-size = <32>; 21 erase-block-size = <DT_SIZE_K(128)>; 22 /* maximum erase time for a 128K sector */ 23 max-erase-time = <4000>; 24 }; 25 }; 26 27 uart9: serial@40011800 { 28 compatible = "st,stm32-uart"; 29 reg = <0x40011800 0x400>; 30 clocks = <&rcc STM32_CLOCK(APB2, 6U)>; 31 resets = <&rctl STM32_RESET(APB2, 6U)>; 32 interrupts = <155 0>; 33 status = "disabled"; 34 }; 35 36 usart10: serial@40011c00 { 37 compatible = "st,stm32-usart", "st,stm32-uart"; 38 reg = <0x40011c00 0x400>; 39 clocks = <&rcc STM32_CLOCK(APB2, 7U)>; 40 resets = <&rctl STM32_RESET(APB2, 7U)>; 41 interrupts = <156 0>; 42 status = "disabled"; 43 }; 44 45 /* 46 * ADC3 on STM32H723, 725, 730, 733 & 735 is a 12-bit resolution 47 * ADC, so we redefine the resolution for these devices. 48 */ 49 adc3: adc@58026000 { 50 resolutions = <STM32H72X_ADC3_RES(12, 0x00) 51 STM32H72X_ADC3_RES(10, 0x01) 52 STM32H72X_ADC3_RES(8, 0x02) 53 STM32H72X_ADC3_RES(6, 0x03)>; 54 sampling-times = <3 7 13 25 48 93 248 641>; 55 st,adc-sequencer = "FULLY_CONFIGURABLE"; 56 st,adc-oversampler = "OVERSAMPLER_MINIMAL"; 57 }; 58 59 dmamux1: dmamux@40020800 { 60 dma-requests= <129>; 61 }; 62 63 dmamux2: dmamux@58025800 { 64 dma-requests= <129>; 65 }; 66 67 rng: rng@48021800 { 68 health-test-magic = <0x17590abc>; 69 health-test-config = <0xaa74>; 70 }; 71 72 usbotg_hs: usb@40040000 { 73 compatible = "st,stm32-otghs"; 74 reg = <0x40040000 0x40000>; 75 interrupts = <77 0>, <74 0>, <75 0>; 76 interrupt-names = "otghs", "ep1_out", "ep1_in"; 77 num-bidir-endpoints = <9>; 78 ram-size = <DT_SIZE_K(4)>; 79 maximum-speed = "full-speed"; 80 clocks = <&rcc STM32_CLOCK(AHB1, 25U)>, 81 <&rcc STM32_SRC_HSI48 USB_SEL(3)>; 82 phys = <&otghs_fs_phy>; 83 status = "disabled"; 84 }; 85 86 ltdc: display-controller@50001000 { 87 compatible = "st,stm32-ltdc"; 88 reg = <0x50001000 0x200>; 89 interrupts = <88 0>, <89 0>; 90 interrupt-names = "ltdc", "ltdc_er"; 91 clocks = <&rcc STM32_CLOCK(APB3, 3U)>; 92 resets = <&rctl STM32_RESET(APB3, 4U)>; 93 status = "disabled"; 94 }; 95 96 octospi1: octospi@52005000 { 97 compatible = "st,stm32-ospi"; 98 reg = <0x52005000 0x1000>; 99 interrupts = <92 0>; 100 clock-names = "ospix", "ospi-ker"; 101 clocks = <&rcc STM32_CLOCK(AHB3, 14U)>, 102 <&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>; 103 #address-cells = <1>; 104 #size-cells = <0>; 105 status = "disabled"; 106 }; 107 108 octospi2: octospi@5200a000 { 109 compatible = "st,stm32-ospi"; 110 reg = <0x5200a000 0x1000>; 111 interrupts = <150 0>; 112 clock-names = "ospix", "ospi-ker"; 113 clocks = <&rcc STM32_CLOCK(AHB3, 19U)>, 114 <&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>; 115 #address-cells = <1>; 116 #size-cells = <0>; 117 status = "disabled"; 118 }; 119 120 fdcan3: can@4000d400 { 121 compatible = "st,stm32h7-fdcan"; 122 reg = <0x4000d400 0x400>, <0x4000ac00 0x9f0>; 123 reg-names = "m_can", "message_ram"; 124 clocks = <&rcc STM32_CLOCK(APB1_2, 8U)>; 125 interrupts = <159 0>, <160 0>, <63 0>; 126 interrupt-names = "int0", "int1", "calib"; 127 bosch,mram-cfg = <0x6a0 28 8 3 3 0 3 3>; 128 status = "disabled"; 129 }; 130 131 rtc@58004000 { 132 bbram: backup_regs { 133 compatible = "st,stm32-bbram"; 134 st,backup-regs = <32>; 135 status = "disabled"; 136 }; 137 }; 138 139 timers23: timers@4000e000 { 140 compatible = "st,stm32-timers"; 141 reg = <0x4000e000 0x400>; 142 clocks = <&rcc STM32_CLOCK(APB1_2, 24U)>; 143 resets = <&rctl STM32_RESET(APB1H, 24U)>; 144 interrupts = <161 0>; 145 interrupt-names = "global"; 146 st,prescaler = <0>; 147 status = "disabled"; 148 149 pwm { 150 compatible = "st,stm32-pwm"; 151 status = "disabled"; 152 #pwm-cells = <3>; 153 }; 154 155 counter { 156 compatible = "st,stm32-counter"; 157 status = "disabled"; 158 }; 159 }; 160 161 timers24: timers@4000e400 { 162 compatible = "st,stm32-timers"; 163 reg = <0x4000e400 0x400>; 164 clocks = <&rcc STM32_CLOCK(APB1_2, 25U)>; 165 resets = <&rctl STM32_RESET(APB1H, 25U)>; 166 interrupts = <162 0>; 167 interrupt-names = "global"; 168 st,prescaler = <0>; 169 status = "disabled"; 170 171 pwm { 172 compatible = "st,stm32-pwm"; 173 status = "disabled"; 174 #pwm-cells = <3>; 175 }; 176 177 counter { 178 compatible = "st,stm32-counter"; 179 status = "disabled"; 180 }; 181 }; 182 183 digi_die_temp: digi_dietemp@58006800 { 184 compatible = "st,stm32-digi-temp"; 185 reg = <0x58006800 0x400>; 186 interrupts = <147 0>; 187 interrupt-names = "digi_temp"; 188 clocks = <&rcc STM32_CLOCK(APB4, 26U)>; 189 status = "disabled"; 190 }; 191 }; 192 193 /* D1 domain, AXI SRAM (128KB with shared ITCM 192KB as `TCM_AXI_SHARED` is `000`) */ 194 sram0: memory@24000000 { 195 reg = <0x24000000 DT_SIZE_K(320)>; 196 compatible = "mmio-sram"; 197 }; 198 199 /* D2 domain, AHB SRAM */ 200 sram1: memory@30000000 { 201 reg = <0x30000000 DT_SIZE_K(16)>; 202 compatible = "zephyr,memory-region", "mmio-sram"; 203 zephyr,memory-region = "SRAM1"; 204 }; 205 206 /* D2 domain, AHB SRAM */ 207 sram2: memory@30004000 { 208 reg = <0x30004000 DT_SIZE_K(16)>; 209 compatible = "zephyr,memory-region", "mmio-sram"; 210 zephyr,memory-region = "SRAM2"; 211 }; 212 213 /* D3 domain, AHB SRAM */ 214 sram4: memory@38000000 { 215 reg = <0x38000000 DT_SIZE_K(16)>; 216 compatible = "zephyr,memory-region", "mmio-sram"; 217 zephyr,memory-region = "SRAM4"; 218 }; 219 220 /* Data TCM RAM */ 221 dtcm: memory@20000000 { 222 compatible = "zephyr,memory-region", "arm,dtcm"; 223 reg = <0x20000000 DT_SIZE_K(128)>; 224 zephyr,memory-region = "DTCM"; 225 }; 226 227 /* Instruction TCM RAM (64KB as `TCM_AXI_SHARED` is `000`) */ 228 itcm: memory@0 { 229 compatible = "zephyr,memory-region", "arm,itcm"; 230 reg = <0x00000000 DT_SIZE_K(64)>; 231 zephyr,memory-region = "ITCM"; 232 }; 233 234 otghs_fs_phy: otghs_fs_phy { 235 compatible = "usb-nop-xceiv"; 236 #phy-cells = <0>; 237 }; 238 239 die_temp: dietemp { 240 io-channels = <&adc3 17>; 241 ts-cal2-temp = <130>; 242 }; 243 244 vref: vref { 245 io-channels = <&adc3 18>; 246 }; 247 248 vbat: vbat { 249 io-channels = <&adc3 16>; 250 }; 251}; 252
