1/*
2 * Copyright (c) 2023 STMicroelectronics
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/h5/stm32h5.dtsi>
8#include <zephyr/dt-bindings/flash_controller/ospi.h>
9/* keep both header files for compatibility */
10#include <zephyr/dt-bindings/flash_controller/xspi.h>
11
12/ {
13	clocks {
14		/* The pll scheme is similar to stm32u5 */
15		pll3: pll3 {
16			#clock-cells = <0>;
17			compatible = "st,stm32u5-pll-clock";
18			status = "disabled";
19		};
20	};
21
22	soc {
23		compatible = "st,stm32h562", "st,stm32h5", "simple-bus";
24
25		pinctrl: pin-controller@42020000 {
26			gpioe: gpio@42021000 {
27				compatible = "st,stm32-gpio";
28				gpio-controller;
29				#gpio-cells = <2>;
30				reg = <0x42021000 0x400>;
31				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
32			};
33
34			gpiof: gpio@42021400 {
35				compatible = "st,stm32-gpio";
36				gpio-controller;
37				#gpio-cells = <2>;
38				reg = <0x42021400 0x400>;
39				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
40			};
41
42			gpiog: gpio@42021800 {
43				compatible = "st,stm32-gpio";
44				gpio-controller;
45				#gpio-cells = <2>;
46				reg = <0x42021800 0x400>;
47				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
48			};
49
50			gpioi: gpio@42022000 {
51				compatible = "st,stm32-gpio";
52				gpio-controller;
53				#gpio-cells = <2>;
54				reg = <0x42022000 0x400>;
55				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000100>;
56			};
57		};
58
59		backup_sram: memory@40036400 {
60			compatible = "zephyr,memory-region", "st,stm32-backup-sram";
61			reg = <0x40036400 DT_SIZE_K(4)>;
62			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
63			zephyr,memory-region = "BACKUP_SRAM";
64			status = "disabled";
65		};
66
67		lptim3: timers@44004800 {
68			compatible = "st,stm32-lptim";
69			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x1000>;
70			#address-cells = <1>;
71			#size-cells = <0>;
72			reg = <0x44004800 0x400>;
73			interrupts = <127 1>;
74			interrupt-names = "wakeup";
75			status = "disabled";
76		};
77
78		lptim4: timers@44004c00 {
79			compatible = "st,stm32-lptim";
80			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x2000>;
81			#address-cells = <1>;
82			#size-cells = <0>;
83			reg = <0x44004c00 0x400>;
84			interrupts = <128 1>;
85			interrupt-names = "wakeup";
86			status = "disabled";
87		};
88
89		lptim5: timers@44005000 {
90			compatible = "st,stm32-lptim";
91			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x4000>;
92			#address-cells = <1>;
93			#size-cells = <0>;
94			reg = <0x44005000 0x400>;
95			interrupts = <129 1>;
96			interrupt-names = "wakeup";
97			status = "disabled";
98		};
99
100		lptim6: timers@44005400 {
101			compatible = "st,stm32-lptim";
102			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x8000>;
103			#address-cells = <1>;
104			#size-cells = <0>;
105			reg = <0x44005400 0x400>;
106			interrupts = <130 1>;
107			interrupt-names = "wakeup";
108			status = "disabled";
109		};
110
111		uart4: serial@40004c00 {
112			compatible = "st,stm32-uart";
113			reg = <0x40004c00 0x400>;
114			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
115			resets = <&rctl STM32_RESET(APB1L, 19U)>;
116			interrupts = <61 0>;
117			status = "disabled";
118		};
119
120		uart5: serial@40005000 {
121			compatible = "st,stm32-uart";
122			reg = <0x40005000 0x400>;
123			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
124			resets = <&rctl STM32_RESET(APB1L, 20U)>;
125			interrupts = <62 0>;
126			status = "disabled";
127		};
128
129		uart7: serial@40007800 {
130			compatible = "st,stm32-uart";
131			reg = <0x40007800 0x400>;
132			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
133			resets = <&rctl STM32_RESET(APB1L, 30U)>;
134			interrupts = <98 0>;
135			status = "disabled";
136		};
137
138		uart8: serial@40007c00 {
139			compatible = "st,stm32-uart";
140			reg = <0x40007c00 0x400>;
141			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
142			resets = <&rctl STM32_RESET(APB1L, 31U)>;
143			interrupts = <99 0>;
144			status = "disabled";
145		};
146
147		uart9: serial@40008000 {
148			compatible = "st,stm32-uart";
149			reg = <0x40008000 0x400>;
150			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>;
151			resets = <&rctl STM32_RESET(APB1H, 0U)>;
152			interrupts = <100 0>;
153			status = "disabled";
154		};
155
156		usart6: serial@40006400 {
157			compatible = "st,stm32-usart", "st,stm32-uart";
158			reg = <0x40006400 0x400>;
159			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
160			resets = <&rctl STM32_RESET(APB1L, 25U)>;
161			interrupts = <85 0>;
162			status = "disabled";
163		};
164
165		usart10: serial@40006800 {
166			compatible = "st,stm32-usart", "st,stm32-uart";
167			reg = <0x40006800 0x400>;
168			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
169			resets = <&rctl STM32_RESET(APB1L, 26U)>;
170			interrupts = <86 0>;
171			status = "disabled";
172		};
173
174		usart11: serial@40006c00 {
175			compatible = "st,stm32-usart", "st,stm32-uart";
176			reg = <0x40006c00 0x400>;
177			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x08000000>;
178			resets = <&rctl STM32_RESET(APB1L, 27U)>;
179			interrupts = <87 0>;
180			status = "disabled";
181		};
182
183		uart12: serial@40008400 {
184			compatible = "st,stm32-uart";
185			reg = <0x40008400 0x400>;
186			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
187			resets = <&rctl STM32_RESET(APB1H, 1U)>;
188			interrupts = <101 0>;
189			status = "disabled";
190		};
191
192		i2c3: i2c@44002800 {
193			compatible = "st,stm32-i2c-v2";
194			clock-frequency = <I2C_BITRATE_STANDARD>;
195			#address-cells = <1>;
196			#size-cells = <0>;
197			reg = <0x44002800 0x400>;
198			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000080>;
199			interrupts = <80 0>, <81 0>;
200			interrupt-names = "event", "error";
201			status = "disabled";
202		};
203
204		i2c4: i2c@44002c00 {
205			compatible = "st,stm32-i2c-v2";
206			clock-frequency = <I2C_BITRATE_STANDARD>;
207			#address-cells = <1>;
208			#size-cells = <0>;
209			reg = <0x44002c00 0x400>;
210			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000100>;
211			interrupts = <125 0>, <126 0>;
212			interrupt-names = "event", "error";
213			status = "disabled";
214		};
215
216		spi4: spi@40014c00 {
217			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
218			#address-cells = <1>;
219			#size-cells = <0>;
220			reg = <0x40014c00 0x400>;
221			interrupts = <82 5>;
222			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00080000>;
223			status = "disabled";
224		};
225
226		spi5: spi@44002000 {
227			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
228			#address-cells = <1>;
229			#size-cells = <0>;
230			reg = <0x44002000 0x400>;
231			interrupts = <83 5>;
232			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000020>;
233			status = "disabled";
234		};
235
236		spi6: spi@40015000 {
237			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
238			#address-cells = <1>;
239			#size-cells = <0>;
240			reg = <0x40015000 0x400>;
241			interrupts = <84 5>;
242			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
243			status = "disabled";
244		};
245
246		xspi1: xspi@47001400 {
247			compatible = "st,stm32-xspi";
248			reg = <0x47001400 0x400>;
249			interrupts = <78 0>;
250			clock-names = "xspix", "xspi-ker";
251			clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00100000>,
252				<&rcc STM32_SRC_PLL1_Q OCTOSPI1_SEL(1)>;
253			#address-cells = <1>;
254			#size-cells = <0>;
255			status = "disabled";
256		};
257
258		adc2: adc@42028100 {
259			compatible = "st,stm32-adc";
260			reg = <0x42028100 0x400>;
261			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000400>;
262			interrupts = <69 0>;
263			status = "disabled";
264			vref-mv = <3300>;
265			#io-channel-cells = <1>;
266			resolutions = <STM32_ADC_RES(12, 0x00)
267					STM32_ADC_RES(10, 0x01)
268					STM32_ADC_RES(8, 0x02)
269					STM32_ADC_RES(6, 0x03)>;
270			sampling-times = <3 7 13 25 48 93 248 641>;
271			st,adc-sequencer = <FULLY_CONFIGURABLE>;
272		};
273
274		timers4: timers@40000800 {
275			compatible = "st,stm32-timers";
276			reg = <0x40000800 0x400>;
277			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
278			resets = <&rctl STM32_RESET(APB1L, 2U)>;
279			interrupts = <47 0>;
280			interrupt-names = "global";
281			status = "disabled";
282
283			pwm {
284				compatible = "st,stm32-pwm";
285				status = "disabled";
286				#pwm-cells = <3>;
287			};
288
289			counter {
290				compatible = "st,stm32-counter";
291				status = "disabled";
292			};
293		};
294
295		timers5: timers@40000c00 {
296			compatible = "st,stm32-timers";
297			reg = <0x40000c00 0x400>;
298			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
299			resets = <&rctl STM32_RESET(APB1L, 3U)>;
300			interrupts = <48 0>;
301			interrupt-names = "global";
302			status = "disabled";
303
304			pwm {
305				compatible = "st,stm32-pwm";
306				status = "disabled";
307				#pwm-cells = <3>;
308			};
309
310			counter {
311				compatible = "st,stm32-counter";
312				status = "disabled";
313			};
314		};
315
316		timers12: timers@40001800 {
317			compatible = "st,stm32-timers";
318			reg = <0x40001800 0x400>;
319			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
320			resets = <&rctl STM32_RESET(APB1L, 6U)>;
321			interrupts = <120 0>;
322			interrupt-names = "global";
323			status = "disabled";
324
325			pwm {
326				compatible = "st,stm32-pwm";
327				status = "disabled";
328				#pwm-cells = <3>;
329			};
330
331			counter {
332				compatible = "st,stm32-counter";
333				status = "disabled";
334			};
335		};
336
337		timers13: timers@40001c00 {
338			compatible = "st,stm32-timers";
339			reg = <0x40001c00 0x400>;
340			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
341			resets = <&rctl STM32_RESET(APB1L, 7U)>;
342			interrupts = <121 0>;
343			interrupt-names = "global";
344			status = "disabled";
345
346			pwm {
347				compatible = "st,stm32-pwm";
348				status = "disabled";
349				#pwm-cells = <3>;
350			};
351
352			counter {
353				compatible = "st,stm32-counter";
354				status = "disabled";
355			};
356		};
357
358		timers14: timers@40002000 {
359			compatible = "st,stm32-timers";
360			reg = <0x40002000 0x400>;
361			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
362			resets = <&rctl STM32_RESET(APB1L, 8U)>;
363			interrupts = <122 0>;
364			interrupt-names = "global";
365			status = "disabled";
366
367			pwm {
368				compatible = "st,stm32-pwm";
369				status = "disabled";
370				#pwm-cells = <3>;
371			};
372
373			counter {
374				compatible = "st,stm32-counter";
375				status = "disabled";
376			};
377		};
378
379		timers15: timers@40014000 {
380			compatible = "st,stm32-timers";
381			reg = <0x40014000 0x400>;
382			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
383			resets = <&rctl STM32_RESET(APB2, 16U)>;
384			interrupts = <71 0>;
385			interrupt-names = "global";
386			status = "disabled";
387
388			pwm {
389				compatible = "st,stm32-pwm";
390				status = "disabled";
391				#pwm-cells = <3>;
392			};
393
394			counter {
395				compatible = "st,stm32-counter";
396				status = "disabled";
397			};
398		};
399
400		timers16: timers@40014400 {
401			compatible = "st,stm32-timers";
402			reg = <0x40014400 0x400>;
403			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
404			resets = <&rctl STM32_RESET(APB2, 17U)>;
405			interrupts = <72 0>;
406			interrupt-names = "global";
407			status = "disabled";
408
409			pwm {
410				compatible = "st,stm32-pwm";
411				status = "disabled";
412				#pwm-cells = <3>;
413			};
414
415			counter {
416				compatible = "st,stm32-counter";
417				status = "disabled";
418			};
419		};
420
421		timers17: timers@40014800 {
422			compatible = "st,stm32-timers";
423			reg = <0x40014800 0x400>;
424			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
425			resets = <&rctl STM32_RESET(APB2, 18U)>;
426			interrupts = <73 0>;
427			interrupt-names = "global";
428			status = "disabled";
429
430			pwm {
431				compatible = "st,stm32-pwm";
432				status = "disabled";
433				#pwm-cells = <3>;
434			};
435
436			counter {
437				compatible = "st,stm32-counter";
438				status = "disabled";
439			};
440		};
441
442		aes: aes@420c0000 {
443			compatible = "st,stm32-aes";
444			reg = <0x420c0000 0x400>;
445			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00010000>;
446			resets = <&rctl STM32_RESET(AHB2, 16U)>;
447			interrupts = <116 0>;
448			status = "disabled";
449		};
450
451		fdcan2: can@4000a800 {
452			compatible = "st,stm32-fdcan";
453			reg = <0x4000a800 0x400>, <0x4000ac00 0x6a0>;
454			reg-names = "m_can", "message_ram";
455			interrupts = <109 0>, <110 0>;
456			interrupt-names = "int0", "int1";
457			/* common clock FDCAN 1 & 2 */
458			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>;
459			bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>;
460			status = "disabled";
461		};
462
463		sdmmc1: sdmmc@46008000 {
464			compatible = "st,stm32-sdmmc";
465			reg = <0x46008000 0x400>;
466			clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000800>,
467				 <&rcc STM32_SRC_PLL1_Q SDMMC1_SEL(0)>;
468			resets = <&rctl STM32_RESET(AHB4, 11U)>;
469			interrupts = <79 0>;
470			status = "disabled";
471		};
472	};
473
474	smbus3: smbus3 {
475		compatible = "st,stm32-smbus";
476		#address-cells = <1>;
477		#size-cells = <0>;
478		i2c = <&i2c3>;
479		status = "disabled";
480	};
481
482	smbus4: smbus4 {
483		compatible = "st,stm32-smbus";
484		#address-cells = <1>;
485		#size-cells = <0>;
486		i2c = <&i2c4>;
487		status = "disabled";
488	};
489};
490