1/* 2 * Copyright (c) 2023-2024 STMicroelectronics 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 8#include <arm/armv8-m.dtsi> 9#include <zephyr/dt-bindings/adc/adc.h> 10#include <zephyr/dt-bindings/clock/stm32h5_clock.h> 11#include <zephyr/dt-bindings/gpio/gpio.h> 12#include <zephyr/dt-bindings/i2c/i2c.h> 13#include <zephyr/dt-bindings/reset/stm32h5_reset.h> 14#include <zephyr/dt-bindings/dma/stm32_dma.h> 15#include <zephyr/dt-bindings/pwm/pwm.h> 16#include <zephyr/dt-bindings/adc/stm32l4_adc.h> 17#include <freq.h> 18 19/ { 20 chosen { 21 zephyr,flash-controller = &flash; 22 zephyr,entropy = &rng; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu0: cpu@0 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-m33"; 32 reg = <0>; 33 cpu-power-states = <&stop>; 34 #address-cells = <1>; 35 #size-cells = <1>; 36 37 mpu: mpu@e000ed90 { 38 compatible = "arm,armv8m-mpu"; 39 reg = <0xe000ed90 0x40>; 40 }; 41 }; 42 }; 43 44 clocks { 45 clk_hse: clk-hse { 46 #clock-cells = <0>; 47 compatible = "st,stm32-hse-clock"; 48 status = "disabled"; 49 }; 50 51 clk_hsi: clk-hsi { 52 #clock-cells = <0>; 53 compatible = "st,stm32h7-hsi-clock"; 54 hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */ 55 clock-frequency = <DT_FREQ_M(64)>; 56 status = "disabled"; 57 }; 58 59 clk_hsi48: clk-hsi48 { 60 #clock-cells = <0>; 61 compatible = "fixed-clock"; 62 clock-frequency = <DT_FREQ_M(48)>; 63 status = "disabled"; 64 }; 65 66 clk_csi: clk-csi { 67 #clock-cells = <0>; 68 compatible = "fixed-clock"; 69 clock-frequency = <DT_FREQ_M(4)>; 70 status = "disabled"; 71 }; 72 73 clk_lse: clk-lse { 74 #clock-cells = <0>; 75 compatible = "st,stm32-lse-clock"; 76 clock-frequency = <32768>; 77 driving-capability = <2>; 78 status = "disabled"; 79 }; 80 81 clk_lsi: clk-lsi { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <DT_FREQ_K(32)>; 85 status = "disabled"; 86 }; 87 /* The pll scheme is similar to stm32u5 */ 88 pll1: pll: pll { 89 #clock-cells = <0>; 90 compatible = "st,stm32u5-pll-clock"; 91 status = "disabled"; 92 }; 93 94 pll2: pll2 { 95 #clock-cells = <0>; 96 compatible = "st,stm32u5-pll-clock"; 97 status = "disabled"; 98 }; 99 }; 100 101 soc { 102 flash: flash-controller@40022000 { 103 compatible = "st,stm32-flash-controller", "st,stm32l5-flash-controller"; 104 reg = <0x40022000 0x400>; 105 interrupts = <6 0>; 106 107 #address-cells = <1>; 108 #size-cells = <1>; 109 110 flash0: flash@8000000 { 111 compatible = "st,stm32-nv-flash", "soc-nv-flash"; 112 113 write-block-size = <16>; 114 erase-block-size = <8192>; 115 /* maximum erase time(ms) for a 8K sector */ 116 max-erase-time = <5>; 117 }; 118 }; 119 120 power-states { 121 stop: state0 { 122 compatible = "zephyr,power-state"; 123 power-state-name = "suspend-to-idle"; 124 substate-id = <1>; 125 min-residency-us = <20>; 126 }; 127 }; 128 129 rcc: rcc@44020c00 { 130 compatible = "st,stm32u5-rcc"; 131 clocks-controller; 132 #clock-cells = <2>; 133 reg = <0x44020c00 0x400>; 134 135 rctl: reset-controller { 136 compatible = "st,stm32-rcc-rctl"; 137 #reset-cells = <1>; 138 }; 139 }; 140 141 exti: interrupt-controller@44022000 { 142 compatible = "st,stm32g0-exti", "st,stm32-exti"; 143 interrupt-controller; 144 #interrupt-cells = <1>; 145 #address-cells = <1>; 146 reg = <0x44022000 0x400>; 147 num-lines = <16>; 148 interrupts = <11 0>, <12 0>, <13 0>, <14 0>, 149 <15 0>, <16 0>, <17 0>, <18 0>, 150 <19 0>, <20 0>, <21 0>, <22 0>, 151 <23 0>, <24 0>, <25 0>, <26 0>; 152 interrupt-names = "line0", "line1", "line2", "line3", 153 "line4", "line5", "line6", "line7", 154 "line8", "line9", "line10", "line11", 155 "line12", "line13", "line14", "line15"; 156 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, 157 <4 1>, <5 1>, <6 1>, <7 1>, 158 <8 1>, <9 1>, <10 1>, <11 1>, 159 <12 1>, <13 1>, <14 1>, <15 1>; 160 }; 161 162 pinctrl: pin-controller@42020000 { 163 compatible = "st,stm32-pinctrl"; 164 #address-cells = <1>; 165 #size-cells = <1>; 166 reg = <0x42020000 0x2000>; 167 168 gpioa: gpio@42020000 { 169 compatible = "st,stm32-gpio"; 170 gpio-controller; 171 #gpio-cells = <2>; 172 reg = <0x42020000 0x400>; 173 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>; 174 }; 175 176 gpiob: gpio@42020400 { 177 compatible = "st,stm32-gpio"; 178 gpio-controller; 179 #gpio-cells = <2>; 180 reg = <0x42020400 0x400>; 181 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>; 182 }; 183 184 gpioc: gpio@42020800 { 185 compatible = "st,stm32-gpio"; 186 gpio-controller; 187 #gpio-cells = <2>; 188 reg = <0x42020800 0x400>; 189 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>; 190 }; 191 192 gpiod: gpio@42020c00 { 193 compatible = "st,stm32-gpio"; 194 gpio-controller; 195 #gpio-cells = <2>; 196 reg = <0x42020c00 0x400>; 197 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>; 198 }; 199 200 gpioh: gpio@42021c00 { 201 compatible = "st,stm32-gpio"; 202 gpio-controller; 203 #gpio-cells = <2>; 204 reg = <0x42021c00 0x400>; 205 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>; 206 }; 207 }; 208 209 lptim1: timers@44004400 { 210 compatible = "st,stm32-lptim"; 211 clocks = <&rcc STM32_CLOCK_BUS_APB3 0x800>; 212 #address-cells = <1>; 213 #size-cells = <0>; 214 reg = <0x44004400 0x400>; 215 interrupts = <64 1>; 216 interrupt-names = "wakeup"; 217 status = "disabled"; 218 }; 219 220 lptim2: timers@40009400 { 221 compatible = "st,stm32-lptim"; 222 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x20>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 reg = <0x40009400 0x400>; 226 interrupts = <70 1>; 227 interrupt-names = "wakeup"; 228 status = "disabled"; 229 }; 230 231 usart1: serial@40013800 { 232 compatible = "st,stm32-usart", "st,stm32-uart"; 233 reg = <0x40013800 0x400>; 234 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>; 235 resets = <&rctl STM32_RESET(APB2, 14U)>; 236 interrupts = <58 0>; 237 status = "disabled"; 238 }; 239 240 usart2: serial@40004400 { 241 compatible = "st,stm32-usart", "st,stm32-uart"; 242 reg = <0x40004400 0x400>; 243 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>; 244 resets = <&rctl STM32_RESET(APB1L, 17U)>; 245 interrupts = <59 0>; 246 status = "disabled"; 247 }; 248 249 usart3: serial@40004800 { 250 compatible = "st,stm32-usart", "st,stm32-uart"; 251 reg = <0x40004800 0x400>; 252 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>; 253 resets = <&rctl STM32_RESET(APB1L, 18U)>; 254 interrupts = <60 0>; 255 status = "disabled"; 256 }; 257 258 lpuart1: serial@44002400 { 259 compatible = "st,stm32-lpuart", "st,stm32-uart"; 260 reg = <0x44002400 0x400>; 261 clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000040>; 262 resets = <&rctl STM32_RESET(APB3, 6U)>; 263 interrupts = <63 0>; 264 status = "disabled"; 265 }; 266 267 iwdg: watchdog@40003000 { 268 compatible = "st,stm32-watchdog"; 269 reg = <0x40003000 0x400>; 270 status = "disabled"; 271 }; 272 273 wwdg: watchdog@40002c00 { 274 compatible = "st,stm32-window-watchdog"; 275 reg = <0x40002c00 0x400>; 276 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>; 277 interrupts = <0 7>; 278 status = "disabled"; 279 }; 280 281 dac1: dac@42028400 { 282 compatible = "st,stm32-dac"; 283 reg = <0x42028400 0x400>; 284 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000800>; 285 status = "disabled"; 286 #io-channel-cells = <1>; 287 }; 288 289 adc1: adc@42028000 { 290 compatible = "st,stm32-adc"; 291 reg = <0x42028000 0x400>; 292 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000400>; 293 interrupts = <37 0>; 294 status = "disabled"; 295 vref-mv = <3300>; 296 #io-channel-cells = <1>; 297 resolutions = <STM32_ADC_RES(12, 0x00) 298 STM32_ADC_RES(10, 0x01) 299 STM32_ADC_RES(8, 0x02) 300 STM32_ADC_RES(6, 0x03)>; 301 sampling-times = <3 7 13 25 48 93 248 641>; 302 st,adc-sequencer = <FULLY_CONFIGURABLE>; 303 }; 304 305 rtc: rtc@44007800 { 306 compatible = "st,stm32-rtc"; 307 reg = <0x44007800 0x400>; 308 interrupts = <2 0>; 309 clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00200000>; 310 prescaler = <32768>; 311 alarms-count = <2>; 312 alrm-exti-line = <17>; 313 status = "disabled"; 314 }; 315 316 timers1: timers@40012c00 { 317 compatible = "st,stm32-timers"; 318 reg = <0x40012c00 0x400>; 319 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>; 320 resets = <&rctl STM32_RESET(APB2, 11U)>; 321 interrupts = <41 0>, <42 0>, <43 0>, <44 0>; 322 interrupt-names = "brk", "up", "trgcom", "cc"; 323 status = "disabled"; 324 325 pwm { 326 compatible = "st,stm32-pwm"; 327 status = "disabled"; 328 #pwm-cells = <3>; 329 }; 330 }; 331 332 timers2: timers@40000000 { 333 compatible = "st,stm32-timers"; 334 reg = <0x40000000 0x400>; 335 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>; 336 resets = <&rctl STM32_RESET(APB1L, 0U)>; 337 interrupts = <45 0>; 338 interrupt-names = "global"; 339 status = "disabled"; 340 341 pwm { 342 compatible = "st,stm32-pwm"; 343 status = "disabled"; 344 #pwm-cells = <3>; 345 }; 346 347 counter { 348 compatible = "st,stm32-counter"; 349 status = "disabled"; 350 }; 351 }; 352 353 timers3: timers@40000400 { 354 compatible = "st,stm32-timers"; 355 reg = <0x40000400 0x400>; 356 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>; 357 resets = <&rctl STM32_RESET(APB1L, 1U)>; 358 interrupts = <46 0>; 359 interrupt-names = "global"; 360 status = "disabled"; 361 362 pwm { 363 compatible = "st,stm32-pwm"; 364 status = "disabled"; 365 #pwm-cells = <3>; 366 }; 367 368 counter { 369 compatible = "st,stm32-counter"; 370 status = "disabled"; 371 }; 372 }; 373 374 timers6: timers@40001000 { 375 compatible = "st,stm32-timers"; 376 reg = <0x40001000 0x400>; 377 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>; 378 resets = <&rctl STM32_RESET(APB1L, 4U)>; 379 interrupts = <49 0>; 380 interrupt-names = "global"; 381 status = "disabled"; 382 383 pwm { 384 compatible = "st,stm32-pwm"; 385 status = "disabled"; 386 #pwm-cells = <3>; 387 }; 388 389 counter { 390 compatible = "st,stm32-counter"; 391 status = "disabled"; 392 }; 393 }; 394 395 timers7: timers@40001400 { 396 compatible = "st,stm32-timers"; 397 reg = <0x40001400 0x400>; 398 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>; 399 resets = <&rctl STM32_RESET(APB1L, 5U)>; 400 interrupts = <50 0>; 401 interrupt-names = "global"; 402 status = "disabled"; 403 404 pwm { 405 compatible = "st,stm32-pwm"; 406 status = "disabled"; 407 #pwm-cells = <3>; 408 }; 409 410 counter { 411 compatible = "st,stm32-counter"; 412 status = "disabled"; 413 }; 414 }; 415 416 i2c1: i2c@40005400 { 417 compatible = "st,stm32-i2c-v2"; 418 clock-frequency = <I2C_BITRATE_STANDARD>; 419 #address-cells = <1>; 420 #size-cells = <0>; 421 reg = <0x40005400 0x400>; 422 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>; 423 interrupts = <51 0>, <52 0>; 424 interrupt-names = "event", "error"; 425 status = "disabled"; 426 }; 427 428 i2c2: i2c@40005800 { 429 compatible = "st,stm32-i2c-v2"; 430 clock-frequency = <I2C_BITRATE_STANDARD>; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 reg = <0x40005800 0x400>; 434 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>; 435 interrupts = <53 0>, <54 0>; 436 interrupt-names = "event", "error"; 437 status = "disabled"; 438 }; 439 440 spi1: spi@40013000 { 441 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 reg = <0x40013000 0x400>; 445 interrupts = <55 5>; 446 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>; 447 status = "disabled"; 448 }; 449 450 spi2: spi@40003800 { 451 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 reg = <0x40003800 0x400>; 455 interrupts = <56 5>; 456 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>; 457 status = "disabled"; 458 }; 459 460 spi3: spi@40003c00 { 461 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 reg = <0x40003c00 0x400>; 465 interrupts = <57 5>; 466 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>; 467 status = "disabled"; 468 }; 469 470 fdcan1: can@4000a400 { 471 compatible = "st,stm32-fdcan"; 472 reg = <0x4000a400 0x400>, <0x4000ac00 0x350>; 473 reg-names = "m_can", "message_ram"; 474 interrupts = <39 0>, <40 0>; 475 interrupt-names = "int0", "int1"; 476 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>; 477 bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>; 478 status = "disabled"; 479 }; 480 481 rng: rng@420c0800 { 482 compatible = "st,stm32-rng"; 483 reg = <0x420c0800 0x400>; 484 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>; 485 interrupts = <114 0>; 486 nist-config = <0xf00d00>; 487 health-test-config = <0xaac7>; 488 status = "disabled"; 489 }; 490 491 mac: ethernet@40028000 { 492 compatible = "st,stm32-ethernet"; 493 reg = <0x40028000 0x8000>; 494 interrupts = <106 0>; 495 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; 496 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00080000>, 497 <&rcc STM32_CLOCK_BUS_AHB1 0x00100000>, 498 <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>; 499 status = "disabled"; 500 501 mdio: mdio { 502 compatible = "st,stm32-mdio"; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 status = "disabled"; 506 }; 507 }; 508 509 gpdma1: dma@40020000 { 510 compatible = "st,stm32u5-dma"; 511 #dma-cells = <3>; 512 reg = <0x40020000 0x1000>; 513 interrupts = <27 0 28 0 29 0 30 0 31 0 32 0 33 0 34 0>; 514 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>; 515 dma-channels = <8>; 516 dma-requests = <140>; 517 dma-offset = <0>; 518 status = "disabled"; 519 }; 520 521 gpdma2: dma@40021000 { 522 compatible = "st,stm32u5-dma"; 523 #dma-cells = <3>; 524 reg = <0x40021000 0x1000>; 525 interrupts = <90 0 91 0 92 0 93 0 94 0 95 0 96 0 97 0>; 526 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>; 527 dma-channels = <8>; 528 dma-requests = <140>; 529 dma-offset = <8>; 530 status = "disabled"; 531 }; 532 533 i2s1: i2s@40013000 { 534 compatible = "st,stm32h7-i2s", "st,stm32-i2s"; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 reg = <0x40013000 0x400>; 538 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>, 539 <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>; 540 dmas = <&gpdma1 0 7 (STM32_DMA_PERIPH_TX |STM32_DMA_16BITS | \ 541 STM32_DMA_PRIORITY_HIGH) 542 &gpdma1 1 6 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | \ 543 STM32_DMA_PRIORITY_HIGH)>; 544 dma-names = "tx", "rx"; 545 interrupts = <55 3>; 546 status = "disabled"; 547 }; 548 549 i2s2: i2s@40003800 { 550 compatible = "st,stm32h7-i2s", "st,stm32-i2s"; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 reg = <0x40003800 0x400>; 554 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>, 555 <&rcc STM32_SRC_PLL1_Q SPI2_SEL(0)>; 556 dmas = <&gpdma1 2 9 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | \ 557 STM32_DMA_PRIORITY_HIGH) 558 &gpdma1 3 8 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | \ 559 STM32_DMA_PRIORITY_HIGH)>; 560 dma-names = "tx", "rx"; 561 interrupts = <56 3>; 562 status = "disabled"; 563 }; 564 565 i2s3: i2s@40003c00 { 566 compatible = "st,stm32h7-i2s", "st,stm32-i2s"; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 reg = <0x40003c00 0x400>; 570 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>, 571 <&rcc STM32_SRC_PLL1_Q SPI3_SEL(0)>; 572 dmas = <&gpdma1 4 11 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | \ 573 STM32_DMA_PRIORITY_HIGH) 574 &gpdma1 5 10 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | \ 575 STM32_DMA_PRIORITY_HIGH)>; 576 dma-names = "tx", "rx"; 577 interrupts = <57 3>; 578 status = "disabled"; 579 }; 580 581 usb: usb@40016000 { 582 compatible = "st,stm32-usb"; 583 reg = <0x40016000 0x400>; 584 interrupts = <74 0>; 585 interrupt-names = "usb"; 586 num-bidir-endpoints = <8>; 587 ram-size = <2048>; 588 phys = <&usb_fs_phy>; 589 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x01000000>, 590 <&rcc STM32_SRC_HSI48 USB_SEL(3)>; 591 status = "disabled"; 592 }; 593 }; 594 595 die_temp: dietemp { 596 compatible = "st,stm32-temp-cal"; 597 ts-cal1-addr = <0x08fff814>; 598 ts-cal2-addr = <0x08fff818>; 599 ts-cal1-temp = <30>; 600 ts-cal2-temp = <130>; 601 ts-cal-vrefanalog = <3300>; 602 ts-cal-resolution = <12>; 603 io-channels = <&adc1 16>; 604 status = "disabled"; 605 }; 606 607 vref: vref { 608 compatible = "st,stm32-vref"; 609 vrefint-cal-addr = <0x08FFF810>; 610 vrefint-cal-mv = <3300>; 611 io-channels = <&adc1 17>; 612 status = "disabled"; 613 }; 614 615 vbat: vbat { 616 compatible = "st,stm32-vbat"; 617 ratio = <4>; 618 io-channels = <&adc1 2>; 619 status = "disabled"; 620 }; 621 622 usb_fs_phy: usbphy { 623 compatible = "usb-nop-xceiv"; 624 #phy-cells = <0>; 625 }; 626 627 smbus1: smbus1 { 628 compatible = "st,stm32-smbus"; 629 #address-cells = <1>; 630 #size-cells = <0>; 631 i2c = <&i2c1>; 632 status = "disabled"; 633 }; 634 635 smbus2: smbus2 { 636 compatible = "st,stm32-smbus"; 637 #address-cells = <1>; 638 #size-cells = <0>; 639 i2c = <&i2c2>; 640 status = "disabled"; 641 }; 642}; 643 644&nvic { 645 arm,num-irq-priority-bits = <4>; 646}; 647
