1/*
2 * Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
3 * Copyright (c) 2019-2024 STMicroelectronics
4 * Copyright (c) 2019 Centaur Analytics, Inc
5 * Copyright (C) 2020 Framework Computer LLC <ktl@frame.work>
6 * Copyright (c) 2021 G-Technologies Sdn. Bhd.
7 *
8 * SPDX-License-Identifier: Apache-2.0
9 */
10
11#include <arm/armv6-m.dtsi>
12#include <zephyr/dt-bindings/clock/stm32g0_clock.h>
13#include <zephyr/dt-bindings/gpio/gpio.h>
14#include <zephyr/dt-bindings/i2c/i2c.h>
15#include <zephyr/dt-bindings/pwm/pwm.h>
16#include <zephyr/dt-bindings/dma/stm32_dma.h>
17#include <zephyr/dt-bindings/adc/adc.h>
18#include <zephyr/dt-bindings/adc/stm32l4_adc.h>
19#include <zephyr/dt-bindings/pwm/stm32_pwm.h>
20#include <zephyr/dt-bindings/reset/stm32g0_reset.h>
21#include <freq.h>
22
23/ {
24	chosen {
25		zephyr,flash-controller = &flash;
26	};
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		cpu0: cpu@0 {
33			device_type = "cpu";
34			compatible = "arm,cortex-m0+";
35			reg = <0>;
36			cpu-power-states = <&stop0 &stop1>;
37		};
38
39		power-states {
40			stop0: state0 {
41				compatible = "zephyr,power-state";
42				power-state-name = "suspend-to-idle";
43				substate-id = <1>;
44				min-residency-us = <20>;
45			};
46			stop1: state1 {
47				compatible = "zephyr,power-state";
48				power-state-name = "suspend-to-idle";
49				substate-id = <2>;
50				min-residency-us = <100>;
51			};
52		};
53	};
54
55	sram0: memory@20000000 {
56		compatible = "mmio-sram";
57	};
58
59	clocks {
60		clk_hse: clk-hse {
61			#clock-cells = <0>;
62			compatible = "st,stm32-hse-clock";
63			status = "disabled";
64		};
65
66		clk_hsi: clk-hsi {
67			#clock-cells = <0>;
68			compatible = "st,stm32g0-hsi-clock";
69			hsi-div = <1>;
70			clock-frequency = <DT_FREQ_M(16)>;
71			status = "disabled";
72		};
73
74		clk_lse: clk-lse {
75			#clock-cells = <0>;
76			compatible = "st,stm32-lse-clock";
77			clock-frequency = <32768>;
78			driving-capability = <0>;
79			status = "disabled";
80		};
81
82		clk_lsi: clk-lsi {
83			#clock-cells = <0>;
84			compatible = "fixed-clock";
85			clock-frequency = <DT_FREQ_K(32)>;
86			status = "disabled";
87		};
88
89		pll: pll {
90			#clock-cells = <0>;
91			compatible = "st,stm32g0-pll-clock";
92			status = "disabled";
93		};
94	};
95
96	soc {
97		flash: flash-controller@40022000 {
98			compatible = "st,stm32-flash-controller", "st,stm32g0-flash-controller";
99			reg = <0x40022000 0x400>;
100			interrupts = <3 0>;
101			clocks = <&rcc STM32_CLOCK(AHB1, 8U)>;
102
103			#address-cells = <1>;
104			#size-cells = <1>;
105
106			flash0: flash@8000000 {
107				compatible = "st,stm32-nv-flash", "soc-nv-flash";
108
109				write-block-size = <8>;
110				erase-block-size = <2048>;
111				/* maximum erase time(ms) for a 2K sector */
112				max-erase-time = <40>;
113			};
114		};
115
116		rcc: rcc@40021000 {
117			compatible = "st,stm32f0-rcc";
118			#clock-cells = <2>;
119			reg = <0x40021000 0x400>;
120
121			rctl: reset-controller {
122				compatible = "st,stm32-rcc-rctl";
123				#reset-cells = <1>;
124			};
125		};
126
127		exti: interrupt-controller@40021800 {
128			compatible = "st,stm32g0-exti", "st,stm32-exti";
129			interrupt-controller;
130			#interrupt-cells = <1>;
131			#address-cells = <1>;
132			reg = <0x40021800 0x400>;
133			num-lines = <16>;
134			interrupts = <5 0>, <6 0>, <7 0>;
135			interrupt-names = "line0-1", "line2-3", "line4-15";
136			line-ranges = <0 2>, <2 2>, <4 12>;
137		};
138
139		pinctrl: pin-controller@50000000 {
140			compatible = "st,stm32-pinctrl";
141			#address-cells = <1>;
142			#size-cells = <1>;
143			reg = <0x50000000 0x2000>;
144
145			gpioa: gpio@50000000 {
146				compatible = "st,stm32-gpio";
147				gpio-controller;
148				#gpio-cells = <2>;
149				reg = <0x50000000 0x400>;
150				clocks = <&rcc STM32_CLOCK(IOP, 0U)>;
151			};
152
153			gpiob: gpio@50000400 {
154				compatible = "st,stm32-gpio";
155				gpio-controller;
156				#gpio-cells = <2>;
157				reg = <0x50000400 0x400>;
158				clocks = <&rcc STM32_CLOCK(IOP, 1U)>;
159			};
160
161			gpioc: gpio@50000800 {
162				compatible = "st,stm32-gpio";
163				gpio-controller;
164				#gpio-cells = <2>;
165				reg = <0x50000800 0x400>;
166				clocks = <&rcc STM32_CLOCK(IOP, 2U)>;
167			};
168
169			gpiod: gpio@50000c00 {
170				compatible = "st,stm32-gpio";
171				gpio-controller;
172				#gpio-cells = <2>;
173				reg = <0x50000c00 0x400>;
174				clocks = <&rcc STM32_CLOCK(IOP, 3U)>;
175			};
176
177			gpiof: gpio@50001400 {
178				compatible = "st,stm32-gpio";
179				gpio-controller;
180				#gpio-cells = <2>;
181				reg = <0x50001400 0x400>;
182				clocks = <&rcc STM32_CLOCK(IOP, 5U)>;
183			};
184		};
185
186		rtc: rtc@40002800 {
187			compatible = "st,stm32-rtc";
188			reg = <0x40002800 0x400>;
189			interrupts = <2 0>;
190			clocks = <&rcc STM32_CLOCK(APB1, 10U)>;
191			prescaler = <32768>;
192			alarms-count = <2>;
193			alrm-exti-line = <19>;
194			status = "disabled";
195
196			/* In STM32G0, the backup registers are defined as part of the TAMP
197			 * peripheral. This peripheral is not implemented in Zephyr yet, however,
198			 * the reference manual states that tamp_pclk is connected to rtc_pclk.
199			 * It makes sense to have BBRAM instantiated as a child of RTC, so that
200			 * the driver can verify that its parent device (RTC) is ready.
201			 */
202			bbram: backup_regs {
203				compatible = "st,stm32-bbram";
204				st,backup-regs = <5>;
205				status = "disabled";
206			};
207		};
208
209		iwdg: watchdog@40003000 {
210			compatible = "st,stm32-watchdog";
211			reg = <0x40003000 0x400>;
212			status = "disabled";
213		};
214
215		wwdg: watchdog@40002c00 {
216			compatible = "st,stm32-window-watchdog";
217			reg = <0x40002C00 0x400>;
218			clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
219			interrupts = <0 2>;
220			status = "disabled";
221		};
222
223		usart1: serial@40013800 {
224			compatible = "st,stm32-usart", "st,stm32-uart";
225			reg = <0x40013800 0x400>;
226			clocks = <&rcc STM32_CLOCK(APB1_2, 14U)>;
227			resets = <&rctl STM32_RESET(APB1H, 14U)>;
228			interrupts = <27 0>;
229			status = "disabled";
230		};
231
232		usart2: serial@40004400 {
233			compatible = "st,stm32-usart", "st,stm32-uart";
234			reg = <0x40004400 0x400>;
235			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
236			resets = <&rctl STM32_RESET(APB1L, 17U)>;
237			interrupts = <28 0>;
238			status = "disabled";
239		};
240
241		lptim1: timers@40007c00 {
242			compatible = "st,stm32-lptim";
243			clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
244			#address-cells = <1>;
245			#size-cells = <0>;
246			reg = <0x40007c00 0x400>;
247			interrupts = <17 1>;
248			interrupt-names = "wakeup";
249			status = "disabled";
250		};
251
252		timers1: timers@40012c00 {
253			compatible = "st,stm32-timers";
254			reg = <0x40012C00 0x400>;
255			clocks = <&rcc STM32_CLOCK(APB1_2, 11U)>;
256			resets = <&rctl STM32_RESET(APB1H, 11U)>;
257			interrupts = <13 0>, <14 0>;
258			interrupt-names = "brk_up_trg_com", "cc";
259			st,prescaler = <0>;
260			status = "disabled";
261
262			pwm {
263				compatible = "st,stm32-pwm";
264				status = "disabled";
265				#pwm-cells = <3>;
266			};
267
268			counter {
269				compatible = "st,stm32-counter";
270				status = "disabled";
271			};
272		};
273
274		timers3: timers@40000400 {
275			compatible = "st,stm32-timers";
276			reg = <0x40000400 0x400>;
277			clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
278			resets = <&rctl STM32_RESET(APB1L, 1U)>;
279			interrupts = <16 0>;
280			interrupt-names = "global";
281			st,prescaler = <0>;
282			status = "disabled";
283
284			pwm {
285				compatible = "st,stm32-pwm";
286				status = "disabled";
287				#pwm-cells = <3>;
288			};
289
290			counter {
291				compatible = "st,stm32-counter";
292				status = "disabled";
293			};
294		};
295
296		timers14: timers@40002000 {
297			compatible = "st,stm32-timers";
298			reg = <0x40002000 0x400>;
299			clocks = <&rcc STM32_CLOCK(APB1_2, 15U)>;
300			resets = <&rctl STM32_RESET(APB1H, 15U)>;
301			interrupts = <19 0>;
302			interrupt-names = "global";
303			st,prescaler = <0>;
304			status = "disabled";
305
306			pwm {
307				compatible = "st,stm32-pwm";
308				status = "disabled";
309				#pwm-cells = <3>;
310			};
311
312			counter {
313				compatible = "st,stm32-counter";
314				status = "disabled";
315			};
316		};
317
318		timers16: timers@40014400 {
319			compatible = "st,stm32-timers";
320			reg = <0x40014400 0x400>;
321			clocks = <&rcc STM32_CLOCK(APB1_2, 17U)>;
322			resets = <&rctl STM32_RESET(APB1H, 17U)>;
323			interrupts = <21 0>;
324			interrupt-names = "global";
325			st,prescaler = <0>;
326			status = "disabled";
327
328			pwm {
329				compatible = "st,stm32-pwm";
330				status = "disabled";
331				#pwm-cells = <3>;
332			};
333
334			counter {
335				compatible = "st,stm32-counter";
336				status = "disabled";
337			};
338		};
339
340		timers17: timers@40014800 {
341			compatible = "st,stm32-timers";
342			reg = <0x40014800 0x400>;
343			clocks = <&rcc STM32_CLOCK(APB1_2, 18U)>;
344			resets = <&rctl STM32_RESET(APB1H, 18U)>;
345			interrupts = <22 0>;
346			interrupt-names = "global";
347			st,prescaler = <0>;
348			status = "disabled";
349
350			pwm {
351				compatible = "st,stm32-pwm";
352				status = "disabled";
353				#pwm-cells = <3>;
354			};
355
356			counter {
357				compatible = "st,stm32-counter";
358				status = "disabled";
359			};
360		};
361
362		i2c1: i2c@40005400 {
363			compatible = "st,stm32-i2c-v2";
364			clock-frequency = <I2C_BITRATE_STANDARD>;
365			#address-cells = <1>;
366			#size-cells = <0>;
367			reg = <0x40005400 0x400>;
368			clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
369			interrupts = <23 0>;
370			interrupt-names = "combined";
371			status = "disabled";
372		};
373
374		i2c2: i2c@40005800 {
375			compatible = "st,stm32-i2c-v2";
376			clock-frequency = <I2C_BITRATE_STANDARD>;
377			#address-cells = <1>;
378			#size-cells = <0>;
379			reg = <0x40005800 0x400>;
380			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
381			interrupts = <24 0>;
382			interrupt-names = "combined";
383			status = "disabled";
384		};
385
386		spi1: spi@40013000 {
387			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
388			#address-cells = <1>;
389			#size-cells = <0>;
390			reg = <0x40013000 0x400>;
391			clocks = <&rcc STM32_CLOCK(APB1_2, 12U)>;
392			interrupts = <25 0>;
393			status = "disabled";
394		};
395
396		spi2: spi@40003800 {
397			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
398			#address-cells = <1>;
399			#size-cells = <0>;
400			reg = <0x40003800 0x400>;
401			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
402			interrupts = <26 0>;
403			status = "disabled";
404		};
405
406		adc1: adc@40012400 {
407			compatible = "st,stm32-adc";
408			reg = <0x40012400 0x400>;
409			clocks = <&rcc STM32_CLOCK(APB1_2, 20U)>;
410			interrupts = <12 0>;
411			status = "disabled";
412			#io-channel-cells = <1>;
413			resolutions = <STM32_ADC_RES(12, 0x00)
414				       STM32_ADC_RES(10, 0x01)
415				       STM32_ADC_RES(8, 0x02)
416				       STM32_ADC_RES(6, 0x03)>;
417			/* Errata ES0418: For sampling time set to 1.5 or 3.5
418			 * cycles, the sampling in a single ADC conversion or in
419			 * the first conversion of a sequence takes one extra
420			 * cycle.
421			 * So instead of 2 4, we set 3 5.
422			 */
423			sampling-times = <3 5 8 13 20 40 80 161>;
424			num-sampling-time-common-channels = <2>;
425			st,adc-sequencer = "NOT_FULLY_CONFIGURABLE";
426			st,adc-oversampler = "OVERSAMPLER_MINIMAL";
427		};
428
429		dma1: dma@40020000 {
430			compatible = "st,stm32-dma-v2";
431			#dma-cells = <3>;
432			reg = <0x40020000 0x400>;
433			interrupts = <9 0 10 0 10 0 11 0 11 0>;
434			clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
435			dma-requests = <5>;
436			dma-offset = <0>;
437			status = "disabled";
438		};
439
440		/* DMAMUX clock is enabled as long as DMA1 or DMA2 is enabled */
441		dmamux1: dmamux@40020800 {
442			compatible = "st,stm32-dmamux";
443			#dma-cells = <3>;
444			reg = <0x40020800 0x800>;
445			interrupts = <11 0>;
446			dma-channels = <5>;
447			dma-generators = <4>;
448			dma-requests= <49>;
449			status = "disabled";
450		};
451	};
452
453	die_temp: dietemp {
454		compatible = "st,stm32-temp-cal";
455		ts-cal1-addr = <0x1FFF75A8>;
456		ts-cal2-addr = <0x1FFF75CA>;
457		ts-cal1-temp = <30>;
458		ts-cal2-temp = <130>;
459		ts-cal-vrefanalog = <3000>;
460		io-channels = <&adc1 12>;
461		status = "disabled";
462	};
463
464	vref: vref {
465		compatible = "st,stm32-vref";
466		vrefint-cal-addr = <0x1FFF75AA>;
467		vrefint-cal-mv = <3000>;
468		io-channels = <&adc1 13>;
469		status = "disabled";
470	};
471
472	vbat: vbat {
473		compatible = "st,stm32-vbat";
474		ratio = <3>;
475		io-channels = <&adc1 14>;
476		status = "disabled";
477	};
478
479	smbus1: smbus1 {
480		compatible = "st,stm32-smbus";
481		#address-cells = <1>;
482		#size-cells = <0>;
483		i2c = <&i2c1>;
484		status = "disabled";
485	};
486
487	smbus2: smbus2 {
488		compatible = "st,stm32-smbus";
489		#address-cells = <1>;
490		#size-cells = <0>;
491		i2c = <&i2c2>;
492		status = "disabled";
493	};
494};
495
496&nvic {
497	arm,num-irq-priority-bits = <2>;
498};
499