1/*
2 * Copyright (c) 2023 Evan Perry Grove
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/f7/stm32f7.dtsi>
8
9/ {
10	/* 16KB ITCM @ 0x0, 64KB DTCM @ 0x20000000,
11	 * 176KB SRAM1 @ 0x20010000, 16KB SRAM2 @ 0x2003C00
12	 */
13
14	sram0: memory@20010000 {
15		compatible = "zephyr,memory-region", "mmio-sram";
16		reg = <0x20010000 DT_SIZE_K(192)>;
17		zephyr,memory-region = "SRAM0";
18	};
19
20	dtcm: memory@20000000 {
21		compatible = "zephyr,memory-region", "arm,dtcm";
22		reg = <0x20000000 DT_SIZE_K(64)>;
23		zephyr,memory-region = "DTCM";
24	};
25
26	itcm: memory@0 {
27		compatible = "zephyr,memory-region", "arm,itcm";
28		reg = <0x00000000 DT_SIZE_K(16)>;
29		zephyr,memory-region = "ITCM";
30	};
31
32	soc {
33		compatible = "st,stm32f722", "st,stm32f7", "simple-bus";
34
35		sdmmc2: sdmmc@40011c00 {
36			compatible = "st,stm32-sdmmc";
37			reg = <0x40011c00 0x400>;
38			clocks = <&rcc STM32_CLOCK(APB2, 7U)>,
39				<&rcc STM32_SRC_PLL_Q SDMMC2_SEL(0)>;
40			resets = <&rctl STM32_RESET(APB2, 7U)>;
41			interrupts = <103 0>;
42			status = "disabled";
43		};
44	};
45
46	die_temp: dietemp {
47		ts-cal1-addr = <0x1FF07A2C>;
48		ts-cal2-addr = <0x1FF07A2E>;
49	};
50
51	vref: vref {
52		vrefint-cal-addr = <0x1FF07A2A>;
53	};
54};
55