1/* 2 * Copyright (c) 2018 Yurii Hamann 3 * Copyright (c) 2019 Centaur Analytics, Inc 4 * Copyright (c) 2024 STMicroelectronics 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 9#include <arm/armv7-m.dtsi> 10#include <zephyr/dt-bindings/clock/stm32f7_clock.h> 11#include <zephyr/dt-bindings/i2c/i2c.h> 12#include <zephyr/dt-bindings/gpio/gpio.h> 13#include <zephyr/dt-bindings/pwm/pwm.h> 14#include <zephyr/dt-bindings/pwm/stm32_pwm.h> 15#include <zephyr/dt-bindings/dma/stm32_dma.h> 16#include <zephyr/dt-bindings/adc/stm32f4_adc.h> 17#include <zephyr/dt-bindings/reset/stm32f2_4_7_reset.h> 18#include <zephyr/dt-bindings/adc/adc.h> 19#include <zephyr/dt-bindings/memory-controller/stm32-fmc-sdram.h> 20#include <zephyr/dt-bindings/memory-attr/memory-attr.h> 21#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h> 22#include <freq.h> 23 24/ { 25 chosen { 26 zephyr,entropy = &rng; 27 zephyr,flash-controller = &flash; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 cpu0: cpu@0 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-m7"; 37 reg = <0>; 38 #address-cells = <1>; 39 #size-cells = <1>; 40 41 mpu: mpu@e000ed90 { 42 compatible = "arm,armv7m-mpu"; 43 reg = <0xe000ed90 0x40>; 44 }; 45 }; 46 }; 47 48 quadspi_memory: memory-placeholder@90000000 { 49 compatible = "zephyr,memory-region", "mmio-sram"; 50 reg = <0x90000000 DT_SIZE_M(256)>; 51 zephyr,memory-region = "QSPI_PLACEHOLDER"; 52 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_EXTMEM) )>; 53 }; 54 55 clocks { 56 clk_hse: clk-hse { 57 #clock-cells = <0>; 58 compatible = "st,stm32-hse-clock"; 59 status = "disabled"; 60 }; 61 62 clk_hsi: clk-hsi { 63 #clock-cells = <0>; 64 compatible = "fixed-clock"; 65 clock-frequency = <DT_FREQ_M(16)>; 66 status = "disabled"; 67 }; 68 69 clk_lse: clk-lse { 70 #clock-cells = <0>; 71 compatible = "st,stm32-lse-clock"; 72 clock-frequency = <32768>; 73 driving-capability = <0>; 74 status = "disabled"; 75 }; 76 77 clk_lsi: clk-lsi { 78 #clock-cells = <0>; 79 compatible = "fixed-clock"; 80 clock-frequency = <DT_FREQ_K(32)>; 81 status = "disabled"; 82 }; 83 84 pll: pll { 85 #clock-cells = <0>; 86 compatible = "st,stm32f7-pll-clock"; 87 status = "disabled"; 88 }; 89 }; 90 91 mcos { 92 mco1: mco1 { 93 compatible = "st,stm32-clock-mco"; 94 status = "disabled"; 95 }; 96 97 mco2: mco2 { 98 compatible = "st,stm32-clock-mco"; 99 status = "disabled"; 100 }; 101 }; 102 103 soc { 104 fmc: memory-controller@a0000000 { 105 compatible = "st,stm32-fmc"; 106 reg = <0xa0000000 0x400>; 107 clocks = <&rcc STM32_CLOCK(AHB3, 0U)>; 108 status = "disabled"; 109 110 sdram: sdram { 111 compatible = "st,stm32-fmc-sdram"; 112 #address-cells = <1>; 113 #size-cells = <0>; 114 status = "disabled"; 115 }; 116 }; 117 118 flash: flash-controller@40023c00 { 119 compatible = "st,stm32-flash-controller", "st,stm32f7-flash-controller"; 120 reg = <0x40023c00 0x400>; 121 interrupts = <4 0>; 122 123 #address-cells = <1>; 124 #size-cells = <1>; 125 126 flash0: flash@8000000 { 127 compatible = "st,stm32-nv-flash", "soc-nv-flash"; 128 129 write-block-size = <1>; 130 /* maximum erase time (ms) for a 256K sector */ 131 max-erase-time = <4000>; 132 }; 133 }; 134 135 rcc: rcc@40023800 { 136 compatible = "st,stm32-rcc"; 137 #clock-cells = <2>; 138 reg = <0x40023800 0x400>; 139 140 rctl: reset-controller { 141 compatible = "st,stm32-rcc-rctl"; 142 #reset-cells = <1>; 143 }; 144 }; 145 146 exti: interrupt-controller@40013c00 { 147 compatible = "st,stm32-exti"; 148 interrupt-controller; 149 #interrupt-cells = <1>; 150 #address-cells = <1>; 151 reg = <0x40013c00 0x400>; 152 num-lines = <16>; 153 interrupts = <6 0>, <7 0>, <8 0>, <9 0>, 154 <10 0>, <23 0>, <40 0>; 155 interrupt-names = "line0", "line1", "line2", "line3", 156 "line4", "line5-9", "line10-15"; 157 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, 158 <4 1>, <5 5>, <10 6>; 159 }; 160 161 pinctrl: pin-controller@40020000 { 162 compatible = "st,stm32-pinctrl"; 163 #address-cells = <1>; 164 #size-cells = <1>; 165 reg = <0x40020000 0x2400>; 166 167 gpioa: gpio@40020000 { 168 compatible = "st,stm32-gpio"; 169 gpio-controller; 170 #gpio-cells = <2>; 171 reg = <0x40020000 0x400>; 172 clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; 173 }; 174 175 gpiob: gpio@40020400 { 176 compatible = "st,stm32-gpio"; 177 gpio-controller; 178 #gpio-cells = <2>; 179 reg = <0x40020400 0x400>; 180 clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; 181 }; 182 183 gpioc: gpio@40020800 { 184 compatible = "st,stm32-gpio"; 185 gpio-controller; 186 #gpio-cells = <2>; 187 reg = <0x40020800 0x400>; 188 clocks = <&rcc STM32_CLOCK(AHB1, 2U)>; 189 }; 190 191 gpiod: gpio@40020C00 { 192 compatible = "st,stm32-gpio"; 193 gpio-controller; 194 #gpio-cells = <2>; 195 reg = <0x40020C00 0x400>; 196 clocks = <&rcc STM32_CLOCK(AHB1, 3U)>; 197 }; 198 199 gpioe: gpio@40021000 { 200 compatible = "st,stm32-gpio"; 201 gpio-controller; 202 #gpio-cells = <2>; 203 reg = <0x40021000 0x400>; 204 clocks = <&rcc STM32_CLOCK(AHB1, 4U)>; 205 }; 206 207 gpiof: gpio@40021400 { 208 compatible = "st,stm32-gpio"; 209 gpio-controller; 210 #gpio-cells = <2>; 211 reg = <0x40021400 0x400>; 212 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>; 213 }; 214 215 gpiog: gpio@40021800 { 216 compatible = "st,stm32-gpio"; 217 gpio-controller; 218 #gpio-cells = <2>; 219 reg = <0x40021800 0x400>; 220 clocks = <&rcc STM32_CLOCK(AHB1, 6U)>; 221 }; 222 223 gpioh: gpio@40021C00 { 224 compatible = "st,stm32-gpio"; 225 gpio-controller; 226 #gpio-cells = <2>; 227 reg = <0x40021C00 0x400>; 228 clocks = <&rcc STM32_CLOCK(AHB1, 7U)>; 229 }; 230 231 gpioi: gpio@40022000 { 232 compatible = "st,stm32-gpio"; 233 gpio-controller; 234 #gpio-cells = <2>; 235 reg = <0x40022000 0x400>; 236 clocks = <&rcc STM32_CLOCK(AHB1, 8U)>; 237 }; 238 }; 239 240 iwdg: watchdog@40003000 { 241 compatible = "st,stm32-watchdog"; 242 reg = <0x40003000 0x400>; 243 status = "disabled"; 244 }; 245 246 wwdg: watchdog@40002c00 { 247 compatible = "st,stm32-window-watchdog"; 248 reg = <0x40002C00 0x400>; 249 clocks = <&rcc STM32_CLOCK(APB1, 11U)>; 250 interrupts = <0 7>; 251 status = "disabled"; 252 }; 253 254 usart1: serial@40011000 { 255 compatible = "st,stm32-usart", "st,stm32-uart"; 256 reg = <0x40011000 0x400>; 257 clocks = <&rcc STM32_CLOCK(APB2, 4U)>; 258 resets = <&rctl STM32_RESET(APB2, 4U)>; 259 interrupts = <37 0>; 260 status = "disabled"; 261 }; 262 263 usart2: serial@40004400 { 264 compatible = "st,stm32-usart", "st,stm32-uart"; 265 reg = <0x40004400 0x400>; 266 clocks = <&rcc STM32_CLOCK(APB1, 17U)>; 267 resets = <&rctl STM32_RESET(APB1, 17U)>; 268 interrupts = <38 0>; 269 status = "disabled"; 270 }; 271 272 usart3: serial@40004800 { 273 compatible = "st,stm32-usart", "st,stm32-uart"; 274 reg = <0x40004800 0x400>; 275 clocks = <&rcc STM32_CLOCK(APB1, 18U)>; 276 resets = <&rctl STM32_RESET(APB1, 18U)>; 277 interrupts = <39 0>; 278 status = "disabled"; 279 }; 280 281 uart4: serial@40004c00 { 282 compatible ="st,stm32-uart"; 283 reg = <0x40004c00 0x400>; 284 clocks = <&rcc STM32_CLOCK(APB1, 19U)>; 285 resets = <&rctl STM32_RESET(APB1, 19U)>; 286 interrupts = <52 0>; 287 status = "disabled"; 288 }; 289 290 uart5: serial@40005000 { 291 compatible = "st,stm32-uart"; 292 reg = <0x40005000 0x400>; 293 clocks = <&rcc STM32_CLOCK(APB1, 20U)>; 294 resets = <&rctl STM32_RESET(APB1, 20U)>; 295 interrupts = <53 0>; 296 status = "disabled"; 297 }; 298 299 usart6: serial@40011400 { 300 compatible = "st,stm32-usart", "st,stm32-uart"; 301 reg = <0x40011400 0x400>; 302 clocks = <&rcc STM32_CLOCK(APB2, 5U)>; 303 resets = <&rctl STM32_RESET(APB2, 5U)>; 304 interrupts = <71 0>; 305 status = "disabled"; 306 }; 307 308 uart7: serial@40007800 { 309 compatible = "st,stm32-uart"; 310 reg = <0x40007800 0x400>; 311 clocks = <&rcc STM32_CLOCK(APB1, 30U)>; 312 resets = <&rctl STM32_RESET(APB1, 30U)>; 313 interrupts = <82 0>; 314 status = "disabled"; 315 }; 316 317 uart8: serial@40007c00 { 318 compatible = "st,stm32-uart"; 319 reg = <0x40007c00 0x400>; 320 clocks = <&rcc STM32_CLOCK(APB1, 31U)>; 321 resets = <&rctl STM32_RESET(APB1, 31U)>; 322 interrupts = <83 0>; 323 status = "disabled"; 324 }; 325 326 i2c1: i2c@40005400 { 327 compatible = "st,stm32-i2c-v2"; 328 clock-frequency = <I2C_BITRATE_STANDARD>; 329 #address-cells = <1>; 330 #size-cells = <0>; 331 reg = <0x40005400 0x400>; 332 clocks = <&rcc STM32_CLOCK(APB1, 21U)>; 333 interrupts = <31 0>, <32 0>; 334 interrupt-names = "event", "error"; 335 status = "disabled"; 336 }; 337 338 i2c2: i2c@40005800 { 339 compatible = "st,stm32-i2c-v2"; 340 clock-frequency = <I2C_BITRATE_STANDARD>; 341 #address-cells = <1>; 342 #size-cells = <0>; 343 reg = <0x40005800 0x400>; 344 clocks = <&rcc STM32_CLOCK(APB1, 22U)>; 345 interrupts = <33 0>, <34 0>; 346 interrupt-names = "event", "error"; 347 status = "disabled"; 348 }; 349 350 i2c3: i2c@40005c00 { 351 compatible = "st,stm32-i2c-v2"; 352 clock-frequency = <I2C_BITRATE_STANDARD>; 353 #address-cells = <1>; 354 #size-cells = <0>; 355 reg = <0x40005c00 0x400>; 356 clocks = <&rcc STM32_CLOCK(APB1, 23U)>; 357 interrupts = <72 0>, <73 0>; 358 interrupt-names = "event", "error"; 359 status = "disabled"; 360 }; 361 362 spi1: spi@40013000 { 363 compatible = "st,stm32-spi-fifo", "st,stm32-spi"; 364 #address-cells = <1>; 365 #size-cells = <0>; 366 reg = <0x40013000 0x400>; 367 clocks = <&rcc STM32_CLOCK(APB2, 12U)>; 368 interrupts = <35 5>; 369 status = "disabled"; 370 }; 371 372 spi2: spi@40003800 { 373 compatible = "st,stm32-spi-fifo", "st,stm32-spi"; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 reg = <0x40003800 0x400>; 377 clocks = <&rcc STM32_CLOCK(APB1, 14U)>; 378 interrupts = <36 5>; 379 status = "disabled"; 380 }; 381 382 spi3: spi@40003c00 { 383 compatible = "st,stm32-spi-fifo", "st,stm32-spi"; 384 #address-cells = <1>; 385 #size-cells = <0>; 386 reg = <0x40003c00 0x400>; 387 clocks = <&rcc STM32_CLOCK(APB1, 15U)>; 388 interrupts = <51 5>; 389 status = "disabled"; 390 }; 391 392 spi4: spi@40013400 { 393 compatible = "st,stm32-spi-fifo", "st,stm32-spi"; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 reg = <0x40013400 0x400>; 397 clocks = <&rcc STM32_CLOCK(APB2, 13U)>; 398 interrupts = <84 5>; 399 status = "disabled"; 400 }; 401 402 spi5: spi@40015000 { 403 compatible = "st,stm32-spi-fifo", "st,stm32-spi"; 404 #address-cells = <1>; 405 #size-cells = <0>; 406 reg = <0x40015000 0x400>; 407 clocks = <&rcc STM32_CLOCK(APB2, 20U)>; 408 interrupts = <85 5>; 409 status = "disabled"; 410 }; 411 412 can1: can@40006400 { 413 compatible = "st,stm32-bxcan"; 414 reg = <0x40006400 0x400>; 415 interrupts = <19 0>, <20 0>, <21 0>, <22 0>; 416 interrupt-names = "TX", "RX0", "RX1", "SCE"; 417 clocks = <&rcc STM32_CLOCK(APB1, 25U)>; 418 status = "disabled"; 419 }; 420 421 timers1: timers@40010000 { 422 compatible = "st,stm32-timers"; 423 reg = <0x40010000 0x400>; 424 clocks = <&rcc STM32_CLOCK(APB2, 0U)>; 425 resets = <&rctl STM32_RESET(APB2, 0U)>; 426 interrupts = <24 0>, <25 0>, <26 0>, <27 0>; 427 interrupt-names = "brk", "up", "trgcom", "cc"; 428 st,prescaler = <0>; 429 status = "disabled"; 430 431 pwm { 432 compatible = "st,stm32-pwm"; 433 status = "disabled"; 434 #pwm-cells = <3>; 435 }; 436 }; 437 438 timers2: timers@40000000 { 439 compatible = "st,stm32-timers"; 440 reg = <0x40000000 0x400>; 441 clocks = <&rcc STM32_CLOCK(APB1, 0U)>; 442 resets = <&rctl STM32_RESET(APB1, 0U)>; 443 interrupts = <28 0>; 444 interrupt-names = "global"; 445 st,prescaler = <0>; 446 status = "disabled"; 447 448 pwm { 449 compatible = "st,stm32-pwm"; 450 status = "disabled"; 451 #pwm-cells = <3>; 452 }; 453 454 counter { 455 compatible = "st,stm32-counter"; 456 status = "disabled"; 457 }; 458 }; 459 460 timers3: timers@40000400 { 461 compatible = "st,stm32-timers"; 462 reg = <0x40000400 0x400>; 463 clocks = <&rcc STM32_CLOCK(APB1, 1U)>; 464 resets = <&rctl STM32_RESET(APB1, 1U)>; 465 interrupts = <29 0>; 466 interrupt-names = "global"; 467 st,prescaler = <0>; 468 status = "disabled"; 469 470 pwm { 471 compatible = "st,stm32-pwm"; 472 status = "disabled"; 473 #pwm-cells = <3>; 474 }; 475 476 counter { 477 compatible = "st,stm32-counter"; 478 status = "disabled"; 479 }; 480 }; 481 482 timers4: timers@40000800 { 483 compatible = "st,stm32-timers"; 484 reg = <0x40000800 0x400>; 485 clocks = <&rcc STM32_CLOCK(APB1, 2U)>; 486 resets = <&rctl STM32_RESET(APB1, 2U)>; 487 interrupts = <30 0>; 488 interrupt-names = "global"; 489 st,prescaler = <0>; 490 status = "disabled"; 491 492 pwm { 493 compatible = "st,stm32-pwm"; 494 status = "disabled"; 495 #pwm-cells = <3>; 496 }; 497 498 counter { 499 compatible = "st,stm32-counter"; 500 status = "disabled"; 501 }; 502 }; 503 504 timers5: timers@40000c00 { 505 compatible = "st,stm32-timers"; 506 reg = <0x40000c00 0x400>; 507 clocks = <&rcc STM32_CLOCK(APB1, 3U)>; 508 resets = <&rctl STM32_RESET(APB1, 3U)>; 509 interrupts = <50 0>; 510 interrupt-names = "global"; 511 st,prescaler = <0>; 512 status = "disabled"; 513 514 pwm { 515 compatible = "st,stm32-pwm"; 516 status = "disabled"; 517 #pwm-cells = <3>; 518 }; 519 520 counter { 521 compatible = "st,stm32-counter"; 522 status = "disabled"; 523 }; 524 }; 525 526 timers6: timers@40001000 { 527 compatible = "st,stm32-timers"; 528 reg = <0x40001000 0x400>; 529 clocks = <&rcc STM32_CLOCK(APB1, 4U)>; 530 resets = <&rctl STM32_RESET(APB1, 4U)>; 531 interrupts = <54 0>; 532 interrupt-names = "global"; 533 st,prescaler = <0>; 534 status = "disabled"; 535 536 counter { 537 compatible = "st,stm32-counter"; 538 status = "disabled"; 539 }; 540 }; 541 542 timers7: timers@40001400 { 543 compatible = "st,stm32-timers"; 544 reg = <0x40001400 0x400>; 545 clocks = <&rcc STM32_CLOCK(APB1, 5U)>; 546 resets = <&rctl STM32_RESET(APB1, 5U)>; 547 interrupts = <55 0>; 548 interrupt-names = "global"; 549 st,prescaler = <0>; 550 status = "disabled"; 551 552 counter { 553 compatible = "st,stm32-counter"; 554 status = "disabled"; 555 }; 556 }; 557 558 timers8: timers@40010400 { 559 compatible = "st,stm32-timers"; 560 reg = <0x40010400 0x400>; 561 clocks = <&rcc STM32_CLOCK(APB2, 1U)>; 562 resets = <&rctl STM32_RESET(APB2, 1U)>; 563 interrupts = <43 0>, <44 0>, <45 0>, <46 0>; 564 interrupt-names = "brk", "up", "trgcom", "cc"; 565 st,prescaler = <0>; 566 status = "disabled"; 567 568 pwm { 569 compatible = "st,stm32-pwm"; 570 status = "disabled"; 571 #pwm-cells = <3>; 572 }; 573 }; 574 575 timers9: timers@40014000 { 576 compatible = "st,stm32-timers"; 577 reg = <0x40014000 0x400>; 578 clocks = <&rcc STM32_CLOCK(APB2, 16U)>; 579 resets = <&rctl STM32_RESET(APB2, 16U)>; 580 interrupts = <24 0>; 581 interrupt-names = "global"; 582 st,prescaler = <0>; 583 status = "disabled"; 584 585 pwm { 586 compatible = "st,stm32-pwm"; 587 status = "disabled"; 588 #pwm-cells = <3>; 589 }; 590 591 counter { 592 compatible = "st,stm32-counter"; 593 status = "disabled"; 594 }; 595 }; 596 597 timers10: timers@40014400 { 598 compatible = "st,stm32-timers"; 599 reg = <0x40014400 0x400>; 600 clocks = <&rcc STM32_CLOCK(APB2, 17U)>; 601 resets = <&rctl STM32_RESET(APB2, 17U)>; 602 interrupts = <25 0>; 603 interrupt-names = "global"; 604 st,prescaler = <0>; 605 status = "disabled"; 606 607 pwm { 608 compatible = "st,stm32-pwm"; 609 status = "disabled"; 610 #pwm-cells = <3>; 611 }; 612 613 counter { 614 compatible = "st,stm32-counter"; 615 status = "disabled"; 616 }; 617 }; 618 619 timers11: timers@40014800 { 620 compatible = "st,stm32-timers"; 621 reg = <0x40014800 0x400>; 622 clocks = <&rcc STM32_CLOCK(APB2, 18U)>; 623 resets = <&rctl STM32_RESET(APB2, 18U)>; 624 interrupts = <26 0>; 625 interrupt-names = "global"; 626 st,prescaler = <0>; 627 status = "disabled"; 628 629 pwm { 630 compatible = "st,stm32-pwm"; 631 status = "disabled"; 632 #pwm-cells = <3>; 633 }; 634 635 counter { 636 compatible = "st,stm32-counter"; 637 status = "disabled"; 638 }; 639 }; 640 641 timers12: timers@40001800 { 642 compatible = "st,stm32-timers"; 643 reg = <0x40001800 0x400>; 644 clocks = <&rcc STM32_CLOCK(APB1, 6U)>; 645 resets = <&rctl STM32_RESET(APB1, 6U)>; 646 interrupts = <43 0>; 647 interrupt-names = "global"; 648 st,prescaler = <0>; 649 status = "disabled"; 650 651 pwm { 652 compatible = "st,stm32-pwm"; 653 status = "disabled"; 654 #pwm-cells = <3>; 655 }; 656 657 counter { 658 compatible = "st,stm32-counter"; 659 status = "disabled"; 660 }; 661 }; 662 663 timers13: timers@40001c00 { 664 compatible = "st,stm32-timers"; 665 reg = <0x40001c00 0x400>; 666 clocks = <&rcc STM32_CLOCK(APB1, 7U)>; 667 resets = <&rctl STM32_RESET(APB1, 7U)>; 668 interrupts = <44 0>; 669 interrupt-names = "global"; 670 st,prescaler = <0>; 671 status = "disabled"; 672 673 pwm { 674 compatible = "st,stm32-pwm"; 675 status = "disabled"; 676 #pwm-cells = <3>; 677 }; 678 679 counter { 680 compatible = "st,stm32-counter"; 681 status = "disabled"; 682 }; 683 }; 684 685 timers14: timers@40002000 { 686 compatible = "st,stm32-timers"; 687 reg = <0x40002000 0x400>; 688 clocks = <&rcc STM32_CLOCK(APB1, 8U)>; 689 resets = <&rctl STM32_RESET(APB1, 8U)>; 690 interrupts = <45 0>; 691 interrupt-names = "global"; 692 st,prescaler = <0>; 693 status = "disabled"; 694 695 pwm { 696 compatible = "st,stm32-pwm"; 697 status = "disabled"; 698 #pwm-cells = <3>; 699 }; 700 701 counter { 702 compatible = "st,stm32-counter"; 703 status = "disabled"; 704 }; 705 }; 706 707 usbotg_fs: usb@50000000 { 708 compatible = "st,stm32-otgfs"; 709 reg = <0x50000000 0x40000>; 710 interrupts = <67 0>; 711 interrupt-names = "otgfs"; 712 num-bidir-endpoints = <6>; 713 ram-size = <1280>; 714 maximum-speed = "full-speed"; 715 phys = <&otgfs_phy>; 716 clocks = <&rcc STM32_CLOCK(AHB2, 7U)>, 717 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>; 718 status = "disabled"; 719 }; 720 721 usbotg_hs: usb@40040000 { 722 compatible = "st,stm32-otghs"; 723 reg = <0x40040000 0x40000>; 724 interrupts = <77 0>, <74 0>, <75 0>; 725 interrupt-names = "otghs", "ep1_out", "ep1_in"; 726 num-bidir-endpoints = <9>; 727 ram-size = <4096>; 728 maximum-speed = "full-speed"; 729 clocks = <&rcc STM32_CLOCK(AHB1, 29U)>, 730 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>; 731 phys = <&otghs_fs_phy>; 732 status = "disabled"; 733 }; 734 735 rtc: rtc@40002800 { 736 compatible = "st,stm32-rtc"; 737 reg = <0x40002800 0x300>; 738 interrupts = <41 0>; 739 clocks = <&rcc STM32_CLOCK(APB1, 28U)>; 740 prescaler = <32768>; 741 alarms-count = <2>; 742 alrm-exti-line = <17>; 743 status = "disabled"; 744 745 bbram: backup_regs { 746 compatible = "st,stm32-bbram"; 747 st,backup-regs = <32>; 748 status = "disabled"; 749 }; 750 }; 751 752 adc1: adc@40012000 { 753 compatible = "st,stm32f4-adc", "st,stm32-adc"; 754 reg = <0x40012000 0x50>; 755 clocks = <&rcc STM32_CLOCK(APB2, 8U)>; 756 interrupts = <18 0>; 757 status = "disabled"; 758 #io-channel-cells = <1>; 759 resolutions = <STM32_ADC_RES(12, 0x00) 760 STM32_ADC_RES(10, 0x01) 761 STM32_ADC_RES(8, 0x02) 762 STM32_ADC_RES(6, 0x03)>; 763 sampling-times = <3 15 28 56 84 112 144 480>; 764 st,adc-clock-source = "SYNC"; 765 st,adc-sequencer = "FULLY_CONFIGURABLE"; 766 st,adc-oversampler = "OVERSAMPLER_NONE"; 767 }; 768 769 adc2: adc@40012100 { 770 compatible = "st,stm32f4-adc", "st,stm32-adc"; 771 reg = <0x40012100 0x50>; 772 clocks = <&rcc STM32_CLOCK(APB2, 9U)>; 773 interrupts = <18 0>; 774 status = "disabled"; 775 #io-channel-cells = <1>; 776 resolutions = <STM32_ADC_RES(12, 0x00) 777 STM32_ADC_RES(10, 0x01) 778 STM32_ADC_RES(8, 0x02) 779 STM32_ADC_RES(6, 0x03)>; 780 sampling-times = <3 15 28 56 84 112 144 480>; 781 st,adc-clock-source = "SYNC"; 782 st,adc-sequencer = "FULLY_CONFIGURABLE"; 783 st,adc-oversampler = "OVERSAMPLER_NONE"; 784 }; 785 786 adc3: adc@40012200 { 787 compatible = "st,stm32f4-adc", "st,stm32-adc"; 788 reg = <0x40012200 0x50>; 789 clocks = <&rcc STM32_CLOCK(APB2, 10U)>; 790 interrupts = <18 0>; 791 status = "disabled"; 792 #io-channel-cells = <1>; 793 resolutions = <STM32_ADC_RES(12, 0x00) 794 STM32_ADC_RES(10, 0x01) 795 STM32_ADC_RES(8, 0x02) 796 STM32_ADC_RES(6, 0x03)>; 797 sampling-times = <3 15 28 56 84 112 144 480>; 798 st,adc-clock-source = "SYNC"; 799 st,adc-sequencer = "FULLY_CONFIGURABLE"; 800 st,adc-oversampler = "OVERSAMPLER_NONE"; 801 }; 802 803 dac1: dac@40007400 { 804 compatible = "st,stm32-dac"; 805 reg = <0x40007400 0x400>; 806 clocks = <&rcc STM32_CLOCK(APB1, 29U)>; 807 status = "disabled"; 808 #io-channel-cells = <1>; 809 }; 810 811 dma1: dma@40026000 { 812 compatible = "st,stm32-dma-v1"; 813 #dma-cells = <4>; 814 reg = <0x40026000 0x400>; 815 interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>; 816 clocks = <&rcc STM32_CLOCK(AHB1, 21U)>; 817 status = "disabled"; 818 }; 819 820 dma2: dma@40026400 { 821 compatible = "st,stm32-dma-v1"; 822 #dma-cells = <4>; 823 reg = <0x40026400 0x400>; 824 interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>; 825 clocks = <&rcc STM32_CLOCK(AHB1, 22U)>; 826 st,mem2mem; 827 status = "disabled"; 828 }; 829 830 rng: rng@50060800 { 831 compatible = "st,stm32-rng"; 832 reg = <0x50060800 0x400>; 833 interrupts = <80 0>; 834 clocks = <&rcc STM32_CLOCK(AHB2, 6U)>, 835 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>; 836 status = "disabled"; 837 }; 838 839 sdmmc1: sdmmc@40012c00 { 840 compatible = "st,stm32-sdmmc"; 841 reg = <0x40012c00 0x400>; 842 clocks = <&rcc STM32_CLOCK(APB2, 11U)>, 843 <&rcc STM32_SRC_PLL_Q SDMMC1_SEL(0)>; 844 resets = <&rctl STM32_RESET(APB2, 11U)>; 845 interrupts = <49 0>; 846 status = "disabled"; 847 }; 848 849 backup_sram: memory@40024000 { 850 compatible = "zephyr,memory-region", "st,stm32-backup-sram"; 851 reg = <0x40024000 DT_SIZE_K(4)>; 852 clocks = <&rcc STM32_CLOCK(AHB1, 18U)>; 853 zephyr,memory-region = "BACKUP_SRAM"; 854 status = "disabled"; 855 }; 856 857 quadspi: quadspi@a0001000 { 858 compatible = "st,stm32-qspi"; 859 #address-cells = <0x1>; 860 #size-cells = <0x0>; 861 reg = <0xa0001000 0x34>; 862 interrupts = <92 0>; 863 clocks = <&rcc STM32_CLOCK(AHB3, 1U)>; 864 status = "disabled"; 865 }; 866 }; 867 868 die_temp: dietemp { 869 compatible = "st,stm32-temp-cal"; 870 ts-cal1-addr = <0x1FF0F44C>; 871 ts-cal2-addr = <0x1FF0F44E>; 872 ts-cal1-temp = <30>; 873 ts-cal2-temp = <110>; 874 ts-cal-vrefanalog = <3300>; 875 io-channels = <&adc1 18>; 876 status = "disabled"; 877 }; 878 879 vref: vref { 880 compatible = "st,stm32-vref"; 881 vrefint-cal-addr = <0x1FF0F44A>; 882 vrefint-cal-mv = <3300>; 883 io-channels = <&adc1 17>; 884 status = "disabled"; 885 }; 886 887 vbat: vbat { 888 compatible = "st,stm32-vbat"; 889 ratio = <4>; 890 io-channels = <&adc1 18>; 891 status = "disabled"; 892 }; 893 894 otghs_fs_phy: otghs_fs_phy { 895 compatible = "usb-nop-xceiv"; 896 #phy-cells = <0>; 897 }; 898 899 otgfs_phy: otgfs_phy { 900 compatible = "usb-nop-xceiv"; 901 #phy-cells = <0>; 902 }; 903 904 smbus1: smbus1 { 905 compatible = "st,stm32-smbus"; 906 #address-cells = <1>; 907 #size-cells = <0>; 908 i2c = <&i2c2>; 909 status = "disabled"; 910 }; 911 912 smbus2: smbus2 { 913 compatible = "st,stm32-smbus"; 914 #address-cells = <1>; 915 #size-cells = <0>; 916 i2c = <&i2c2>; 917 status = "disabled"; 918 }; 919 920 smbus3: smbus3 { 921 compatible = "st,stm32-smbus"; 922 #address-cells = <1>; 923 #size-cells = <0>; 924 i2c = <&i2c3>; 925 status = "disabled"; 926 }; 927}; 928 929&nvic { 930 arm,num-irq-priority-bits = <4>; 931}; 932
