1/*
2 * Copyright (c) 2017 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/f4/stm32f401.dtsi>
8
9/ {
10	clocks {
11		plli2s: plli2s {
12			#clock-cells = <0>;
13			compatible = "st,stm32f411-plli2s-clock";
14			status = "disabled";
15		};
16	};
17
18	soc {
19		compatible = "st,stm32f411", "st,stm32f4", "simple-bus";
20
21		spi5: spi@40015000 {
22			compatible = "st,stm32-spi";
23			#address-cells = <1>;
24			#size-cells = <0>;
25			reg = <0x40015000 0x400>;
26			clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
27			interrupts = <85 5>;
28			status = "disabled";
29		};
30
31		i2s1: i2s@40013000 {
32			compatible = "st,stm32-i2s";
33			#address-cells = <1>;
34			#size-cells = <0>;
35			reg = <0x40013000 0x400>;
36			clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
37			interrupts = <35 5>;
38			dmas = <&dma2 3 3 0x400 0x3
39				&dma2 2 3 0x400 0x3>;
40			dma-names = "tx", "rx";
41			status = "disabled";
42		};
43
44		i2s4: i2s@40013400 {
45			compatible = "st,stm32-i2s";
46			#address-cells = <1>;
47			#size-cells = <0>;
48			reg = <0x40013400 0x400>;
49			clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
50			interrupts = <84 5>;
51			dmas = <&dma2 1 4 0x400 0x3
52				&dma2 0 4 0x400 0x3>;
53			dma-names = "tx", "rx";
54			status = "disabled";
55		};
56
57		i2s5: i2s@40015000 {
58			compatible = "st,stm32-i2s";
59			#address-cells = <1>;
60			#size-cells = <0>;
61			reg = <0x40015000 0x400>;
62			clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
63			interrupts = <85 5>;
64			dmas = <&dma2 6 7 0x400 0x3
65				&dma2 5 7 0x400 0x3>;
66			dma-names = "tx", "rx";
67			status = "disabled";
68		};
69	};
70
71	die_temp: dietemp {
72		io-channels = <&adc1 18>;
73	};
74};
75