1/* 2 * Copyright (c) 2017 Linaro Limited 3 * Copyright (c) 2021 Marius Scholtz, RIC Electronics 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8#include <st/f4/stm32f401.dtsi> 9 10/ { 11 chosen { 12 zephyr,entropy = &rng; 13 }; 14 15 soc { 16 compatible = "st,stm32f405", "st,stm32f4", "simple-bus"; 17 18 pinctrl: pin-controller@40020000 { 19 reg = <0x40020000 0x2400>; 20 21 gpiof: gpio@40021400 { 22 compatible = "st,stm32-gpio"; 23 gpio-controller; 24 #gpio-cells = <2>; 25 reg = <0x40021400 0x400>; 26 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>; 27 }; 28 29 gpiog: gpio@40021800 { 30 compatible = "st,stm32-gpio"; 31 gpio-controller; 32 #gpio-cells = <2>; 33 reg = <0x40021800 0x400>; 34 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>; 35 }; 36 37 gpioi: gpio@40022000 { 38 compatible = "st,stm32-gpio"; 39 gpio-controller; 40 #gpio-cells = <2>; 41 reg = <0x40022000 0x400>; 42 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>; 43 }; 44 }; 45 46 usart3: serial@40004800 { 47 compatible = "st,stm32-usart", "st,stm32-uart"; 48 reg = <0x40004800 0x400>; 49 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>; 50 resets = <&rctl STM32_RESET(APB1, 18U)>; 51 interrupts = <39 0>; 52 status = "disabled"; 53 }; 54 55 uart4: serial@40004c00 { 56 compatible ="st,stm32-uart"; 57 reg = <0x40004c00 0x400>; 58 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>; 59 resets = <&rctl STM32_RESET(APB1, 19U)>; 60 interrupts = <52 0>; 61 status = "disabled"; 62 }; 63 64 uart5: serial@40005000 { 65 compatible = "st,stm32-uart"; 66 reg = <0x40005000 0x400>; 67 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>; 68 resets = <&rctl STM32_RESET(APB1, 20U)>; 69 interrupts = <53 0>; 70 status = "disabled"; 71 }; 72 73 timers6: timers@40001000 { 74 compatible = "st,stm32-timers"; 75 reg = <0x40001000 0x400>; 76 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>; 77 resets = <&rctl STM32_RESET(APB1, 4U)>; 78 interrupts = <54 0>; 79 interrupt-names = "global"; 80 st,prescaler = <0>; 81 status = "disabled"; 82 83 counter { 84 compatible = "st,stm32-counter"; 85 status = "disabled"; 86 }; 87 }; 88 89 timers7: timers@40001400 { 90 compatible = "st,stm32-timers"; 91 reg = <0x40001400 0x400>; 92 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>; 93 resets = <&rctl STM32_RESET(APB1, 5U)>; 94 interrupts = <55 0>; 95 interrupt-names = "global"; 96 st,prescaler = <0>; 97 status = "disabled"; 98 99 counter { 100 compatible = "st,stm32-counter"; 101 status = "disabled"; 102 }; 103 }; 104 105 timers8: timers@40010400 { 106 compatible = "st,stm32-timers"; 107 reg = <0x40010400 0x400>; 108 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>; 109 resets = <&rctl STM32_RESET(APB2, 1U)>; 110 interrupts = <43 0>, <44 0>, <45 0>, <46 0>; 111 interrupt-names = "brk", "up", "trgcom", "cc"; 112 st,prescaler = <0>; 113 status = "disabled"; 114 115 pwm { 116 compatible = "st,stm32-pwm"; 117 status = "disabled"; 118 #pwm-cells = <3>; 119 }; 120 121 qdec { 122 compatible = "st,stm32-qdec"; 123 status = "disabled"; 124 st,input-filter-level = <NO_FILTER>; 125 }; 126 }; 127 128 timers12: timers@40001800 { 129 compatible = "st,stm32-timers"; 130 reg = <0x40001800 0x400>; 131 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>; 132 resets = <&rctl STM32_RESET(APB1, 6U)>; 133 interrupts = <43 0>; 134 interrupt-names = "global"; 135 st,prescaler = <0>; 136 status = "disabled"; 137 138 pwm { 139 compatible = "st,stm32-pwm"; 140 status = "disabled"; 141 #pwm-cells = <3>; 142 }; 143 144 counter { 145 compatible = "st,stm32-counter"; 146 status = "disabled"; 147 }; 148 }; 149 150 timers13: timers@40001c00 { 151 compatible = "st,stm32-timers"; 152 reg = <0x40001c00 0x400>; 153 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>; 154 resets = <&rctl STM32_RESET(APB1, 7U)>; 155 interrupts = <44 0>; 156 interrupt-names = "global"; 157 st,prescaler = <0>; 158 status = "disabled"; 159 160 pwm { 161 compatible = "st,stm32-pwm"; 162 status = "disabled"; 163 #pwm-cells = <3>; 164 }; 165 166 counter { 167 compatible = "st,stm32-counter"; 168 status = "disabled"; 169 }; 170 }; 171 172 timers14: timers@40002000 { 173 compatible = "st,stm32-timers"; 174 reg = <0x40002000 0x400>; 175 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>; 176 resets = <&rctl STM32_RESET(APB1, 8U)>; 177 interrupts = <45 0>; 178 interrupt-names = "global"; 179 st,prescaler = <0>; 180 status = "disabled"; 181 182 pwm { 183 compatible = "st,stm32-pwm"; 184 status = "disabled"; 185 #pwm-cells = <3>; 186 }; 187 188 counter { 189 compatible = "st,stm32-counter"; 190 status = "disabled"; 191 }; 192 }; 193 194 usbotg_hs: usb@40040000 { 195 compatible = "st,stm32-otghs"; 196 reg = <0x40040000 0x40000>; 197 interrupts = <77 0>, <74 0>, <75 0>; 198 interrupt-names = "otghs", "ep1_out", "ep1_in"; 199 num-bidir-endpoints = <6>; 200 ram-size = <4096>; 201 maximum-speed = "full-speed"; 202 phys = <&otghs_fs_phy>; 203 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x20000000>, 204 <&rcc STM32_SRC_PLL_Q NO_SEL>; 205 status = "disabled"; 206 }; 207 208 can1: can@40006400 { 209 compatible = "st,stm32-bxcan"; 210 reg = <0x40006400 0x400>; 211 interrupts = <19 0>, <20 0>, <21 0>, <22 0>; 212 interrupt-names = "TX", "RX0", "RX1", "SCE"; 213 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; 214 status = "disabled"; 215 }; 216 217 can2: can@40006800 { 218 compatible = "st,stm32-bxcan"; 219 reg = <0x40006800 0x400>; 220 interrupts = <63 0>, <64 0>, <65 0>, <66 0>; 221 interrupt-names = "TX", "RX0", "RX1", "SCE"; 222 /* also enabling clock for can1 (master instance) */ 223 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>; 224 master-can-reg = <0x40006400>; 225 status = "disabled"; 226 }; 227 228 rng: rng@50060800 { 229 compatible = "st,stm32-rng"; 230 reg = <0x50060800 0x400>; 231 interrupts = <80 0>; 232 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>; 233 status = "disabled"; 234 }; 235 236 backup_sram: memory@40024000 { 237 compatible = "zephyr,memory-region", "st,stm32-backup-sram"; 238 reg = <0x40024000 DT_SIZE_K(4)>; 239 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>; 240 zephyr,memory-region = "BACKUP_SRAM"; 241 status = "disabled"; 242 }; 243 244 adc2: adc@40012100 { 245 compatible = "st,stm32-adc"; 246 reg = <0x40012100 0x050>; 247 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>; 248 interrupts = <18 0>; 249 status = "disabled"; 250 #io-channel-cells = <1>; 251 resolutions = <STM32_ADC_RES(12, 0x00) 252 STM32_ADC_RES(10, 0x01) 253 STM32_ADC_RES(8, 0x02) 254 STM32_ADC_RES(6, 0x03)>; 255 sampling-times = <3 15 28 56 84 112 144 480>; 256 st,adc-clock-source = <SYNC>; 257 st,adc-sequencer = <FULLY_CONFIGURABLE>; 258 }; 259 260 adc3: adc@40012200 { 261 compatible = "st,stm32-adc"; 262 reg = <0x40012200 0x050>; 263 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>; 264 interrupts = <18 0>; 265 status = "disabled"; 266 #io-channel-cells = <1>; 267 resolutions = <STM32_ADC_RES(12, 0x00) 268 STM32_ADC_RES(10, 0x01) 269 STM32_ADC_RES(8, 0x02) 270 STM32_ADC_RES(6, 0x03)>; 271 sampling-times = <3 15 28 56 84 112 144 480>; 272 st,adc-clock-source = <SYNC>; 273 st,adc-sequencer = <FULLY_CONFIGURABLE>; 274 }; 275 276 dac1: dac@40007400 { 277 compatible = "st,stm32-dac"; 278 reg = <0x40007400 0x400>; 279 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>; 280 status = "disabled"; 281 #io-channel-cells = <1>; 282 }; 283 }; 284 285 otghs_fs_phy: otghs_fs_phy { 286 compatible = "usb-nop-xceiv"; 287 #phy-cells = <0>; 288 }; 289}; 290
