1/*
2 * Copyright (c) 2017 I-SENSE group of ICCS
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/f3/stm32f3.dtsi>
8#include <zephyr/dt-bindings/adc/stm32l4_adc.h>
9
10/ {
11	soc {
12		compatible = "st,stm32f303", "st,stm32f3", "simple-bus";
13
14		usb: usb@40005c00 {
15			/* Remap USB_LP IRQ to enable use with CAN_1 */
16			interrupts = <75 0>;
17		};
18
19		i2c2: i2c@40005800 {
20			compatible = "st,stm32-i2c-v2";
21			clock-frequency = <I2C_BITRATE_STANDARD>;
22			#address-cells = <1>;
23			#size-cells = <0>;
24			reg = <0x40005800 0x400>;
25			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>,
26				 /* I2C clock source should always be defined,
27				  * even for the default value
28				  */
29				 <&rcc STM32_SRC_SYSCLK I2C2_SEL(1)>;
30			interrupts = <33 0>, <34 0>;
31			interrupt-names = "event", "error";
32			status = "disabled";
33		};
34
35		spi2: spi@40003800 {
36			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
37			#address-cells = <1>;
38			#size-cells = <0>;
39			reg = <0x40003800 0x400>;
40			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
41			interrupts = <36 5>;
42			status = "disabled";
43		};
44
45		spi3: spi@40003c00 {
46			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
47			#address-cells = <1>;
48			#size-cells = <0>;
49			reg = <0x40003c00 0x400>;
50			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
51			interrupts = <51 5>;
52			status = "disabled";
53		};
54
55		uart5: serial@40005000 {
56			compatible = "st,stm32-uart";
57			reg = <0x40005000 0x400>;
58			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
59			resets = <&rctl STM32_RESET(APB1, 20U)>;
60			interrupts = <53 0>;
61			status = "disabled";
62		};
63
64		pinctrl: pin-controller@48000000 {
65
66			gpioe: gpio@48001000 {
67				compatible = "st,stm32-gpio";
68				gpio-controller;
69				#gpio-cells = <2>;
70				reg = <0x48001000 0x400>;
71				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
72			};
73		};
74
75		timers1: timers@40012c00 {
76			compatible = "st,stm32-timers";
77			reg = <0x40012c00 0x400>;
78			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
79			resets = <&rctl STM32_RESET(APB2, 11U)>;
80			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
81			interrupt-names = "brk", "up", "trgcom", "cc";
82			st,prescaler = <0>;
83			status = "disabled";
84
85			pwm {
86				compatible = "st,stm32-pwm";
87				status = "disabled";
88				#pwm-cells = <3>;
89			};
90		};
91
92		timers4: timers@40000800 {
93			compatible = "st,stm32-timers";
94			reg = <0x40000800 0x400>;
95			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
96			resets = <&rctl STM32_RESET(APB1, 2U)>;
97			interrupts = <30 0>;
98			interrupt-names = "global";
99			st,prescaler = <0>;
100			status = "disabled";
101
102			pwm {
103				compatible = "st,stm32-pwm";
104				status = "disabled";
105				#pwm-cells = <3>;
106			};
107		};
108
109		timers8: timers@40013400 {
110			compatible = "st,stm32-timers";
111			reg = <0x40013400 0x400>;
112			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
113			resets = <&rctl STM32_RESET(APB2, 13U)>;
114			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
115			interrupt-names = "brk", "up", "trgcom", "cc";
116			st,prescaler = <0>;
117			status = "disabled";
118
119			pwm {
120				compatible = "st,stm32-pwm";
121				status = "disabled";
122				#pwm-cells = <3>;
123			};
124		};
125
126		timers20: timers@40015000 {
127			compatible = "st,stm32-timers";
128			reg = <0x40015000 0x400>;
129			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
130			resets = <&rctl STM32_RESET(APB2, 20U)>;
131			interrupts = <77 0>, <78 0>, <79 0>, <80 0>;
132			interrupt-names = "brk", "up", "trgcom", "cc";
133			st,prescaler = <0>;
134			status = "disabled";
135
136			pwm {
137				compatible = "st,stm32-pwm";
138				status = "disabled";
139				#pwm-cells = <3>;
140			};
141		};
142
143		adc1: adc@50000000 {
144			compatible = "st,stm32-adc";
145			reg = <0x50000000 0x400>;
146			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
147			interrupts = <18 0>;
148			status = "disabled";
149			vref-mv = <3000>;
150			#io-channel-cells = <1>;
151			resolutions = <STM32_ADC_RES(12, 0x00)
152				       STM32_ADC_RES(10, 0x01)
153				       STM32_ADC_RES(8, 0x02)
154				       STM32_ADC_RES(6, 0x03)>;
155			sampling-times = <2 3 5 8 20 62 182 602>;
156			st,adc-sequencer = <FULLY_CONFIGURABLE>;
157		};
158
159		adc2: adc@50000100 {
160			compatible = "st,stm32-adc";
161			reg = <0x50000100 0x4c>;
162			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
163			interrupts = <18 0>;
164			status = "disabled";
165			vref-mv = <3000>;
166			#io-channel-cells = <1>;
167			resolutions = <STM32_ADC_RES(12, 0x00)
168				       STM32_ADC_RES(10, 0x01)
169				       STM32_ADC_RES(8, 0x02)
170				       STM32_ADC_RES(6, 0x03)>;
171			sampling-times = <2 3 5 8 20 62 182 602>;
172			st,adc-sequencer = <FULLY_CONFIGURABLE>;
173		};
174	};
175
176	smbus2: smbus2 {
177		compatible = "st,stm32-smbus";
178		#address-cells = <1>;
179		#size-cells = <0>;
180		i2c = <&i2c2>;
181		status = "disabled";
182	};
183};
184