1/*
2 * Copyright (c) 2019 Argentum Systems Ltd.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <zephyr/dt-bindings/clock/stm32f10x_clock.h>
8#include <st/f1/stm32f1.dtsi>
9
10/ {
11	clocks {
12		/delete-node/ pll;
13
14		pll: pll {
15			#clock-cells = <0>;
16			compatible = "st,stm32f105-pll-clock";
17			status = "disabled";
18		};
19
20		pll2: pll2 {
21			#clock-cells = <0>;
22			compatible = "st,stm32f105-pll2-clock";
23			clocks = <&clk_hse>;
24			status = "disabled";
25		};
26	};
27
28	soc {
29		compatible = "st,stm32f105", "st,stm32f1", "simple-bus";
30
31		flash-controller@40022000 {
32			flash0: flash@8000000 {
33				erase-block-size = <DT_SIZE_K(2)>;
34			};
35		};
36
37		can1: can@40006400 {
38			compatible = "st,stm32-bxcan";
39			reg = <0x40006400 0x400>;
40			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
41			interrupt-names = "TX", "RX0", "RX1", "SCE";
42			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
43			status = "disabled";
44		};
45
46		can2: can@40006800 {
47			compatible = "st,stm32-bxcan";
48			reg = <0x40006800 0x400>;
49			interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
50			interrupt-names = "TX", "RX0", "RX1", "SCE";
51			/* also enabling clock for can1 (master instance) */
52			clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
53			status = "disabled";
54		};
55
56		dac1: dac@40007400 {
57			compatible = "st,stm32-dac";
58			reg = <0x40007400 0x400>;
59			clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
60			status = "disabled";
61			#io-channel-cells = <1>;
62		};
63
64		uart4: serial@40004c00 {
65			compatible = "st,stm32-uart";
66			reg = <0x40004c00 0x400>;
67			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
68			resets = <&rctl STM32_RESET(APB1, 19U)>;
69			interrupts = <52 0>;
70			status = "disabled";
71		};
72
73		uart5: serial@40005000 {
74			compatible = "st,stm32-uart";
75			reg = <0x40005000 0x400>;
76			clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
77			resets = <&rctl STM32_RESET(APB1, 20U)>;
78			interrupts = <53 0>;
79			status = "disabled";
80		};
81
82		spi2: spi@40003800 {
83			compatible = "st,stm32-spi";
84			#address-cells = <1>;
85			#size-cells = <0>;
86			reg = <0x40003800 0x400>;
87			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
88			interrupts = <36 5>;
89			status = "disabled";
90		};
91
92		spi3: spi@40003c00 {
93			compatible = "st,stm32-spi";
94			#address-cells = <1>;
95			#size-cells = <0>;
96			reg = <0x40003c00 0x400>;
97			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
98			interrupts = <51 5>;
99			status = "disabled";
100		};
101
102		timers5: timers@40000c00 {
103			compatible = "st,stm32-timers";
104			reg = <0x40000c00 0x400>;
105			clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
106			resets = <&rctl STM32_RESET(APB1, 3U)>;
107			interrupts = <50 0>;
108			interrupt-names = "global";
109			st,prescaler = <0>;
110			status = "disabled";
111
112			pwm {
113				compatible = "st,stm32-pwm";
114				status = "disabled";
115				#pwm-cells = <3>;
116			};
117		};
118
119		timers6: timers@40001000 {
120			compatible = "st,stm32-timers";
121			reg = <0x40001000 0x400>;
122			clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
123			resets = <&rctl STM32_RESET(APB1, 4U)>;
124			interrupts = <54 0>;
125			interrupt-names = "global";
126			st,prescaler = <0>;
127			status = "disabled";
128		};
129
130		timers7: timers@40001400 {
131			compatible = "st,stm32-timers";
132			reg = <0x40001400 0x400>;
133			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
134			resets = <&rctl STM32_RESET(APB1, 5U)>;
135			interrupts = <55 0>;
136			interrupt-names = "global";
137			st,prescaler = <0>;
138			status = "disabled";
139		};
140
141		usbotg_fs: usb@50000000 {
142			compatible = "st,stm32-otgfs";
143			reg = <0x50000000 0x40000>;
144			interrupts = <67 0>;
145			interrupt-names = "otgfs";
146			num-bidir-endpoints = <4>;
147			ram-size = <1280>;
148			clocks = <&rcc STM32_CLOCK(AHB1, 12U)>;
149			phys = <&otgfs_phy>;
150			status = "disabled";
151		};
152	};
153
154	otgfs_phy: otgfs_phy {
155		compatible = "usb-nop-xceiv";
156		#phy-cells = <0>;
157	};
158};
159