1/*
2 * Copyright (c) 2020 Jonas Eriksson, Up to Code AB
3 *
4 * SoC device tree include for STM32F100xB SoCs
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9#include <mem.h>
10#include <st/f1/stm32f1.dtsi>
11
12/ {
13	sram0: memory@20000000 {
14		reg = <0x20000000 DT_SIZE_K(8)>;
15	};
16
17	clocks {
18		/delete-node/ pll;
19
20		pll: pll {
21			#clock-cells = <0>;
22			compatible = "st,stm32f100-pll-clock";
23			status = "disabled";
24		};
25	};
26
27	soc {
28		compatible = "st,stm32f100", "st,stm32f1", "simple-bus";
29
30		flash-controller@40022000 {
31			flash0: flash@8000000 {
32				reg = <0x08000000 DT_SIZE_K(128)>;
33				erase-block-size = <DT_SIZE_K(1)>;
34			};
35		};
36
37		spi2: spi@40003800 {
38			compatible = "st,stm32-spi";
39			#address-cells = <1>;
40			#size-cells = <0>;
41			reg = <0x40003800 0x400>;
42			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
43			interrupts = <36 5>;
44			status = "disabled";
45		};
46
47		dac1: dac@40007400 {
48			compatible = "st,stm32-dac";
49			reg = <0x40007400 0x400>;
50			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
51			status = "disabled";
52			#io-channel-cells = <1>;
53		};
54	};
55};
56