1/*
2 * Copyright (c) 2018 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#include <mem.h>
7#include <st/f0/stm32f070.dtsi>
8
9/ {
10	sram0: memory@20000000 {
11		reg = <0x20000000 DT_SIZE_K(16)>;
12	};
13
14	soc {
15		flash-controller@40022000 {
16			flash0: flash@8000000 {
17				erase-block-size = <2048>;
18				reg = <0x08000000 DT_SIZE_K(128)>;
19			};
20		};
21
22		/*
23		 * USARTs 3-4 share the same IRQ on stm32f070Xb devices. This
24		 * configuration is not currently supported, so at most one of
25		 * these may be enabled at a time. Enabling more than one will
26		 * result in a build failure.
27		 */
28		usart3: serial@40004800 {
29			compatible = "st,stm32-usart", "st,stm32-uart";
30			reg = <0x40004800 0x400>;
31			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
32			resets = <&rctl STM32_RESET(APB1, 18U)>;
33			interrupts = <29 0>;
34			status = "disabled";
35		};
36
37		usart4: serial@40004c00 {
38			compatible = "st,stm32-usart", "st,stm32-uart";
39			reg = <0x40004c00 0x400>;
40			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
41			resets = <&rctl STM32_RESET(APB1, 19U)>;
42			interrupts = <29 0>;
43			status = "disabled";
44		};
45
46		i2c2: i2c@40005800 {
47			compatible = "st,stm32-i2c-v2";
48			clock-frequency = <I2C_BITRATE_STANDARD>;
49			#address-cells = <1>;
50			#size-cells = <0>;
51			reg = <0x40005800 0x400>;
52			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
53			interrupts = <24 0>;
54			interrupt-names = "combined";
55			status = "disabled";
56		};
57
58		spi2: spi@40003800 {
59			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
60			#address-cells = <1>;
61			#size-cells = <0>;
62			reg = <0x40003800 0x400>;
63			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
64			interrupts = <26 3>;
65			status = "disabled";
66		};
67
68		timers6: timers@40001000 {
69			compatible = "st,stm32-timers";
70			reg = <0x40001000 0x400>;
71			clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
72			resets = <&rctl STM32_RESET(APB1, 4U)>;
73			interrupts = <17 0>;
74			interrupt-names = "global";
75			st,prescaler = <0>;
76			status = "disabled";
77		};
78
79		timers7: timers@40001400 {
80			compatible = "st,stm32-timers";
81			reg = <0x40001400 0x400>;
82			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
83			resets = <&rctl STM32_RESET(APB1, 5U)>;
84			interrupts = <18 0>;
85			interrupt-names = "global";
86			st,prescaler = <0>;
87			status = "disabled";
88		};
89	};
90
91	smbus2: smbus2 {
92		compatible = "st,stm32-smbus";
93		#address-cells = <1>;
94		#size-cells = <0>;
95		i2c = <&i2c2>;
96		status = "disabled";
97	};
98};
99