1/*
2 * Copyright (c) 2018 qianfan Zhao
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/f0/stm32f030.dtsi>
8
9/ {
10	soc {
11		compatible = "st,stm32f070", "st,stm32f0", "simple-bus";
12
13		usart2: serial@40004400 {
14			compatible = "st,stm32-usart", "st,stm32-uart";
15			reg = <0x40004400 0x400>;
16			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
17			resets = <&rctl STM32_RESET(APB1, 17U)>;
18			interrupts = <28 0>;
19			status = "disabled";
20		};
21
22		timers15: timers@40014000 {
23			compatible = "st,stm32-timers";
24			reg = <0x40014000 0x400>;
25			clocks = <&rcc STM32_CLOCK(APB2, 16U)>;
26			resets = <&rctl STM32_RESET(APB2, 16U)>;
27			interrupts = <20 0>;
28			interrupt-names = "global";
29			st,prescaler = <0>;
30			status = "disabled";
31
32			pwm {
33				compatible = "st,stm32-pwm";
34				status = "disabled";
35				#pwm-cells = <3>;
36			};
37		};
38
39		usb: usb@40005c00 {
40			compatible = "st,stm32-usb";
41			reg = <0x40005c00 0x400>;
42			interrupts = <31 0>;
43			interrupt-names = "usb";
44			num-bidir-endpoints = <8>;
45			ram-size = <1024>;
46			phys = <&usb_fs_phy>;
47			clocks = <&rcc STM32_CLOCK(APB1, 23U)>,
48				 <&rcc STM32_SRC_PLLCLK USB_SEL(1)>;
49			status = "disabled";
50		};
51	};
52
53	usb_fs_phy: usbphy {
54		compatible = "usb-nop-xceiv";
55		#phy-cells = <0>;
56	};
57};
58