1/* 2 * Copyright (c) 2018 Nathan Tsoi <nathan@vertile.com> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <st/f0/stm32f031.dtsi> 8 9/ { 10 soc { 11 compatible = "st,stm32f051", "st,stm32f0", "simple-bus"; 12 13 usart2: serial@40004400 { 14 compatible = "st,stm32-usart", "st,stm32-uart"; 15 reg = <0x40004400 0x400>; 16 clocks = <&rcc STM32_CLOCK(APB1, 17U)>; 17 resets = <&rctl STM32_RESET(APB1, 17U)>; 18 interrupts = <28 0>; 19 status = "disabled"; 20 }; 21 22 i2c2: i2c@40005800 { 23 compatible = "st,stm32-i2c-v2"; 24 clock-frequency = <I2C_BITRATE_STANDARD>; 25 #address-cells = <1>; 26 #size-cells = <0>; 27 reg = <0x40005800 0x400>; 28 clocks = <&rcc STM32_CLOCK(APB1, 22U)>; 29 interrupts = <24 0>; 30 interrupt-names = "combined"; 31 status = "disabled"; 32 }; 33 34 spi2: spi@40003800 { 35 compatible = "st,stm32-spi-fifo", "st,stm32-spi"; 36 #address-cells = <1>; 37 #size-cells = <0>; 38 reg = <0x40003800 0x400>; 39 clocks = <&rcc STM32_CLOCK(APB1, 14U)>; 40 interrupts = <26 3>; 41 status = "disabled"; 42 }; 43 44 timers6: timers@40001000 { 45 compatible = "st,stm32-timers"; 46 reg = <0x40001000 0x400>; 47 clocks = <&rcc STM32_CLOCK(APB1, 4U)>; 48 resets = <&rctl STM32_RESET(APB1, 4U)>; 49 interrupts = <17 0>; 50 interrupt-names = "global"; 51 st,prescaler = <0>; 52 status = "disabled"; 53 }; 54 55 timers15: timers@40014000 { 56 compatible = "st,stm32-timers"; 57 reg = <0x40014000 0x400>; 58 clocks = <&rcc STM32_CLOCK(APB2, 16U)>; 59 resets = <&rctl STM32_RESET(APB2, 16U)>; 60 interrupts = <20 0>; 61 interrupt-names = "global"; 62 st,prescaler = <0>; 63 status = "disabled"; 64 65 pwm { 66 compatible = "st,stm32-pwm"; 67 status = "disabled"; 68 #pwm-cells = <3>; 69 }; 70 }; 71 72 dac1: dac@40007400 { 73 compatible = "st,stm32-dac"; 74 reg = <0x40007400 0x400>; 75 clocks = <&rcc STM32_CLOCK(APB1, 29U)>; 76 status = "disabled"; 77 #io-channel-cells = <1>; 78 }; 79 }; 80 81 smbus2: smbus2 { 82 compatible = "st,stm32-smbus"; 83 #address-cells = <1>; 84 #size-cells = <0>; 85 i2c = <&i2c2>; 86 status = "disabled"; 87 }; 88}; 89