1/*
2 * Copyright (c) 2021 Sebastian Schwabe <sebastian.schwabe@mailbox.tu-dresden.de>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/f0/stm32f0.dtsi>
8
9/ {
10	soc {
11		compatible = "st,stm32f031", "st,stm32f0", "simple-bus";
12
13		timers2: timers@40000000 {
14			compatible = "st,stm32-timers";
15			reg = <0x40000000 0x400>;
16			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
17			resets = <&rctl STM32_RESET(APB1, 0U)>;
18			interrupts = <15 0>;
19			interrupt-names = "global";
20			st,prescaler = <0>;
21			status = "disabled";
22
23			pwm {
24				compatible = "st,stm32-pwm";
25				status = "disabled";
26				#pwm-cells = <3>;
27			};
28
29			counter {
30					compatible = "st,stm32-counter";
31					status = "disabled";
32				};
33		};
34
35		rtc@40002800 {
36			bbram: backup_regs {
37				compatible = "st,stm32-bbram";
38				st,backup-regs = <5>;
39				status = "disabled";
40			};
41		};
42	};
43
44	die_temp: dietemp {
45		compatible = "st,stm32-temp-cal";
46		ts-cal1-addr = <0x1FFFF7B8>;
47		ts-cal2-addr = <0x1FFFF7C2>;
48		ts-cal1-temp = <30>;
49		ts-cal2-temp = <110>;
50		ts-cal-vrefanalog = <3300>;
51		io-channels = <&adc1 16>;
52		status = "disabled";
53	};
54
55	/* All STM32F0 series have ADC VBAT channel, except STM32F0x0 value line */
56	vbat: vbat {
57		compatible = "st,stm32-vbat";
58		ratio = <2>;
59		io-channels = <&adc1 18>;
60		status = "disabled";
61	};
62};
63