1/* 2 * Copyright (c) 2018 Intel Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6#include <mem.h> 7#include <st/f0/stm32f030.dtsi> 8 9/ { 10 sram0: memory@20000000 { 11 reg = <0x20000000 DT_SIZE_K(8)>; 12 }; 13 14 soc { 15 flash-controller@40022000 { 16 flash0: flash@8000000 { 17 reg = <0x08000000 DT_SIZE_K(64)>; 18 }; 19 }; 20 21 usart2: serial@40004400 { 22 compatible = "st,stm32-usart", "st,stm32-uart"; 23 reg = <0x40004400 0x400>; 24 clocks = <&rcc STM32_CLOCK(APB1, 17U)>; 25 resets = <&rctl STM32_RESET(APB1, 17U)>; 26 interrupts = <28 0>; 27 status = "disabled"; 28 }; 29 30 i2c2: i2c@40005800 { 31 compatible = "st,stm32-i2c-v2"; 32 clock-frequency = <I2C_BITRATE_STANDARD>; 33 #address-cells = <1>; 34 #size-cells = <0>; 35 reg = <0x40005800 0x400>; 36 clocks = <&rcc STM32_CLOCK(APB1, 22U)>; 37 interrupts = <24 0>; 38 interrupt-names = "combined"; 39 status = "disabled"; 40 }; 41 42 spi2: spi@40003800 { 43 compatible = "st,stm32-spi-fifo", "st,stm32-spi"; 44 #address-cells = <1>; 45 #size-cells = <0>; 46 reg = <0x40003800 0x400>; 47 clocks = <&rcc STM32_CLOCK(APB1, 14U)>; 48 interrupts = <26 3>; 49 status = "disabled"; 50 }; 51 52 timers6: timers@40001000 { 53 compatible = "st,stm32-timers"; 54 reg = <0x40001000 0x400>; 55 clocks = <&rcc STM32_CLOCK(APB1, 4U)>; 56 resets = <&rctl STM32_RESET(APB1, 4U)>; 57 interrupts = <17 0>; 58 interrupt-names = "global"; 59 st,prescaler = <0>; 60 status = "disabled"; 61 }; 62 63 timers15: timers@40014000 { 64 compatible = "st,stm32-timers"; 65 reg = <0x40014000 0x400>; 66 clocks = <&rcc STM32_CLOCK(APB2, 16U)>; 67 resets = <&rctl STM32_RESET(APB2, 16U)>; 68 interrupts = <20 0>; 69 interrupt-names = "global"; 70 st,prescaler = <0>; 71 status = "disabled"; 72 73 pwm { 74 compatible = "st,stm32-pwm"; 75 status = "disabled"; 76 #pwm-cells = <3>; 77 }; 78 }; 79 }; 80 81 smbus2: smbus2 { 82 compatible = "st,stm32-smbus"; 83 #address-cells = <1>; 84 #size-cells = <0>; 85 i2c = <&i2c2>; 86 status = "disabled"; 87 }; 88}; 89