1/*
2 * Copyright (c) 2017 RnDity Sp. z o.o.
3 * Copyright (c) 2019 Centaur Analytics, Inc
4 * Copyright (c) 2024 STMicroelectronics
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9#include <arm/armv6-m.dtsi>
10#include <zephyr/dt-bindings/clock/stm32f0_clock.h>
11#include <zephyr/dt-bindings/i2c/i2c.h>
12#include <zephyr/dt-bindings/gpio/gpio.h>
13#include <zephyr/dt-bindings/pwm/pwm.h>
14#include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15#include <zephyr/dt-bindings/dma/stm32_dma.h>
16#include <zephyr/dt-bindings/adc/stm32l4_adc.h>
17#include <zephyr/dt-bindings/reset/stm32f0_1_3_reset.h>
18#include <zephyr/dt-bindings/adc/adc.h>
19#include <freq.h>
20
21/ {
22	chosen {
23		zephyr,flash-controller = &flash;
24	};
25
26	cpus {
27		#address-cells = <1>;
28		#size-cells = <0>;
29
30		cpu0: cpu@0 {
31			device_type = "cpu";
32			compatible = "arm,cortex-m0";
33			reg = <0>;
34		};
35	};
36
37	sram0: memory@20000000 {
38		compatible = "mmio-sram";
39	};
40
41	clocks {
42		clk_hse: clk-hse {
43			#clock-cells = <0>;
44			compatible = "st,stm32-hse-clock";
45			status = "disabled";
46		};
47
48		clk_hsi: clk-hsi {
49			#clock-cells = <0>;
50			compatible = "fixed-clock";
51			clock-frequency = <DT_FREQ_M(8)>;
52			status = "disabled";
53		};
54
55		clk_hsi14: clk-hsi14 {
56			#clock-cells = <0>;
57			compatible = "fixed-clock";
58			clock-frequency = <DT_FREQ_M(14)>;
59			status = "disabled";
60		};
61
62		clk_lse: clk-lse {
63			#clock-cells = <0>;
64			compatible = "st,stm32-lse-clock";
65			clock-frequency = <32768>;
66			driving-capability = <0>;
67			status = "disabled";
68		};
69
70		clk_lsi: clk-lsi {
71			#clock-cells = <0>;
72			compatible = "fixed-clock";
73			clock-frequency = <DT_FREQ_K(40)>;
74			status = "disabled";
75		};
76
77		pll: pll {
78			#clock-cells = <0>;
79			compatible = "st,stm32f0-pll-clock";
80			status = "disabled";
81		};
82	};
83
84	soc {
85		flash: flash-controller@40022000 {
86			compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller";
87			reg = <0x40022000 0x400>;
88			interrupts = <3 0>;
89			clocks = <&rcc STM32_CLOCK(AHB1, 4U)>;
90
91			#address-cells = <1>;
92			#size-cells = <1>;
93
94			flash0: flash@8000000 {
95				compatible = "st,stm32-nv-flash", "soc-nv-flash";
96				erase-block-size = <1024>;
97				write-block-size = <2>;
98				/* maximum erase time for a 2K sector */
99				max-erase-time = <40>;
100			};
101		};
102
103		rcc: rcc@40021000 {
104			compatible = "st,stm32f0-rcc";
105			#clock-cells = <2>;
106			reg = <0x40021000 0x400>;
107
108			rctl: reset-controller {
109				compatible = "st,stm32-rcc-rctl";
110				#reset-cells = <1>;
111			};
112		};
113
114		exti: interrupt-controller@40010400 {
115			compatible = "st,stm32-exti";
116			interrupt-controller;
117			#interrupt-cells = <1>;
118			#address-cells = <1>;
119			reg = <0x40010400 0x400>;
120			num-lines = <16>;
121			interrupts = <5 0>, <6 0>, <7 0>;
122			interrupt-names = "line0-1", "line2-3", "line4-15";
123			line-ranges = <0 2>, <2 2>, <4 12>;
124		};
125
126		pinctrl: pin-controller@48000000 {
127			compatible = "st,stm32-pinctrl";
128			#address-cells = <1>;
129			#size-cells = <1>;
130			reg = <0x48000000 0x1800>;
131
132			gpioa: gpio@48000000 {
133				compatible = "st,stm32-gpio";
134				gpio-controller;
135				#gpio-cells = <2>;
136				reg = <0x48000000 0x400>;
137				clocks = <&rcc STM32_CLOCK(AHB1, 17U)>;
138			};
139
140			gpiob: gpio@48000400 {
141				compatible = "st,stm32-gpio";
142				gpio-controller;
143				#gpio-cells = <2>;
144				reg = <0x48000400 0x400>;
145				clocks = <&rcc STM32_CLOCK(AHB1, 18U)>;
146			};
147
148			gpioc: gpio@48000800 {
149				compatible = "st,stm32-gpio";
150				gpio-controller;
151				#gpio-cells = <2>;
152				reg = <0x48000800 0x400>;
153				clocks = <&rcc STM32_CLOCK(AHB1, 19U)>;
154			};
155
156			gpiod: gpio@48000c00 {
157				compatible = "st,stm32-gpio";
158				gpio-controller;
159				#gpio-cells = <2>;
160				reg = <0x48000c00 0x400>;
161				clocks = <&rcc STM32_CLOCK(AHB1, 20U)>;
162			};
163
164			gpiof: gpio@48001400 {
165				compatible = "st,stm32-gpio";
166				gpio-controller;
167				#gpio-cells = <2>;
168				reg = <0x48001400 0x400>;
169				clocks = <&rcc STM32_CLOCK(AHB1, 22U)>;
170			};
171		};
172
173		usart1: serial@40013800 {
174			compatible = "st,stm32-usart", "st,stm32-uart";
175			reg = <0x40013800 0x400>;
176			clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
177			resets = <&rctl STM32_RESET(APB2, 14U)>;
178			interrupts = <27 0>;
179			status = "disabled";
180		};
181
182		i2c1: i2c@40005400 {
183			compatible = "st,stm32-i2c-v2";
184			clock-frequency = <I2C_BITRATE_STANDARD>;
185			#address-cells = <1>;
186			#size-cells = <0>;
187			reg = <0x40005400 0x400>;
188			clocks = <&rcc STM32_CLOCK(APB1, 21U)>,
189				 /* I2C1 clock source should always be defined,
190				  * even for the default value
191				  */
192				 <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>;
193			interrupts = <23 0>;
194			interrupt-names = "combined";
195			status = "disabled";
196		};
197
198		spi1: spi@40013000 {
199			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
200			#address-cells = <1>;
201			#size-cells = <0>;
202			reg = <0x40013000 0x400>;
203			clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
204			interrupts = <25 3>;
205			status = "disabled";
206		};
207
208		rtc: rtc@40002800 {
209			compatible = "st,stm32-rtc";
210			reg = <0x40002800 0x400>;
211			clocks = <&rcc STM32_CLOCK(APB1, 28U)>;
212			interrupts = <2 0>;
213			prescaler = <32768>;
214			alarms-count = <1>;
215			alrm-exti-line = <17>;
216			status = "disabled";
217		};
218
219		iwdg: watchdog@40003000 {
220			compatible = "st,stm32-watchdog";
221			reg = <0x40003000 0x400>;
222			status = "disabled";
223		};
224
225		wwdg: watchdog@40002c00 {
226			compatible = "st,stm32-window-watchdog";
227			reg = <0x40002C00 0x400>;
228			clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
229			interrupts = <0 2>;
230			status = "disabled";
231		};
232
233		timers1: timers@40012c00 {
234			compatible = "st,stm32-timers";
235			reg = <0x40012c00 0x400>;
236			clocks = <&rcc STM32_CLOCK(APB2, 11U)>;
237			resets = <&rctl STM32_RESET(APB2, 11U)>;
238			interrupts = <13 0>, <14 0>;
239			interrupt-names = "brk_up_trg_com", "cc";
240			st,prescaler = <0>;
241			status = "disabled";
242
243			pwm {
244				compatible = "st,stm32-pwm";
245				status = "disabled";
246				#pwm-cells = <3>;
247			};
248		};
249
250		timers3: timers@40000400 {
251			compatible = "st,stm32-timers";
252			reg = <0x40000400 0x400>;
253			clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
254			resets = <&rctl STM32_RESET(APB1, 1U)>;
255			interrupts = <16 0>;
256			interrupt-names = "global";
257			st,prescaler = <0>;
258			status = "disabled";
259
260			pwm {
261				compatible = "st,stm32-pwm";
262				status = "disabled";
263				#pwm-cells = <3>;
264			};
265
266			counter {
267				compatible = "st,stm32-counter";
268				status = "disabled";
269			};
270		};
271
272		timers14: timers@40002000 {
273			compatible = "st,stm32-timers";
274			reg = <0x40002000 0x400>;
275			clocks = <&rcc STM32_CLOCK(APB1, 8U)>;
276			resets = <&rctl STM32_RESET(APB1, 8U)>;
277			interrupts = <19 0>;
278			interrupt-names = "global";
279			st,prescaler = <0>;
280			status = "disabled";
281
282			pwm {
283				compatible = "st,stm32-pwm";
284				status = "disabled";
285				#pwm-cells = <3>;
286			};
287
288			counter {
289				compatible = "st,stm32-counter";
290				status = "disabled";
291			};
292		};
293
294		timers16: timers@40014400 {
295			compatible = "st,stm32-timers";
296			reg = <0x40014400 0x400>;
297			clocks = <&rcc STM32_CLOCK(APB2, 17U)>;
298			resets = <&rctl STM32_RESET(APB2, 17U)>;
299			interrupts = <21 0>;
300			interrupt-names = "global";
301			st,prescaler = <0>;
302			status = "disabled";
303
304			pwm {
305				compatible = "st,stm32-pwm";
306				status = "disabled";
307				#pwm-cells = <3>;
308			};
309
310			counter {
311				compatible = "st,stm32-counter";
312				status = "disabled";
313			};
314		};
315
316		timers17: timers@40014800 {
317			compatible = "st,stm32-timers";
318			reg = <0x40014800 0x400>;
319			clocks = <&rcc STM32_CLOCK(APB2, 18U)>;
320			resets = <&rctl STM32_RESET(APB2, 18U)>;
321			interrupts = <22 0>;
322			interrupt-names = "global";
323			st,prescaler = <0>;
324			status = "disabled";
325
326			pwm {
327				compatible = "st,stm32-pwm";
328				status = "disabled";
329				#pwm-cells = <3>;
330			};
331
332			counter {
333				compatible = "st,stm32-counter";
334				status = "disabled";
335			};
336		};
337
338		adc1: adc@40012400 {
339			compatible = "st,stm32-adc";
340			reg = <0x40012400 0x400>;
341			clocks = <&rcc STM32_CLOCK(APB2, 9U)>;
342			interrupts = <12 0>;
343			status = "disabled";
344			#io-channel-cells = <1>;
345			resolutions = <STM32_ADC_RES(12, 0x00)
346				       STM32_ADC_RES(10, 0x01)
347				       STM32_ADC_RES(8, 0x02)
348				       STM32_ADC_RES(6, 0x03)>;
349			sampling-times = <2 8 14 29 42 56 72 240>;
350			num-sampling-time-common-channels = <1>;
351			st,adc-sequencer = "NOT_FULLY_CONFIGURABLE";
352			st,adc-oversampler = "OVERSAMPLER_NONE";
353		};
354
355		dma1: dma@40020000 {
356			compatible = "st,stm32-dma-v2bis";
357			#dma-cells = <2>;
358			reg = <0x40020000 0x400>;
359			clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
360			interrupts = <9 0 10 0 10 0 11 0 11 0>;
361			status = "disabled";
362		};
363	};
364
365	vref: vref {
366		compatible = "st,stm32-vref";
367		vrefint-cal-addr = <0x1FFFF7BA>;
368		vrefint-cal-mv = <3300>;
369		io-channels = <&adc1 17>;
370		status = "disabled";
371	};
372
373	smbus1: smbus1 {
374		compatible = "st,stm32-smbus";
375		#address-cells = <1>;
376		#size-cells = <0>;
377		i2c = <&i2c1>;
378		status = "disabled";
379	};
380};
381
382&nvic {
383	arm,num-irq-priority-bits = <2>;
384};
385