1 /* 2 * Copyright (c) 2022 Intel Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef __INTEL_DAI_DRIVER_SSP_REGSV2_H__ 8 #define __INTEL_DAI_DRIVER_SSP_REGSV2_H__ 9 10 /* SSP register offsets */ 11 #define SSCR0 0x00 12 #define SSCR1 0x04 13 #define SSSR 0x08 14 #define SSITR 0x0C 15 #define SSTO 0x28 16 #define SSPSP 0x2C 17 #define SSTSS 0x38 18 #define SSCR2 0x40 19 #define SSPSP2 0x44 20 21 #define SSIOC 0x4C 22 #define SSGFS 0x50 23 #define SSDR 0x10 /* Not PTL */ 24 #define SSTSA 0x30 /* Not PTL */ 25 #define SSRSA 0x34 /* Not PTL */ 26 27 #define OUT_FIFO SSDR 28 #define IN_FIFO SSDR 29 30 /* SSCR0 bits */ 31 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1) 32 #define SSCR0_DSIZE_GET(x) (((x) & DAI_INTEL_SSP_MASK(3, 0)) + 1) 33 #define SSCR0_FRF DAI_INTEL_SSP_MASK(5, 4) 34 #define SSCR0_MOT DAI_INTEL_SSP_SET_BITS(5, 4, 0) 35 #define SSCR0_TI DAI_INTEL_SSP_SET_BITS(5, 4, 1) 36 #define SSCR0_NAT DAI_INTEL_SSP_SET_BITS(5, 4, 2) 37 #define SSCR0_PSP DAI_INTEL_SSP_SET_BITS(5, 4, 3) 38 #define SSCR0_ECS BIT(6) 39 #define SSCR0_SSE BIT(7) 40 #define SSCR0_SCR_MASK DAI_INTEL_SSP_MASK(19, 8) 41 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x) 42 #define SSCR0_EDSS BIT(20) 43 #define SSCR0_NCS BIT(21) 44 #define SSCR0_RIM BIT(22) 45 #define SSCR0_TIM BIT(23) 46 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1) 47 #define SSCR0_FRDC_GET(x) ((((x) & DAI_INTEL_SSP_MASK(26, 24)) >> 24) + 1) 48 #define SSCR0_ACS BIT(30) 49 #define SSCR0_MOD BIT(31) 50 51 /* SSCR1 bits */ 52 #define SSCR1_RIE BIT(0) 53 #define SSCR1_TIE BIT(1) 54 #define SSCR1_LBM BIT(2) 55 #define SSCR1_SPO BIT(3) 56 #define SSCR1_SPH BIT(4) 57 #define SSCR1_MWDS BIT(5) 58 #define SSCR1_TFT_MASK DAI_INTEL_SSP_MASK(9, 6) 59 #define SSCR1_TFT(x) DAI_INTEL_SSP_SET_BITS(9, 6, (x) - 1) 60 #define SSCR1_RFT_MASK DAI_INTEL_SSP_MASK(13, 10) 61 #define SSCR1_RFT(x) DAI_INTEL_SSP_SET_BITS(13, 10, (x) - 1) 62 #define SSCR1_EFWR BIT(14) 63 #define SSCR1_STRF BIT(15) 64 #define SSCR1_IFS BIT(16) 65 #define SSCR1_PINTE BIT(18) 66 #define SSCR1_TINTE BIT(19) 67 #define SSCR1_RSRE BIT(20) 68 #define SSCR1_TSRE BIT(21) 69 #define SSCR1_TRAIL BIT(22) 70 #define SSCR1_RWOT BIT(23) 71 #define SSCR1_SFRMDIR BIT(24) 72 #define SSCR1_SCLKDIR BIT(25) 73 #define SSCR1_ECRB BIT(26) 74 #define SSCR1_ECRA BIT(27) 75 #define SSCR1_SCFR BIT(28) 76 #define SSCR1_EBCEI BIT(29) 77 #define SSCR1_TTE BIT(30) 78 #define SSCR1_TTELP BIT(31) 79 80 #define SSCR2_TURM1 BIT(1) 81 #define SSCR2_PSPSRWFDFD BIT(3) 82 #define SSCR2_PSPSTWFDFD BIT(4) 83 #define SSCR2_SDFD BIT(14) 84 #define SSCR2_SDPM BIT(16) 85 #define SSCR2_LJDFD BIT(17) 86 #define SSCR2_MMRATF BIT(18) 87 #define SSCR2_SMTATF BIT(19) 88 #define SSCR2_SFRMEN BIT(20) 89 #define SSCR2_ACIOLBS BIT(21) 90 91 /* SSR bits */ 92 #define SSSR_TNF BIT(2) 93 #define SSSR_RNE BIT(3) 94 #define SSSR_BSY BIT(4) 95 #define SSSR_TFS BIT(5) 96 #define SSSR_RFS BIT(6) 97 #define SSSR_ROR BIT(7) 98 #define SSSR_TUR BIT(21) 99 100 /* SSPSP bits */ 101 #define SSPSP_SCMODE(x) DAI_INTEL_SSP_SET_BITS(1, 0, x) 102 #define SSPSP_SFRMP(x) DAI_INTEL_SSP_SET_BIT(2, x) 103 #define SSPSP_ETDS BIT(3) 104 #define SSPSP_STRTDLY(x) DAI_INTEL_SSP_SET_BITS(6, 4, x) 105 #define SSPSP_DMYSTRT(x) DAI_INTEL_SSP_SET_BITS(8, 7, x) 106 #define SSPSP_SFRMDLY(x) DAI_INTEL_SSP_SET_BITS(15, 9, x) 107 #define SSPSP_SFRMWDTH(x) DAI_INTEL_SSP_SET_BITS(21, 16, x) 108 #define SSPSP_DMYSTOP(x) DAI_INTEL_SSP_SET_BITS(24, 23, x) 109 #define SSPSP_DMYSTOP_BITS 2 110 #define SSPSP_DMYSTOP_MASK DAI_INTEL_SSP_MASK(SSPSP_DMYSTOP_BITS - 1, 0) 111 #define SSPSP_FSRT BIT(25) 112 #define SSPSP_EDMYSTOP(x) DAI_INTEL_SSP_SET_BITS(28, 26, x) 113 114 #define SSPSP2 0x44 115 #define SSPSP2_FEP_MASK 0xff 116 117 #define SSCR3 0x48 118 #define SSIOC 0x4C 119 #define SSP_REG_MAX SSIOC 120 121 /* SSTSA bits */ 122 #define SSTSA_SSTSA(x) DAI_INTEL_SSP_SET_BITS(7, 0, x) 123 #define SSTSA_GET(x) ((x) & DAI_INTEL_SSP_MASK(7, 0)) 124 #define SSTSA_TXEN BIT(8) 125 126 /* SSRSA bits */ 127 #define SSRSA_SSRSA(x) DAI_INTEL_SSP_SET_BITS(7, 0, x) 128 #define SSRSA_GET(x) ((x) & DAI_INTEL_SSP_MASK(7, 0)) 129 #define SSRSA_RXEN BIT(8) 130 131 /* SSCR3 bits */ 132 #define SSCR3_FRM_MST_EN BIT(0) 133 #define SSCR3_I2S_MODE_EN BIT(1) 134 #define SSCR3_I2S_FRM_POL(x) DAI_INTEL_SSP_SET_BIT(2, x) 135 #define SSCR3_I2S_TX_SS_FIX_EN BIT(3) 136 #define SSCR3_I2S_RX_SS_FIX_EN BIT(4) 137 #define SSCR3_I2S_TX_EN BIT(9) 138 #define SSCR3_I2S_RX_EN BIT(10) 139 #define SSCR3_CLK_EDGE_SEL BIT(12) 140 #define SSCR3_STRETCH_TX BIT(14) 141 #define SSCR3_STRETCH_RX BIT(15) 142 #define SSCR3_MST_CLK_EN BIT(16) 143 #define SSCR3_SYN_FIX_EN BIT(17) 144 145 /* SSCR4 bits */ 146 #define SSCR4_TOT_FRM_PRD(x) ((x) << 7) 147 148 /* SSCR5 bits */ 149 #define SSCR5_FRM_ASRT_CLOCKS(x) (((x) - 1) << 1) 150 #define SSCR5_FRM_POLARITY(x) DAI_INTEL_SSP_SET_BIT(0, x) 151 152 /* SFIFOTT bits */ 153 #define SFIFOTT_TX(x) ((x) - 1) 154 #define SFIFOTT_RX(x) (((x) - 1) << 16) 155 156 /* SFIFOL bits */ 157 #define SFIFOL_TFL(x) ((x) & 0xFFFF) 158 #define SFIFOL_RFL(x) ((x) >> 16) 159 160 #define SSTSA_TSEN BIT(8) 161 #define SSRSA_RSEN BIT(8) 162 163 #define SSCR3_TFL_MASK DAI_INTEL_SSP_MASK(5, 0) 164 #define SSCR3_RFL_MASK DAI_INTEL_SSP_MASK(13, 8) 165 #define SSCR3_TFL_VAL(scr3_val) (((scr3_val) >> 0) & DAI_INTEL_SSP_MASK(5, 0)) 166 #define SSCR3_RFL_VAL(scr3_val) (((scr3_val) >> 8) & DAI_INTEL_SSP_MASK(5, 0)) 167 #define SSCR3_TX(x) DAI_INTEL_SSP_SET_BITS(21, 16, (x) - 1) 168 #define SSCR3_RX(x) DAI_INTEL_SSP_SET_BITS(29, 24, (x) - 1) 169 170 #define SSIOC_TXDPDEB BIT(1) 171 #define SSIOC_SFCR BIT(4) 172 #define SSIOC_SCOE BIT(5) 173 174 /* SSMIDyCS */ 175 #define SSMIDyCS_RXEN BIT(0) 176 #define SSMIDyCS_RSRE BIT(1) 177 #define SSMIDyCS_RFL DAI_INTEL_SSP_MASK(23, 16) 178 #define SSMIDyCS_RFL_VAL(rfl_val) (((rfl_val) >> 16) & DAI_INTEL_SSP_MASK(7, 0)) 179 #define SSMIDyCS_RNE BIT(26) 180 #define SSMIDyCS_RFS BIT(27) 181 #define SSMIDyCS_ROR BIT(28) 182 #define SSMIDyCS_PINT BIT(29) 183 #define SSMIDyCS_TINT BIT(30) 184 #define SSMIDyCS_EOC BIT(31) 185 186 /* SSMIDyTSA */ 187 #define SSMIDyTSA_RTSA DAI_INTEL_SSP_MASK(63, 0) 188 #define SSMIDyTSA_SRTSA(x) DAI_INTEL_SSP_MASK(63, 0, x) 189 190 /* SSMODyCS */ 191 #define SSMODyCS_TXEN BIT(0) 192 #define SSMODyCS_TSRE BIT(1) 193 #define SSMODyCS_TFL DAI_INTEL_SSP_MASK(23, 16) 194 #define SSMIDyCS_TFL_VAL(rfl_val) (((rfl_val) >> 16) & DAI_INTEL_SSP_MASK(7, 0)) 195 #define SSMODyCS_TNF BIT(26) 196 #define SSMODyCS_TFS BIT(27) 197 #define SSMODyCS_TUR BIT(28) 198 199 /* SSMODyTSA */ 200 #define SSMODyTSA_TTSA DAI_INTEL_SSP_MASK(63, 0) 201 #define SSMODyTSA_STTSA(x) DAI_INTEL_SSP_MASK(63, 0, x) 202 203 /* For 8000 Hz rate one sample is transmitted within 125us */ 204 #define DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE 125 205 206 /* SSP flush retry counts maximum */ 207 #define DAI_INTEL_SSP_RX_FLUSH_RETRY_MAX 16 208 209 #define SSP_CLK_MCLK_ES_REQ BIT(0) 210 #define SSP_CLK_MCLK_ACTIVE BIT(1) 211 #define SSP_CLK_BCLK_ES_REQ BIT(2) 212 #define SSP_CLK_BCLK_ACTIVE BIT(3) 213 214 #define I2SLCTL_OFFSET 0x04 215 #define I2SLCTL_OFLEN BIT(4) 216 #define I2SLCTL_SPA(x) BIT(16 + x) 217 #define I2SLCTL_CPA(x) BIT(23 + x) 218 #define PCMS0CM_OFFSET 0x16 219 #define PCMS1CM_OFFSET 0x1A 220 221 #define I2CLCTL_MLCS(x) DAI_INTEL_SSP_SET_BITS(30, 27, x) 222 #define SHIM_CLKCTL 0x78 223 #define SHIM_CLKCTL_I2SFDCGB(x) BIT(20 + x) 224 #define SHIM_CLKCTL_I2SEFDCGB(x) BIT(18 + x) 225 226 /** \brief Offset of MCLK Divider Control Register. */ 227 #define MN_MDIVCTRL 0x100 228 229 /** \brief Offset of MCLK Divider x Ratio Register. */ 230 #define MN_MDIVR(x) (0x180 + (x) * 0x4) 231 232 /** \brief Enables the output of MCLK Divider. */ 233 #define MN_MDIVCTRL_M_DIV_ENABLE(x) BIT(x) 234 235 /** \brief Bits for setting MCLK source clock. */ 236 #define MCDSS(x) DAI_INTEL_SSP_SET_BITS(17, 16, x) 237 238 /** \brief Offset of BCLK x M/N Divider M Value Register. */ 239 #define MN_MDIV_M_VAL(x) (0x100 + (x) * 0x8 + 0x0) 240 241 /** \brief Offset of BCLK x M/N Divider N Value Register. */ 242 #define MN_MDIV_N_VAL(x) (0x100 + (x) * 0x8 + 0x4) 243 244 /** \brief Bits for setting M/N source clock. */ 245 #define MNDSS(x) DAI_INTEL_SSP_SET_BITS(21, 20, x) 246 247 /** \brief Mask for clearing mclk and bclk source in MN_MDIVCTRL */ 248 #define MN_SOURCE_CLKS_MASK 0x3 249 250 #endif /* __INTEL_DAI_DRIVER_SSP_REGSV2_H__ */ 251
