1 /*
2  * Copyright (c) 2022 Intel Corporation.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef __INTEL_DAI_DRIVER_SSP_REGSV1_H__
8 #define __INTEL_DAI_DRIVER_SSP_REGSV1_H__
9 
10 /* SSP register offsets */
11 #define SSCR0			0x00
12 #define SSCR1			0x04
13 #define SSSR			0x08
14 #define SSITR			0x0C
15 #define SSTO			0x28
16 #define SSPSP			0x2C
17 #define SSTSS			0x38
18 #define SSCR2			0x40
19 #define SSPSP2			0x44
20 #define SSIOC			0x4C
21 #define SSGFS			0x50
22 #define SSDR			0x10 /* Not PTL */
23 #define SSTSA			0x30 /* Not PTL */
24 #define SSRSA			0x34 /* Not PTL */
25 
26 #define OUT_FIFO		SSDR
27 #define IN_FIFO			SSDR
28 
29 /* SSCR0 bits */
30 #define SSCR0_DSIZE(x)		DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
31 #define SSCR0_DSIZE_GET(x)	(((x) & DAI_INTEL_SSP_MASK(3, 0)) + 1)
32 #define SSCR0_FRF		DAI_INTEL_SSP_MASK(5, 4)
33 #define SSCR0_MOT		DAI_INTEL_SSP_SET_BITS(5, 4, 0)
34 #define SSCR0_TI		DAI_INTEL_SSP_SET_BITS(5, 4, 1)
35 #define SSCR0_NAT		DAI_INTEL_SSP_SET_BITS(5, 4, 2)
36 #define SSCR0_PSP		DAI_INTEL_SSP_SET_BITS(5, 4, 3)
37 #define SSCR0_ECS		BIT(6)
38 #define SSCR0_SSE		BIT(7)
39 #define SSCR0_SCR_MASK		DAI_INTEL_SSP_MASK(19, 8)
40 #define SSCR0_SCR(x)		DAI_INTEL_SSP_SET_BITS(19, 8, x)
41 #define SSCR0_EDSS		BIT(20)
42 #define SSCR0_NCS		BIT(21)
43 #define SSCR0_RIM		BIT(22)
44 #define SSCR0_TIM		BIT(23)
45 #define SSCR0_FRDC(x)		DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
46 #define SSCR0_FRDC_GET(x)	((((x) & DAI_INTEL_SSP_MASK(26, 24)) >> 24) + 1)
47 #define SSCR0_ACS		BIT(30)
48 #define SSCR0_MOD		BIT(31)
49 
50 /* SSCR1 bits */
51 #define SSCR1_RIE		BIT(0)
52 #define SSCR1_TIE		BIT(1)
53 #define SSCR1_LBM		BIT(2)
54 #define SSCR1_SPO		BIT(3)
55 #define SSCR1_SPH		BIT(4)
56 #define SSCR1_MWDS		BIT(5)
57 #define SSCR1_TFT_MASK		DAI_INTEL_SSP_MASK(9, 6)
58 #define SSCR1_TFT(x)		DAI_INTEL_SSP_SET_BITS(9, 6, (x) - 1)
59 #define SSCR1_RFT_MASK		DAI_INTEL_SSP_MASK(13, 10)
60 #define SSCR1_RFT(x)		DAI_INTEL_SSP_SET_BITS(13, 10, (x) - 1)
61 #define SSCR1_EFWR		BIT(14)
62 #define SSCR1_STRF		BIT(15)
63 #define SSCR1_IFS		BIT(16)
64 #define SSCR1_PINTE		BIT(18)
65 #define SSCR1_TINTE		BIT(19)
66 #define SSCR1_RSRE		BIT(20)
67 #define SSCR1_TSRE		BIT(21)
68 #define SSCR1_TRAIL		BIT(22)
69 #define SSCR1_RWOT		BIT(23)
70 #define SSCR1_SFRMDIR		BIT(24)
71 #define SSCR1_SCLKDIR		BIT(25)
72 #define SSCR1_ECRB		BIT(26)
73 #define SSCR1_ECRA		BIT(27)
74 #define SSCR1_SCFR		BIT(28)
75 #define SSCR1_EBCEI		BIT(29)
76 #define SSCR1_TTE		BIT(30)
77 #define SSCR1_TTELP		BIT(31)
78 
79 #define SSCR2_TURM1		BIT(1)
80 #define SSCR2_PSPSRWFDFD	BIT(3)
81 #define SSCR2_PSPSTWFDFD	BIT(4)
82 #define SSCR2_SDFD		BIT(14)
83 #define SSCR2_SDPM		BIT(16)
84 #define SSCR2_LJDFD		BIT(17)
85 #define SSCR2_MMRATF		BIT(18)
86 #define SSCR2_SMTATF		BIT(19)
87 #define SSCR2_SFRMEN		BIT(20)
88 #define SSCR2_ACIOLBS		BIT(21)
89 
90 /* SSR bits */
91 #define SSSR_TNF		BIT(2)
92 #define SSSR_RNE		BIT(3)
93 #define SSSR_BSY		BIT(4)
94 #define SSSR_TFS		BIT(5)
95 #define SSSR_RFS		BIT(6)
96 #define SSSR_ROR		BIT(7)
97 #define SSSR_TUR		BIT(21)
98 
99 /* SSPSP bits */
100 #define SSPSP_SCMODE(x)		DAI_INTEL_SSP_SET_BITS(1, 0, x)
101 #define SSPSP_SFRMP(x)		DAI_INTEL_SSP_SET_BIT(2, x)
102 #define SSPSP_ETDS		BIT(3)
103 #define SSPSP_STRTDLY(x)	DAI_INTEL_SSP_SET_BITS(6, 4, x)
104 #define SSPSP_DMYSTRT(x)	DAI_INTEL_SSP_SET_BITS(8, 7, x)
105 #define SSPSP_SFRMDLY(x)	DAI_INTEL_SSP_SET_BITS(15, 9, x)
106 #define SSPSP_SFRMWDTH(x)	DAI_INTEL_SSP_SET_BITS(21, 16, x)
107 #define SSPSP_DMYSTOP(x)	DAI_INTEL_SSP_SET_BITS(24, 23, x)
108 #define SSPSP_DMYSTOP_BITS	2
109 #define SSPSP_DMYSTOP_MASK	DAI_INTEL_SSP_MASK(SSPSP_DMYSTOP_BITS - 1, 0)
110 #define SSPSP_FSRT		BIT(25)
111 #define SSPSP_EDMYSTOP(x)	DAI_INTEL_SSP_SET_BITS(28, 26, x)
112 
113 #define SSPSP2			0x44
114 #define SSPSP2_FEP_MASK		0xff
115 
116 #define SSCR3			0x48
117 #define SSIOC			0x4C
118 #define SSP_REG_MAX		SSIOC
119 
120 /* SSTSA bits */
121 #define SSTSA_SSTSA(x)		DAI_INTEL_SSP_SET_BITS(7, 0, x)
122 #define SSTSA_GET(x)		((x) & DAI_INTEL_SSP_MASK(7, 0))
123 #define SSTSA_TXEN		BIT(8)
124 
125 /* SSRSA bits */
126 #define SSRSA_SSRSA(x)		DAI_INTEL_SSP_SET_BITS(7, 0, x)
127 #define SSRSA_GET(x)		((x) & DAI_INTEL_SSP_MASK(7, 0))
128 #define SSRSA_RXEN		BIT(8)
129 
130 /* SSCR3 bits */
131 #define SSCR3_FRM_MST_EN	BIT(0)
132 #define SSCR3_I2S_MODE_EN	BIT(1)
133 #define SSCR3_I2S_FRM_POL(x)	DAI_INTEL_SSP_SET_BIT(2, x)
134 #define SSCR3_I2S_TX_SS_FIX_EN	BIT(3)
135 #define SSCR3_I2S_RX_SS_FIX_EN	BIT(4)
136 #define SSCR3_I2S_TX_EN		BIT(9)
137 #define SSCR3_I2S_RX_EN		BIT(10)
138 #define SSCR3_CLK_EDGE_SEL	BIT(12)
139 #define SSCR3_STRETCH_TX	BIT(14)
140 #define SSCR3_STRETCH_RX	BIT(15)
141 #define SSCR3_MST_CLK_EN	BIT(16)
142 #define SSCR3_SYN_FIX_EN	BIT(17)
143 
144 /* SSCR4 bits */
145 #define SSCR4_TOT_FRM_PRD(x)	((x) << 7)
146 
147 /* SSCR5 bits */
148 #define SSCR5_FRM_ASRT_CLOCKS(x)	(((x) - 1) << 1)
149 #define SSCR5_FRM_POLARITY(x)	DAI_INTEL_SSP_SET_BIT(0, x)
150 
151 /* SFIFOTT bits */
152 #define SFIFOTT_TX(x)		((x) - 1)
153 #define SFIFOTT_RX(x)		(((x) - 1) << 16)
154 
155 /* SFIFOL bits */
156 #define SFIFOL_TFL(x)		((x) & 0xFFFF)
157 #define SFIFOL_RFL(x)		((x) >> 16)
158 
159 #define SSTSA_TSEN			BIT(8)
160 #define SSRSA_RSEN			BIT(8)
161 
162 #define SSCR3_TFL_MASK	DAI_INTEL_SSP_MASK(5, 0)
163 #define SSCR3_RFL_MASK	DAI_INTEL_SSP_MASK(13, 8)
164 #define SSCR3_TFL_VAL(scr3_val)	(((scr3_val) >> 0) & DAI_INTEL_SSP_MASK(5, 0))
165 #define SSCR3_RFL_VAL(scr3_val)	(((scr3_val) >> 8) & DAI_INTEL_SSP_MASK(5, 0))
166 #define SSCR3_TX(x)	DAI_INTEL_SSP_SET_BITS(21, 16, (x) - 1)
167 #define SSCR3_RX(x)	DAI_INTEL_SSP_SET_BITS(29, 24, (x) - 1)
168 
169 #define SSIOC_TXDPDEB	BIT(1)
170 #define SSIOC_SFCR		BIT(4)
171 #define SSIOC_SCOE		BIT(5)
172 
173 /* SSMIDyCS */
174 #define SSMIDyCS_RXEN			BIT(0)
175 #define SSMIDyCS_RSRE			BIT(1)
176 #define SSMIDyCS_RFL			DAI_INTEL_SSP_MASK(23, 16)
177 #define SSMIDyCS_RFL_VAL(rfl_val) (((rfl_val) >> 16) & DAI_INTEL_SSP_MASK(7, 0))
178 #define SSMIDyCS_RNE			BIT(26)
179 #define SSMIDyCS_RFS			BIT(27)
180 #define SSMIDyCS_ROR			BIT(28)
181 #define SSMIDyCS_PINT			BIT(29)
182 #define SSMIDyCS_TINT			BIT(30)
183 #define SSMIDyCS_EOC			BIT(31)
184 
185 /* SSMIDyTSA */
186 #define SSMIDyTSA_RTSA			DAI_INTEL_SSP_MASK(63, 0)
187 #define SSMIDyTSA_SRTSA(x)		DAI_INTEL_SSP_MASK(63, 0, x)
188 
189 /* SSMODyCS */
190 #define SSMODyCS_TXEN			BIT(0)
191 #define SSMODyCS_TSRE			BIT(1)
192 #define SSMODyCS_TFL			DAI_INTEL_SSP_MASK(23, 16)
193 #define SSMIDyCS_TFL_VAL(rfl_val) (((rfl_val) >> 16) & DAI_INTEL_SSP_MASK(7, 0))
194 #define SSMODyCS_TNF			BIT(26)
195 #define SSMODyCS_TFS			BIT(27)
196 #define SSMODyCS_TUR			BIT(28)
197 
198 /* SSMODyTSA */
199 #define SSMODyTSA_TTSA		DAI_INTEL_SSP_MASK(63, 0)
200 #define SSMODyTSA_STTSA(x)	DAI_INTEL_SSP_MASK(63, 0, x)
201 
202 /* For 8000 Hz rate one sample is transmitted within 125us */
203 #define DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE 125
204 
205 /* SSP flush retry counts maximum */
206 #define DAI_INTEL_SSP_RX_FLUSH_RETRY_MAX	16
207 
208 #define SSP_CLK_MCLK_ES_REQ	BIT(0)
209 #define SSP_CLK_MCLK_ACTIVE	BIT(1)
210 #define SSP_CLK_BCLK_ES_REQ	BIT(2)
211 #define SSP_CLK_BCLK_ACTIVE	BIT(3)
212 
213 #define I2SLCTL_OFFSET		0x04
214 
215 #define I2SLCTL_SPA(x)		BIT(0 + x)
216 #define I2SLCTL_CPA(x)		BIT(8 + x)
217 
218 #define I2CLCTL_MLCS(x)		DAI_INTEL_SSP_SET_BITS(29, 27, x)
219 #define SHIM_CLKCTL		0x78
220 #define SHIM_CLKCTL_I2SFDCGB(x)		BIT(20 + x)
221 #define SHIM_CLKCTL_I2SEFDCGB(x)	BIT(18 + x)
222 
223 #ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
224 /** \brief Offset of MCLK Divider Control Register. */
225 #define MN_MDIVCTRL 0x100
226 
227 /** \brief Offset of MCLK Divider x Ratio Register. */
228 #define MN_MDIVR(x) (0x180 + (x) * 0x4)
229 #else
230 #define MN_MDIVCTRL 0x0
231 #define MN_MDIVR(x) (0x80 + (x) * 0x4)
232 #endif
233 
234 /** \brief Enables the output of MCLK Divider. */
235 #define MN_MDIVCTRL_M_DIV_ENABLE(x) BIT(x)
236 
237 /** \brief Bits for setting MCLK source clock. */
238 #define MCDSS(x)	DAI_INTEL_SSP_SET_BITS(17, 16, x)
239 
240 /** \brief Offset of BCLK x M/N Divider M Value Register. */
241 #define MN_MDIV_M_VAL(x) (0x100 + (x) * 0x8 + 0x0)
242 
243 /** \brief Offset of BCLK x M/N Divider N Value Register. */
244 #define MN_MDIV_N_VAL(x) (0x100 + (x) * 0x8 + 0x4)
245 
246 /** \brief Bits for setting M/N source clock. */
247 #define MNDSS(x)	DAI_INTEL_SSP_SET_BITS(21, 20, x)
248 
249 /** \brief Mask for clearing mclk and bclk source in MN_MDIVCTRL */
250 #define MN_SOURCE_CLKS_MASK 0x3
251 
252 #endif /* __INTEL_DAI_DRIVER_SSP_REGSV1_H__ */
253