1/*
2 * Some or all of this work - Copyright (c) 2006 - 2021, Intel Corp.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 * Neither the name of Intel Corporation nor the names of its contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/*
30 * The Load operator tests auxiliary SSDT,
31 * specifies the _REG Methods for globally and
32 * dynamically decleared OpRegions.
33 */
34
35DefinitionBlock(
36	"ssdt2.aml",   // Output filename
37	"SSDT",     // Signature
38	0x02,       // DSDT Revision
39	"Intel",    // OEMID
40	"Many",     // TABLE ID
41	0x00000001  // OEM Revision
42	) {
43
44	Device (AUXD) {
45
46		OperationRegion (OPR0, 0x80, 0x1000000, 0x4)
47
48		Field (OPR0, DWordAcc, NoLock, Preserve) {
49			RF00,   32}
50
51		Name (REGC, 0xFFFFFFFF)
52		Name (REGP, 0)
53
54		Name (REGD, 0xFFFFFFFF)
55		Name (REGR, 0)
56
57		Method(_REG, 2)
58		{
59			Store("\\AUXD._REG:", Debug)
60			Store(arg0, Debug)
61			Store(arg1, Debug)
62
63			if (LEqual(arg0, 0x80)) {
64				Store(REGC, REGP)
65				Store(arg1, REGC)
66			}
67		}
68
69		Method(M000)
70		{
71			Method(_REG, 2)
72			{
73				Store("\\AUXD.M000._REG:", Debug)
74				Store(arg0, Debug)
75				Store(arg1, Debug)
76
77				if (LEqual(arg0, 0x80)) {
78					Store(REGD, REGR)
79					Store(arg1, REGD)
80				}
81			}
82
83			OperationRegion (OPR1, 0x80, 0x1000010, 0x4)
84
85			Field (OPR1, DWordAcc, NoLock, Preserve) {
86				RF01,   32}
87
88			Store("\\AUXD.M000:", Debug)
89			Store(RF01, Debug)
90			Store(REGR, Debug)
91		}
92	}
93}
94