1 /*
2 * Copyright (c) 2001-2019, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7
8 /************* Include Files *************************************************/
9 #include "cc_pal_types.h"
10 #include "cc_pal_mutex.h"
11 #include "cc_pal_interrupt_ctrl_plat.h"
12 #include "cc_regs.h"
13 #include "dx_host.h"
14 #include "cc_hal.h"
15 /************************ Defines ********************************************/
16
17 /************************ Enums **********************************************/
18
19 /************************ Typedefs *******************************************/
20
21 /************************ Global Data ****************************************/
22
23 /************************ Private Functions **********************************/
24
25 /************************ Public Functions ***********************************/
26 /**
27 * @brief
28 *
29 * @param[in]
30 *
31 * @param[out]
32 *
33 * @return - CC_SUCCESS for success, CC_FAIL for failure.
34 */
CC_PalInitIrq(void)35 CCError_t CC_PalInitIrq(void)
36 {
37 return CC_SUCCESS;
38 }
39
40 /**
41 * @brief This function removes the interrupt handler for
42 * cryptocell interrupts.
43 *
44 */
CC_PalFinishIrq(void)45 void CC_PalFinishIrq(void)
46 {
47 }
48
49
50 /*!
51 * Busy wait upon Interrupt Request Register (IRR) signals.
52 * This function notifys for any ARM CryptoCell interrupt, it is the caller responsiblity
53 * to verify and prompt the expected case interupt source.
54 *
55 * @param[in] data - input data for future use
56 * \return CCError_t - CC_OK upon success
57 */
CC_PalWaitInterrupt(uint32_t data)58 CCError_t CC_PalWaitInterrupt( uint32_t data){
59 uint32_t irr = 0;
60 CCError_t error = CC_OK;
61
62 /* busy wait upon IRR signal */
63 do {
64 irr = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IRR));
65 /* check APB bus error from HOST */
66 if( CC_REG_FLD_GET(0, HOST_IRR, AHB_ERR_INT, irr) == CC_TRUE){
67 error = CC_FAIL;
68 /*set data for clearing bus error*/
69 CC_REG_FLD_SET(HOST_RGF, HOST_ICR, AXI_ERR_CLEAR, data , 1);
70 break;
71 }
72 } while (!(irr & data));
73
74 /* clear interrupt */
75 CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_ICR), data); // IRR and ICR bit map is the same use data to clear interrupt in ICR
76
77 return error;
78 }
79
