1 /** 2 * @file spixfc_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SPIXFC_REVA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _SPIXFC_REVA_REGS_H_ 27 #define _SPIXFC_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup spixfc_reva 65 * @defgroup spixfc_reva_registers SPIXFC_REVA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the SPIXFC_REVA Peripheral Module. 67 * @details SPI XiP Flash Configuration Controller 68 */ 69 70 /** 71 * @ingroup spixfc_reva_registers 72 * Structure type to access the SPIXFC_REVA Registers. 73 */ 74 typedef struct { 75 __IO uint32_t cfg; /**< <tt>\b 0x00:</tt> SPIXFC_REVA CFG Register */ 76 __IO uint32_t ss_pol; /**< <tt>\b 0x04:</tt> SPIXFC_REVA SS_POL Register */ 77 __IO uint32_t gen_ctrl; /**< <tt>\b 0x08:</tt> SPIXFC_REVA GEN_CTRL Register */ 78 __IO uint32_t fifo_ctrl; /**< <tt>\b 0x0C:</tt> SPIXFC_REVA FIFO_CTRL Register */ 79 __IO uint32_t sp_ctrl; /**< <tt>\b 0x10:</tt> SPIXFC_REVA SP_CTRL Register */ 80 __IO uint32_t int_fl; /**< <tt>\b 0x14:</tt> SPIXFC_REVA INT_FL Register */ 81 __IO uint32_t int_en; /**< <tt>\b 0x18:</tt> SPIXFC_REVA INT_EN Register */ 82 } mxc_spixfc_reva_regs_t; 83 84 /* Register offsets for module SPIXFC_REVA */ 85 /** 86 * @ingroup spixfc_reva_registers 87 * @defgroup SPIXFC_REVA_Register_Offsets Register Offsets 88 * @brief SPIXFC_REVA Peripheral Register Offsets from the SPIXFC_REVA Base Peripheral Address. 89 * @{ 90 */ 91 #define MXC_R_SPIXFC_REVA_CFG ((uint32_t)0x00000000UL) /**< Offset from SPIXFC_REVA Base Address: <tt> 0x0000</tt> */ 92 #define MXC_R_SPIXFC_REVA_SS_POL ((uint32_t)0x00000004UL) /**< Offset from SPIXFC_REVA Base Address: <tt> 0x0004</tt> */ 93 #define MXC_R_SPIXFC_REVA_GEN_CTRL ((uint32_t)0x00000008UL) /**< Offset from SPIXFC_REVA Base Address: <tt> 0x0008</tt> */ 94 #define MXC_R_SPIXFC_REVA_FIFO_CTRL ((uint32_t)0x0000000CUL) /**< Offset from SPIXFC_REVA Base Address: <tt> 0x000C</tt> */ 95 #define MXC_R_SPIXFC_REVA_SP_CTRL ((uint32_t)0x00000010UL) /**< Offset from SPIXFC_REVA Base Address: <tt> 0x0010</tt> */ 96 #define MXC_R_SPIXFC_REVA_INT_FL ((uint32_t)0x00000014UL) /**< Offset from SPIXFC_REVA Base Address: <tt> 0x0014</tt> */ 97 #define MXC_R_SPIXFC_REVA_INT_EN ((uint32_t)0x00000018UL) /**< Offset from SPIXFC_REVA Base Address: <tt> 0x0018</tt> */ 98 /**@} end of group spixfc_reva_registers */ 99 100 /** 101 * @ingroup spixfc_reva_registers 102 * @defgroup SPIXFC_REVA_CFG SPIXFC_REVA_CFG 103 * @brief Configuration Register. 104 * @{ 105 */ 106 #define MXC_F_SPIXFC_REVA_CFG_SSEL_POS 0 /**< CFG_SSEL Position */ 107 #define MXC_F_SPIXFC_REVA_CFG_SSEL ((uint32_t)(0x7UL << MXC_F_SPIXFC_REVA_CFG_SSEL_POS)) /**< CFG_SSEL Mask */ 108 #define MXC_V_SPIXFC_REVA_CFG_SSEL_SLAVE_0 ((uint32_t)0x0UL) /**< CFG_SSEL_SLAVE_0 Value */ 109 #define MXC_S_SPIXFC_REVA_CFG_SSEL_SLAVE_0 (MXC_V_SPIXFC_REVA_CFG_SSEL_SLAVE_0 << MXC_F_SPIXFC_REVA_CFG_SSEL_POS) /**< CFG_SSEL_SLAVE_0 Setting */ 110 #define MXC_V_SPIXFC_REVA_CFG_SSEL_SLAVE_1 ((uint32_t)0x1UL) /**< CFG_SSEL_SLAVE_1 Value */ 111 #define MXC_S_SPIXFC_REVA_CFG_SSEL_SLAVE_1 (MXC_V_SPIXFC_REVA_CFG_SSEL_SLAVE_1 << MXC_F_SPIXFC_REVA_CFG_SSEL_POS) /**< CFG_SSEL_SLAVE_1 Setting */ 112 113 #define MXC_F_SPIXFC_REVA_CFG_MODE_POS 4 /**< CFG_MODE Position */ 114 #define MXC_F_SPIXFC_REVA_CFG_MODE ((uint32_t)(0x3UL << MXC_F_SPIXFC_REVA_CFG_MODE_POS)) /**< CFG_MODE Mask */ 115 #define MXC_V_SPIXFC_REVA_CFG_MODE_SPIX_MODE_0 ((uint32_t)0x0UL) /**< CFG_MODE_SPIX_MODE_0 Value */ 116 #define MXC_S_SPIXFC_REVA_CFG_MODE_SPIX_MODE_0 (MXC_V_SPIXFC_REVA_CFG_MODE_SPIX_MODE_0 << MXC_F_SPIXFC_REVA_CFG_MODE_POS) /**< CFG_MODE_SPIX_MODE_0 Setting */ 117 #define MXC_V_SPIXFC_REVA_CFG_MODE_SPIX_MODE_3 ((uint32_t)0x3UL) /**< CFG_MODE_SPIX_MODE_3 Value */ 118 #define MXC_S_SPIXFC_REVA_CFG_MODE_SPIX_MODE_3 (MXC_V_SPIXFC_REVA_CFG_MODE_SPIX_MODE_3 << MXC_F_SPIXFC_REVA_CFG_MODE_POS) /**< CFG_MODE_SPIX_MODE_3 Setting */ 119 120 #define MXC_F_SPIXFC_REVA_CFG_PAGE_SIZE_POS 6 /**< CFG_PAGE_SIZE Position */ 121 #define MXC_F_SPIXFC_REVA_CFG_PAGE_SIZE ((uint32_t)(0x3UL << MXC_F_SPIXFC_REVA_CFG_PAGE_SIZE_POS)) /**< CFG_PAGE_SIZE Mask */ 122 #define MXC_V_SPIXFC_REVA_CFG_PAGE_SIZE_4_BYTES ((uint32_t)0x0UL) /**< CFG_PAGE_SIZE_4_BYTES Value */ 123 #define MXC_S_SPIXFC_REVA_CFG_PAGE_SIZE_4_BYTES (MXC_V_SPIXFC_REVA_CFG_PAGE_SIZE_4_BYTES << MXC_F_SPIXFC_REVA_CFG_PAGE_SIZE_POS) /**< CFG_PAGE_SIZE_4_BYTES Setting */ 124 #define MXC_V_SPIXFC_REVA_CFG_PAGE_SIZE_8_BYTES ((uint32_t)0x1UL) /**< CFG_PAGE_SIZE_8_BYTES Value */ 125 #define MXC_S_SPIXFC_REVA_CFG_PAGE_SIZE_8_BYTES (MXC_V_SPIXFC_REVA_CFG_PAGE_SIZE_8_BYTES << MXC_F_SPIXFC_REVA_CFG_PAGE_SIZE_POS) /**< CFG_PAGE_SIZE_8_BYTES Setting */ 126 #define MXC_V_SPIXFC_REVA_CFG_PAGE_SIZE_16_BYTES ((uint32_t)0x2UL) /**< CFG_PAGE_SIZE_16_BYTES Value */ 127 #define MXC_S_SPIXFC_REVA_CFG_PAGE_SIZE_16_BYTES (MXC_V_SPIXFC_REVA_CFG_PAGE_SIZE_16_BYTES << MXC_F_SPIXFC_REVA_CFG_PAGE_SIZE_POS) /**< CFG_PAGE_SIZE_16_BYTES Setting */ 128 #define MXC_V_SPIXFC_REVA_CFG_PAGE_SIZE_32_BYTES ((uint32_t)0x3UL) /**< CFG_PAGE_SIZE_32_BYTES Value */ 129 #define MXC_S_SPIXFC_REVA_CFG_PAGE_SIZE_32_BYTES (MXC_V_SPIXFC_REVA_CFG_PAGE_SIZE_32_BYTES << MXC_F_SPIXFC_REVA_CFG_PAGE_SIZE_POS) /**< CFG_PAGE_SIZE_32_BYTES Setting */ 130 131 #define MXC_F_SPIXFC_REVA_CFG_HI_CLK_POS 8 /**< CFG_HI_CLK Position */ 132 #define MXC_F_SPIXFC_REVA_CFG_HI_CLK ((uint32_t)(0xFUL << MXC_F_SPIXFC_REVA_CFG_HI_CLK_POS)) /**< CFG_HI_CLK Mask */ 133 #define MXC_V_SPIXFC_REVA_CFG_HI_CLK_16_SCLK ((uint32_t)0x0UL) /**< CFG_HI_CLK_16_SCLK Value */ 134 #define MXC_S_SPIXFC_REVA_CFG_HI_CLK_16_SCLK (MXC_V_SPIXFC_REVA_CFG_HI_CLK_16_SCLK << MXC_F_SPIXFC_REVA_CFG_HI_CLK_POS) /**< CFG_HI_CLK_16_SCLK Setting */ 135 136 #define MXC_F_SPIXFC_REVA_CFG_LO_CLK_POS 12 /**< CFG_LO_CLK Position */ 137 #define MXC_F_SPIXFC_REVA_CFG_LO_CLK ((uint32_t)(0xFUL << MXC_F_SPIXFC_REVA_CFG_LO_CLK_POS)) /**< CFG_LO_CLK Mask */ 138 #define MXC_V_SPIXFC_REVA_CFG_LO_CLK_16_SCLK ((uint32_t)0x0UL) /**< CFG_LO_CLK_16_SCLK Value */ 139 #define MXC_S_SPIXFC_REVA_CFG_LO_CLK_16_SCLK (MXC_V_SPIXFC_REVA_CFG_LO_CLK_16_SCLK << MXC_F_SPIXFC_REVA_CFG_LO_CLK_POS) /**< CFG_LO_CLK_16_SCLK Setting */ 140 141 #define MXC_F_SPIXFC_REVA_CFG_SSACT_POS 16 /**< CFG_SSACT Position */ 142 #define MXC_F_SPIXFC_REVA_CFG_SSACT ((uint32_t)(0x3UL << MXC_F_SPIXFC_REVA_CFG_SSACT_POS)) /**< CFG_SSACT Mask */ 143 #define MXC_V_SPIXFC_REVA_CFG_SSACT_0_CLKS ((uint32_t)0x0UL) /**< CFG_SSACT_0_CLKS Value */ 144 #define MXC_S_SPIXFC_REVA_CFG_SSACT_0_CLKS (MXC_V_SPIXFC_REVA_CFG_SSACT_0_CLKS << MXC_F_SPIXFC_REVA_CFG_SSACT_POS) /**< CFG_SSACT_0_CLKS Setting */ 145 #define MXC_V_SPIXFC_REVA_CFG_SSACT_2_CLKS ((uint32_t)0x1UL) /**< CFG_SSACT_2_CLKS Value */ 146 #define MXC_S_SPIXFC_REVA_CFG_SSACT_2_CLKS (MXC_V_SPIXFC_REVA_CFG_SSACT_2_CLKS << MXC_F_SPIXFC_REVA_CFG_SSACT_POS) /**< CFG_SSACT_2_CLKS Setting */ 147 #define MXC_V_SPIXFC_REVA_CFG_SSACT_4_CLKS ((uint32_t)0x2UL) /**< CFG_SSACT_4_CLKS Value */ 148 #define MXC_S_SPIXFC_REVA_CFG_SSACT_4_CLKS (MXC_V_SPIXFC_REVA_CFG_SSACT_4_CLKS << MXC_F_SPIXFC_REVA_CFG_SSACT_POS) /**< CFG_SSACT_4_CLKS Setting */ 149 #define MXC_V_SPIXFC_REVA_CFG_SSACT_8_CLKS ((uint32_t)0x3UL) /**< CFG_SSACT_8_CLKS Value */ 150 #define MXC_S_SPIXFC_REVA_CFG_SSACT_8_CLKS (MXC_V_SPIXFC_REVA_CFG_SSACT_8_CLKS << MXC_F_SPIXFC_REVA_CFG_SSACT_POS) /**< CFG_SSACT_8_CLKS Setting */ 151 152 #define MXC_F_SPIXFC_REVA_CFG_SSIACT_POS 18 /**< CFG_SSIACT Position */ 153 #define MXC_F_SPIXFC_REVA_CFG_SSIACT ((uint32_t)(0x3UL << MXC_F_SPIXFC_REVA_CFG_SSIACT_POS)) /**< CFG_SSIACT Mask */ 154 #define MXC_V_SPIXFC_REVA_CFG_SSIACT_4_CLKS ((uint32_t)0x0UL) /**< CFG_SSIACT_4_CLKS Value */ 155 #define MXC_S_SPIXFC_REVA_CFG_SSIACT_4_CLKS (MXC_V_SPIXFC_REVA_CFG_SSIACT_4_CLKS << MXC_F_SPIXFC_REVA_CFG_SSIACT_POS) /**< CFG_SSIACT_4_CLKS Setting */ 156 #define MXC_V_SPIXFC_REVA_CFG_SSIACT_6_CLKS ((uint32_t)0x1UL) /**< CFG_SSIACT_6_CLKS Value */ 157 #define MXC_S_SPIXFC_REVA_CFG_SSIACT_6_CLKS (MXC_V_SPIXFC_REVA_CFG_SSIACT_6_CLKS << MXC_F_SPIXFC_REVA_CFG_SSIACT_POS) /**< CFG_SSIACT_6_CLKS Setting */ 158 #define MXC_V_SPIXFC_REVA_CFG_SSIACT_8_CLKS ((uint32_t)0x2UL) /**< CFG_SSIACT_8_CLKS Value */ 159 #define MXC_S_SPIXFC_REVA_CFG_SSIACT_8_CLKS (MXC_V_SPIXFC_REVA_CFG_SSIACT_8_CLKS << MXC_F_SPIXFC_REVA_CFG_SSIACT_POS) /**< CFG_SSIACT_8_CLKS Setting */ 160 #define MXC_V_SPIXFC_REVA_CFG_SSIACT_12_CLKS ((uint32_t)0x3UL) /**< CFG_SSIACT_12_CLKS Value */ 161 #define MXC_S_SPIXFC_REVA_CFG_SSIACT_12_CLKS (MXC_V_SPIXFC_REVA_CFG_SSIACT_12_CLKS << MXC_F_SPIXFC_REVA_CFG_SSIACT_POS) /**< CFG_SSIACT_12_CLKS Setting */ 162 163 #define MXC_F_SPIXFC_REVA_CFG_IOSMPL_POS 20 /**< CFG_IOSMPL Position */ 164 #define MXC_F_SPIXFC_REVA_CFG_IOSMPL ((uint32_t)(0xFUL << MXC_F_SPIXFC_REVA_CFG_IOSMPL_POS)) /**< CFG_IOSMPL Mask */ 165 166 /**@} end of group SPIXFC_REVA_CFG_Register */ 167 168 /** 169 * @ingroup spixfc_reva_registers 170 * @defgroup SPIXFC_REVA_SS_POL SPIXFC_REVA_SS_POL 171 * @brief SPIX Controller Slave Select Polarity Register. 172 * @{ 173 */ 174 #define MXC_F_SPIXFC_REVA_SS_POL_SS_POLARITY_POS 0 /**< SS_POL_SS_POLARITY Position */ 175 #define MXC_F_SPIXFC_REVA_SS_POL_SS_POLARITY ((uint32_t)(0x1UL << MXC_F_SPIXFC_REVA_SS_POL_SS_POLARITY_POS)) /**< SS_POL_SS_POLARITY Mask */ 176 177 /**@} end of group SPIXFC_REVA_SS_POL_Register */ 178 179 /** 180 * @ingroup spixfc_reva_registers 181 * @defgroup SPIXFC_REVA_GEN_CTRL SPIXFC_REVA_GEN_CTRL 182 * @brief SPIX Controller General Controller Register. 183 * @{ 184 */ 185 #define MXC_F_SPIXFC_REVA_GEN_CTRL_ENABLE_POS 0 /**< GEN_CTRL_ENABLE Position */ 186 #define MXC_F_SPIXFC_REVA_GEN_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_SPIXFC_REVA_GEN_CTRL_ENABLE_POS)) /**< GEN_CTRL_ENABLE Mask */ 187 188 #define MXC_F_SPIXFC_REVA_GEN_CTRL_TX_FIFO_EN_POS 1 /**< GEN_CTRL_TX_FIFO_EN Position */ 189 #define MXC_F_SPIXFC_REVA_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPIXFC_REVA_GEN_CTRL_TX_FIFO_EN_POS)) /**< GEN_CTRL_TX_FIFO_EN Mask */ 190 191 #define MXC_F_SPIXFC_REVA_GEN_CTRL_RX_FIFO_EN_POS 2 /**< GEN_CTRL_RX_FIFO_EN Position */ 192 #define MXC_F_SPIXFC_REVA_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPIXFC_REVA_GEN_CTRL_RX_FIFO_EN_POS)) /**< GEN_CTRL_RX_FIFO_EN Mask */ 193 194 #define MXC_F_SPIXFC_REVA_GEN_CTRL_BBMODE_POS 3 /**< GEN_CTRL_BBMODE Position */ 195 #define MXC_F_SPIXFC_REVA_GEN_CTRL_BBMODE ((uint32_t)(0x1UL << MXC_F_SPIXFC_REVA_GEN_CTRL_BBMODE_POS)) /**< GEN_CTRL_BBMODE Mask */ 196 197 #define MXC_F_SPIXFC_REVA_GEN_CTRL_SSDR_POS 4 /**< GEN_CTRL_SSDR Position */ 198 #define MXC_F_SPIXFC_REVA_GEN_CTRL_SSDR ((uint32_t)(0x1UL << MXC_F_SPIXFC_REVA_GEN_CTRL_SSDR_POS)) /**< GEN_CTRL_SSDR Mask */ 199 200 #define MXC_F_SPIXFC_REVA_GEN_CTRL_SCLK_DR_POS 6 /**< GEN_CTRL_SCLK_DR Position */ 201 #define MXC_F_SPIXFC_REVA_GEN_CTRL_SCLK_DR ((uint32_t)(0x1UL << MXC_F_SPIXFC_REVA_GEN_CTRL_SCLK_DR_POS)) /**< GEN_CTRL_SCLK_DR Mask */ 202 203 #define MXC_F_SPIXFC_REVA_GEN_CTRL_SDIO_DATA_IN_POS 8 /**< GEN_CTRL_SDIO_DATA_IN Position */ 204 #define MXC_F_SPIXFC_REVA_GEN_CTRL_SDIO_DATA_IN ((uint32_t)(0xFUL << MXC_F_SPIXFC_REVA_GEN_CTRL_SDIO_DATA_IN_POS)) /**< GEN_CTRL_SDIO_DATA_IN Mask */ 205 #define MXC_V_SPIXFC_REVA_GEN_CTRL_SDIO_DATA_IN_SDIO0 ((uint32_t)0x0UL) /**< GEN_CTRL_SDIO_DATA_IN_SDIO0 Value */ 206 #define MXC_S_SPIXFC_REVA_GEN_CTRL_SDIO_DATA_IN_SDIO0 (MXC_V_SPIXFC_REVA_GEN_CTRL_SDIO_DATA_IN_SDIO0 << MXC_F_SPIXFC_REVA_GEN_CTRL_SDIO_DATA_IN_POS) /**< GEN_CTRL_SDIO_DATA_IN_SDIO0 Setting */ 207 #define MXC_V_SPIXFC_REVA_GEN_CTRL_SDIO_DATA_IN_SDIO1 ((uint32_t)0x1UL) /**< GEN_CTRL_SDIO_DATA_IN_SDIO1 Value */ 208 #define MXC_S_SPIXFC_REVA_GEN_CTRL_SDIO_DATA_IN_SDIO1 (MXC_V_SPIXFC_REVA_GEN_CTRL_SDIO_DATA_IN_SDIO1 << MXC_F_SPIXFC_REVA_GEN_CTRL_SDIO_DATA_IN_POS) /**< GEN_CTRL_SDIO_DATA_IN_SDIO1 Setting */ 209 #define MXC_V_SPIXFC_REVA_GEN_CTRL_SDIO_DATA_IN_SDIO2 ((uint32_t)0x2UL) /**< GEN_CTRL_SDIO_DATA_IN_SDIO2 Value */ 210 #define MXC_S_SPIXFC_REVA_GEN_CTRL_SDIO_DATA_IN_SDIO2 (MXC_V_SPIXFC_REVA_GEN_CTRL_SDIO_DATA_IN_SDIO2 << MXC_F_SPIXFC_REVA_GEN_CTRL_SDIO_DATA_IN_POS) /**< GEN_CTRL_SDIO_DATA_IN_SDIO2 Setting */ 211 #define MXC_V_SPIXFC_REVA_GEN_CTRL_SDIO_DATA_IN_SDIO3 ((uint32_t)0x3UL) /**< GEN_CTRL_SDIO_DATA_IN_SDIO3 Value */ 212 #define MXC_S_SPIXFC_REVA_GEN_CTRL_SDIO_DATA_IN_SDIO3 (MXC_V_SPIXFC_REVA_GEN_CTRL_SDIO_DATA_IN_SDIO3 << MXC_F_SPIXFC_REVA_GEN_CTRL_SDIO_DATA_IN_POS) /**< GEN_CTRL_SDIO_DATA_IN_SDIO3 Setting */ 213 214 #define MXC_F_SPIXFC_REVA_GEN_CTRL_BB_DATA_POS 12 /**< GEN_CTRL_BB_DATA Position */ 215 #define MXC_F_SPIXFC_REVA_GEN_CTRL_BB_DATA ((uint32_t)(0xFUL << MXC_F_SPIXFC_REVA_GEN_CTRL_BB_DATA_POS)) /**< GEN_CTRL_BB_DATA Mask */ 216 #define MXC_V_SPIXFC_REVA_GEN_CTRL_BB_DATA_SDIO0 ((uint32_t)0x0UL) /**< GEN_CTRL_BB_DATA_SDIO0 Value */ 217 #define MXC_S_SPIXFC_REVA_GEN_CTRL_BB_DATA_SDIO0 (MXC_V_SPIXFC_REVA_GEN_CTRL_BB_DATA_SDIO0 << MXC_F_SPIXFC_REVA_GEN_CTRL_BB_DATA_POS) /**< GEN_CTRL_BB_DATA_SDIO0 Setting */ 218 #define MXC_V_SPIXFC_REVA_GEN_CTRL_BB_DATA_SDIO1 ((uint32_t)0x1UL) /**< GEN_CTRL_BB_DATA_SDIO1 Value */ 219 #define MXC_S_SPIXFC_REVA_GEN_CTRL_BB_DATA_SDIO1 (MXC_V_SPIXFC_REVA_GEN_CTRL_BB_DATA_SDIO1 << MXC_F_SPIXFC_REVA_GEN_CTRL_BB_DATA_POS) /**< GEN_CTRL_BB_DATA_SDIO1 Setting */ 220 #define MXC_V_SPIXFC_REVA_GEN_CTRL_BB_DATA_SDIO2 ((uint32_t)0x2UL) /**< GEN_CTRL_BB_DATA_SDIO2 Value */ 221 #define MXC_S_SPIXFC_REVA_GEN_CTRL_BB_DATA_SDIO2 (MXC_V_SPIXFC_REVA_GEN_CTRL_BB_DATA_SDIO2 << MXC_F_SPIXFC_REVA_GEN_CTRL_BB_DATA_POS) /**< GEN_CTRL_BB_DATA_SDIO2 Setting */ 222 #define MXC_V_SPIXFC_REVA_GEN_CTRL_BB_DATA_SDIO3 ((uint32_t)0x3UL) /**< GEN_CTRL_BB_DATA_SDIO3 Value */ 223 #define MXC_S_SPIXFC_REVA_GEN_CTRL_BB_DATA_SDIO3 (MXC_V_SPIXFC_REVA_GEN_CTRL_BB_DATA_SDIO3 << MXC_F_SPIXFC_REVA_GEN_CTRL_BB_DATA_POS) /**< GEN_CTRL_BB_DATA_SDIO3 Setting */ 224 225 #define MXC_F_SPIXFC_REVA_GEN_CTRL_BB_DATA_OUT_EN_POS 16 /**< GEN_CTRL_BB_DATA_OUT_EN Position */ 226 #define MXC_F_SPIXFC_REVA_GEN_CTRL_BB_DATA_OUT_EN ((uint32_t)(0xFUL << MXC_F_SPIXFC_REVA_GEN_CTRL_BB_DATA_OUT_EN_POS)) /**< GEN_CTRL_BB_DATA_OUT_EN Mask */ 227 #define MXC_V_SPIXFC_REVA_GEN_CTRL_BB_DATA_OUT_EN_SDIO0 ((uint32_t)0x0UL) /**< GEN_CTRL_BB_DATA_OUT_EN_SDIO0 Value */ 228 #define MXC_S_SPIXFC_REVA_GEN_CTRL_BB_DATA_OUT_EN_SDIO0 (MXC_V_SPIXFC_REVA_GEN_CTRL_BB_DATA_OUT_EN_SDIO0 << MXC_F_SPIXFC_REVA_GEN_CTRL_BB_DATA_OUT_EN_POS) /**< GEN_CTRL_BB_DATA_OUT_EN_SDIO0 Setting */ 229 #define MXC_V_SPIXFC_REVA_GEN_CTRL_BB_DATA_OUT_EN_SDIO1 ((uint32_t)0x1UL) /**< GEN_CTRL_BB_DATA_OUT_EN_SDIO1 Value */ 230 #define MXC_S_SPIXFC_REVA_GEN_CTRL_BB_DATA_OUT_EN_SDIO1 (MXC_V_SPIXFC_REVA_GEN_CTRL_BB_DATA_OUT_EN_SDIO1 << MXC_F_SPIXFC_REVA_GEN_CTRL_BB_DATA_OUT_EN_POS) /**< GEN_CTRL_BB_DATA_OUT_EN_SDIO1 Setting */ 231 #define MXC_V_SPIXFC_REVA_GEN_CTRL_BB_DATA_OUT_EN_SDIO2 ((uint32_t)0x2UL) /**< GEN_CTRL_BB_DATA_OUT_EN_SDIO2 Value */ 232 #define MXC_S_SPIXFC_REVA_GEN_CTRL_BB_DATA_OUT_EN_SDIO2 (MXC_V_SPIXFC_REVA_GEN_CTRL_BB_DATA_OUT_EN_SDIO2 << MXC_F_SPIXFC_REVA_GEN_CTRL_BB_DATA_OUT_EN_POS) /**< GEN_CTRL_BB_DATA_OUT_EN_SDIO2 Setting */ 233 #define MXC_V_SPIXFC_REVA_GEN_CTRL_BB_DATA_OUT_EN_SDIO3 ((uint32_t)0x3UL) /**< GEN_CTRL_BB_DATA_OUT_EN_SDIO3 Value */ 234 #define MXC_S_SPIXFC_REVA_GEN_CTRL_BB_DATA_OUT_EN_SDIO3 (MXC_V_SPIXFC_REVA_GEN_CTRL_BB_DATA_OUT_EN_SDIO3 << MXC_F_SPIXFC_REVA_GEN_CTRL_BB_DATA_OUT_EN_POS) /**< GEN_CTRL_BB_DATA_OUT_EN_SDIO3 Setting */ 235 236 #define MXC_F_SPIXFC_REVA_GEN_CTRL_SIMPLE_POS 20 /**< GEN_CTRL_SIMPLE Position */ 237 #define MXC_F_SPIXFC_REVA_GEN_CTRL_SIMPLE ((uint32_t)(0x1UL << MXC_F_SPIXFC_REVA_GEN_CTRL_SIMPLE_POS)) /**< GEN_CTRL_SIMPLE Mask */ 238 239 #define MXC_F_SPIXFC_REVA_GEN_CTRL_SIMPLE_RX_POS 21 /**< GEN_CTRL_SIMPLE_RX Position */ 240 #define MXC_F_SPIXFC_REVA_GEN_CTRL_SIMPLE_RX ((uint32_t)(0x1UL << MXC_F_SPIXFC_REVA_GEN_CTRL_SIMPLE_RX_POS)) /**< GEN_CTRL_SIMPLE_RX Mask */ 241 242 #define MXC_F_SPIXFC_REVA_GEN_CTRL_SIMPLE_SS_POS 22 /**< GEN_CTRL_SIMPLE_SS Position */ 243 #define MXC_F_SPIXFC_REVA_GEN_CTRL_SIMPLE_SS ((uint32_t)(0x1UL << MXC_F_SPIXFC_REVA_GEN_CTRL_SIMPLE_SS_POS)) /**< GEN_CTRL_SIMPLE_SS Mask */ 244 245 #define MXC_F_SPIXFC_REVA_GEN_CTRL_SCLK_FB_POS 24 /**< GEN_CTRL_SCLK_FB Position */ 246 #define MXC_F_SPIXFC_REVA_GEN_CTRL_SCLK_FB ((uint32_t)(0x1UL << MXC_F_SPIXFC_REVA_GEN_CTRL_SCLK_FB_POS)) /**< GEN_CTRL_SCLK_FB Mask */ 247 248 #define MXC_F_SPIXFC_REVA_GEN_CTRL_SCLK_FB_INVERT_POS 25 /**< GEN_CTRL_SCLK_FB_INVERT Position */ 249 #define MXC_F_SPIXFC_REVA_GEN_CTRL_SCLK_FB_INVERT ((uint32_t)(0x1UL << MXC_F_SPIXFC_REVA_GEN_CTRL_SCLK_FB_INVERT_POS)) /**< GEN_CTRL_SCLK_FB_INVERT Mask */ 250 251 /**@} end of group SPIXFC_REVA_GEN_CTRL_Register */ 252 253 /** 254 * @ingroup spixfc_reva_registers 255 * @defgroup SPIXFC_REVA_FIFO_CTRL SPIXFC_REVA_FIFO_CTRL 256 * @brief SPIX Controller FIFO Control and Status Register. 257 * @{ 258 */ 259 #define MXC_F_SPIXFC_REVA_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0 /**< FIFO_CTRL_TX_FIFO_AE_LVL Position */ 260 #define MXC_F_SPIXFC_REVA_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0xFUL << MXC_F_SPIXFC_REVA_FIFO_CTRL_TX_FIFO_AE_LVL_POS)) /**< FIFO_CTRL_TX_FIFO_AE_LVL Mask */ 261 262 #define MXC_F_SPIXFC_REVA_FIFO_CTRL_TX_FIFO_CNT_POS 8 /**< FIFO_CTRL_TX_FIFO_CNT Position */ 263 #define MXC_F_SPIXFC_REVA_FIFO_CTRL_TX_FIFO_CNT ((uint32_t)(0x1FUL << MXC_F_SPIXFC_REVA_FIFO_CTRL_TX_FIFO_CNT_POS)) /**< FIFO_CTRL_TX_FIFO_CNT Mask */ 264 265 #define MXC_F_SPIXFC_REVA_FIFO_CTRL_RX_FIFO_AF_LVL_POS 16 /**< FIFO_CTRL_RX_FIFO_AF_LVL Position */ 266 #define MXC_F_SPIXFC_REVA_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x1FUL << MXC_F_SPIXFC_REVA_FIFO_CTRL_RX_FIFO_AF_LVL_POS)) /**< FIFO_CTRL_RX_FIFO_AF_LVL Mask */ 267 268 #define MXC_F_SPIXFC_REVA_FIFO_CTRL_RX_FIFO_CNT_POS 24 /**< FIFO_CTRL_RX_FIFO_CNT Position */ 269 #define MXC_F_SPIXFC_REVA_FIFO_CTRL_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPIXFC_REVA_FIFO_CTRL_RX_FIFO_CNT_POS)) /**< FIFO_CTRL_RX_FIFO_CNT Mask */ 270 271 /**@} end of group SPIXFC_REVA_FIFO_CTRL_Register */ 272 273 /** 274 * @ingroup spixfc_reva_registers 275 * @defgroup SPIXFC_REVA_SP_CTRL SPIXFC_REVA_SP_CTRL 276 * @brief SPIX Controller Special Control Register. 277 * @{ 278 */ 279 #define MXC_F_SPIXFC_REVA_SP_CTRL_SAMPL_POS 0 /**< SP_CTRL_SAMPL Position */ 280 #define MXC_F_SPIXFC_REVA_SP_CTRL_SAMPL ((uint32_t)(0x1UL << MXC_F_SPIXFC_REVA_SP_CTRL_SAMPL_POS)) /**< SP_CTRL_SAMPL Mask */ 281 282 #define MXC_F_SPIXFC_REVA_SP_CTRL_SDIO_OUT_POS 4 /**< SP_CTRL_SDIO_OUT Position */ 283 #define MXC_F_SPIXFC_REVA_SP_CTRL_SDIO_OUT ((uint32_t)(0xFUL << MXC_F_SPIXFC_REVA_SP_CTRL_SDIO_OUT_POS)) /**< SP_CTRL_SDIO_OUT Mask */ 284 285 #define MXC_F_SPIXFC_REVA_SP_CTRL_SDIO_OUT_EN_POS 8 /**< SP_CTRL_SDIO_OUT_EN Position */ 286 #define MXC_F_SPIXFC_REVA_SP_CTRL_SDIO_OUT_EN ((uint32_t)(0xFUL << MXC_F_SPIXFC_REVA_SP_CTRL_SDIO_OUT_EN_POS)) /**< SP_CTRL_SDIO_OUT_EN Mask */ 287 288 #define MXC_F_SPIXFC_REVA_SP_CTRL_SCLKINH3_POS 16 /**< SP_CTRL_SCLKINH3 Position */ 289 #define MXC_F_SPIXFC_REVA_SP_CTRL_SCLKINH3 ((uint32_t)(0x1UL << MXC_F_SPIXFC_REVA_SP_CTRL_SCLKINH3_POS)) /**< SP_CTRL_SCLKINH3 Mask */ 290 291 /**@} end of group SPIXFC_REVA_SP_CTRL_Register */ 292 293 /** 294 * @ingroup spixfc_reva_registers 295 * @defgroup SPIXFC_REVA_INT_FL SPIXFC_REVA_INT_FL 296 * @brief SPIX Controller Interrupt Status Register. 297 * @{ 298 */ 299 #define MXC_F_SPIXFC_REVA_INT_FL_TX_STALLED_POS 0 /**< INT_FL_TX_STALLED Position */ 300 #define MXC_F_SPIXFC_REVA_INT_FL_TX_STALLED ((uint32_t)(0x1UL << MXC_F_SPIXFC_REVA_INT_FL_TX_STALLED_POS)) /**< INT_FL_TX_STALLED Mask */ 301 302 #define MXC_F_SPIXFC_REVA_INT_FL_RX_STALLED_POS 1 /**< INT_FL_RX_STALLED Position */ 303 #define MXC_F_SPIXFC_REVA_INT_FL_RX_STALLED ((uint32_t)(0x1UL << MXC_F_SPIXFC_REVA_INT_FL_RX_STALLED_POS)) /**< INT_FL_RX_STALLED Mask */ 304 305 #define MXC_F_SPIXFC_REVA_INT_FL_TX_READY_POS 2 /**< INT_FL_TX_READY Position */ 306 #define MXC_F_SPIXFC_REVA_INT_FL_TX_READY ((uint32_t)(0x1UL << MXC_F_SPIXFC_REVA_INT_FL_TX_READY_POS)) /**< INT_FL_TX_READY Mask */ 307 308 #define MXC_F_SPIXFC_REVA_INT_FL_RX_DONE_POS 3 /**< INT_FL_RX_DONE Position */ 309 #define MXC_F_SPIXFC_REVA_INT_FL_RX_DONE ((uint32_t)(0x1UL << MXC_F_SPIXFC_REVA_INT_FL_RX_DONE_POS)) /**< INT_FL_RX_DONE Mask */ 310 311 #define MXC_F_SPIXFC_REVA_INT_FL_TX_FIFO_AE_POS 4 /**< INT_FL_TX_FIFO_AE Position */ 312 #define MXC_F_SPIXFC_REVA_INT_FL_TX_FIFO_AE ((uint32_t)(0x1UL << MXC_F_SPIXFC_REVA_INT_FL_TX_FIFO_AE_POS)) /**< INT_FL_TX_FIFO_AE Mask */ 313 314 #define MXC_F_SPIXFC_REVA_INT_FL_RX_FIFO_AF_POS 5 /**< INT_FL_RX_FIFO_AF Position */ 315 #define MXC_F_SPIXFC_REVA_INT_FL_RX_FIFO_AF ((uint32_t)(0x1UL << MXC_F_SPIXFC_REVA_INT_FL_RX_FIFO_AF_POS)) /**< INT_FL_RX_FIFO_AF Mask */ 316 317 /**@} end of group SPIXFC_REVA_INT_FL_Register */ 318 319 /** 320 * @ingroup spixfc_reva_registers 321 * @defgroup SPIXFC_REVA_INT_EN SPIXFC_REVA_INT_EN 322 * @brief SPIX Controller Interrupt Enable Register. 323 * @{ 324 */ 325 #define MXC_F_SPIXFC_REVA_INT_EN_TX_STALLED_POS 0 /**< INT_EN_TX_STALLED Position */ 326 #define MXC_F_SPIXFC_REVA_INT_EN_TX_STALLED ((uint32_t)(0x1UL << MXC_F_SPIXFC_REVA_INT_EN_TX_STALLED_POS)) /**< INT_EN_TX_STALLED Mask */ 327 328 #define MXC_F_SPIXFC_REVA_INT_EN_RX_STALLED_POS 1 /**< INT_EN_RX_STALLED Position */ 329 #define MXC_F_SPIXFC_REVA_INT_EN_RX_STALLED ((uint32_t)(0x1UL << MXC_F_SPIXFC_REVA_INT_EN_RX_STALLED_POS)) /**< INT_EN_RX_STALLED Mask */ 330 331 #define MXC_F_SPIXFC_REVA_INT_EN_TX_READY_POS 2 /**< INT_EN_TX_READY Position */ 332 #define MXC_F_SPIXFC_REVA_INT_EN_TX_READY ((uint32_t)(0x1UL << MXC_F_SPIXFC_REVA_INT_EN_TX_READY_POS)) /**< INT_EN_TX_READY Mask */ 333 334 #define MXC_F_SPIXFC_REVA_INT_EN_RX_DONE_POS 3 /**< INT_EN_RX_DONE Position */ 335 #define MXC_F_SPIXFC_REVA_INT_EN_RX_DONE ((uint32_t)(0x1UL << MXC_F_SPIXFC_REVA_INT_EN_RX_DONE_POS)) /**< INT_EN_RX_DONE Mask */ 336 337 #define MXC_F_SPIXFC_REVA_INT_EN_TX_FIFO_AE_POS 4 /**< INT_EN_TX_FIFO_AE Position */ 338 #define MXC_F_SPIXFC_REVA_INT_EN_TX_FIFO_AE ((uint32_t)(0x1UL << MXC_F_SPIXFC_REVA_INT_EN_TX_FIFO_AE_POS)) /**< INT_EN_TX_FIFO_AE Mask */ 339 340 #define MXC_F_SPIXFC_REVA_INT_EN_RX_FIFO_AF_POS 5 /**< INT_EN_RX_FIFO_AF Position */ 341 #define MXC_F_SPIXFC_REVA_INT_EN_RX_FIFO_AF ((uint32_t)(0x1UL << MXC_F_SPIXFC_REVA_INT_EN_RX_FIFO_AF_POS)) /**< INT_EN_RX_FIFO_AF Mask */ 342 343 /**@} end of group SPIXFC_REVA_INT_EN_Register */ 344 345 #ifdef __cplusplus 346 } 347 #endif 348 349 #endif /* _SPIXFC_REVA_REGS_H_ */ 350
