1 // Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 //     http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 
15 #include <stdlib.h>
16 #include "spi_flash_chip_generic.h"
17 #include "spi_flash_defs.h"
18 #include "esp_log.h"
19 #include "string.h"
20 #include <sys/param.h> // For MIN/MAX
21 #include "hal/spi_flash_hal.h"
22 
23 #define CMD_OPI_FLASH_MXIC(cmd)              ((((~(cmd) & 0xff) << 8)) | ((cmd) & 0xff))
24 #define CMD_OPI_FLASH_MXIC_CHIP_ERASE        0x9F60
25 #define CMD_OPI_FLASH_MXIC_READ_STR          0x13EC
26 #define CMD_OPI_FLASH_MXIC_READ_DTR          0x11EE
27 #define CMD_OPI_FLASH_MXIC_RDCR2             0x8E71
28 #define CMD_OPI_FLASH_MXIC_WRCR2             0x8D72
29 
30 /* Driver for MXIC OPI flash chip */
31 static const char chip_name[] = "mxic (opi)";
32 
spi_flash_chip_mxic_opi_probe(esp_flash_t * chip,uint32_t flash_id)33 esp_err_t spi_flash_chip_mxic_opi_probe(esp_flash_t *chip, uint32_t flash_id)
34 {
35     /* Check manufacturer and product IDs match our desired masks */
36     const uint8_t MFG_ID = 0xC2;
37     if (flash_id >> 16 != MFG_ID) {
38         return ESP_ERR_NOT_FOUND;
39     }
40 
41     if (chip->read_mode < SPI_FLASH_OPI_FLAG) {
42         // The code here serve for opi flash under opi mode only, for ordinary mxic chip, go `spi_flash_chip_mxic.c`
43         return ESP_ERR_NOT_FOUND;
44     }
45 
46     return ESP_OK;
47 }
48 
spi_flash_chip_mxic_opi_get_caps(esp_flash_t * chip)49 spi_flash_caps_t spi_flash_chip_mxic_opi_get_caps(esp_flash_t *chip)
50 {
51     spi_flash_caps_t caps_flags = 0;
52     caps_flags |= SPI_FLASH_CHIP_CAP_32MB_SUPPORT;
53     // flash-suspend is not supported yet. // IDF-3852
54     // reading unique id is not supported.
55     return caps_flags;
56 }
57 
spi_flash_chip_mxic_opi_set_write_protect(esp_flash_t * chip,bool write_protect)58 esp_err_t spi_flash_chip_mxic_opi_set_write_protect(esp_flash_t *chip, bool write_protect)
59 {
60     esp_err_t err = ESP_OK;
61 
62     err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->idle_timeout);
63     spi_flash_trans_t t = {};
64     if (err == ESP_OK || err == ESP_ERR_NOT_SUPPORTED) {
65         if(write_protect) {
66             t.command = CMD_OPI_FLASH_MXIC(CMD_WRDI);
67         } else {
68             t.command = CMD_OPI_FLASH_MXIC(CMD_WREN);
69         }
70         err = chip->host->driver->common_command(chip->host, &t);
71     }
72 
73     bool wp_read;
74     err = chip->chip_drv->get_chip_write_protect(chip, &wp_read);
75     if (err == ESP_OK && wp_read != write_protect) {
76         err = ESP_ERR_NOT_FOUND;
77     }
78     return err;
79 }
80 
spi_flash_chip_mxic_opi_get_data_length_zoom(esp_flash_io_mode_t io_mode,uint32_t * length_zoom)81 static void spi_flash_chip_mxic_opi_get_data_length_zoom(esp_flash_io_mode_t io_mode, uint32_t *length_zoom)
82 {
83     /* Under STR mode, one byte occupies one single clock. While under DTR mode, one byte occupies half clock.
84        For exmaple, if an operation needs 3 clock dummy, host send 3 dummy bytes under STR mode, while 6 dummy bytes under DTR mode.
85        Therefore, we need to adjust data zoom to fit the clock here. */
86     assert((io_mode == SPI_FLASH_OPI_STR) || (io_mode == SPI_FLASH_OPI_DTR));
87     *length_zoom = (io_mode == SPI_FLASH_OPI_STR) ? 1 : 2;
88 }
89 
spi_flash_chip_mxic_opi_read_id(esp_flash_t * chip,uint32_t * out_chip_id)90 esp_err_t spi_flash_chip_mxic_opi_read_id(esp_flash_t *chip, uint32_t* out_chip_id)
91 {
92     uint64_t id_buf = 0;
93     uint32_t length_zoom;
94     spi_flash_chip_mxic_opi_get_data_length_zoom(chip->read_mode, &length_zoom);
95     spi_flash_trans_t t = {
96         .command = CMD_OPI_FLASH_MXIC(CMD_RDID),
97         .miso_len = 3 * length_zoom,
98         .dummy_bitlen = 4 * length_zoom,
99         .address_bitlen = 32,
100         .miso_data = ((uint8_t*) &id_buf),
101     };
102 
103     chip->host->driver->common_command(chip->host, &t);
104 
105     if(chip->read_mode == SPI_FLASH_OPI_DTR) {
106         // Adjust the id_buf in DTR mode, because in DTR mode, the data back in STR rule.
107         // So it looks like [MD, MD, MT, MT, MID, MID], adjust it to [MD, MT, MID] here.
108         ESP_EARLY_LOGV(chip_name, "raw_chip_id: %llx\n", id_buf);
109         id_buf = (id_buf & 0xff) | ((id_buf & 0xff0000) >> 8) | ((id_buf & 0xff00000000) >> 16);
110     } else {
111         ESP_EARLY_LOGV(chip_name, "raw_chip_id: %X\n", id_buf);
112     }
113 
114     uint32_t raw_flash_id = __builtin_bswap32(id_buf);
115     if (raw_flash_id == 0xFFFFFF || raw_flash_id == 0) {
116         ESP_EARLY_LOGE(chip_name, "no response\n");
117         return ESP_ERR_FLASH_NO_RESPONSE;
118     }
119 
120     *out_chip_id = (raw_flash_id >> 8);
121     ESP_EARLY_LOGV(chip_name, "chip_id: %X\n", *out_chip_id);
122     return ESP_OK;
123 }
124 
spi_flash_chip_mxic_opi_read_reg(esp_flash_t * chip,spi_flash_register_t reg_id,uint32_t * out_reg)125 esp_err_t spi_flash_chip_mxic_opi_read_reg(esp_flash_t *chip, spi_flash_register_t reg_id, uint32_t* out_reg)
126 {
127     uint32_t stat_buf = 0;
128     uint32_t length_zoom;
129     spi_flash_chip_mxic_opi_get_data_length_zoom(chip->read_mode, &length_zoom);
130     spi_flash_trans_t t = {
131         .command = CMD_OPI_FLASH_MXIC(CMD_RDSR),
132         .miso_data = ((uint8_t*) &stat_buf),
133         .miso_len = 1 * length_zoom,
134         .address_bitlen = 32,
135         .dummy_bitlen = 4 * length_zoom,
136     };
137     esp_err_t err = chip->host->driver->common_command(chip->host, &t);
138     if (err != ESP_OK) {
139         return err;
140     }
141 
142     // For DTR mode, RDSR result like [SR1, SR1], just keeping one SR1.
143     *out_reg = (stat_buf & 0xff);
144     return ESP_OK;
145 }
146 
spi_flash_chip_mxic_opi_get_write_protect(esp_flash_t * chip,bool * out_write_protected)147 esp_err_t spi_flash_chip_mxic_opi_get_write_protect(esp_flash_t *chip, bool *out_write_protected)
148 {
149     esp_err_t err = ESP_OK;
150     uint32_t status;
151     assert(out_write_protected!=NULL);
152     err = chip->chip_drv->read_reg(chip, SPI_FLASH_REG_STATUS, &status);
153     if (err != ESP_OK) {
154         return err;
155     }
156 
157     *out_write_protected = ((status & SR_WREN) == 0);
158     return err;
159 }
160 
spi_flash_chip_mxic_opi_erase_chip(esp_flash_t * chip)161 esp_err_t spi_flash_chip_mxic_opi_erase_chip(esp_flash_t *chip)
162 {
163     esp_err_t err;
164 
165     err = chip->chip_drv->set_chip_write_protect(chip, false);
166     if (err == ESP_OK) {
167         err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->idle_timeout);
168     }
169 
170     if (err == ESP_OK || err == ESP_ERR_NOT_SUPPORTED) {
171         // Do erase chip here.
172         spi_flash_trans_t t = {
173             .command = CMD_OPI_FLASH_MXIC_CHIP_ERASE,
174         };
175         err = chip->host->driver->common_command(chip->host, &t);
176         chip->busy = 1;
177 #ifdef CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED
178         err = chip->chip_drv->wait_idle(chip, ESP_FLASH_CHIP_GENERIC_NO_TIMEOUT);
179 #else
180         err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->chip_erase_timeout);
181 #endif
182     }
183     // Ensure WEL is 0, even if the erase failed.
184     if (err == ESP_ERR_NOT_SUPPORTED) {
185         chip->chip_drv->set_chip_write_protect(chip, true);
186     }
187 
188     return err;
189 
190 }
191 
spi_flash_chip_mxic_opi_erase_sector(esp_flash_t * chip,uint32_t start_address)192 esp_err_t spi_flash_chip_mxic_opi_erase_sector(esp_flash_t *chip, uint32_t start_address)
193 {
194     esp_err_t err = chip->chip_drv->set_chip_write_protect(chip, false);
195     if (err == ESP_OK) {
196         err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->idle_timeout);
197     }
198     //The chip didn't accept the previous write command. Ignore this in preparationstage.
199     if (err == ESP_OK || err == ESP_ERR_NOT_SUPPORTED) {
200         spi_flash_trans_t t = {
201             .command = CMD_OPI_FLASH_MXIC(CMD_SECTOR_ERASE_4B),
202             .address_bitlen = 32,
203             .address = start_address,
204         };
205         err = chip->host->driver->common_command(chip->host, &t);
206         chip->busy = 1;
207 #ifdef CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED
208         err = chip->chip_drv->wait_idle(chip, ESP_FLASH_CHIP_GENERIC_NO_TIMEOUT);
209 #else
210         err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->sector_erase_timeout);
211 #endif
212     }
213     // Ensure WEL is 0, even if the erase failed.
214     if (err == ESP_ERR_NOT_SUPPORTED) {
215         err = chip->chip_drv->set_chip_write_protect(chip, true);
216     }
217 
218     return err;
219 }
220 
spi_flash_chip_mxic_opi_erase_block(esp_flash_t * chip,uint32_t start_address)221 esp_err_t spi_flash_chip_mxic_opi_erase_block(esp_flash_t *chip, uint32_t start_address)
222 {
223     esp_err_t err = chip->chip_drv->set_chip_write_protect(chip, false);
224     if (err == ESP_OK) {
225         err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->idle_timeout);
226     }
227     //The chip didn't accept the previous write command. Ignore this in preparationstage.
228     if (err == ESP_OK || err == ESP_ERR_NOT_SUPPORTED) {
229         spi_flash_trans_t t = {
230             .command = CMD_OPI_FLASH_MXIC(CMD_LARGE_BLOCK_ERASE_4B),
231             .address_bitlen = 32,
232             .address = start_address,
233         };
234         err = chip->host->driver->common_command(chip->host, &t);
235         chip->busy = 1;
236 #ifdef CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED
237         err = chip->chip_drv->wait_idle(chip, ESP_FLASH_CHIP_GENERIC_NO_TIMEOUT);
238 #else
239         err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->block_erase_timeout);
240 #endif
241     }
242     // Ensure WEL is 0, even if the erase failed.
243     if (err == ESP_ERR_NOT_SUPPORTED) {
244         err = chip->chip_drv->set_chip_write_protect(chip, true);
245     }
246 
247     return err;
248 }
249 
spi_flash_chip_mxic_opi_page_program(esp_flash_t * chip,const void * buffer,uint32_t address,uint32_t length)250 esp_err_t spi_flash_chip_mxic_opi_page_program(esp_flash_t *chip, const void *buffer, uint32_t address, uint32_t length)
251 {
252     esp_err_t err;
253 
254     err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->idle_timeout);
255     //The chip didn't accept the previous write command. Ignore this in preparationstage.
256     if (err == ESP_OK || err == ESP_ERR_NOT_SUPPORTED) {
257         // Perform the actual Page Program command
258         spi_flash_trans_t t = {
259             .command = CMD_OPI_FLASH_MXIC(CMD_PROGRAM_PAGE_4B),
260             .address_bitlen = 32,
261             .address = address,
262             .mosi_len = length,
263             .mosi_data = buffer,
264         };
265         chip->host->driver->common_command(chip->host, &t);
266         chip->busy = 1;
267 
268         err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->page_program_timeout);
269     }
270     // Ensure WEL is 0, even if the page program failed.
271     if (err == ESP_ERR_NOT_SUPPORTED) {
272         err = chip->chip_drv->set_chip_write_protect(chip, true);
273     }
274     return err;
275 }
276 
spi_flash_chip_mxic_opi_write(esp_flash_t * chip,const void * buffer,uint32_t address,uint32_t length)277 esp_err_t spi_flash_chip_mxic_opi_write(esp_flash_t *chip, const void *buffer, uint32_t address, uint32_t length)
278 {
279     esp_err_t err = ESP_OK;
280     const uint32_t page_size = chip->chip_drv->page_size;
281     uint32_t align_address;
282     uint8_t temp_buffer[64]; //spiflash hal max length of write no longer than 64byte
283 
284     while (err == ESP_OK && length > 0) {
285         memset(temp_buffer, 0xFF, sizeof(temp_buffer));
286         uint32_t page_len = chip->host->driver->write_data_slicer(chip->host, address, length, &align_address, page_size);
287         uint32_t left_off = address - align_address;
288         uint32_t write_len = MIN(align_address + page_len, address + length) - address;
289         memcpy(temp_buffer + left_off, buffer, write_len);
290 
291         err = chip->chip_drv->set_chip_write_protect(chip, false);
292         if (err == ESP_OK && length > 0) {
293             err = chip->chip_drv->program_page(chip, temp_buffer, align_address, page_len);
294 
295             address += write_len;
296             buffer = (void *)((intptr_t)buffer + write_len);
297             length -= write_len;
298         }
299     }
300     // The caller is responsible to do host->driver->flush_cache, because this function may be
301     // called in small pieces. Frequency call of flush cache will do harm to the performance.
302     return err;
303 }
304 
spi_flash_chip_mxic_opi_get_io_mode(esp_flash_t * chip,esp_flash_io_mode_t * out_io_mode)305 esp_err_t spi_flash_chip_mxic_opi_get_io_mode(esp_flash_t *chip, esp_flash_io_mode_t* out_io_mode)
306 {
307     uint32_t stat_buf = 0;
308     uint32_t length_zoom;
309     spi_flash_chip_mxic_opi_get_data_length_zoom(chip->read_mode, &length_zoom);
310 
311     spi_flash_trans_t t = {
312         .command = CMD_OPI_FLASH_MXIC_RDCR2,
313         .dummy_bitlen = 4 * length_zoom,
314         .miso_data = ((uint8_t*) &stat_buf),
315         .miso_len = 1 * length_zoom,
316         .address_bitlen = 32,
317     };
318     esp_err_t err = chip->host->driver->common_command(chip->host, &t);
319     if (err != ESP_OK) {
320         return err;
321     }
322 
323     // For DTR mode, RDSR result like [CR1, CR1], just keeping one CR1.
324     switch (stat_buf & 0xff)
325     {
326     case 0x1:
327         *out_io_mode = SPI_FLASH_OPI_STR;
328         break;
329     case 0x2:
330         *out_io_mode = SPI_FLASH_OPI_DTR;
331         break;
332     default:
333         // wrong mode.
334         *out_io_mode = 0;
335         break;
336     }
337     if (*out_io_mode != chip->read_mode) {
338         // Current chip mode is not the mode we configured.
339         *out_io_mode = 0;
340     }
341 
342     return ESP_OK;
343 }
344 
spi_flash_chip_xmic_opi_set_io_mode(esp_flash_t * chip)345 esp_err_t spi_flash_chip_xmic_opi_set_io_mode(esp_flash_t *chip)
346 {
347     // TODO: configure opi flash chip set io mode, only useful for external flash currently.
348     // For main flash, we already set io mode when chip starts up. But for external flash,
349     // We need to set mode when flash initialized, so keeping this for future usage.
350     return ESP_OK;
351 }
352 
353 // This function should only be called after opi mode initialization. So, only configure for OPI-STR/OPI-DTR mode
354 // not support other mode in this file, return `ESP_ERR_FLASH_NOT_INITIALISED` directely.
spi_flash_chip_xmic_opi_config_host_io_mode(esp_flash_t * chip,uint32_t flags)355 esp_err_t spi_flash_chip_xmic_opi_config_host_io_mode(esp_flash_t *chip, uint32_t flags)
356 {
357     uint32_t dummy_cyclelen_base;
358     uint32_t addr_bitlen;
359     uint32_t read_command;
360     esp_flash_io_mode_t read_mode = chip->read_mode;
361 
362     switch (read_mode & 0xFFFF) {
363     case SPI_FLASH_OPI_STR:
364         addr_bitlen = SPI_FLASH_OPISTR_ADDR_BITLEN;
365         dummy_cyclelen_base = SPI_FLASH_OPISTR_DUMMY_BITLEN;
366         read_command = CMD_OPI_FLASH_MXIC_READ_STR;
367         break;
368     case SPI_FLASH_OPI_DTR:
369         addr_bitlen = SPI_FLASH_OPIDTR_ADDR_BITLEN;
370         dummy_cyclelen_base = SPI_FLASH_OPIDTR_DUMMY_BITLEN;
371         read_command = CMD_OPI_FLASH_MXIC_READ_DTR;
372         break;
373     default:
374         return ESP_ERR_FLASH_NOT_INITIALISED;
375     }
376 
377     return chip->host->driver->configure_host_io_mode(chip->host, read_command, addr_bitlen, dummy_cyclelen_base, read_mode);
378 }
379 
380 // Most of mxic opi implementations are totally different from that is generic.
381 // Replace them to opi implementation.
382 const spi_flash_chip_t esp_flash_chip_mxic_opi = {
383     .name = chip_name,
384     .timeout = &spi_flash_chip_generic_timeout,
385     .probe = spi_flash_chip_mxic_opi_probe,
386     .reset = spi_flash_chip_generic_reset,
387     .detect_size = spi_flash_chip_generic_detect_size,
388     .erase_chip = spi_flash_chip_mxic_opi_erase_chip,
389     .erase_sector = spi_flash_chip_mxic_opi_erase_sector,
390     .erase_block = spi_flash_chip_mxic_opi_erase_block,
391     .sector_size = 4 * 1024,
392     .block_erase_size = 64 * 1024,
393 
394     .get_chip_write_protect = spi_flash_chip_mxic_opi_get_write_protect,
395     .set_chip_write_protect = spi_flash_chip_mxic_opi_set_write_protect,
396 
397     .num_protectable_regions = 0,
398     .protectable_regions = NULL,
399     .get_protected_regions = NULL,
400     .set_protected_regions = NULL,
401 
402     .read = spi_flash_chip_generic_read,
403     .write = spi_flash_chip_mxic_opi_write,
404     .program_page = spi_flash_chip_mxic_opi_page_program,
405     .page_size = 256,
406     .write_encrypted = spi_flash_chip_generic_write_encrypted,
407 
408     .wait_idle = spi_flash_chip_generic_wait_idle,
409 
410     .set_io_mode = spi_flash_chip_xmic_opi_set_io_mode,
411     .get_io_mode = spi_flash_chip_mxic_opi_get_io_mode,
412 
413     .read_id = spi_flash_chip_mxic_opi_read_id,
414     .read_reg = spi_flash_chip_mxic_opi_read_reg,
415     .yield = spi_flash_chip_generic_yield,
416     .sus_setup = spi_flash_chip_generic_suspend_cmd_conf,
417     .read_unique_id = spi_flash_chip_generic_read_unique_id_none,
418     .get_chip_caps = spi_flash_chip_mxic_opi_get_caps,
419     .config_host_io_mode = spi_flash_chip_xmic_opi_config_host_io_mode,
420 };
421