1 /*
2 * Copyright (c) 2017-2019, Texas Instruments Incorporated
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 */
7
8 /* =========================== SPI Driver Fxns ========================= */
9 #include <ti/devices/cc32xx/inc/hw_ints.h>
10 #include <ti/devices/cc32xx/inc/hw_memmap.h>
11 #include <ti/devices/cc32xx/inc/hw_types.h>
12
13 #include <ti/devices/cc32xx/driverlib/rom.h>
14 #include <ti/devices/cc32xx/driverlib/rom_map.h>
15 #include <ti/devices/cc32xx/driverlib/prcm.h>
16 #include <ti/devices/cc32xx/driverlib/spi.h>
17 #include <ti/devices/cc32xx/driverlib/udma.h>
18
19 typedef enum CC3220SF_LAUNCHXL_SPIName {
20 CC3220SF_LAUNCHXL_SPI0 = 0,
21 CC3220SF_LAUNCHXL_SPI1 = 1,
22 CC3220SF_LAUNCHXL_SPICOUNT
23 } CC3220SF_LAUNCHXL_SPIName;
24
25 #include <ti/drivers/SPI.h>
26 #include <ti/drivers/spi/SPICC32XXDMA.h>
27
28 SPICC32XXDMA_Object spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPICOUNT];
29
30 uint32_t spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPICOUNT];
31
32 const SPICC32XXDMA_HWAttrsV1 spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPICOUNT] = {
33 /* index 0 is reserved for LSPI that links to the NWP */
34 {
35 .baseAddr = LSPI_BASE,
36 .intNum = INT_LSPI,
37 .intPriority = (~0),
38 .spiPRCM = PRCM_LSPI,
39 .csControl = SPI_SW_CTRL_CS,
40 .csPolarity = SPI_CS_ACTIVEHIGH,
41 .pinMode = SPI_4PIN_MODE,
42 .turboMode = SPI_TURBO_OFF,
43 .scratchBufPtr = &spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPI0],
44 .defaultTxBufValue = 0,
45 .rxChannelIndex = UDMA_CH12_LSPI_RX,
46 .txChannelIndex = UDMA_CH13_LSPI_TX,
47 .minDmaTransferSize = 100,
48 .mosiPin = SPICC32XXDMA_PIN_NO_CONFIG,
49 .misoPin = SPICC32XXDMA_PIN_NO_CONFIG,
50 .clkPin = SPICC32XXDMA_PIN_NO_CONFIG,
51 .csPin = SPICC32XXDMA_PIN_NO_CONFIG
52 },
53 {
54 .baseAddr = GSPI_BASE,
55 .intNum = INT_GSPI,
56 .intPriority = (~0),
57 .spiPRCM = PRCM_GSPI,
58 .csControl = SPI_HW_CTRL_CS,
59 .csPolarity = SPI_CS_ACTIVELOW,
60 .pinMode = SPI_4PIN_MODE,
61 .turboMode = SPI_TURBO_OFF,
62 .scratchBufPtr = &spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPI1],
63 .defaultTxBufValue = 0,
64 .rxChannelIndex = UDMA_CH6_GSPI_RX,
65 .txChannelIndex = UDMA_CH7_GSPI_TX,
66 .minDmaTransferSize = 10,
67 .mosiPin = SPICC32XXDMA_PIN_07_MOSI,
68 .misoPin = SPICC32XXDMA_PIN_06_MISO,
69 .clkPin = SPICC32XXDMA_PIN_05_CLK,
70 .csPin = SPICC32XXDMA_PIN_08_CS
71 }
72 };
73
74 const SPI_Config SPI_config[CC3220SF_LAUNCHXL_SPICOUNT] = {
75 {
76 .fxnTablePtr = &SPICC32XXDMA_fxnTable,
77 .object = &spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPI0],
78 .hwAttrs = &spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPI0]
79 },
80 {
81 .fxnTablePtr = &SPICC32XXDMA_fxnTable,
82 .object = &spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPI1],
83 .hwAttrs = &spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPI1]
84 }
85 };
86
87 const uint_least8_t SPI_count = CC3220SF_LAUNCHXL_SPICOUNT;
88
89 /*
90 * =============================== DMA ===============================
91 */
92 #include <ti/drivers/dma/UDMACC32XX.h>
93
94 static tDMAControlTable dmaControlTable[64] __attribute__ ((aligned (1024)));
95
96 /*
97 * ======== dmaErrorFxn ========
98 * This is the handler for the uDMA error interrupt.
99 */
dmaErrorFxn(uintptr_t arg)100 static void dmaErrorFxn(uintptr_t arg)
101 {
102 int status = MAP_uDMAErrorStatusGet();
103 MAP_uDMAErrorStatusClear();
104
105 /* Suppress unused variable warning */
106 (void)status;
107
108 while (1);
109 }
110
111 UDMACC32XX_Object udmaCC3220SObject;
112
113 const UDMACC32XX_HWAttrs udmaCC3220SHWAttrs = {
114 .controlBaseAddr = (void *)dmaControlTable,
115 .dmaErrorFxn = (UDMACC32XX_ErrorFxn)dmaErrorFxn,
116 .intNum = INT_UDMAERR,
117 .intPriority = (~0)
118 };
119
120 const UDMACC32XX_Config UDMACC32XX_config = {
121 .object = &udmaCC3220SObject,
122 .hwAttrs = &udmaCC3220SHWAttrs
123 };
124
125 /*
126 * ======== CC3220SF_LAUNCHXL_init ========
127 * Zephyr-port-specific general initialization
128 */
CC3220SF_LAUNCHXL_init()129 void CC3220SF_LAUNCHXL_init()
130 {
131 MAP_PRCMLPDSWakeupSourceEnable(PRCM_LPDS_HOST_IRQ);
132 SPI_init();
133 }
134
135 /*
136 * ======== Board_debugHeader ========
137 * This structure prevents the CC32XXSF bootloader from overwriting the
138 * internal FLASH; this allows us to flash a program that will not be
139 * overwritten by the bootloader with the encrypted program saved in
140 * "secure/serial flash".
141 *
142 * This structure must be placed at the beginning of internal FLASH (so
143 * the bootloader is able to recognize that it should not overwrite
144 * internal FLASH).
145 */
146 #if defined (__SF_DEBUG__) || defined(__SF_NODEBUG__)
147 #if defined(__TI_COMPILER_VERSION__)
148 #pragma DATA_SECTION(Board_debugHeader, ".dbghdr")
149 #pragma RETAIN(Board_debugHeader)
150 #elif defined(__IAR_SYSTEMS_ICC__)
151 #pragma location=".dbghdr"
152 #elif defined(__GNUC__)
153 __attribute__ ((section (".dbghdr")))
154 #endif
155 #if defined(__SF_DEBUG__)
156 const uint32_t Board_debugHeader[] = {
157 0x5AA5A55A,
158 0x000FF800,
159 0xEFA3247D
160 };
161 #elif defined (__SF_NODEBUG__)
162 const uint32_t Board_debugHeader[] = {
163 0xFFFFFFFF,
164 0xFFFFFFFF,
165 0xFFFFFFFF
166 };
167 #endif
168 #endif
169
