1 /*
2 * Copyright (c) 2017 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /*
8 * This driver is written based on the Altera's
9 * Nios-II QSPI Controller HAL driver.
10 */
11
12 #define DT_DRV_COMPAT altr_nios2_qspi_nor
13
14 #include <zephyr/kernel.h>
15 #include <zephyr/device.h>
16 #include <string.h>
17 #include <zephyr/drivers/flash.h>
18 #include <errno.h>
19 #include <zephyr/init.h>
20 #include <soc.h>
21 #include <zephyr/sys/util.h>
22 #include "flash_priv.h"
23 #include "altera_generic_quad_spi_controller2_regs.h"
24 #include "altera_generic_quad_spi_controller2.h"
25
26 #define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL
27 #include <zephyr/logging/log.h>
28 LOG_MODULE_REGISTER(flash_nios2_qspi);
29
30 /*
31 * Remove the following macros once the Altera HAL
32 * supports the QSPI Controller v2 IP.
33 */
34 #define ALTERA_QSPI_CONTROLLER2_FLAG_STATUS_REG 0x0000001C
35 #define FLAG_STATUS_PROTECTION_ERROR (1 << 1)
36 #define FLAG_STATUS_PROGRAM_SUSPENDED (1 << 2)
37 #define FLAG_STATUS_PROGRAM_ERROR (1 << 4)
38 #define FLAG_STATUS_ERASE_ERROR (1 << 5)
39 #define FLAG_STATUS_ERASE_SUSPENDED (1 << 6)
40 #define FLAG_STATUS_CONTROLLER_READY (1 << 7)
41
42 /* ALTERA_QSPI_CONTROLLER2_STATUS_REG bits */
43 #define STATUS_PROTECTION_POS 2
44 #define STATUS_PROTECTION_MASK 0x1F
45 #define STATUS_PROTECTION_EN_VAL 0x17
46 #define STATUS_PROTECTION_DIS_VAL 0x0
47
48 /* ALTERA_QSPI_CONTROLLER2_MEM_OP_REG bits */
49 #define MEM_OP_ERASE_CMD 0x00000002
50 #define MEM_OP_WRITE_EN_CMD 0x00000004
51 #define MEM_OP_SECTOR_OFFSET_BIT_POS 8
52 #define MEM_OP_UNLOCK_ALL_SECTORS 0x00000003
53 #define MEM_OP_LOCK_ALL_SECTORS 0x00000F03
54
55 #define NIOS2_QSPI_BLANK_WORD 0xFFFFFFFF
56
57 #define NIOS2_WRITE_BLOCK_SIZE 4
58
59 #define USEC_TO_MSEC(x) (x / 1000)
60
61 struct flash_nios2_qspi_config {
62 alt_qspi_controller2_dev qspi_dev;
63 struct k_sem sem_lock;
64 };
65
66 static const struct flash_parameters flash_nios2_qspi_parameters = {
67 .write_block_size = NIOS2_WRITE_BLOCK_SIZE,
68 .erase_value = 0xff,
69 };
70
71 static int flash_nios2_qspi_write_protection(const struct device *dev,
72 bool enable);
73
flash_nios2_qspi_erase(const struct device * dev,off_t offset,size_t len)74 static int flash_nios2_qspi_erase(const struct device *dev, off_t offset,
75 size_t len)
76 {
77 struct flash_nios2_qspi_config *flash_cfg = dev->data;
78 alt_qspi_controller2_dev *qspi_dev = &flash_cfg->qspi_dev;
79 uint32_t block_offset, offset_in_block, length_to_erase;
80 uint32_t erase_offset = offset; /* address of next byte to erase */
81 uint32_t remaining_length = len; /* length of data left to be erased */
82 uint32_t flag_status;
83 int32_t rc = 0, i, timeout, rc2;
84
85 k_sem_take(&flash_cfg->sem_lock, K_FOREVER);
86
87 rc = flash_nios2_qspi_write_protection(dev, false);
88 if (rc) {
89 goto qspi_erase_err;
90 }
91 /*
92 * check if offset is word aligned and
93 * length is with in the range
94 */
95 if (((offset + len) > qspi_dev->data_end) ||
96 (0 != (erase_offset &
97 (NIOS2_WRITE_BLOCK_SIZE - 1)))) {
98 LOG_ERR("erase failed at offset 0x%lx", (long)offset);
99 rc = -EINVAL;
100 goto qspi_erase_err;
101 }
102
103 for (i = offset/qspi_dev->sector_size;
104 i < qspi_dev->number_of_sectors; i++) {
105
106 if ((remaining_length <= 0U) ||
107 erase_offset >= (offset + len)) {
108 break;
109 }
110
111 block_offset = 0U; /* block offset in byte addressing */
112 offset_in_block = 0U; /* offset into current sector to erase */
113 length_to_erase = 0U; /* length to erase in current sector */
114
115 /* calculate current sector/block offset in byte addressing */
116 block_offset = erase_offset & ~(qspi_dev->sector_size - 1);
117
118 /* calculate offset into sector/block if there is one */
119 if (block_offset != erase_offset) {
120 offset_in_block = erase_offset - block_offset;
121 }
122
123 /* calculate the byte size of data to be written in a sector */
124 length_to_erase = MIN(qspi_dev->sector_size - offset_in_block,
125 remaining_length);
126
127 /* Erase sector */
128 IOWR_32DIRECT(qspi_dev->csr_base,
129 ALTERA_QSPI_CONTROLLER2_MEM_OP_REG,
130 MEM_OP_WRITE_EN_CMD);
131 IOWR_32DIRECT(qspi_dev->csr_base,
132 ALTERA_QSPI_CONTROLLER2_MEM_OP_REG,
133 (i << MEM_OP_SECTOR_OFFSET_BIT_POS)
134 | MEM_OP_ERASE_CMD);
135
136 /*
137 * poll the status register to know the
138 * completion of the erase operation.
139 */
140 timeout = ALTERA_QSPI_CONTROLLER2_1US_TIMEOUT_VALUE;
141 while (timeout > 0) {
142 /* wait for 1 usec */
143 k_busy_wait(1);
144
145 flag_status = IORD_32DIRECT(qspi_dev->csr_base,
146 ALTERA_QSPI_CONTROLLER2_FLAG_STATUS_REG);
147
148 if (flag_status & FLAG_STATUS_CONTROLLER_READY) {
149 break;
150 }
151
152 timeout--;
153 }
154
155 if ((flag_status & FLAG_STATUS_ERASE_ERROR) ||
156 (flag_status & FLAG_STATUS_PROTECTION_ERROR)) {
157 LOG_ERR("erase failed, Flag Status Reg:0x%x",
158 flag_status);
159 rc = -EIO;
160 goto qspi_erase_err;
161 }
162
163 /* update remaining length and erase_offset */
164 remaining_length -= length_to_erase;
165 erase_offset += length_to_erase;
166 }
167
168 qspi_erase_err:
169 rc2 = flash_nios2_qspi_write_protection(dev, true);
170
171 if (!rc) {
172 rc = rc2;
173 }
174
175 k_sem_give(&flash_cfg->sem_lock);
176 return rc;
177
178 }
179
flash_nios2_qspi_write_block(const struct device * dev,int block_offset,int mem_offset,const void * data,size_t len)180 static int flash_nios2_qspi_write_block(const struct device *dev,
181 int block_offset,
182 int mem_offset, const void *data,
183 size_t len)
184 {
185 struct flash_nios2_qspi_config *flash_cfg = dev->data;
186 alt_qspi_controller2_dev *qspi_dev = &flash_cfg->qspi_dev;
187 uint32_t buffer_offset = 0U; /* offset into data buffer to get write data */
188 int32_t remaining_length = len; /* length left to write */
189 uint32_t write_offset = mem_offset; /* offset into flash to write too */
190 uint32_t word_to_write, padding, bytes_to_copy;
191 uint32_t flag_status;
192 int32_t rc = 0;
193
194 while (remaining_length > 0) {
195 /* initialize word to write to blank word */
196 word_to_write = NIOS2_QSPI_BLANK_WORD;
197
198 /* bytes to pad the next word that is written */
199 padding = 0U;
200
201 /* number of bytes from source to copy */
202 bytes_to_copy = NIOS2_WRITE_BLOCK_SIZE;
203
204 /*
205 * we need to make sure the write is word aligned
206 * this should only be true at most 1 time
207 */
208 if (0 != (write_offset & (NIOS2_WRITE_BLOCK_SIZE - 1))) {
209 /*
210 * data is not word aligned calculate padding bytes
211 * need to add before start of a data offset
212 */
213 padding = write_offset & (NIOS2_WRITE_BLOCK_SIZE - 1);
214
215 /*
216 * update variables to account
217 * for padding being added
218 */
219 bytes_to_copy -= padding;
220
221 if (bytes_to_copy > remaining_length) {
222 bytes_to_copy = remaining_length;
223 }
224
225 write_offset = write_offset - padding;
226
227 if (0 != (write_offset &
228 (NIOS2_WRITE_BLOCK_SIZE - 1))) {
229 rc = -EINVAL;
230 goto qspi_write_block_err;
231 }
232 } else {
233 if (bytes_to_copy > remaining_length) {
234 bytes_to_copy = remaining_length;
235 }
236 }
237
238 /* Check memcpy length is within NIOS2_WRITE_BLOCK_SIZE */
239 if (padding + bytes_to_copy > NIOS2_WRITE_BLOCK_SIZE) {
240 rc = -EINVAL;
241 goto qspi_write_block_err;
242 }
243
244 /* prepare the word to be written */
245 memcpy((uint8_t *)&word_to_write + padding,
246 (const uint8_t *)data + buffer_offset,
247 bytes_to_copy);
248
249 /* enable write */
250 IOWR_32DIRECT(qspi_dev->csr_base,
251 ALTERA_QSPI_CONTROLLER2_MEM_OP_REG,
252 MEM_OP_WRITE_EN_CMD);
253
254 /* write to flash 32 bits at a time */
255 IOWR_32DIRECT(qspi_dev->data_base, write_offset, word_to_write);
256
257 /* check whether write operation is successful */
258 flag_status = IORD_32DIRECT(qspi_dev->csr_base,
259 ALTERA_QSPI_CONTROLLER2_FLAG_STATUS_REG);
260
261 if ((flag_status & FLAG_STATUS_PROGRAM_ERROR) ||
262 (flag_status & FLAG_STATUS_PROTECTION_ERROR)) {
263 LOG_ERR("write failed, Flag Status Reg:0x%x",
264 flag_status);
265 rc = -EIO; /* sector might be protected */
266 goto qspi_write_block_err;
267 }
268
269 /* update offset and length variables */
270 buffer_offset += bytes_to_copy;
271 remaining_length -= bytes_to_copy;
272 write_offset = write_offset + NIOS2_WRITE_BLOCK_SIZE;
273 }
274
275 qspi_write_block_err:
276 return rc;
277 }
278
flash_nios2_qspi_write(const struct device * dev,off_t offset,const void * data,size_t len)279 static int flash_nios2_qspi_write(const struct device *dev, off_t offset,
280 const void *data, size_t len)
281 {
282 struct flash_nios2_qspi_config *flash_cfg = dev->data;
283 alt_qspi_controller2_dev *qspi_dev = &flash_cfg->qspi_dev;
284 uint32_t block_offset, offset_in_block, length_to_write;
285 uint32_t write_offset = offset; /* address of next byte to write */
286 uint32_t buffer_offset = 0U; /* offset into source buffer */
287 uint32_t remaining_length = len; /* length of data left to be written */
288 int32_t rc = 0, i, rc2;
289
290 k_sem_take(&flash_cfg->sem_lock, K_FOREVER);
291
292 rc = flash_nios2_qspi_write_protection(dev, false);
293 if (rc) {
294 goto qspi_write_err;
295 }
296 /*
297 * check if offset is word aligned and
298 * length is with in the range
299 */
300 if ((data == NULL) || ((offset + len) > qspi_dev->data_end) ||
301 (0 != (write_offset &
302 (NIOS2_WRITE_BLOCK_SIZE - 1)))) {
303 LOG_ERR("write failed at offset 0x%lx", (long)offset);
304 rc = -EINVAL;
305 goto qspi_write_err;
306 }
307
308 for (i = offset/qspi_dev->sector_size;
309 i < qspi_dev->number_of_sectors; i++) {
310
311 if (remaining_length <= 0U) {
312 break;
313 }
314
315 block_offset = 0U; /* block offset in byte addressing */
316 offset_in_block = 0U; /* offset into current sector to write */
317 length_to_write = 0U; /* length to write to current sector */
318
319 /* calculate current sector/block offset in byte addressing */
320 block_offset = write_offset & ~(qspi_dev->sector_size - 1);
321
322 /* calculate offset into sector/block if there is one */
323 if (block_offset != write_offset) {
324 offset_in_block = write_offset - block_offset;
325 }
326
327 /* calculate the byte size of data to be written in a sector */
328 length_to_write = MIN(qspi_dev->sector_size - offset_in_block,
329 remaining_length);
330
331 rc = flash_nios2_qspi_write_block(dev,
332 block_offset, write_offset,
333 (const uint8_t *)data + buffer_offset,
334 length_to_write);
335 if (rc < 0) {
336 goto qspi_write_err;
337 }
338
339 /* update remaining length and buffer_offset */
340 remaining_length -= length_to_write;
341 buffer_offset += length_to_write;
342 write_offset += length_to_write;
343 }
344
345 qspi_write_err:
346 rc2 = flash_nios2_qspi_write_protection(dev, true);
347
348 if (!rc) {
349 rc = rc2;
350 }
351
352 k_sem_give(&flash_cfg->sem_lock);
353 return rc;
354 }
355
flash_nios2_qspi_read(const struct device * dev,off_t offset,void * data,size_t len)356 static int flash_nios2_qspi_read(const struct device *dev, off_t offset,
357 void *data, size_t len)
358 {
359 struct flash_nios2_qspi_config *flash_cfg = dev->data;
360 alt_qspi_controller2_dev *qspi_dev = &flash_cfg->qspi_dev;
361 uint32_t buffer_offset = 0U; /* offset into data buffer to get read data */
362 uint32_t remaining_length = len; /* length left to read */
363 uint32_t read_offset = offset; /* offset into flash to read from */
364 uint32_t word_to_read, bytes_to_copy;
365 int32_t rc = 0;
366
367 /*
368 * check if offset and length are within the range
369 */
370 if ((data == NULL) || (offset < qspi_dev->data_base) ||
371 ((offset + len) > qspi_dev->data_end)) {
372 LOG_ERR("read failed at offset 0x%lx", (long)offset);
373 return -EINVAL;
374 }
375
376 if (!len) {
377 return 0;
378 }
379
380 k_sem_take(&flash_cfg->sem_lock, K_FOREVER);
381
382 /* first unaligned start */
383 read_offset &= ~(NIOS2_WRITE_BLOCK_SIZE - 1U);
384 if (offset > read_offset) {
385 /* number of bytes from source to copy */
386 bytes_to_copy = NIOS2_WRITE_BLOCK_SIZE - (offset - read_offset);
387 if (bytes_to_copy > remaining_length) {
388 bytes_to_copy = remaining_length;
389 }
390 /* read from flash 32 bits at a time */
391 word_to_read = IORD_32DIRECT(qspi_dev->data_base, read_offset);
392 memcpy((uint8_t *)data, (uint8_t *)&word_to_read + offset -
393 read_offset, bytes_to_copy);
394 /* update offset and length variables */
395 read_offset += NIOS2_WRITE_BLOCK_SIZE;
396 buffer_offset += bytes_to_copy;
397 remaining_length -= bytes_to_copy;
398 }
399
400 /* aligned part, including unaligned end */
401 while (remaining_length > 0) {
402 /* number of bytes from source to copy */
403 bytes_to_copy = NIOS2_WRITE_BLOCK_SIZE;
404
405 if (bytes_to_copy > remaining_length) {
406 bytes_to_copy = remaining_length;
407 }
408
409 /* read from flash 32 bits at a time */
410 word_to_read = IORD_32DIRECT(qspi_dev->data_base, read_offset);
411 memcpy((uint8_t *)data + buffer_offset, &word_to_read,
412 bytes_to_copy);
413 /* update offset and length variables */
414 read_offset += bytes_to_copy;
415 buffer_offset += bytes_to_copy;
416 remaining_length -= bytes_to_copy;
417 }
418
419 k_sem_give(&flash_cfg->sem_lock);
420 return rc;
421 }
422
flash_nios2_qspi_write_protection(const struct device * dev,bool enable)423 static int flash_nios2_qspi_write_protection(const struct device *dev,
424 bool enable)
425 {
426 struct flash_nios2_qspi_config *flash_cfg = dev->data;
427 alt_qspi_controller2_dev *qspi_dev = &flash_cfg->qspi_dev;
428 uint32_t status, lock_val;
429 int32_t rc = 0, timeout;
430
431 /* set write enable */
432 IOWR_32DIRECT(qspi_dev->csr_base,
433 ALTERA_QSPI_CONTROLLER2_MEM_OP_REG,
434 MEM_OP_WRITE_EN_CMD);
435 if (enable) {
436 IOWR_32DIRECT(qspi_dev->csr_base,
437 ALTERA_QSPI_CONTROLLER2_MEM_OP_REG,
438 MEM_OP_LOCK_ALL_SECTORS);
439 lock_val = STATUS_PROTECTION_EN_VAL;
440 } else {
441 IOWR_32DIRECT(qspi_dev->csr_base,
442 ALTERA_QSPI_CONTROLLER2_MEM_OP_REG,
443 MEM_OP_UNLOCK_ALL_SECTORS);
444 lock_val = STATUS_PROTECTION_DIS_VAL;
445 }
446
447 /*
448 * poll the status register to know the
449 * completion of the erase operation.
450 */
451 timeout = ALTERA_QSPI_CONTROLLER2_1US_TIMEOUT_VALUE;
452 while (timeout > 0) {
453 /* wait for 1 usec */
454 k_busy_wait(1);
455
456 /*
457 * read flash flag status register before
458 * checking the QSPI status
459 */
460 IORD_32DIRECT(qspi_dev->csr_base,
461 ALTERA_QSPI_CONTROLLER2_FLAG_STATUS_REG);
462
463 /* read QPSI status register */
464 status = IORD_32DIRECT(qspi_dev->csr_base,
465 ALTERA_QSPI_CONTROLLER2_STATUS_REG);
466 if (((status >> STATUS_PROTECTION_POS) &
467 STATUS_PROTECTION_MASK) == lock_val) {
468 break;
469 }
470
471 timeout--;
472 }
473
474 if (timeout <= 0) {
475 LOG_ERR("locking failed, status-reg 0x%x", status);
476 rc = -EIO;
477 }
478
479 /* clear flag status register */
480 IOWR_32DIRECT(qspi_dev->csr_base,
481 ALTERA_QSPI_CONTROLLER2_FLAG_STATUS_REG, 0x0);
482 return rc;
483 }
484
485 static const struct flash_parameters *
flash_nios2_qspi_get_parameters(const struct device * dev)486 flash_nios2_qspi_get_parameters(const struct device *dev)
487 {
488 ARG_UNUSED(dev);
489
490 return &flash_nios2_qspi_parameters;
491 }
492
493 static const struct flash_driver_api flash_nios2_qspi_api = {
494 .erase = flash_nios2_qspi_erase,
495 .write = flash_nios2_qspi_write,
496 .read = flash_nios2_qspi_read,
497 .get_parameters = flash_nios2_qspi_get_parameters,
498 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
499 .page_layout = (flash_api_pages_layout)
500 flash_page_layout_not_implemented,
501 #endif
502 };
503
flash_nios2_qspi_init(const struct device * dev)504 static int flash_nios2_qspi_init(const struct device *dev)
505 {
506 struct flash_nios2_qspi_config *flash_cfg = dev->data;
507
508 k_sem_init(&flash_cfg->sem_lock, 1, 1);
509 return 0;
510 }
511
512 struct flash_nios2_qspi_config flash_cfg = {
513 .qspi_dev = {
514 .data_base = EXT_FLASH_AVL_MEM_BASE,
515 .data_end = EXT_FLASH_AVL_MEM_BASE + EXT_FLASH_AVL_MEM_SPAN,
516 .csr_base = EXT_FLASH_AVL_CSR_BASE,
517 .size_in_bytes = EXT_FLASH_AVL_MEM_SPAN,
518 .is_epcs = EXT_FLASH_AVL_MEM_IS_EPCS,
519 .number_of_sectors = EXT_FLASH_AVL_MEM_NUMBER_OF_SECTORS,
520 .sector_size = EXT_FLASH_AVL_MEM_SECTOR_SIZE,
521 .page_size = EXT_FLASH_AVL_MEM_PAGE_SIZE,
522 }
523 };
524
525 BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
526 "only one 'altr,nios2-qspi-nor' compatible node may be present");
527
528 DEVICE_DT_INST_DEFINE(0,
529 flash_nios2_qspi_init, NULL, &flash_cfg, NULL,
530 POST_KERNEL, CONFIG_FLASH_INIT_PRIORITY,
531 &flash_nios2_qspi_api);
532
